A1369 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications FEATURES AND BENEFITS * Customer programmable offset, and sensitivity * Sensitivity & QVO temperature coefficients programmed at Allegro for improved accuracy * Output value decreases with South Magnetic Field and increases with North Magnetic field. * 3-pin SIP package for easy integration with magnetic concentrator * Low noise, moderate bandwidth, analog output * High speed chopping scheme minimizes QVO drift over temperature * Temperature-stable quiescent voltage output and sensitivity * Precise recoverability after temperature cycling * Output voltage clamps provide short circuit diagnostic capabilities * Under voltage lock-out (UVLO) Continued on the next page... Package: 3-Pin SIP (suffix UA) DESCRIPTION The AllegroTM A1369 is a customer programmable, high accuracy linear Hall effect-based current sensor IC. It is packaged in a thin 3-pin SIP package to allow for easy integration with a magnetic core to create a highly accurate current sensing module. The programmable nature of the A1369 enables it to account for manufacturing tolerances in the final current sensing module assembly. This temperature-stable device is available in a through-hole single in-line package (TO-92). The accuracy of the device is enhanced via programmability on the output pin for endof-line optimization without the added complexity and cost of a fully programmable device. The device features One-TimeProgramming (OTP), using non-volatile memory, to optimize device sensitivity and the quiescent output voltage (QVO) (output with no magnetic field) for a given application or circuit. The A1369 also allow for optimized performance over temperature through programming the temperature coefficient for both Sensitivity and QVO at Allegro end of line test. These ratiometric Hall effect sensors provide a voltage output that is proportional to the applied magnetic field. The quiescent voltage output is user adjustable around 50% of the supply voltage and the output sensitivity is programmable within a range of 8.5 mV/G to 12.5 mV/G for the A1369-10 and 22 mV/G to 26 mV/G for the A1369-24. Not to scale Continued on the next page... Tuned Filter VCC Dynamic Offset Cancellation V+ Sensitivity and Sensitivity TC Offset and Offset TC Trim Control GND Functional Block Drawing A1369-DS VOUT/ Programming Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 FEATURES AND BENEFITS (CONTINUED) * Wide ambient temperature range: -40C to +85C * Immune to mechanical stress DESCRIPTION (CONTINUED) The features of this linear device makes it ideal for use in industrial applications requiring high accuracy and are guaranteed over a wide temperature range, -40C to+85C. Selection Guide Part Number Sensitivity Range (mV/G) A1369EUA-10-T 8.5 to 12.5 A1369EUA-24-T 22 to 26 *Contact AllegroTM for additional packing options. Functional Block Diagram Specifications Absolute Maximum Ratings Thermal Characteristics Pin-out Diagram and Terminal List Electrical Characteristics Characteristic Definitions Chopper Stabilization Technique 1 3 3 3 3 4 7 10 Programming Guidelines 11 Programming procedures 13 Overview Definition of Terms Mode/Parameter Selection Try Mode Bitfield Addressing 11 11 13 13 Table of Contents Fuse Blowing Locking the Device Additional Guidelines 14 15 15 Programming Modes 16 Programming State Machine 18 Package Outline Drawing 21 Try Mode Blow Mode Read Mode Initial State Mode Selection State Parameter Selection State Bitfield Addressing State Fuse Blowing State 16 16 16 19 19 19 19 19 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 SPECIFICATIONS Absolute Maximum Ratings Rating Unit Forward Supply Voltage Characteristic Symbol VCC 8 V Reverse Supply Voltage VRCC -0.1 V Forward Output Voltage VOUT 15 V Reverse Output Voltage VROUT Output Source Current IOUT(SOURCE) Output Sink Current IOUT(SINK) Notes VOUT to VCC to VOUT -0.1 V 2 mA 10 mA Operating Ambient Temperature TA -40 to 85 C Maximum Junction Temperature TJ(max) 165 C Tstg -65 to 170 C Storage Temperature Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol Test Conditions* Value Unit RJA Package UA, on 1-layer PCB with copper limited to solder pads 165 C/W *Additional thermal information available on the Allegro website. Pin-out Diagram and Terminal List Table Terminal List Table Number 1 2 3 Name Function 1 VCC Input power supply; tie to GND with bypass capacitor 2 GND Ground 3 VOUT Output Signal; also used for programming Package UA, 3-Pin SIP Pin-out Diagram Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 ELECTRICAL CHARACTERISTICS: valid over TA, CBYPASS = 0.1 F, VCC = 5 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Unit Electrical Characteristics Supply Voltage Under-voltage Threshold1 VCC 4.5 5.0 5.5 V VUVLOHI TA = 25C (device power on) - - 3 V VUVLOLOW TA = 25C (device power on) 2.5 - - V ICC No load on VOUT - 9 12 mA Power On Time2 tPO TA = 25C, CL(PROBE) = 10 pF - 60 - s Delay to Clamp3 tCLP TA = 25C, CL = 10 nF - 30 - s Supply Zener Clamp Voltage VZ TA = 25C, ICC = 24.5 mA 6 7.3 - V Small signal -3 dB - 7 - kHz TA = 25C - 400 - kHz TA = 25C, Sens = 10.5 mV/G, CL = 1 nF - 10 - mV(p-p) TA = 25C, Sens = 24 mV/G, CL = 1 nF - 24 - mV(p-p) TA = 25C, No load out VOUT, f <<BWi - 1.5 - mG/Hz Supply Current Internal Bandwidth Chopping Frequency4 BWi fC Output Characteristics Output Referred Noise5 VN Input Referred Noise Density VNRMS DC Output Resistance ROUT - <1 - Output Load Resistance RL VOUT to GND 4.7 - - k Output Load Capacitance CL VOUT to GND Output Voltage Clamp6 - - 1 nF VCLP(HIGH) TA = 25C, B = + X G; RL = 10 k (VOUT to GND) 4.55 - - V VCLP(LOW) TA = 25C, B = -X G; RL = 10 k (VOUT to GND) - - 0.45 V VOUT(Q)init B = 0 G, TA = 25C - 2.5 - V A1369-10, TA = 25C - -10 - mV/G A1369-24, TA = 25C - -24 - mV/G Initial QVO and Sensitivity Pre-Programming Quiescent Voltage Output Pre-Programming Sensitivity Sensinit Target Sensitivity Temperature Coefficient TCSens TA = 85C, calculated relative to 25C - 0 - %/C VOUT(Q) TA = 85C, calculated relative to 25C - 0 - %/C Target Quiescent Voltage Output Drift Continued on the next page... 1On power-up, the output of the A1369 will be held low until VCC exceeds VUVLOHI. Once powered, the output will remain valid until VCC drops below VUVLOLO, when the output will be pulled low 2See Characteristic Definitions 3See Characteristic Definitions 4f varies up to approximately 20% over the full operating ambient temperature range & process C 5 Value is derived as 6 sigma value from the spectral noise density. 6V CLP(LOW) and VCLP(HIGH) will scale with VCC due to ratiometry Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 ELECTRICAL CHARACTERISTICS (continued): valid over TA, CBYPASS = 0.1 F, VCC = 5 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Unit 2.45 - 2.55 V - 5 - Bits 4.75 7.5 10.5 mV - StepVOUT(Q) x 0.5 Customer Quiescent Voltage Output Programming Guaranteed Quiescent Voltage Output Range7 VOUT(Q) TA = 25C Quiescent Voltage Output Programming Bits Average Quiescent Voltage Output Step Size8,9 StepVOUT(Q) Quiescent Voltage Output Programming Resolution10 ErrPGVOUT(Q) TA = 25C TA = 25C Customer Sensitivity Programming Sensitivity Programming Bits Default Sensitivity Sens Guaranteed Fine Step Sensitivity Range11 Sens Average Sensitivity Step Size8,9 StepSens Sensitivity Programming Resolution10 - 7 - Bits - -10.5 - mV/G A1369-24, TA = 25C - -24 - mV/G A1369-10, TA = 25C -8.5 - -12.5 mV/G A1369-24, TA = 25C -22 - -26 mV/G A1369-10, TA = 25C -72 -102 -133 V/G A1369-24, TA = 25C -163 -233 -303 V/G - StepSens x 0.5 - V/G - 1 - Bit A1369-10, TA = 25C ErrPROGSENS TA = 25C Customer Clamp Disable Programming Clamp Disable Bit Output Voltage12 VSAT,HIGH B = -X G; RL = 4.7 k (VOUT to GND) 4.75 - - V VSAT,LOW B = + X G; RL = 4.7 k (VOUT to GND) - - 0.25 V - 1 - Bit Customer Lock Overall Programming Lock Bit LOCK Continued on the next page... 7V OUT(Q)(max) is the value available with all programming fuses blown (maximum programming code set). VOUT(Q) is the total range from VOUT(Q)init up to and including VOUT(Q)(max). See Characteristic Definitions. 8Step size is larger than required to account for manufacturing spread. See Characteristics Definitions 9Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be twice the maximum specified value of StepV OUT(Q) or StepSENS 10Fine programming value accuracy. See Characteristic Definitions 11Sens (max) is the value available with all programming fuses blown (maximum programming code set). Sens range is the total range from Sensinit up to and including Sens(max). See Characteristic Definitions. 12 V SAT,HIGH and VVSAT,LOW will scale with the supply voltage due to the Ratiometry of the part Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 ELECTRICAL CHARACTERISTICS (continued): valid over TA, CBYPASS = 0.1 F, VCC = 5 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Unit Error Components13 Linearity Sensitivity Error Symmetry Sensitivity Error Ratiometry Quiescent Voltage Output Error14 Ratiometry Sensitivity Error Ratiometry Clamp Error LinERR SymERR RatVOUT(Q) RatSENS RatVOUTVLP A1369-10 - 1.0 - % A1369-24 - 1.5 - % A1369-10 - 1.5 - % A1369-24 - 1.7 - % A1369-10, over guaranteed supply voltage (relative to VCC = 5 V) - 0.5 - % A1369-24, over guaranteed supply voltage (relative to VCC = 5 V) - 0.5 - % A1369-10, over guaranteed supply voltage (relative to VCC = 5 V) - 1.0 - % A1369-24, over guaranteed supply voltage (relative to VCC = 5 V) - 1.0 - % A1369-10, over guaranteed supply voltage (relative to VCC = 5 V), TA = 25C - 0.5 - % A1369-24, over guaranteed supply voltage (relative to VCC = 5 V), TA = 25C - 0.5 - % Additional Characteristics15 Guaranteed Quiescent Voltage Output Drift Through Temperature Range VOUT(Q) Sensitivity Drift Through Temperature Range SensTC Sensitivity Drift Due to Package Hysteresis SensPKG A1369-10, TA = 85C -20 - +20 mV A1369-24, TA = 85C -30 - +30 mV A1369-10, TA = -40C - 40 - mV A1369-24, TA = -40C - 50 - mV A1369-10, measured at 85C, calculated relative to 25C - 1.6 - % A1369-24, measured at 85C, calculated relative to 25C TA = 25C; after temperature cycling 1.8 - 2 % - % Typical error is based on 3 value of sample distribution. change from actual value at VCC = 5 V for a given temperature 15 Typical error is based on 3 value around mean value of sample distribution. 12 13 Percent Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 CHARACTERISTIC DEFINITIONS Power On Time. When the supply is ramped to its operating voltage, the device output requires a finite time to react to an input magnetic field. Power On Time is defined as the time it takes for the output voltage begin responding to an applied magnetic field after the power supply has reached its minimum specified operating voltage, VCC(min). Delay to Clamp. A large magnetic input step may cause the clamp to overshoot its steady state value. The delay to clamp is defined as the time it takes for the output voltage to settle within 1% of its steady state value after initially passing through its steady state voltage. Magnetic Input V VCLP,HIGH VCC VCC(typ.) VOUT t1 VCC(min.) tPO t1 tCLP Sensor Output t2 VOUT 90% VOUT t2 t1 = time at which power supply reaches minimum specified operating voltage t1 = time at which output voltage initially reaches steady state clamp voltage t2 = time at which output voltage settles within 10% of its steady state value under and applied magnetic field t2 = time at which output voltage settles to within 1% of steady state clamp voltage 0 time (s) +t Figure 1: Power On Time Guaranteed Quiescent Voltage Output Range. The quiescent voltage output can be programmed around 2.5 V within the guaranteed quiescent voltage range limits, VOUT(Q)(max) and VOUT(Q) (min). The available guaranteed programming range falls within the distribution of initial VOUT(Q) and the max code VOUT(Q). VOUT(Q)init(typ) range. range. 2N Figure 3: Delay to Clamp - 1 is the value of the max programming code in the Quiescent Voltage Output Programming Resolution. The programming resolution for any device is half of its programming step size. Therefore the typical programming resolution will be: 0.5 x StepVOUT(Q)(typ) Garanteed VOUT(Q) Programming Range Initial VOUT(Q) Distribution VOUT(Q)(min) Max Code VOUT(Q) Distribution VOUT(Q)(max) Figure 2: QVO Range Average Quiescent Voltage Output Step Size. The average quiescent voltage output step size for a single device is determined using the following calculation: N StepVOUT(Q) - VOUT(Q)(2 - 1) - VOUT(Q)init N 2 -1 where N is the number of available programming bits in the trim Quiescent Voltage Output Drift Through Temperature Range. Due to internal component tolerances and thermal considerations the quiescent voltage output, VOUT(Q), may drift from its nominal value over the operating ambient temperature, TA. For purposes of specification, the Quiescent Voltage Output Drift Through Temperature Range, VOUT(Q) (mV), is defined as: VOUT(Q) = VOUT(Q, TA) - VOUT(Q, 25C) Sensitivity. The presence of a south-pole magnetic field perpendicular to the branded surface of the package face increases the output voltage from its quiescent value toward the supply voltage rail. The amount of the output voltage increase is proportional to the magnitude of the magnetic field applied. Conversely, the application of a north pole will decrease the output voltage from Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 its quiescent value. This proportionality is specified as the magnetic sensitivity, Sens (mV/G), of the device and is defined as: Sens = VOUT(B+) - VOUT(B-) B+ - B- sensitivity temperature coefficient effects cause the magnetic sensitivity to drift from its ideal value over the operating ambient temperature, TA. For purposes of specification, the sensitivity drift through temperature range, SensTC, is defined: SensTC - where B+ and B- are two magnetic fields with opposite polarities. Guaranteed Sensitivity Range. The magnetic sensitivity can be programmed around its nominal value within the sensitivity range limits, Sens(max) and Sens(min). Refer to the section on guaranteed quiescent voltage output range for a conceptual explanation. Average Sensitivity Step Size. Refer to the section on average quiescent voltage output step size for a conceptual explanation. Sensitivity Programming Resolution. Refer to the section on quiescent voltage output programming resolution for a conceptual explanation. Sensitivity Temperature Coefficient. The device sensitivity changes over temperature with respect to its sensitivity temperature coefficient, TCSENS. TCSENS is programmed at 85C, and calculated relative to the nominal sensitivity programming temperature of 25C. TCSENS (%/C) is defined as: TCSENS = ( SensSens- Sens T2 T1 T1 )(T2 -1 T1 ) x 100% where T1 is the nominal Sens programming temperature of 25C, and T2 is the TCSENS programming temperature of 85C. The ideal value of sensitivity over temperature, SensIDEAL(TA), is defined as: Sensitivity Drift Due to Package Hysteresis. Package stress and relaxation can cause the device sensitivity at TA = 25C to change during/after temperature cycling. This change in sensitivity follows a hysteresis curve. For purposes of specification, the sensitivity drift due to package hysteresis, SensPKG, is defined: SensPKG = Average Sensitivity Temperature Coefficient Step Size. Refer to the section on average quiescent voltage output step size for a conceptual explanation. Sensitivity Temperature Coefficient Programming Resolution. Refer to the section on quiescent voltage output programming resolution for a conceptual explanation. ( Sens Sens- Sens ) x 100% (25V, 2) (25C, 1) (25C, 1) where Sens(25C ,1) is the programmed value of sensitivity at TA = 25C, and Sens(25C ,2) is the value of sensitivity at TA = 25C after temperature cycling TA up to 85C, down to - 40C, and back to up 25C. Linearity Sensitivity Error. The A1369 is designed to provide linear output in response to a ramping applied magnetic field. Consider two magnetic fields, B1 and B2. Ideally the sensitivity of a device is the same for both fields for a given supply voltage and temperature. Linearity error is present when there is a difference between the sensitivities measured at B1 and B2. Linearity Error is calculated separately for the positive (LinERR+) and negative (LinERR-) applied magnetic fields. Linearity error (%) is measured and defined as: x 100% ( Sens Sens ) Sens = (1 - x 100% Sens ) B++ LinERR+ = 1 - SensIDEAL(TA) = SensT1 x (100% + TCSENS(TA - T1)) Guaranteed Sensitivity Temperature Coefficient Range. The magnetic sensitivity temperature coefficient can be programmed within its limits of TCSens(max) and TCSens(min). Refer to the section on guaranteed quiescent voltage output range for a conceptual explanation. SensTA - SensIDEAL(TA) x 100% SensIDEAL(TA) B+ LinERR- B-- B- LinERR = max(|LinERR+|,|LinERR-|) where SensBx = ( |V OUTBx ) - VOUT(Q)| Dx and B++, B+, B--, and B- are positive and negative magnetic fields with respect to the quiescent voltage output such that |B++| > |B+| and |B--| > |B-|. Sensitivity Drift Through Temperature Range. Second order Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 The output voltage clamps, VCLP(HIGH) and VCLP(LOW), limit the operating magnetic range of the applied field in which the device provides a linear output. The maximum positive and negative applied magnetic fields in the operating range can be calculated: |BMAX(+)| - VCLP,HIGH - VOUT(Q) Sens |BMAX(-)| - VOUT(Q) - VCLP,LOW Sens Sens(B+) Sens(B-) ( ) x 100% where SensBx = ( Sens(VCC) / Sens(5 V) x 100% VCC /5 V RATVOUTCLP = 1 - Symmetry error, SymERR (%), is measured and defined as: ( ) ( RATERRSens = 1 - The ratiometric error in the clamp voltages, RatVOUTCLP (%), for a given supply voltage, VCC, is defined as: Symmetry Sensitivity Error. The magnetic sensitivity of a device is constant for any two applied magnetic fields of equal magnitude and opposite polarities. SymERR = 1 - The ratiometric error in magnetic sensitivity, RatSens (%), for a given supply voltage, VCC, is defined as: ) |VOUT(BX) - VOUT(Q)| Bx and B+, B- are positive and negative magnetic fields such that |B+| = |B-|. Ratiometry Error. The A1369 provides a ratiometric output. This means that the quiescent voltage output, VOUT(Q), magnetic sensitivity, Sens, and clamp voltage, VCLP(HIGH) and VCLP(LOW), are proportional to the supply voltage, VCC. In other words, when the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same percentage. Error is the difference between the measured change in the supply voltage relative to 5 V, and the measured change in each characteristic. ) VCLP(VCC) / VCLP(5 V) x 100% VCC /5 V where VCLP is either VCLP(HIGH) or VCLP(LOW). Undervoltage Lockout. The A1369 features an undervoltage lockout feature that ensures that the device will output a valid signal when VCC is above certain threshold VUVLOHI, and remains valid until VCC falls below a lower threshold, VUVLOLOW. The undervoltage lockout feature provides a hysteresis of operation to eliminate indeterminate output states. The output of the A1369 is held low (GND) until VCC exceeds VUVLOHI. Once VCC exceeds VUVLOHI, the device powers up, and the output will provide a ratiometric output voltage proportional to the input magnetic signal, and VCC. If VCC should drop back down below VUVLOLOW for more than tuvlo after the device is powered up, the output will be pulled low. VCC VUVLOHI VUVLOLOW VOUT The ratiometric error in quiescent voltage output, RatVOUT(Q) (%), for a given supply voltage, VCC, is defined as: ( RATERRVOUT(Q) = 1 - ) VOUTO(VCC) / VOUTO(5 V) x 100% VCC /5 V Figure 4: UVLO Operation Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 VCC + - 5V 0.1 F A1369 GND VOUT Figure 5: Typical Application Circuit Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switch point accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. Allegro employs a patented technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the dc offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. In addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the hall sensor while completely removing the modulated residue resulting from the chopper operation. The chopper stabilization technique uses a high frequency sampling clock. For demodulation process, a sample and hold technique is used. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with highdensity logic integration and sample-and-hold circuits. Regulator Clock/Logic Hall Element AMP Anti-aliasing Tuned Filter LP-Filter Figure 6: Concept of Chopper Stabilization Technique Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A1369 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications PROGRAMMING GUIDELINES Overview Definition of Terms Programming is accomplished by sending a series of input voltage pulses serially through the VOUT pin of the device. A unique combination of different voltage level pulses controls the internal programming logic of the device to select a desired programmable parameter and change its value. There are three voltage levels that must be taken into account when programming. These levels are referred to as high (VPH), mid (VPM), and low (VPL). Register. The section of the programming logic that controls the choice of programmable modes and parameters. The A1369 features a Try mode, Blow mode, and Read mode: * In Try mode, the value of multiple programmable parameters may be set and measured simultaneously. The parameter values are stored temporarily, and reset after cycling the supply voltage. * In Blow mode, the value of a single programmable parameter may be permanently set by blowing solid-state fuses internal to the device. Additional parameters may be blown sequentially. This mode is used for blowing the device-level fuse, which permanently blocks the further programming of all parameters. Device locking is also accomplished in this mode. * In Read mode, the current state of the programming fuses can be read back for verification of programmed value. The programming sequence is designed to help prevent the device from being programmed accidentally; for example, as a result of noise on the supply line. Although any programmable variable power supply can be used to generate the pulse waveforms, Allegro highly recommends using the Allegro Sensor Evaluation Kit, available on the Allegro Web site On-line Store. The manual for that kit is available for Bit Field. The internal fuses unique to each register, represented as a binary number. Incrementing the bit field of a particular register causes its programmable parameter to change, based on the internal programming logic. Key. A series of mid-level voltage pulses used to select a register, with a value expressed as the decimal equivalent of the binary value. The LSB of a register is denoted as key 1, or bit 0. Code. The number used to identify the combination of fuses activated in a bit field, expressed as the decimal equivalent of the binary value. The LSB of a bit field is denoted as code 1, or bit 0. Addressing. Incrementing the bit field code of a selected register by serially applying a pulse train through the VCC pin of the device. Each parameter can be measured during the addressing process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent. Fuse Blowing. Applying a high voltage pulse of sufficient duration to permanently set an addressed bit by blowing a fuse internal to the device. Once a bit (fuse) has been blown, it cannot be reset. Blow Pulse. A high voltage pulse of sufficient duration to blow the addressed fuse. Cycling the Supply. Powering-down, and then powering-up the supply voltage. Cycling the supply is used to clear the programming settings in Try mode. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 Table 1: Programming Pulse Requirements Part Number Characteristic Symbol Test Conditions Limits Min. Typ. Max. Units VPL 4.5 - 5.5 V VPM 12.5 13 13.5 V VPH 18 18.5 19 V 200 - - m Programming Protocol (TA = +25C) Programming Voltage23 Programming Current24 A1369 IP CBLOW = 0.1 F tLOW 20 - - tACTIVE27 20 - - tBLOW28 90 100 - Pulse Rise Time t29 5 - 100 Pulse Fall Time t30 5 - 100 Blow Pulse Slew Rate SRBLOW 0.375 - - V/s 26 Pulse Width 23Programming voltages are measured at the VOUT pin of the package. supply current available during programming to ensure proper fuse blowing. 25A minimum capacitance, C BLOW, of 0.1 F must be connected from VOUT to GND of the SIP during programming to provide the current necessary to blow a fuse. 26Duration of V time between bits. PL 27V and V PL PH durations required during register selection and bit field addressing sequences. 28Pulse duration required to permanently blow a fuse/ 29Rise time required for programming voltage transitions from V to V PL PM or VPL to VPH. 30Fall time required for programming voltage transitions from V PM to VPL or VPH to VPL. 24Minimum Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 PROGRAMMING PROCEDURES Mode/Parameter Selection Accessible only in READ MODE Each programmable mode/parameter can be accessed through a specific register. To select a register, a sequence of voltage pulses consisting of a VPH pulse, a series of VPM pulses, and a VPH pulse (with no VCC supply interruptions) must be applied serially to the VOUT pin. The number of VPM pulses is called the key, and uniquely identifies each register. The pulse train used for selection of the first register, key 1, is shown in Figure 7. V+ * Register 4: Margin Low Margin Comparator Margin High Overall Lock Bit (LOCK) Try Mode Bitfield Addressing In Try Mode, after a programmable parameter has been selected, a VPH pulse transitions the programming logic into the bitfield addressing state. A series of VPM pulses to the VOUT pin of the device, as shown in Figure 8, increments the bitfield of the selected parameter. VP(HIGH) VP(MID) VP(LOW) tLOW tACTIVE 0 Figure 7: Parameter Selection Pulse Train The A1369 has three registers that select among the three programmable modes: * Register 1: When addressing the bitfield in Try Mode, the number of VPM pulses is represented by a decimal number called a code. Addressing activates the corresponding fuse locations in the given bitfield by incrementing the binary value of an internal DAC. The value of the bit field (and code) increments by one with the falling edge of each VPM pulse, up to the maximum possible code (see the Programming Logic table). As the value of the bitfield code increases, the value of the programmable parameter changes. Measurements can be taken after each pulse to determine if the desired result for the programmable parameter has been reached. Cycling the supply voltage resets all the locations in the bitfield that have unblown fuses to their initial states. V+ * Register 3: READ VP(MID) Code 2n - 1 TRY Code 2 VP(HIGH) Code 1 * Register 2: Code 2n - 2 BLOW/LOCK And three registers that select among the seven programmable parameters: * Register 1: VP(LOW) Sensitivity (SENS) * Register 2: Quiescent Voltage Output (QVO) * Register 3: Temperature compensation at Factory 0 Figure 8: Try Mode Bit Field Addressing Pulse Train Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 Fuse Blowing After the required code is found for a given parameter, its value can be set permanently by blowing individual fuses in the appropriate register bit field. Blowing is accomplished by applying a VPH pulse, called a blow pulse, of sufficient duration at the VPH level to permanently set an addressed bit by blowing a fuse internal to the device. Due to power requirements, the fuse for each bit in the bit field must be blown individually. The A1369 has built in circuitry that will only allow one fuse to be blown at a time. During blow mode, the bit field can be considered a "onehot" shift register. Table 2 illustrates how to relate the number of VPM pulses to the binary and decimal value for Blow Mode bit field addressing. It should be noted that the simple relationship between the number of VPM pulses and the desired code is: 2n = Code where n is the number of VPM pulses, and the bit field has an initial state of decimal code 1 (binary 000000001). To correctly blow the desired fuses, the code representing the desired parameter value must be translated to a binary number. For example, as shown in Figure 9, decimal code 5 is equivalent to the binary number 101. Therefore bit 2 must be addressed and blown, the device power supply cycled, and then bit 0 must be addressed and blown. An appropriate sequence for blowing code 4 is shown in Figure 10. The order of blowing bits, however, is not important. Blowing bit 0 first, and then bit 2 is acceptable. Note: After blowing, the programming is not reversible, even after cycling the supply power. Although a register bitf ield fuse cannot be reset after it is blown, additional bits within the same register can be blown at any time until the device is locked. For example, if bit 1 (binary 10) has been blown, it is still possible to blow bit 0. The end result would be binary 11 (decimal code 3). Bitfield Selection Address Code Format (Decimal Equivalent) Code 5 Code in Binary (Binary) 1 0 1 Fuse Blowing Target Bits Bit 2 Fuse Blowing Address Code Format Bit 0 Code 4 Code 1 (Decimal Equivalents) Figure 9: Example of Code 5 Broken Into Its Binary Components, which are Code 4 and Code 1 Table 2: Blow Mode Bitf ield Addressing # of VPM Pulse (decimal) Binary Register Equivalent Code (2n) 0 000000001 1 1 000000010 2 2 000000100 4 3 000001000 8 4 000010000 16 5 000100000 32 6 001000000 64 7 010000000 128 8 100000000 256 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 Locking the Device * The application capacitance, CL, should be used when measuring the output duty cycle during programming. The blowing capacitor, CBLOW, should be removed during measurement and should only be applied when blowing fuses. After the desired code for each parameter is programmed, the device can be locked to prevent further programming of any parameters. Additional Guidelines * The power supply used for programming must be capable of delivering at least 18 V and 175 mA. The additional guidelines in this section should be followed to ensure the proper behavior of these devices: * Be careful to observe the tLOW delay time before powering down the device after blowing each bit. * A 0.1 F blowing capacitor, CBLOW, must be mounted between the VOUT pin and the GND pin during programming, to ensure enough current is available to blow fuses. The following programming order is required: * Sens * QVO * The CBLOW blowing capacitor must be replaced in the final application with the load capacitor, CL, for proper operation. * LOCK (only after all other parameters have been programmed and validated, because this prevents any further programming of the device) VP(HIGH) VP(MID) 1 1 2 1 2 Mode Selection (Key 1) Parameter Selection (Key 2) Addressing Code 4 (Bit 3) { VP(LOW) tBLOW Cycle VCC 0 Figure 10: Example of Blow Mode Programming Pulses Applied to the VOUT Pin. In this example, Sensitivity (Parameter Key 1) is addressed to blow bit 3. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 PROGRAMMING MODES Try Mode make its value permanent. To do this, select the required parameter register, and address and blow each required bit separately (as described in the Fuse Blowing section). The supply must be cycled between blowing each bit of a given code. After a bit is blown, cycling the supply will not reset its value. Try mode allows multiple programmable parameters to be tested simultaneously without permanently setting any values. In this mode, each high pulse will indefinitely loop the programming logic through the mode, register, and bit field states. There must be no interruptions in the VCC supply. Read Mode After powering the VCC supply, select mode key 1, the desired parameter register, and address its bit field. When addressing the bit field, each VPM pulse increments the value of the parameter register up to the maximum possible code (see Programming Logic section). The addressed parameter value will be stored in the device even after the programming drive voltage is removed from the VOUT pin, allowing its value to be measured. To test an additional programmable parameter in conjunction with the original, enter an additional VPH pulse on the VOUT pin to reenter the parameter selection field. Select a different parameter register, and address its bit field without any supply interruptions. Both parameter values will be stored and can be measured after removing the programming drive voltage. Multiple programming combinations can be tested to achieve optimal application accuracy. See Figure 11 for an example of the Try Mode pulse train. The state of the internal fuses can be read at any time in Read Mode. Read Mode is available before, and after locking the device. Read mode allows the programmer to verify that the intended bits were blown. Registers can be addressed and re-addressed an indefinite number of times in any order. Once the desired code is found for each register, cycle the supply and blow the bit field using blow mode. Note that for accurate time measurements the blow capacitor, CBLOW, should be removed during output voltage measurement. Blow Mode After the required value of the programmable parameter is found using Hold/Try mode, the corresponding code should be blown to After power the VCC supply, select mode key 3, the desired parameter register, and address its bit field. Upon completing the selection of mode key 3, ICC will increase by 250 A to indicate the device is in read fuse mode. On the falling edge of the VPH pulse that terminates the register selection, ICC will increase by another 250 A (total of 500 A above normal ICC) to indicate a fuse is blown, or decrease by 250 A (total of 0 A above nominal ICC) to indicate an un-blown fuse. On each consecutive falling edge of VP\M pulses the A1369 will modify ICC to indicate the state of each fuse (500 A above ICC for a blown fuse, and 0 A above ICC for an un-blown fuse). The read mode indicates the fuse values of the selected register in a serial fashion where one bit is read at a time. The LSB (B0) is selected on the falling edge of the VPH pulse that terminates the key parameter selection, and begins the addressing code. The successive VPM pulses select the succeeding bits in this order: B1, B2, B3, B4, B5, B6, B7, B8. See Figure 12 for an example pulse train. VP(HIGH) VP(MID) 1 2 1 2 1 2 VP(LOW) Mode Selection (Key 2) Parameter Selection (Key 2) Next Parameter Addressing Code 2 (Bit 1) 0 Figure 11: Example of Try Mode Programming Pulses Applied to the VOUT Pin. In this example, Sensitivity (Parameter Key 1) is addressed to code 3 and QVO (Parameter Key 2) is addressed to code 2. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 Mode Selection (Key 3) Parameter Selection (Key 2) Bitfield Addressing VOUT VP(HIGH) VP(MID) VP(LOW) 1 2 3 1 2 0 1 2 3 ... 0 ICC + 500 A ICC ICC + 250 A B0 = 1 B2 = 1 ICC B1 = 0 B2 = 0 Figure 12: Example of Read Mode Programming Pulses Applied to the VOUT Pin and Device Response in ICC. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 PROGRAMMING STATE MACHINE Powerup VPM Initial VPH VPH Mode Select VPM VPM 1 Blow/Lock VPM VPM 2 Try 3 Read 2 x VPH 2 x VPH VPH VPM VPM 1 Sens VPM VPM 2 QVO* 3 TC trim Lock VPH VPH VPH VPH VPM User Power-down Required Selected Mode? Try Key 1-3 Code Select VPM VPM 1 (Bitfield 0) VPM Blow Key 1-4 Try Key 4 Read Key 1-4 VPM 3 (Bitfield 1 and 2) VPM 2n - 1 n = bits in register VPH VPH VPH VPH Blow Fuse 2 (Bitfield 1) Code Select Code 1 (Bitfield 0) 20 VPH VPM VPM Code 2 (Bitfield 1) 21 VPH VPM Code 4 (Bitfield 2) 22 VPH VPM Code 8 (Bitfield 3) 23 VPH VPM Code 2n (Bitfield n) n = bits in register VPH Recommended Repeat Blown Sequence for Final Memory Lock Figure 13: Programming State Machine * QVO parameter needs to be programmed last; otherwise, next high pulse will lead to unwanted output polarity change. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A1369 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications Initial State * 3 pulses - Factory use only After system power-up, the programming logic is reset to a known state. This is referred to as the Initial state. All the bit field locations that have intact fuses are set to logic 0. While in the Initial state, any VPM pulses on the VOUT pin are ignored. To enter the Mode Selection state, apply a single VPH pulse on VOUT pin.. * 4 pulses - Margin Low, Margin comp, margin high, Lock All Mode Selection State This state allows the selection of the mode register containing the parameter to be programmed. To select a mode register, increment through the keys by sending VPM pulses on the VOUT pin. Register keys select among the following programmable modes: * 1 pulses -Blow/Lock * 2 pulses - Try * 3 pulses - Read To enter the Parameter Selection state, apply 2 VPH pulses on VOUT pin. Parameter Selection State This state allows the selection of the parameter register containing the bit fields to be programmed. Applying a VPM pulse to the VOUT pin will increment through the parameter registers. * 1 pulse - Sensitivity * 2 pulses - QVO, Polarity To enter the Bit Field Addressing state, send one VPH pulse on the VOUT pin. Bitfield Addressing State This state allows the selection of the individual bit fields to be programmed in the selected parameter register (see Programming Logic table). Applying VPM pulses to the VOUT pin increments the bitfield. In Try Mode, to re-enter the Parameter Selection state send one VPH pulse on the VOUT pin. The previously addressed parameter will retain its value as long as VCC is not cycled. In Blow/Lock Mode, to leave the Bit Field Addressing state requires either cycle device power or blowing the fuses for the selected code. Note that merely addressing the bit field does not permanently set the value of the selected programming parameter; fuses must be blown to do so. In blow mode, only one bit is active at a time. Fuse Blowing State To blow an addressed bit field, apply a VPH pulse on the VOUT pin. Power to the device should then be cycled before additional programming is attempted. Note: Each bit representing a decimal code must be blown individually (see the Fuse Blowing section). Final memory lock will be executed in two steps: 1. Blowing the "Lock All" bit 2. Repeating the programming blow sequence for any bit of choice. This sequence will not blow that bit; rather, it will blow the final memory fuse. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 Table 3: Programming Logic16 Programmable Mode (Register Key) Bitfield Address Description Binary Format [MSB LSB] Decimal Equivalent Code Blow/Lock (1) 01 1 Try (2) 10 2 Try Read (3) 11 3 Read Registry Selection Key Binary Bitfield Address [MSB LSB] Decimal Equivalent Code Description 0000000 0 Initial value; Sens = SensPRE 0011111 31 Maximum Sensitivity 0111111 63 Minimum Sensitivity value in range 1000000 N/A For factory use only. Do not program this bit. Sensitivity (1) Blow Lock 0000000 0 Initial value 0001111 15 Maximum QVO 0010000 31 Minimum QVO 0100000 32 Disable Output Clamp Reserved (3) 0000000 0 For factory use only. Programming:Sens coarse, Sensitivity TC and QVO TC 000000001 1 Margin 10k Fuse Margin Lock (4) 000000010 2 Margin comparator 000000100 4 Margin 150k 100000000 256 Lock Device QVO, Clamp Disable (2) 16Programming is accomplished through the VOUT pin. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 PACKAGE OUTLINE DRAWING For Reference Only - Not for Tooling Use (Reference DWG-9065) Dimensions in millimeters - NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 2 X 45 B 4.09 +0.08 -0.05 1.52 0.05 E 2.04 C 3 X 10 1.44 E 3.02 E Mold Ejector Pin Indent +0.08 -0.05 45 Branded Face 1.02 MAX 1.02 MAX A 0.79 REF 1 2 3 0.43 +0.05 -0.07 0.41 +0.03 -0.06 1.27 NOM NNN 14.99 0.25 1 D Standard Branding Reference View = Supplier emblem N = Last three digits of device part number A Dambar removal protrusion (6X) B Gate and tie bar burr area C Active Area Depth, 0.50 mm REF D Branding scale and appearance at supplier discretion E Hall element, not to scale Figure 14: Package UA, 3-Pin SIP Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 Customer Programmable Linear Hall-Effect Sensor Optimized for Use in Current Sensing Applications A1369 Revision History Revision Revision Date - November 18, 2014 Description of Revision Initial Release Copyright (c)2014, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22