HOP1,2,3
HON1,2,3
LOP1,2,3
LON1,2,3BR
VS1,2,3
VB1,2,3
LS1,2,3
COM
LIN1,2,3
HIN1,2,3
FAULT
FLTCLR
ITRIP
VCC
VSS
BRIN
SD
DESAT1,2,3
3
uP,Control
Current Feedback
15V
DC
BUS 2137/
2237 U
V
WMotor
GND
HSSD1,2,3
LSSD1,2,3
3
3
Typical Connection
3-PHASE BRIDGE DRIVER
Packages
Features
• Floating channel up to +600V or +1200V
• “soft” over-current shutdown turns off all six
outputs
• Integrated high side desaturation circuit
• Controlled “soft” turn on for EMI reduction
• Integrated brake IGBT driver
• Three independent low side COM pins
• Separate pull-up/pull-down output drive pins
• Matched delay outputs
• 3.3V logic compatible
• Under voltage lockout with hysteresis band
Description
Product Summary
VOFFSET 600V max. or 1200V max.
IO+/- 220mA / 460mA
VOUT 12.5V - 20V
Brake Io+/- 40mA/80mA
Matched delay 75nsec
Deadtime (typ.) 300 nsec
DESAT Blanking time (typ.) 2.0usec
DESAT input voltage
threshold (typ.) Vt+ = 5.0V
64-Lead MQFP 68-Lead PLCC
www.irf.com 1
The IR2137/IR2237(J)(Q) are a high voltage, high
speed 3-phase IGBT driver best suited for AC motor
drive applications. Integrated desaturation logic pro-
vides ground fault protection as well as other mode of
over current protection. Soft shutdown is initiated in
the event of any overcurrent/ground fault conditions,
and all six outputs are simultaneously turned off. Out-
put drivers have separate turn on/off pins to facilitate
independent gate drive impedance with EMI soft turn
on. Optimum matched delays between phases, and
between high/low side enables small deadtime, thus
improving low speed performance. The brake driver
eliminates additional circuits.
IR2137/IR2237(J)(Q)
Data Sheet No. PD60170-G
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
2www.irf.com
IR2137/IR2237(J)(Q)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.
Symbol Definition Min. Max. Units
VS1,2,3 High side offset voltage VB1,2,3 -25 VB1,2,3 +0.3
VB1,2,3 High side floating supply voltage (IR2137) -0.3 625
(IR2237) -0.3 1225
VHO High side floating output voltage (HOP, HON, HSSD) VS1,2,3 - 0.3 VB1,2,3 + 0.3
VCC Low side and logic fixed supply voltage -0.3 25
VSS Logic ground VCC - 25 VCC + 0.3
VLO1,2,3 Low side output voltage (LOP, LON, LSSD) VLS1,2,3 -0.3 VCC + 0.3
VIN Logic input voltage (HIN, LIN,SD, ITRIP, FLTCLR, BRIN)VSS - 0.3 (VSS + 15) or
(VCC + 0.3)
which ever is
lower
VFLT FAULT output voltage VSS - 0.3 VCC + 0.3
VDESAT DESAT input voltage VS1,2,3 - 0.3 VB1,2,3 + 0.3
VBR BRAKE output voltage - 0.3 VCC + 0.3
VLS1,2,3 Low side output return voltage VCC - 25 VCC + 0.3
dV/dt Allowable offset supply voltage slew rate —50 V/ns
PDPackage power dissipation @ TA ≤ +25°C (MQFP64) —2.0
(PLCC68) 3.0
RthJA Thermal resistance, junction to ambient (MQFP64) —60
(PLCC68) —40
TJJunction temperature —150
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) —300
°C/W
W
V
°C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recom-
mended conditions. All voltage parameters are absolute voltages referenced to COM. The VS offset rating is tested with all
supplies biased at 15V differential.
VB1,2,3 High side floating supply voltage VS1,2,3 + 13 VS1,2,3 + 20
VS1,2,3 High side floating supply offset voltage (IR2137) Note 1 600
(IR2237) Note 1 1200
VHO1,2,3 High side output voltage (HOP, HON, HSSD) VS1,2,3 VS1,2,3 + 20
VLO1,2,3 Low side output voltage (LOP, LON, LSSD) VLS1,2,3 VCC
VCC Low side and logic fixed supply voltage 12.5 20
VSS Logic ground -5 +5
VIN Logic input voltage (HIN, LIN,SD, ITRIP, FLTCLR, BRIN)VSS VSS + 5
VBR BRAKE output voltage 0VCC
Symbol Definition Min. Max. Units
V
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IR2137/IR2237(J)(Q)
Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15V and TA = 25oC unless otherwise specified. The VIN, VTH and IIN parameters are
referenced to VSS/COM and are applicable to all six channels (HOP/HON1,2,3 and LOP/LON1,2,3). The VO and IO
parameters are referenced to VLS1,2,3 and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and
LO1,2,3. VDESAT and IDESAT parameters are referenced to VS1,2,3
Symbol Definition Min. Typ. Max. Units Test Conditions
VCCUV+VCC supply undervoltage positive going threshold 10.3 11.4 12.5
VCCUV- VCC supply undervoltage negative going threshold 9.5 10.4 11.3
VCCUVH VCC supply undervoltage lockout hysteresis —1.0 —
VBSUV+ VBS supply undervoltage positive going threshold 10.3 11.4 12.5
VBSUV- VBS supply undervoltage negative going threshold 9.5 10.4 11.3
VBSUVH VBS supply undervoltage lockout hysteresis —1.0 —
ILK Offset supply leakage current — — 50
(IR2137)
(IR2237) — — 50
IQBS Quiescent VBS supply current —120 200
IQCC Quiescent VCC supply current —2 6 mA
VIH Logic “0” input voltage (OUT=LO) 3.15 — —
(HIN,LIN,ITRIP,SD,BRIN,FLTCLR)
VIL Logic “1” input voltage (OUT=HI) — — 0.8
(HIN,LIN,ITRIP,SD,BRIN,FLTCLR)
Vt+Logic input positive going threshold 1.6 2.5 3.1
(HIN,LIN,ITRIP,SD,BRIN,FLTCLR)
Vt-Logic input negative going threshold 0.9 1.5 2.4
(HIN,LIN,ITRIP,SD,BRIN,FLTCLR)
VTLogic input hysteresis 0.7 1.0 —
(HIN,LIN,ITRIP,SD,BRIN,FLTCLR)
V
VB1,2,3 = VS1,2,3
= 600V
VB1,2,3 = VS1,2,3
= 1200V
V
VCC = 12.5 to 20V
µA
Note 1: Logic operational for VS of COM -5 to COM +600V/+1200V. Logic state held for VS of COM -5V to -COM VBS.
Note 2: All input pins are internally clamped with a 5.2V zener diode.
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recom-
mended conditions. All voltage parameters are absolute voltages referenced to COM. The VS offset rating is tested with all
supplies biased at 15V differential.
VFLT FAULT output voltage VSS VCC
VLS1,2,3 Low side output return voltage -5.0 +5.0
VDESAT DESAT pin input voltage VS1,2,3 VB1,2,3
TAAmbient temperature -40 125 °C
Symbol Definition Min. Max. Units
V
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IR2137/IR2237(J)(Q)
Static Electrical Characteristics - cont.
VBIAS (VCC, VBS1,2,3) = 15V and TA = 25oC unless otherwise specified. The VIN, VTH and IIN parameters are
referenced to VSS/COM and are applicable to all six channels (HOP/HON1,2,3 and LOP/LON1,2,3). The VO and IO
parameters are referenced to VLS1,2,3 and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and
LO1,2,3. VDESAT and IDESAT parameters are referenced to VS1,2,3
VOH High level output voltage, VBIAS - VO— — 100
(normal switching) HOP, LOP
VOL Low level output voltage, VO— — 100
(normal switching) HON, LON
IIN+ Logic “1” input bias current —150 —VIN = 0V
IIN-Logic “0” input bias current —80 —VIN = 5V
IDESAT+“high” DESAT input bias current — — 15 VDESAT = 15V
IDESAT-“low” DESAT input bias current — — .1 VDESAT = 0V
IO+Output high short circuit pulsed current 220 300 —VO = 0V, VIN = 0V
PW ≤ 10 µs
IO-Output low short circuit pulsed current 460 550 —VO = 15V, VIN = 5V
PW ≤ 10 µs
IOBR+BR output high short circuit pulsed current 40 75 —VBR=0V, VBRIN=0V
PW ≤ 10 µs
IOBR-BR output low short circuit pulsed current 80 120 —VBR=15V,VBRIN=5V
PW ≤ 10 µs
VOHB BR high level output voltage, VBIAS-VBR — — 300
VOLB BR low level output voltage, VBR — — 150
RON,SS Soft shutdown on resistance —500 —ITRIP = 0V
RON,FLT FAULT low on resistance —60 —
VDESAT+High DESAT input threshold voltage —5.2 —V
Symbol Definition Min. Typ. Max. Units Test Conditions
Ω
mA
mV IBR = 1mA
IO = 1 mA
µA
mV
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IR2137/IR2237(J)(Q)
AC Electrical Characteristics
VBIAS (VCC, VBS) = 15V, VS1,2,3 = VSS, TA = 25oC and CL = 1000 pF unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
ton Turn-on propagation delay 150 400 600
toff Turn-off propagation delay 150 400 600
trTurn-on rise time —115 —
tfTurn-off fall time —25 —
tITRIP ITRIP to output shutdown propagation delay —1000 1400 VIN,VDESAT=0
VSD = 5V
tSD SD to output shutdown propagation delay —1200 1500 VIN,VDESAT = 0
VITRIP = 5V, fig. 7
tDESAT1 DESAT to output shutdown propagation delay 1400 2800 4200 ITRIP = 5V
at HOPx turn-on
tDESAT2 DESAT to output shutdown propagation delay 600 1150 1700
after blanking
tFLT, IT ITRIP to FAULT output delay —800 1100
tFLTCLR FLTCLR to FAULT output delay —1100 1400 VSD = 5V,
VDESAT = 0V, fig. 7
tFLT,DESAT1 DESAT to FAULT output delay propagation delay —2500 —
at HOPx turn-on
tFLT,DESAT2 DESAT to FAULT output delay propagation delay —850 —
after blanking
tBL DESAT blanking time at turn-on —2000 —
tonBR BR output turn-on propagation delay —120 200
toffBR BR output turn-off propagation delay —85 150
trBR BR output turn-on rise time —300 —
tfBR BR output turn-off fall time —150 —
DT Deadtime —300 —Figure 6
MDT Matching delay, max (ton,toff) - min (ton,toff), —075 External dead time
(ton,toff are applicable to all six channels) >400nsec
PM Output pulse width matching, IPWin - PWoutl —075 External dead time
(exclude BRIN/BR) >400nsec, Fig. 4
VIN = 0 & 5V
VS1,2,3 = 0 to 600V
or 1200V
HOP=HON,LOP=LON
Figure 4
VS1,2,3 = 0 to 600V
or 1200V
VHIN = 0V,
VSD, VITRIP = 5V,
VDESAT = 15V, fig. 5
VIN,VITRIP =0V,
VSD = 5V,
VDESAT= 0V, fig. 7
VS1,2,3 = 0 to 600V
or 1200V
VIN = 0V,
VSD, VITRIP = 5V,
VDESAT = 15V,
Figure 5
Figure 4
ns
ns
Deadtime/Delay Matching Characteristics
Propagation Delay Characteristics
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IR2137/IR2237(J)(Q)
Functional Block Diagram
SCHMITT
TRIGGER INPUT
&
SHOOT
THROUGH
PREVENTION
FAULT
LOGIC
SCHMITT
TRIGGER
INPUT &
SHOOT
THROUGH
PREVENTION
SCHMITT
TRIGGER INPUT
&
SHOOT
THROUGH
PREVENTION
200nsec
Deadtime
200nsec
Deadtime
200nsec
Deadtime
LEVEL
SHIFTERS
LEVEL
SHIFTERS
LEVEL
SHIFTERS
LATCH
SOFT
SHUTDOWN
DESAT
DETECTION
UV DETECT
UV
DETECT
HIN1
HIN2
HIN3
SOFT SHUTDOWN
SOFT SHUTDOWN
SOFT SHUTDOWN
SOFT
SHUTDOWN
SOFT
SHUTDOWN
SOFT
SHUTDOWN
SCHMITT
TRIGGER
ITRIP
SD
FLTCLR
FAULT
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
LOP1
LON1
LON2
LOP2
LOP3
LON3
COM
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
HOP3
HON3
VS3
VB3
VB2
HOP2
HON2
VS2
VB1
HOP1
HON1
VS1
VCC
VSS
SCHMITT
TRIGGER
BRAKE
DRIVER BR
BRIN
LS1
LS2
LS3
DESAT1
DESAT
LATCH
SOFT
SHUTDOWN
DESAT
DETECTION
UV DETECT
LATCH
SOFT
SHUTDOWN
DESAT
DETECTION
UV DETECT
DESAT2
DESAT3
DESAT
DESAT
HSSD1
HSSD2
HSSD3
LSSD1
LSSD2
LSSD3
SCHMITT
TRIGGER
SOFT SHUTDOWN
VSS/LS3
LEVEL
SHIFTER
VSS/LS2
LEVEL
SHIFTER
VSS/LS1
LEVEL
SHIFTER
www.irf.com 7
IR2137/IR2237(J)(Q)
Lead Definitions
Symbol Description
VCC Low side and logic supply voltage
VSS Logic Ground
HIN1,2,3 Logic inputs for high side gate driver outputs (HOP1,2,3/HON1,2,3, out of phase)
LIN1,2,3 Logic inputs for low side gate driver outputs (LOP1,2,3/LON1,2,3, out of phase)
SD Logic input for shutdown (hard shutdown, level sensitive signal, negative logic)
ITRIP Logic input for overcurrent shutdown (soft shutdown, edge sensitive, negative signal)
FLTCLR Logic input for FAULT clear (edge sensitive, negative signal)
BRIN Logic input for brake driver, out of phase with BR
FAULT Fault output indicates over current and desaturation shutdown (open drain)
BR Brake driver output
COM Brake driver return
VB1,2,3 High side gate drive floating supply
HOP1,2,3 High side driver pull up output
HON1,2,3 High side driver pull down output
HSSD1,2,3 High side soft shutdown output
DESAT1,2,3 IGBT desaturation protection input
VS1,2,3 High voltage floating supply return
LOP1,2,3 Low side driver pull up output
LON1,2,3 Low side driver pull down output
LSSD1,2,3 Low side soft shutdown output
LS1,2,3 Low side driver returns
Driver Output Circuit Block Diagram
PRE
DRIVER
350nsec
Filter
2usec
Blanking
VB
HOP
LOP
DESAT
VS
Soft Shutdown
Impedence =
500 ohms
Soft Shutdown
SSD
Desat Fault
High Side Gate
600nsec
Filter
8www.irf.com
IR2137/IR2237(J)(Q)
Figure 3. Timing Diagram
HIN1,2,3
LIN1,2,3
SD
ITRIP
DESAT
FAULT
FLTCLR
HO(HOP/HON)
LO(LOP/LON)
64 Lead MQFP 68 Lead PLCC
IR2137Q/ IR2237Q IR2137J/IR2237J
Lead Assignments
VCC
VB1
HOP1
HON1
DESAT1
VS1
VB2
HOP2
HON2
DESAT2
VS2
VB3
HOP3
HON3
DESAT3
VS3
HIN1
LIN1
HIN2
LIN2
LIN3
HIN3
SD
FAULT
FLTCLR
ITRIP
BRIN
VSS
COM
LS3
LS2
LS1
LON3
LOP3
LON2
LOP2
LON1
LOP1
BR
LSSD1
LSSD2
LSSD2
HSSD1
HSSD2
HSSD3
PLCC68
1 68
MQFP64
www.irf.com 9
IR2137/IR2237(J)(Q)
Figure 4. Switching Time Waveforms
HIN
LIN
HO (HOP=HON)
LO (LOP=LON)
t
on
t
r
50%
90%
10%
50%
90%
10%
t
off
t
f
BRIN
BR
5V
PW
in
PW
out
Figure 5. DESAT Timing
HIN1,2,3
LIN1,2,3
SD
ITRIP
DESAT
FAULT
FLTCLR
HO(HOP/HON)
LO(LOP/LON)
>2.0usec
(typ)
t
DESAT1
t
DESAT2
t
FLT,DESAT2
t
FLT,DESAT1
SOFT SHUTDOWN SOFT SHUTDOWN
6V
50% 90%
50%
50%
50%
90%
6V
t
BL
t
BL
Blanking
in effect Blanking
in effect 5V
5V
5V
5V
5V
15V
10 www.irf.com
IR2137/IR2237(J)(Q)
Figure 7. SD, ITRIP Timing
SD
ITRIP
HO
LO
50%
50%
90%
t
SD
FAULT
FLTCLR
t
FLT,ITRIP
90%
t
FLTCLR
50%
10%
t
ITRIP
90%
5V
5V
5V
Figure 6. Internal Deadtime Timing
HIN
LIN
HO (HOP=HON)
LO (LOP=LON) DT DT
50% 50%
50%
50% 50%
50%
www.irf.com 11
IR2137/IR2237(J)(Q)
Case outlines
01-6054 00
01-2023 01 MS-022GA-2
64-Lead MQFP
12 www.irf.com
IR2137/IR2237(J)(Q)
01-6055 00
01-3068 01 (MS-018AC)
68-Lead PLCC
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 1/28/2002