www.irf.com 110/30/03
IRF7805Z
HEXFET® Power MOSFET
Notes through are on page 10
Benefits
lVery Low RDS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
Top View
8
1
2
3
45
6
7
D
D
D
DG
S
A
S
S
A
SO-8
VDSS RDS(on) max Qg (typ.)
30V 6.8m:@VGS = 10V 18nC
Applications
lHigh Frequency Point-of-Load
Synchronous Buck Converter for
Applications in Networking &
Computing Systems.
Absolute Maximum Rat ings
Parameter Units
VDS Drain-to-Sourc e V ol tage V
VGS Gate-to-Source Voltage
ID @ TA = 25°C Continuous Drai n Current , VGS @ 10V
ID @ TA = 70°C Continuous Drai n Current , VGS @ 10V A
IDM Pulsed Drai n Current
c
PD @TA = 25°C Power Dissipation
f
W
PD @TA = 70°C Power Dissipation
f
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Storage Temperat ure Range
Thermal Resistance Parameter Typ. Max. Units
RθJL Junct i on-t o-Drai n Lead
g
––– 20 °C/W
RθJA Junction-to-Ambient
fg
––– 50
Max.
16
12
120
± 20
30
-55 to + 150
2.5
0.02
1.6
PD - 94635A
IRF7805Z
2www.irf.com
Static @ TJ = 25°C ( unl ess otherwise specif i ed)
Parameter Min. Typ. Max. Units
BVDSS Drain-to-S ource Breakdown Vol tage 30 ––– ––– V
∆ΒVDSS
/
TJ Breakdown Voltage Temp. Coeffici ent ––– 0.023 ––– V/°C
RDS(on) Static Drai n-t o -S ource On-Resistance ––– 5. 5 6.8 m
––– 7.0 8.7
VGS(th) Gate Threshol d V ol tage 1.35 ––– 2.25 V
VGS(th) Gate Threshol d V ol tage Coeffic i ent ––– - 4.7 ––– mV/°C
IDSS Drain-to-S ource Leakage Current ––– ––– 1.0 µA
––– ––– 150
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leak age ––– ––– -100
gfs Forward Transconductance 64 ––– ––– S
QgTotal Gate Charge ––– 18 27
Qgs1 Pre-Vth Gate-t o-Source Charge ––– 4. 7 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 1. 6 ––– nC
Qgd Gate-to-Drain Charge ––– 6. 2 –––
Qgodr Gate Charge Overdriv e ––– 5. 5 ––– See Fig. 16
Qsw Switc h Charge (Q gs2 + Qgd)––– 7.8 –––
Qoss Output Charge ––– 10 ––– nC
td(on) Turn-On Delay Time ––– 11 –––
trRise Time ––– 10 –––
td(off) Turn-Off Del ay Ti m e ––– 14 ––– ns
tfFall Time ––– 3. 7 –––
Ciss Input Capacit ance ––– 2080 –––
Coss Output Capacit ance ––– 480 ––– pF
Crss Reverse Transfer Capacitance ––– 220 –––
Avalanche Characterist i cs
Parameter Units
EAS Single Pul se Avalanche Energy
d
mJ
IAR Avalanche Current
c
A
Diode Characterist i cs
Parameter Min. Typ. Max. Units
ISContinuous S ource Current ––– ––– 3. 1
(Body Diode) A
ISM Pulsed S ource Current ––– ––– 120
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– 1. 0 V
trr Reverse Rec overy Time ––– 29 44 ns
Qrr Reverse Rec overy Charge ––– 20 30 nC
ton Forward Turn-On Time Intrinsic t urn-on t i me is negligible (t urn-on is dominated by LS+LD)
–––
ID = 12A
VGS = 0V
VDS = 15V
VGS = 4.5V, I D = 13A
e
VGS = 4.5V
Typ.
–––
VDS = VGS, ID = 250µA
Clamped Induc tive Load
VDS = 15V, I D = 12A
VDS = 24V, VGS = 0V, TJ = 125°C
TJ = 25°C, IF = 12A, V DD = 15V
di/dt = 100A/µs
e
TJ = 25°C, IS = 12A, V GS = 0V
e
showing the
integral rev erse
p-n juncti on di ode.
MOSFET symbol
VDS = 16V, VGS = 0V
VDD = 15V, VGS = 4. 5V
e
ID = 12A
VDS = 15V
VGS = 20V
VGS = -20V
VDS = 24V, VGS = 0V
Conditions
VGS = 0V, ID = 250µA
Reference t o 25° C, ID = 1mA
VGS = 10V, ID = 16A
e
Conditions
Max.
72
12
ƒ = 1.0MHz
IRF7805Z
www.irf.com 3
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
2.5 3.0 3.5 4.0 4.5
VGS, Gat e-t o-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 150°C
VDS = 15V
20µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 16A
VGS = 10V
0.01 0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
2.5V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 15V
10V
4.5V
3.75V
3.25V
3.0V
2.75V
BOTTOM 2.5V
0.01 0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
2.5V
20µs PULSE WIDTH
Tj = 150°C
VGS
TOP 15V
10V
4.5V
3.75V
3.25V
3.0V
2.75V
BOTTOM 2.5V
IRF7805Z
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 10203040
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
VGS, Gate-to-Source Voltage (V)
VDS= 24V
VDS= 15V
ID= 12A
0.2 0.4 0.6 0.8 1.0 1.2
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 150°C
VGS = 0V
1.0 10.0 100.0
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATIO N IN THIS AREA
LIMITED BY RDS(on)
100µsec
IRF7805Z
www.irf.com 5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current Vs.
Case Temperature Fig 10. Threshold Voltage Vs. Temperature
25 50 75 100 125 150
TJ , Junction Temperature (°C)
0
4
8
12
16
ID , Drain Current (A)
-75 -50 -25 025 50 75 100 125 150
TJ , Temperature ( °C )
1.0
1.2
1.4
1.6
1.8
2.0
2.2
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1E-006 1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rect angular Pulse Durati on (sec)
0.001
0.01
0.1
1
10
100
Thermal Response ( Z thJA )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGL E PU LSE
( THERM AL R ESPO N SE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
τJ
τJ
τ1
τ1τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci i/Ri
Ci= τi/Ri
τ
τC
τ4
τ4
R4
R4Ri (°C/W) τi (sec)
1.081 0.000437
12.880 0.213428
24.191 2.335
11.862 52
IRF7805Z
6www.irf.com
Fig 13c. Maximum Avalanche Energy
Vs. Drain Current
25 50 75 100 125 150
Starting TJ, Junct i on Tem perat ure (° C)
0
50
100
150
200
250
300
EAS, Single Pulse Avalanche Energy (mJ)
ID
TOP 6.0A
6.9A
BOTTOM 12A
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
Fig 13b. Unclamped Inductive Waveforms
Fig 13a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 12. On-Resistance Vs. Gate Voltage
2.0 4.0 6.0 8.0 10.0
VGS, Gat e-t o-Source Voltage (V)
0.00
0.01
0.02
0.03
RDS(on), Drain-to -Source On Resistance ()
TJ = 25°C
TJ = 125°C
IRF7805Z
www.irf.com 7
D.U.T. VDS
ID
IG
3mA
VGS
.3µF
50K
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 16. Gate Charge Test Circuit
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Fig 17. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRF7805Z
8www.irf.com
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms 2×Rds(on)
()
+I×Qgd
ig
×Vin ×f
+I×Qgs2
ig
×Vin ×f
+Qg×Vg×f
()
+Qoss
2×Vin ×f
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
+Qrr ×Vin ×f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
IRF7805Z
www.irf.com 9
SO-8 Package Details
SO-8 Part Marking
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
.013
.050 BAS IC
.0532
.0040
.2284
.0099
.016
.1968
.1574
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
1.27 BAS IC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX
MIL L IME T E R SINCHES
MIN MAX
DIM
e
c .0075 .0098 0.19 0.25
.025 BAS IC 0.635 BAS IC
87
5
65
D B
E
A
e
6X
H
0.25 [.010] A
6
7
K x 45°
8X L 8X c
y
0.25 [.010] CAB
e1 A
A1
8X b
C
0.10 [.004]
4312
F OOT P R I NT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050]
4. OUT LINE CONFORMS T O JEDEC OUT LINE MS -012AA.
NOT ES :
1. DIMENSIONING & T OLERANCING PER AS ME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENS IONS ARE S HOWN IN MILLIME T E RS [INCHES ].
5 DIMENS ION DOE S NOT INCL UDE MOLD PROT RUS IONS .
6 DIMENS ION DOE S NOT INCL UDE MOLD PROT RUS IONS .
MOL D PROT RUS IONS NOT T O EXCEED 0.25 [.010].
7 DIMENS ION IS T HE LENGT H OF LEAD F OR S OL DERING T O
A S U B S T R AT E .
MOL D PROT RUS IONS NOT T O EXCEED 0.15 [.006].
8X 1.78 [.070]
EXAMPLE: THIS IS AN IRF7101 (MOSFET)
INTERNATIONAL
RECTIFIER
LOGO
F7101
YWW
XXXX
PART NUMBER
LOT CODE
WW = WEEK
Y = LAS T DIGIT OF T HE YEAR
DAT E CODE (YWW)
IRF7805Z
10 www.irf.com
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.94mH
RG = 25, IAS = 12A.
Pulse width 400µs; duty cycle 2%.
When mounted on 1 inch square copper board
Rθ is measured at TJ approximately 90°C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.10/03
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLI NG D IME NS I O N : MILLIME TE R.
2. ALL DIMENSIONS ARE SHOWN IN MILLI MET E RS(I NCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
SO-8 Tape and Reel