Differential PECL Series
Differential PECL Output, Some with Enable/ Disable Function
Standard Specifications
Overall Frequency Stability
Operating Temperature Range 0 to +80°C is standard, but can be extended to
Storage Temperature Range - 55 to +125°C - 40 to +85°C
Mechanical: See Next Pages
Supply Voltage (Vcc) 3.3 volts ± 5% standard, but 5.0 volts or 2.5 volts also available. See Test Cirucit 5.
E/D Internal Pullup 50 kohm minimum to Vcc
All other models Output Enable/Disable (E/D)
Output Enable Time
Output Disable Time
When Disabled
Output Symmetry 45/55% referenced to 50% of amplitude
Output Rise & Fall (Tr & Tf) 1.0 nS maximum when Vth is 10% and 90% of waveform
< 250 MHz = 90 mA maximum, 250 MHz and above = 100 mA maximum
Supply Current (Icc)
2.275 V minimum referenced to Ground, Vcc = 3.300V,
0.975 V minimum referenced to termination voltage,
- 1.025 V minimum referenced to Vcc
Output High Level
1.680 V maximum referenced to Ground, Vcc = 3.300V,
0.380 V maximum referenced to termination voltage,
- 1.620 V maximum referenced to Vcc
Output Low Level
1 pS RMS maximum measured from 12 kHz to 20 MHz from Fnominal
Jitter
V enable 0.7 Vcc minumum referenced to Ground
0.3 Vcc maximum referenced to Ground
V disable
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com 1
Pl tronics, Inc.
100 nS maximum
100 nS maximumOutput Disable Time Q Output = Logic Low, QN Output = Logic High. Both Outputs are active
PE7745D only Output Enable / Disable
± 50 PPM, ± 25 PPM, ± 20 PPM over Operating Temperature Range
Available in 9 Different Package/Configurations, See Next Pages
D Package J Package Replacement B Package M Package
Note 1:
Pl tronics, Inc.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
.
PECL, LVDS, OCXO
Page 1 - 7
Mar 2004
PECL and ECL are identical circuits.
ECL has the most positive pin as ground and is ideally terminated by 50 ohms to - 2.00 V
PECL has the most negative pin as ground and is ideally terminated by 50 ohms to the most (positive voltage less 2.00 V)
Output Enable Time 200 nS maximum at output enable or 1 mS maximum at output enabled and stable
High Level Input Current
Low Level Input Current -20 uA maximum at Enable / Disable Pin = 0.7 Vcc
-200 uA maximum at Enable / Disable Pin = 0 V
200 nS maximum at output disable
Output Disable Time
Vcc Supply Current disabled < 1 mA. Both outputs are high impedance when disabled.
Mechanical: not to scale Solder Padsinches (mm)
Mar 2004
Due to part size and factory abilities, part marking may vary from lot to lot and may contain our part number or an internal code.
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
2A Pl tronics, Inc.
6 Pad 'B Pkg' PECL Series
Differential PECL Output with Enable/ Disable Function
10.00 MHz – 650.00 MHz
6 Pad 14x10x3mm Leadless Surface Mount Clock Oscillator
Pl tronics, Inc.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
.
Consult factory for available frequencies and specs. Not all options available for all frequencies. A special part number may be assigned.
Part Numbering Guide
Frequency Stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration and load
Packaging
Tube or
24mm tape,
16mm pitch
Portions of the part number that appear after the frequency may not be marked on part (C of C provided)
0.055
(1.4)
0.200 (5.08)
1 3
4
2
5
6
0.228 (5.8)
0.118
(3.0)
0 .145
(3.68)
0.400 (10.16) MAX
0.560 (14.23) MAX 0.125 (3.17)
MAX 0.200 (5.08)
12
3
4 5 6
PIN SIGNAL 1 N.C.
2 E/D
3 GND
4 Q OUT
5 QN OUT
6 Vcc
1 N.C.
2 E/D
3 GND
4 Q OUT
5 QN OUT
6 Vcc
PIN SIGNAL 1 E/D
2 N.C.
3 GND
4 Q OUT
5 QN OUT
6 Vcc
PIN SIGNAL
1 QN OUT
2 E/D
3 GND
4 Q OUT
5 N.C.
6 Vcc
PIN SIGNAL
PE1145T PE1145B PE3345B PE3745B
Model Series
Frequency Stability
45 = ± 50 PPM
44 = ± 25 PPM
Frequency in MHz
Special Specifications (choose all that apply)
E: Extended Operating Temperature Range (- 40 to +85 C)
F: 47.5 /52.5% Symmetry at 50% of Vcc
V: Supply Voltage of 3.3 volts ± 10%
W: Supply Voltage of 2.5 volts ± 5%
Y: Supply Voltage of 5.0 volts ± 10%
PE11 45 B V - 70.0M - XXX (Internal Code or blank)
°
20 = ± 20 PPM
PE1145B = E/D on pin2, QN on pin 1
PE3345B = E/D on pin 2, QN on pin 5
PE3745B = E/D on pin 1, QN on pin 5
10.0 MHz to 170 MHz
PE1145T = E/D on pin2
110.0 MHz to 650 MHz
10.0 MHz to 170.0 MHz
110.0 MHz to
650.0 MHz
PE1145T, PE1145B, PE3345B, PE3745B
See page 6 for Layout Guidelines
PECL, LVDS, OCXO
Page 1 - 7
Mar 2004
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com 6
Pl tronics, Inc.
PECL and LVDS Layout Guidelines
Pl tronics, Inc.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
.
TOP SIDE
BYPASS
BOTTOM
SIDE
BYPASS
MULTI
LAYER
BYPASS
0.055
(1.4) 0.100
(2.54)
0.200 (5.08)
0 .185
(4.7)
0 .087
(2.2)
Solder Pad Layout which
accommodates all PECL surface mount
devices
'B Pkg'
5 x7
SUGGESTED PCB LAYOUTS
The output line should be designed with proper characteristic
impedance. Pletronics recommends laying out for the larger
'B package' with pads long enough to accept the smaller
5 x 7mm device. This permits the best option for alternate
sources of device. Pletronics also recommends connecting
Pin 1 and Pin 2 together on the models with
Q & QN OUT on pins 4 & 5. This allows
having E/D on either pin 1 or pin 2.
For Optimum Jitter Performance, Pletronics recommends:
A ground plane under the device with any other signals below the ground plane
Minimize other RF signals near device
No large transient signals (both current and voltage) should be routed under the device
Do not layout near a large magnetic field such as a high frequency switching power supply
Do not place near piezoelectric buzzers or mechancial fans
250
200
150
100 50 Seconds
215°C ± 10°C
10 Seconds max
260°C max
120 to 160 Seconds
175°C ± 10°C
T Rise= 4 Degree/second max
Temperature °C
Reflow Cycle for lead free processing
PECL, LVDS, OCXO
Page 1 - 7
Mar 2004
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
6A Pl tronics, Inc.
PECL and LVDS Layout Guidelines Continued
Pl tronics, Inc.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
.
Vcc
Vcc - 2.00 V
GND
Out
Vcc
Oscillator
Vcc
GND
Out
Vcc
Oscillator
PECL Terminations:
LVDS Terminations:
Mixed System Power Supply:
50 ohm
Vcc
GND
Out
Vcc
Oscillator R load
Vcc
GND
Q Out
QN Out
Vcc
Oscillator 100 ohm
R1
R2
Suggested Terminations for 50 ohm impedance matched termination
Simple termination for NON impedance matched termination
Vcc
5.0 V
3.3 V
2.5 V
R1
82 ohm
130 ohm
249 ohm
Vcc
5.0 V
3.3 V
2.5 V
R load
274 ohm
147 ohm
86.6 ohm
R2
130 ohm
82 ohm
61.9 ohm
Thevenin Equivalent Termination
Design PCB traces for 50 ohm characteristic impedance
To use multiple supply voltages requires level translation. Direct circuit connection is not valid.
Mixed supply voltages are allowed. No translation is necessary. (ECL is returned to the most positive
supply and this is common to all circuits)
Mixed supply voltages are allowed. LVDS signal levels are power supply independent.
3.3 V LVDS oscillators properly interface 2.5 V Logic Arrays for example.
PECL
ECL
LVDS
