8, 16 MEG x 64 SDRAM DIMMs SYNCHRONOUS DRAM MODULE MT8LSDT864A, MT16LSDT1664A For the latest data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM * PC66-, PC100- and PC133-compliant * JEDEC-standard 168-pin, dual in-line memory module (DIMM) * Utilizes 100 MHz, 125 MHz and 133 MHz SDRAM components * Unbuffered * 64MB (8 Meg x 64) and 128MB (16 Meg x 64) * Single +3.3V 0.3V power supply * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal SDRAM banks for hiding row access/ precharge * Programmable burst lengths: 1, 2, 4, 8 or full page * Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes * Self Refresh Mode * 64ms, 4,096-cycle refresh * LVTTL-compatible inputs and outputs * Serial Presence-Detect (SPD) OPTIONS 64MB, 66 MHz; 64MB, 100 MHz; 128MB PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 VSS 43 VSS 85 VSS 2 DQ0 44 DNU 86 DQ32 3 DQ1 45 S2# 87 DQ33 4 DQ2 46 DQMB2 88 DQ34 5 DQ3 47 DQMB3 89 DQ35 6 VDD 48 DNU 90 VDD 7 DQ4 49 VDD 91 DQ36 8 DQ5 50 NC 92 DQ37 9 DQ6 51 NC 93 DQ38 10 DQ7 52 NC 94 DQ39 11 DQ8 53 NC 95 DQ40 12 VSS 54 VSS 96 VSS 13 DQ9 55 DQ16 97 DQ41 14 DQ10 56 DQ17 98 DQ42 15 DQ11 57 DQ18 99 DQ43 16 DQ12 58 DQ19 100 DQ44 17 DQ13 59 VDD 101 DQ45 18 VDD 60 DQ20 102 VDD 19 DQ14 61 NC 103 DQ46 20 DQ15 62 NC 104 DQ47 21 NC 63 CKE1* 105 NC 22 NC 64 VSS 106 NC 23 VSS 65 DQ21 107 VSS 24 NC 66 DQ22 108 NC 25 NC 67 DQ23 109 NC 26 VDD 68 VSS 110 VDD 27 WE# 69 DQ24 111 CAS# 28 DQMB0 70 DQ25 112 DQMB4 29 DQMB1 71 DQ26 113 DQMB5 30 S0# 72 DQ27 114 S1#* 31 DNU 73 VDD 115 RAS# 32 VSS 74 DQ28 116 VSS 33 A0 75 DQ29 117 A1 34 A2 76 DQ30 118 A3 35 A4 77 DQ31 119 A5 36 A6 78 VSS 120 A7 37 A8 79 CK2 121 A9 38 A10 80 NC 122 BA0 39 BA1 81 NC/WP** 123 A11 40 VDD 82 SDA 124 VDD 41 VDD 83 SCL 125 CK1 42 CK0 84 VDD 126 RFU *128MB version only **-133/-10E versions only MARKING * Operating Temperature Range Commercial (-0oC to +70oC) Extended (-40oC to +85oC) G I * Frequency/CAS Latency 133 MHz/CL = 2 (7.5, 133MHz SDRAMs) 133 MHz/CL = 3 (7.5ns, 133 MHz SDRAMs) 100 MHz/CL = 2 (8ns, 125 MHz SDRAMs) 66 MHz/CL = 2 (10ns, 100 MHz SDRAMs) -13E -133 -10E -662 KEY SDRAM COMPONENT TIMING PARAMETERS MODULE SPEED MARKING GRADE -13E -133 -10E -662 -7E -75 -8E -10 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 CAS ACCESS LATENCY TIME 2 3 2 2 5.4ns 5.4ns 6ns 9ns SETUP TIME HOLD TIME 1.5ns 1.5ns 2ns 3ns 0.8ns 0.8ns 1ns 1ns 1 PIN SYMBOL 127 VSS 128 CKE0 129 S3#* 130 DQMB6 131 DQMB7 132 RFU 133 VDD 134 NC 135 NC 136 NC 137 NC 138 VSS 139 DQ48 140 DQ49 141 DQ50 142 DQ51 143 VDD 144 DQ52 145 NC 146 NC 147 NC 148 VSS 149 DQ53 150 DQ54 151 DQ55 152 VSS 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 VDD 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 VSS 163 CK3 164 NC 165 SA0 166 SA1 167 SA2 168 VDD Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. Micron is a registered trademark of Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs PART NUMBERS PART NUMBER MT8LSDT864AG-13E_ MT8LSDT864AG-133_ MT8LSDT864AG-10E_ MT8LSDT864AG-662_ MT16LSDT1664AG-13E_ MT16LSDT1664AG-133_ MT16LSDT1664AG-10E_ MT16LSDT1664AG-662_ MT8LSDT864AI-133_ MT8LSDT864AI-10E_ MT8LSDT864AI-662_ MT16LSDT1664AI-133_ MT16LSDT1664AI-10E_ MT16LSDT1664AI-662_ CONFIG 8 Meg x 64 8 Meg x 64 8 Meg x 64 8 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 8 Meg x 64 8 Meg x 64 8 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. These modules are designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 64Mb x4, x8, x16 SDRAM data sheet. BUS SPEED TEMP 133 MHz 0o to +70o 133 MHz 0o to +70o 100 MHz 0o to +70o 66 MHz 0o to +70o 133MHz 0o to +70o 133 MHz 0o to +70o 100 MHz 0o to +70o 66 MHz 0o to +70o 133 MHz -40o to +85o 100 MHz -40o to +85o 66 MHz -40o to +85o 133 MHz -40o to +85o 100 MHz -40o to +85o 66 MHz -40o to +85o NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8LSDT864AG-10EB4. GENERAL DESCRIPTION The MT8LSDT864A and MT16LSDT1664A are highspeed CMOS, dynamic random-access, 64MB and 128MB memories organized in a x64 configuration. These modules use internally configured quad-bank SDRAMs with a synchronous interface (all signals are registered on the positive edge of the clock signals CK0-CK3). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 SERIAL PRESENCE-DETECT OPERATION These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/EEPROM addresses. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT8LSDT864A (64MB) S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQM CS# DQ0 DQ1 U1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ0 DQ1 U2 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQM CS# DQ0 DQ1 U3 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U4 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S2# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM CS# DQ0 DQ1 U7 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 DQM CS# DQ0 DQ1 U9 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RAS# RAS#: SDRAMs U0-U7 CAS# CAS#: SDRAMs U0-U7 CKE0 CKE0: SDRAMs U0-U7 WE# WE#: SDRAMs U0-U7 A0-A11 DQM CS# DQ0 DQ1 U6 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CK0 U0 U4 U1 U5 CK1 U2 U6 U3 U7 A0-A11: SDRAMs U0-U7 BA0 BA0: SDRAMs U0-U7 BA1 BA1: SDRAMs U0-U7 VDD SDRAMs U0-U7 VSS SDRAMs U0-U7 DQM CS# DQ0 DQ1 U8 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CK0 3.3pF CK2 3.3pF CK2, CK3 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM CK1, CK3 10pF 10pF SPD SCL WP 47K U10 A0 A1 A2 SA0 SA1 SA2 NOTE: SDA 66 MHz VERSION 100 MHz/133 MHz VERSIONS U0-U7 = MT48LC8M8A2GT SDRAMs All resistor values are 10 ohms. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT16LSDT1664A (128MB) S0# S1# DQMB0 DQMB4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U19 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U3 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U17 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB1 DQM CS# DQ0 DQ1 U2 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U18 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U4 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U16 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U6 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U14 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U8 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U12 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S2# S3# DQMB2 DQMB6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM CS# DQ0 DQ1 U7 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U13 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U9 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U11 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB3 DQMB7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VDD 10K CKE1 CKE: SDRAMs U8-U15 CKE0 CKE: SDRAMs U0-U7 CAS# CAS#: SDRAMs U0-U15 RAS# RAS#: SDRAMs U0-U15 WE# WE#: SDRAMs U0-U15 CK0 3.3pF CK1 A0-A11: SDRAMs U0-U15 A0-A11 BA0 BA0: SDRAMs U0-U15 BA1 BA1: SDRAMs U0-U15 VDD SDRAMs U0-U15 VSS SDRAMs U0-U15 A0 A1 CK2 SDA SDRAM SDRAM SDRAM SDRAM 3.3pF SA0 SA1 SA2 NOTE: SDRAM SDRAM SDRAM SDRAM 3.3pF CK3 A2 SDRAM SDRAM SDRAM SDRAM 3.3pF SPD SCL WP 47K SDRAM SDRAM SDRAM SDRAM U0-U15 = MT48LC8M8A2TG SDRAMs All resistor values are 10 ohms unless otherwise specified. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE 115, 111, 27 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS# and WE# (along with S0#-S3#) define the command being entered. 42, 79, 125, 163 CK0-CK3 Input Clock: CK0-CK3 are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. 63, 128 CKE1, CKE0 Input Clock Enable: CKE0-CKE1 activate (HIGH) and deactivate (LOW) the CK0-CK3 signals. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row ACTIVE in any bank) or CLOCK SUSPEND operation (burst access in progress). CKE0-CKE1 are synchronous except after the device enters power-down and self refresh modes, where CKE0-CKE1 become asynchronous until after exiting the same mode. The input buffers, including CK0-CK3, are disabled during power-down and self refresh modes, providing low standby power. 30, 45, 114, 129 S0#-S3# Input Chip Select: S0#-S3# enable (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S0#-S3# are registered HIGH. S0#-S3# are considered part of the command code. 28-29, 46-47, 112-113, 130-131 DQMB0-DQMB7 Input Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH during a READ cycle. 39, 122 BA0, BA1 Input Bank Address: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. 33-38, 117-121, 123 A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (column-address A0-A8, with A10 defining AUTO PRECHARGE) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 81 WP Input Write Protect: Serial presence-detect hardware write protect. Applies to -10E/-10C versions only. 83 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 165-167 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 DESCRIPTION 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs PIN DESCRIPTIONS (continued) PIN NUMBERS SYMBOL TYPE 2-5, 7-11, 13-17, 19-20, 55-58, 60, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 DQ0-DQ63 Input/ Output Data I/Os: Data bus. 82 SDA Input/ Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 VDD Supply Power Supply: +3.3V 0.3V. 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 VSS Supply Ground. 126, 132 RFU - Reserved for Future Use: These pins should be left unconnected. 31, 44, 48 DNU - Do Not Use: These pins are not connected on these modules but are assigned pins on the compatible DRAM version. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 DESCRIPTION 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SCL SCL SDA DATA STABLE DATA CHANGE DATA STABLE SDA Figure 1 Data Validity START BIT STOP BIT Figure 2 Definition of Start and Stop SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge Figure 3 Acknowledge Response From Receiver 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX BYTE 0 1 2 3 4 5 6 7 8 9 DESCRIPTION NUMBER OF BYTES USED BY MICRON TOTAL NUMBER OF SPD MEMORY BYTES MEMORY TYPE NUMBER OF ROW ADDRESSES NUMBER OF COLUMN ADDRESSES NUMBER OF BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME (CAS LATENCY = 3) 10 SDRAM ACCESS FROM CLOCK (CAS LATENCY = 3) 11 12 13 14 15 MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY FROM BACK-TOBACK RANDOM COLUMN ADDRESSES 16 17 18 19 20 21 22 23 BURST LENGTHS SUPPORTED NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME (CAS LATENCY = 2) 24 SDRAM ACCESS FROM CK (CAS LATENCY = 2) 25 ENTRY (VERSION) SYMBOL 128 256 SDRAM 12 9 1 or 2 64 0 LVTTL tCK 7 (-13E) 7.5 (-133) 8 (-10E) 10 (-662) 5.4 (-13E/-133) 6 (-10E) 7.5 (-662) NONPARITY 15.6s/SELF 8 NONE 1 1, 2, 4, 8, PAGE 4 2, 3 0 0 UNBUFFERED 0E 7.5 (-13E) 10 (-133/-10E) 15 (-662) tAC tCCD tCK MT8LSDT864A 80 08 04 0C 09 01 40 00 01 70 75 80 A0 MT16LSDT1664A 80 08 04 0C 09 02 40 00 01 70 75 80 A0 54 60 75 54 60 75 00 80 08 00 01 00 80 08 00 01 8F 04 06 01 01 00 0E 75 A0 F0 8F 04 06 01 01 00 0E 75 A0 F0 5.4 (-13E) 6 (-133/-10E) 9 (-662) tAC 54 60 90 54 60 90 SDRAM CYCLE TIME (CAS LATENCY = 1) - tCK 00 00 26 SDRAM ACCESS FROM CK (CAS LATENCY = 1) - tAC 00 00 27 MINIMUM ROW PRECHARGE TIME 15 (-13E) 20 (-133/-10E) 30 (-662) tRP 0F 14 1E 0F 14 1E 28 MINIMUM ROW ACTIVE TO ROW ACTIVE 14 (-13E) 15 (-133) 20 (-10E/-662) tRRD 0E 0F 14 0E 0F 14 NOTE: "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (continued) BYTE 29 DESCRIPTION MINIMUM RAS# TO CAS# DELAY ENTRY (VERSION) SYMBOL tRCD 15 (-13E) 20 (-133/-10E) 30 (-662) tRAS 37 (-13E) 44 (-133) 50 (-10E) 60 (-662) 64MB tAS, tCMS 1.5 (-13E/-133) 2 (-10E/-662) MT8LSDT864A 0F 14 1E 25 2C 32 3C 10 15 20 MT16LSDT1664A 0F 14 1E 25 2C 32 3C 10 15 20 30 MINIMUM RAS# PULSE WIDTH 31 32 MODULE BANK DENSITY COMMAND AND ADDRESS SETUP TIME 33 COMMAND AND ADDRESS HOLD TIME 0.8 (-13E/-133) 1 (-10E/-662) tAH, tCMH 08 10 08 10 34 DATA SIGNAL INPUT SETUP TIME 1.5 (-13E/-133) 2 (-10E/-662) tDS 15 20 15 20 35 DATA SIGNAL INPUT HOLD TIME 0.8(-13E/-133) 1 (-10E/-662) tDH 08 10 08 10 REV. 1.2 00 12 00 12 (-13E) (-133) (-10E) (-662) 4F 9D E5 B8 50 9E E6 B9 MICRON 2C FF 2C FF 01 02 03 04 05 06 07 08 09 01 02 03 04 05 06 07 08 09 36-61 62 63 64 65-71 72 73-90 91 RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 MANUFACTURER'S JEDEC ID CODE MANUFACTURER'S JEDEC ID CODE (continued) MANUFACTURING LOCATION MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE 1 2 3 4 5 xx xx 01 02 03 04 05 01 02 03 04 05 NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. x = Variable Data. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (continued) BYTE 91 DESCRIPTION PCB IDENTIFICATION CODE (continued) 92 93 94 95-98 99-125 126 IDENTIFICATION CODE (continued) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY 127 SDRAM COMPONENT AND CLOCK DETAIL ENTRY (VERSION) SYMBOL 6 7 8 9 0 100 MHz (-13E/-133/-10E) 66 MHz (-662) (-13E/-133/-10E) (-662) MT8LSDT864A 06 07 08 09 00 MT16LSDT1664A 06 07 08 09 00 xx xx xx xx xx xx - - 64 64 66 AF CF 66 FF FF NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. x = Variable Data. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs COMMANDS Truth Table 1 provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 64Mb x4, x8, x16 SDRAM data sheet. TRUTH TABLE 1 - COMMANDS AND DQMB OPERATION (Note: 1) NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQs COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X X NOTES ACTIVE (Select bank and activate row) L L H H Bank/Row X 3 READ (Select bank and column, and start READ burst) L H L H L/H8 Bank/Col X 4 WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X X X 6, 7 LOAD MODE REGISTER L L L L X Op-Code X 2 Write Enable/Output Enable - - - - L - Active 8 Write Inhibit/Output High-Z - - - - H - High-Z 8 NOTE: 1. 2. 3. 4. 5. 6. 7. 8. Bank/Col Valid 4 CKE is HIGH for all commands shown except SELF REFRESH. A0-A11 define the op-code written to the Mode Register. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. A0-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine which bank is being precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs A11 A10 11 10 A9 9 Reserved* WB A8 8 A6 A7 6 7 Op Mode A5 5 A4 A3 4 CAS Latency 3 1 2 BT A1 A2 0 Table 1 Burst Definition Address Bus A0 Mode Register (Mx) Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential Type = Interleaved A0 0 0-1 0-1 2 1 1-0 1-0 A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 4 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 8 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Cn, Cn + 1, Cn + 2 Full n = A0-A8 Cn + 3, Cn + 4... Page Not supported ...Cn - 1, (y) (location 0-y) Cn... Burst Length *Should program M11, M10 = "0, 0" to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access NOTE: 1. For full-page accesses: y = 512. 2. For a burst length of two, A1-A8 select the blockof-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A8 select the blockof-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A8 select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected, and A0-A8 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A8 select the unique column to be accessed, and Mode Register bit M3 is ignored. All other states reserved Figure 4 Mode Register Definition 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS .... -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ..................................... -1V to +4.6V Operating Temperature, TA (ambient) ... 0C to +70C Storage Temperature (plastic) ............ -55C to +125C Power Dissipation ................................................... 8W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1,2) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SUPPLY VOLTAGE VDD 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2 VDD + 0.3 V 3 INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.5 0.8 V 3 INPUT LEAKAGE CURRENT: Any input 0V VIN VDD (All other pins not under test = 0V) DQMB0-DQMB7 CK0-CK3, S0#-S3# CKE0-CKE1 RAS#, CAS#, A0-A11, BA0-BA1, WE# I I1 I I2 I I3 I I4 -10 -20 -40 -80 10 20 40 80 A A A A 4 DQ0-DQ63 IOZ -10 10 A 4 VOH 2.4 - V VOL - 0.4 V OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V VOUT VDD OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) UNITS NOTES 4 NOTE: 1. All voltages referenced to VSS. 2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. 4. 64MB module values will be half of those shown. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS (Notes: 1-4) (VDD = +3.3V 0.3V) MAX PARAMETER/CONDITION SYMBOL OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN); CAS latency = 3 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle IDD2 IDD3 OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 IDD4 = tRC (MIN); CL = 3 tRC = 15.625s; CL = 3 -10E -662 760 720 960 64MB 128MB 16 32 16 32 16 32 24 48 64MB 360 360 280 240 720 720 64MB 1,200 1,120 560 480 960 840 UNITS NOTES mA 5, 6, 7, 8 mA 8 mA 5, 9, 7, 8 mA 5, 6, 7, 8 128MB 1,560 1,480 1,240 1,080 IDD6 SELF REFRESH CURRENT: CKE 0.2V -133 920 128MB 1,360 1,280 1,040 128MB IDD5 tRC -13E IDD1 STANDBY CURRENT: Active Mode; S0#-S3# = HIGH; CKE = HIGH; All banks active after tRCD met; No accesses in progress AUTO REFRESH CURRENT: CKE = HIGH; S0#-S3# = HIGH SIZE 64MB 1,000 IDD7 64MB 1,840 1,680 1,520 1,360 128MB 2,200 2,040 1,800 1,600 64MB 24 24 24 24 128MB 48 48 48 48 mA mA 5, 6, 7, 8, 9, 10 64MB 128MB mA 11 8 16 8 16 8 16 16 32 NOTE: 1. All voltages referenced to VSS. 2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crosspover point. 4. IDD specifications are tested after the device is properly initialized. 5. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. The IDD current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 7. Address transitions average one transition every two clocks. 8. tCK = 7.5ns for -133, 10ns for -10E and 15ns for -662. 9. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 10. CKE is high during refresh command period (tRFC [MIN]) else CKE is low. The IDD6 limit is actually a nominal value and does not result in a fail value. 11. Enables on-chip refresh and address counters. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs CAPACITANCE (Note: 1) 64MB PARAMETER 128MB SYMBOL MIN MAX MIN MAX UNITS Input Capacitance: A0-A11, BA0, BA1, RAS#, CAS#, WE# CI 1 22 30 44 60 pF Input Capacitance: CK0-CK3 CI 2 12 18 12 18 pF Input Capacitance: S0#-S3# CI 3 12 16 12 16 pF Input Capacitance: CKE0, CKE1 CI 4 22 30 22 30 pF Input Capacitance: DQMB0#-DQMB7# CI 5 4 6 7 9 pF Input Capacitance: SCL, SA0-SA2 CI 6 - 6 - 6 pF Input/Output Capacitance: DQ0-DQ63, SDA CIO 6 8 10 14 pF NOTE: This parameter is sampled. VDD = +3.3V; f = 1 MHz. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs SDRAM COMPONENT* AC ELECTRICAL CHARACTERISTICS (Notes: 1-6; notes appear below and on next page) AC CHARACTERISTICS PARAMETER Access time from CK (pos. edge) Address hold time Address setup time CK high-level width CK low-level width Clock cycle time CL = 3 CL = 2 CL = 3 CL = 2 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period AUTO REFRESH period ACTIVE to READ or WRITE delay Refresh period (4,096 cycles) PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command -13E (PC133) SYMBOL MIN MAX tAC 5.4 tAC 5.4 tAH 0.8 tAS 1.5 tCH 2.5 tCL 2.5 tCK 7 tCK 7.5 tCKH 0.8 tCKS 1.5 tCMH 0.8 tCMS 1.5 tDH 0.8 tDS 1.5 tHZ 5.4 tHZ 5.4 tLZ 1 tOH 2.7 tOH 1.8 N tRAS 37 120,000 tRC 60 tRCAR 15 tRCD 64 tREF 66 tRP 15 tRRD 14 tT 0.3 1.2 tWR 1 CK + 7ns tXSR 14 67 -133 (PC133) -10E (PC100) -662 (PC66) MIN MAX MIN MAX MIN MAX UNITS NOTES 5.4 6 7.5 ns 7 6 6 9 ns 0.8 1 1 ns 1.5 2 2 ns 2.5 3 3 ns 2.5 3 3 ns 7.5 8 10 ns 8 10 10 15 ns 8 0.8 1 1 ns 1.5 2 2 ns 0.8 1 1 ns 1.5 2 2 ns 0.8 1 1 ns 1.5 2 2 ns 5.4 6 8 ns 9 7 7 10 ns 9 1 1 2 ns 2.7 3 3 ns 1.8 1.8 n/a ns 10 44 120,000 50 120,000 60 120,000 ns 66 70 90 ns 66 70 90 ns 20 20 30 ns 64 64 64 ms 20 20 30 ns 15 20 20 ns 0.3 1.2 0.3 1.2 1 1.2 ns 11 1 CK + 1 CK + 1 CK + - 12 7.5ns 8ns 8ns 15 15 75 15 80 90 ns ns 13 14 *Specifications for the SDRAM components used on the module. NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA +70C) is ensured. 2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC characteristics assume tT = 1ns. 4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 5. Outputs measured at 1.5V with equivalent load: Q 50pF 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs NOTES: (continued) 6. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crosspover point. 7. tAC for -133 at CL = 3 with no load is 4.6ns and is guaranteed by design. 8. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 9. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 10. Parameter guaranteed by design. 11. AC characteristics assume tT = 1ns. 12. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/8ns after the first clock delay, after the last WRITE is executed. 13. Precharge mode only. 14. CK must be toggled a minimum of two times during this period. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs AC FUNCTIONAL CHARACTERISTICS (Notes: 1-6) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH tROH -133 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 -13E/ -10E 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 -662 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 UNITS NOTES tCK 7 tCK 8 tCK 8 tCK 7 tCK 7 tCK 7 tCK 7 tCK 9, 10 tCK 10, 11 tCK 7 tCK 7 tCK 10, 11 tCK 12 tCK 7 tCK 7 NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA +70C) is ensured. 2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC characteristics assume tT = 1ns. 4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 5. Outputs measured at 1.5V with equivalent load: Q 50pF 6. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crosspover point. 7. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 8. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 9. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 10. Based on tCK = 143 MHz for 13E, tCK = 133 MHz for -75, 100 MHz for -10E and 66 MHz for -662. 11. Timing actually specified by tWR. 12. JEDEC and PC100 specify three clocks. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Note: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SUPPLY VOLTAGE VDD 3 3.6 INPUT HIGH VOLTAGE: Logic 1; All inputs VIH INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 OUTPUT LOW VOLTAGE: IOUT = 3mA VDD x 0.7 VDD + 0.5 UNITS NOTES V V V VOL - 0.4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI - 10 A OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO - 10 A STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% ISB - 30 A POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz IDD - 2 mA NOTE: 1. All voltages referenced to VSS. SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (Note: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SCL LOW to SDA data-out valid tAA 0.3 3.5 Time the bus must be free before a new transition can start tBUF 4.7 s Data-out hold time tDH 300 ns tF SDA and SCL fall time 300 UNITS NOTES s ns Data-in hold time tHD:DAT 0 s Start condition hold time tHD:STA 4 s tHIGH 4 s Clock HIGH period tI Noise suppression time constant at SCL, SDA inputs tLOW Clock LOW period SDA and SCL rise time SCL clock frequency 100 4.7 ns s tR 1 s tSCL 100 KHz Data-in setup time tSU:DAT 250 ns Start condition setup time tSU:STA 4.7 s Stop condition setup time tSU:STO 4.7 tWRC WRITE cycle time s 10 ms 2 NOTE: 1. All voltages referenced to VSS. 2. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs SPD EEPROM tF t HIGH tR t LOW SCL t HD:STA t SU:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 MIN 0.3 4.7 300 MAX 3.5 300 0 4 UNITS s s ns ns s s SYMBOL tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO 20 MIN 4 4.7 MAX 1 250 4.7 4.7 UNITS s s s ns s s Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs 168-PIN DIMM (64MB, 66 MHz) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .125 (3.18) MAX .079 (2.00) R (2X) 1.255 (31.88) 1.245 (31.62) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) .039 (1.00)R (2X) 2.625 (66.68) .054 (1.37) .046 (1.17) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP .050 (1.27) TYP PIN 1 (PIN 85 ON BACKSIDE) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) 168-PIN DIMM (64MB, 100 MHz) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .125 (3.18) MAX .079 (2.00) R (2X) 1.380 (35.05) 1.370 (34.80) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) .039 (1.00)R (2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP PIN 1 (PIN 85 ON BACKSIDE) .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16 MEG x 64 SDRAM DIMMs 168-PIN DIMM (128MB) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .157 (4.00) MAX .079 (2.00) R (2X) 1.380 (35.05) 1.370 (34.80) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) .039 (1.00)R (2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP .050 (1.27) TYP PIN 1 (PIN 85 ON BACKSIDE) .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 8, 16 Meg x 64 SDRAM DIMMs ZM06_5.p65 - Rev. 3/00 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. M M OD U L E 3Q0 0 PRODUCT GUIDE PA RT S E L E C TO R PA RT N U M B E R I N G G U I D E S O R D E R I N F O R M AT I O N DRAM Modules SDRAM Modules DDR SDRAM Modules RIMMTM Modules O R D E R I N F O R M AT I O N For more information about our high-quality Micron(R) Modules, visit our Web site or phone us today. www.micronsemi.com 208.368.3900 Micron Semiconductor Products, Inc. 8000 S. Federal Way, P.O. Box 6 * Boise, Idaho 83707-0006 * Tel: 208-368-3900 * Fax: 208-368-4617 Internet: www.micronsemi.com/mti * E-mail: prodmktg@micron.com Customer Comment Line: 800-932-4992 * Customer Comment Fax Line: 01-208-368-5018 Micron Europe Limited Micron House, Wellington Business Park * Dukes Ride, Crowthorne * Berkshire RG45 6LS * United Kingdom Tel: 44-1344-750750 * Fax: 44-1344-750710 Micron Semiconductor (Deutschland) GmbH Sternstrasse 20 * D-85609 Aschheim * Germany * Tel: 49-89-904-8720 * Fax: 49-89-904-87250 Micron Semiconductor Asia, Pte. Ltd. 5 Upper Aljunied Link #06-06 * Quartz Industrial Bldg. * Singapore 367903 * Tel: 65-287-6006 * Fax: 65-287-6556 Micron Technology Asia Pacific, Inc., Taiwan Branch (c)2000, Micron Technology, Inc. Suite 1010, 10th Floor * 333 Keelung Road, Sec 1 * Taipei, 110 Taiwan, ROC * Tel: 886-2-2757-6622 * Fax: 886-2-2757-6656 Micron is a registered trademark of Micron Technology, Inc. Rambus and RDRAM are registered trademarks and RIMM is a trademark of Rambus Inc. Products and specifications are subject to change without notice. Micron Technology Italia, Srl Via Antonio Pacinotti 5/7 * Nucleo Industriale (AQ), Building 2 * Avezzano (AQ) Italia 67051 * Tel: 39-0863-423206 * Fax: 39-0863-423283 Micron Technology Japan, K.K. Rev. 8/00 4-30 Shiba-Koen 3-chome * 32 Mori Building 8F * Minato-ku * Tokyo 105, Japan * Tel: 81-3-3436-5666 * Fax: 81-3-3436-1444 M ICRON. A W ORLD M EMORY L EADER Y ER AD . ORLD M EM AW O R PA RT N U M B E R I N G G U I D E S LE O N DRAM MODULE NUMBERING CR MI MT18LD1672 A G-5 X Micron Technology Module Special Designator Blank = Fast Page Mode X = Extended Data-Out L = Extended Refresh S = Self Refresh Number of Memory Components Access Time 50ns = -5 60ns = -6 70ns = -7 Process Technology L = Low Voltage (3.3V) Package Code G = Gold-Plated SIMM/DIMM M = Tin/Lead-Plated SIMM HG = Small-Outline Gold DIMM DG = Low-Profile, Double-Sided SIMM (gold-plated) DM = Low-Profile, Double-Sided SIMM (tin/lead-plated) Product Family D = DRAM DT = DRAM TSOP Depth Module Version A = 168-pin DIMM; unbuffered, serial presence-detect Width SDRAM/DDR SDRAM/RDRAM (R) MODULE NUMBERING MT18L SDT1672 A G-10EC 7 Micron Technology Number of Memory Components Process Technology L = 3.3V V = 2.5V Product Family SD = SDRAM SDT = SDRAM TSOP DDT = DDR SDRAM TSOP VR = Rambus(R) Depth Width Printed Circuit Board Revision Designator Die Revision Designator Memory Bus Speed 66 MHz CAS Latency 2 (-10 SDRAMs) = -662 100 MHz CAS Latency 3 (-8C SDRAMs) = -10C 100 MHz CAS Latency 2 (-8E SDRAMs) = -10E 133 MHz CAS Latency 3 (-75 SDRAMs) = -133 133 MHz CAS Latency 2 (-7E SDRAMs) = -13E 200 MHz data rate, CAS Latency 2 (-8 DDR SDRAMs) = -202 266 MHz data rate, CAS Latency 2.5 (-75 DDR SDRAMs) = -265 266 MHz data rate, CAS Latency 2 (-7 DDR SDRAMs) = -262 700 MHz data rate, 53ns access time = -750 700 MHz data rate, 45ns access time = -745 800 MHz data rate, 53ns access time = -850 800 MHz data rate, 45ns access time = -845 800 MHz data rate, 40ns access time = -840 Module Version Package Code SDRAM A = 168-pin/184-pin DIMM and 184-pin RIMM TM; unbuffered, serial presence-detect U = 100-pin DIMM; unbuffered, serial presence-detect G = 144-pin graphics SODIMM G = Gold-Plated SIMM/DIMM HG = Small-Outline Gold DIMM DG = Low-Profile, Double-Sided DIMM M ICRON. A W ORLD M EMORY L EADER R ER AD ORLD M EM AW O Y LE D R A M M O D U L E PA RT S E L E C TO R O N . Data sheets are available at www.micronsemi.com/datasheets/datasheet.html. CR MI MODULE KEY DS = Double Sided, SS = Single Sided; M = Tin Plated, G = Gold Plated; U = 100-pin DIMM, H = Small-Outline DIMM (SODIMM), (A) = see footnote references below, (X) = EDO, no X = FPM version DRAM MODULES Module Components Description Module Part Number Family Density 72-pin SODIMM 4MB 8MB 16MB 16MB 32MB SS SS SS DS DS 1 Meg 2 Meg 4 Meg 4 Meg 8 Meg x x x x x 32 32 32 32 32 3.3V Gold 3.3V Gold 3.3V Gold 3.3V Gold 3.3V Gold (2) (4) (2) (8) (4) 1 Meg x 1 Meg x 4 Meg x 4 Meg x 4 Meg x 16 16 16 4 16 72-pin SIMM 4MB 8MB 16MB 16MB 32MB 32MB SS DS SS SS DS DS 1 Meg 2 Meg 4 Meg 4 Meg 8 Meg 8 Meg x x x x x x 32 32 32 36 36 32 Gold/Tin Gold/Tin Gold/Tin ECC Gold/Tin ECC Gold/Tin Gold/Tin (2) 1 Meg x (4) 1 Meg x (8) 4 Meg x (9) 4 Meg x (18) 4 Meg x (16) 4 Meg x 100-pin DIMM 4MB 8MB 16MB 32MB SS SS SS DS 1 Meg 2 Meg 4 Meg 8 Meg x x x x 32 32 32 32 3.3V Gold 3.3V Gold 3.3V Gold 3.3V Gold (2) (4) (2) (4) 1 Meg x 1 Meg x 4 Meg x 4 Meg x 144-pin SODIMM 32MB 64MB DS DS 4 Meg x 64 3.3V Gold 8 Meg x 64 3.3V Gold (4) (8) 4 Meg x 16 TSOP 8 Meg x 8 TSOP 168-pin DIMM 8MB 32MB 32MB 32MB DS SS DS DS 1 Meg 4 Meg 4 Meg 4 Meg 3.3V Gold 3.3V Gold 3.3V Gold 3.3V ECC Gold (4) (4) (16) (18) 1 Meg x 4 Meg x 4 Meg x 4 Meg x 32MB SS 4 Meg x 72 3.3V ECC Gold (5) 64MB 64MB SS DS 8 Meg x 64 3.3V Gold 8 Meg x 72 3.3V ECC Gold 64MB SS 8 Meg x 72 3.3V ECC Gold x x x x 64 64 64 72 TSOP TSOP TSOP TSOP TSOP Speed (ns) Height Sample Prod. MT2LDT132HG MT4LDT232HG MT2LDT432HG MT8LDT432HG MT4LDT832HG 60 60 60 60 60 1.000" 1.000" 1.000" 1.000" 1.000" Now Now Now Now Now Now Now Now Now Now 16 16 4 4 4 4 MT2D132G/M MT4D232DG/M MT8D432G/M MT9D436G/M MT18D836G/M MT16D832G/M 50, 60 50, 60 50, 60 50, 60 50, 60 50, 60 .800" .800" 1.000" 1.000" 1.000" 1.000" Now Now Now Now Now Now Now Now Now Now Now Now 16 16 16 TSOP 16 TSOP MT2LD132UG MT4LD232UG MT2LDT432UG MT4LDT832UG 60 60 60 60 1.000" 1.000" 1.000" 1.000" Now Now Now Now Now Now Now Now MT4LDT464HG (S) MT8LDT864HG (S) 50, 60 60 1.000" 1.050" Now Now Now Now 16 TSOP 16 TSOP 4 4 MT4LDT164AG MT4LDT464AG MT16LD464AG MT18LD472(A)G 60 50, 60 60 60 Now Now Now Now Now Now Now Now 4 Meg x 16 TSOP MT5LDT472(A)G 60 Now Now (8) 8 Meg x 8 (36) 4 Meg x 4 MT8LD864AG MT36LD872(A)G 50, 60 60 Now Now Now Now (9) MT9LD872(A)G 50, 60 1.000" 1.000" 1.000" UB = 1.000" B = 1.000" UB = 1.000" B = 1.050" 1.100" UB = 1.500" B = 1.500" UB = 1.100" B = 1.250" 1.350" 1.250" UB = 1.250" B = 1.100" 2.000" 2.000" 2.000" Now Now Now Now Now Now Now Now Now Now Now Now Now Now 8 Meg x 8 64MB 128MB 128MB SS 8 Meg x 72 3.3V ECC Gold DS 16 Meg x 64 3.3V Gold DS 16 Meg x 72 3.3V ECC Gold (9) 8 Meg x 8 TSOP (16) 16 Meg x 4 (18) 16 Meg x 4 MT9LDT872G MT16LD1664AG MT18LD1672(A)G 50, 60 50, 60 50, 60 128MB 256MB 256MB DS 16 Meg x 72 3.3V ECC Gold DS 32 Meg x 72 3.3V ECC Gold DS 32 Meg x 72 3.3V ECC Gold (18) 16 Meg x 4 TSOP (36) 16 Meg x 4 (36) 16 Meg x 4 TSOP MT18LDT1672G MT36LD3272G MT36LDT3272G 50, 60 50, 60 50, 60 *All DRAM modules are available in EDO or Fast Page Mode. DS = Double Sided; SS = Single Sided; (A) = 8 CAS, SPD version, unbuffered; no A = Buffered version for x72 DIMMs; UB = Unbuffered; B = Buffered. Highlighted parts are not recommended for new designs. M ICRON. A W ORLD M EMORY L EADER R ER AD ORLD M EM AW O Y LE MODULE KEY O N . DS = Double Sided, SS = Single Sided; M = Tin Plated, G = Gold Plated; U = 100-pin DIMM, UDG = Double-sided, dual-bank 100-pin DIMM, H = Small-Outline DIMM (SODIMM), (A) = see footnote references below CR MI SDRAM MODULES Description Module Components Module Part Number 4MB SS 1 Meg x 32 3.3V Gold ( 2) 1 Meg x 16 TSOP MT2LSDT132UG 8MB DS 2 Meg x 32 3.3V Gold ( 4) 1 Meg x 16 TSOP MT4LSDT232UDG 16MB SS 4 Meg x 32 3.3V Gold ( 2) 4 Meg x 16 TSOP MT2LSDT432UG 32MB DS 8 Meg x 32 3.3V Gold ( 4) 4 Meg x 16 TSOP MT4LSDT832UDG 64MB DS 16 Meg x 32 3.3V Gold (4) 16 Meg x 8 TSOP MT4LSDT1632UG 128MB DS 32 Meg x 32 3.3V Gold (8) 16 Meg x 8 TSOP MT8LSDT3232UG 32MB DS 4 Meg x 64 3.3V Gold ( 4) 4 Meg x 16 TSOP MT4LSDT464(L)HG 64MB DS 8 Meg x 64 3.3V Gold ( 8) 64MB DS 8 Meg x 64 3.3V Gold ( 4) 8 Meg x 8 TSOP 4 Meg x 16 TSOP 8 Meg x 16 TSOP MT8LSDT864(L)HG MT8LSDT864(L)HG MT4LSDT864(L)HG 128MB DS 16 Meg x 64 3.3V Gold (8) 16 Meg x 8 TSOP (8) 8 Meg x 16 TSOP MT8LSDT1664(L)HG ( 4) MT4LSDT464AG Family Density 100-pin DIMM 144-pin SODIMM 168-pin DIMM Unbuffered 32MB 64MB 64MB 64MB 128MB 128MB 128MB SS 4 Meg x 64 3.3V Gold SS 8 Meg x 64 3.3V Gold SS 8 Meg x 64 3.3V Gold SS 8 Meg x 72 3.3V ECC Gold DS 16 Meg x 64 3.3V Gold SS 16 Meg x 64 3.3V Gold DS 16 Meg x 72 3.3V ECC Gold ( 8) ( 4) ( 9) (16) 4 Meg x 16 TSOP 8 Meg x 8 TSOP 8 Meg x 16 TSOP 8 Meg x 8 TSOP 8 Meg x 8 TSOP (8) 16 Meg x 8 TSOP (18) 8 Meg x 8 TSOP MT8LSDT864AG MT4LSDT864AG MT9LSDT872AG MT16LSDT1664AG MT8LSDT1664AG MT18LSDT1672AG 128MB SS 16 Meg x 72 3.3V Gold (9) 16 Meg x 8 TSOP MT9LSDT1672AG 256MB DS 32 Meg x 64 3.3V Gold (16) 16 Meg x 8 MT16LSDT3264AG 256MB DS 32 Meg x 72 3.3V ECC Gold (18) 16 Meg x 8 TSOP TSOP MT18LSDT3272AG Speed Die Rev. -10E1 -8E1 -10E1 -8E1 -10C1 -8C1 -10C1 -8C1 -10B1 -8B1 -10B1 -8B1 E = Y72G 1 = 6649 (1") E = Y72G 1 = 6649 (1") C = Y84 1 = 6660 (1") C = Y84 1 = 6660 (1") B = Y85B 1 = 6692 (1.15") B = Y85B 1 = 6692 (1.15") -662C1 -662C2 -10EC3 -662C3 -10EC5 -10EB1 -133B1 -662B2 -10EB1 C = Y84 1 = 6645 (1.15") 2 = 6669 (1") 3 = 0118B (1") 3 = 6678 (1.05") 5 = 0115C (1.25") 1 = 0118B (1") -662C1 -662C6 -10EC6 -133C6 -13EC6 -662C7 -10EC7 -133C7 -13EC7 -662B1 -10EB1 -133B1 -13EB1 -662C7 -10EC7 -133C7 -13EC7 -662C7 -10EC7 -133C7 -13EC7 -662B1 -10EB1 -133B1 -13EB1 -662C7 -10EC7 -133C7 -13EC7 -662B1 -10EB1 -133B1 -13EB1 -10EB1 -133B1 -13EB1 -10EB1 -133B1 -13EB1 C = Y84 C = Y84 B = Y85B B = Y85B C = Y84 B = Y85B C = Y84 C = Y84 B = Y85B C = Y84 PCB (Height) 1 = 0115C (1.25") 2 = 6678 (1.05") 1 = 6652 (1") 6 = 0134 (1") 7 = 0104B (1.375") 1 = 0134 (1") 7 = 0104B (1.375") 7 = 0104B (1.375") 1 = 0104 (1.375") 7 = 0104B (1.375") B = Y85B 1 = 0104 (1.375") B = Y85B 1 = 0104B (1.375") B = Y85B 1 = 0104B (1.375") MHz Samp. Prod. 100 125 100 125 100 125 100 125 100 125 100 125 Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now 66 66 100 66 100 100 133 66 100 Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now 66 66 100 133 133 66 100 133 133 66 100 133 133 66 100 133 133 66 100 133 133 66 100 133 133 66 100 133 133 66 100 133 133 100 133 133 100 133 133 Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Note PC100 PC100 PC100 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 (A) = SPD version, unbuffered; no A = registered version for x72 DIMMs. 144- and 168-pin DIMMs (66 MHz/100 MHz) adhere to Intel's 4-clock SDRAM module specs (66 MHz uses -10 components,100 MHz uses -8, 133 MHz uses -75). For 100-pin DIMMs, 100 MHz uses -10 components; adheres to JEDEC standard. Highlighted parts are available in PC133. M ICRON. A W ORLD M EMORY L EADER MODULE KEY DS = Double Sided, SS = Single Sided; M = Tin Plated, G = Gold Plated; U = 100-pin DIMM, UDG = Double-sided, dual-bank 100-pin DIMM, H = Small-Outline DIMM (SODIMM), (A) = see footnote references below SDRAM MODULES (continued) Family Density 168-pin DIMM Registered 64MB Description Module Components Module Part Number SS 8 Meg x 72 3.3V ECC Gold ( 9) MT9LSDT872G 8 Meg x 8 TSOP 128MB DS 16 Meg x 72 3.3V ECC Gold (18) 16 Meg x 4 TSOP MT18LSDT1672G 128MB SS 16 Meg x 72 3.3V Gold (9) 16 Meg x 8 TSOP MT9LSDT1672G 256MB 512MB 1GB DS 32 Meg x 72 3.3V ECC Gold DS 64 Meg x 72 3.3V ECC Gold DS 128 Meg x 72 3.3V Gold (18) 32 Meg x 4 (36) 32 Meg x 4 (36) 32 Meg x 4 TSOP FBGA TSOP MT18LSDT3272G MT36LSDF6472G MT36LSDT12872G Speed Die Rev. -10EC3 -133C3 -13EC3 -10EC2 -133C2 -13EC2 -10EB1 -133B1 -13EB1 -10EB1 -133B1 -13EB1 -10EB1 -133B2 -13EB2 -10EA1 -133A1 C = Y84 PCB (Height) MHz Samp. Prod. 3 = 0144 (1.5") 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now 9/00 9/00 Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now 4Q00 4Q00 C = Y84 2 = 0129 (1.7") B = Y85B 1 = 0144 (1.7") B = Y85B B = Y85B A = Y86 1 = 0129 (1.7") 1 = 0123 (1.6") 2 = TBD (1.6") 1 = TBD (1.7") Note CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 11x13 pkg. CL3 CL2 CL3 No A = registered version for x72 DIMMs. 144- and 168-pin DIMMs (66 MHz/100 MHz) adhere to Intel's 4-clock SDRAM module specs (66 MHz uses -10 components,100 MHz uses -8, 133 MHz uses -75). Highlighted parts are available in PC133. We're ready with DDR. See below . . . DDR SDRAM MODULES (PC1600 and PC2100) Description Module Components 64MB SS 8 Meg x 64 2.5V Gold (8) 8 Meg x 8 TSOP MT8VDDT864AG 64MB SS 8 Meg x 72 2.5V Gold (9) 8 Meg x 8 TSOP MT9VDDT872AG 128MB SS 16 Meg x 64 2.5V Gold (8) 16 Meg x 8 TSOP MT8VDDT1664AG 128MB SS 16 Meg x 72 2.5V Gold (9) 16 Meg x 8 TSOP MT9VDDT1672AG 256MB DS 32 Meg x 64 2.5V Gold (16) 16 Meg x 8 TSOP MT16VDDT3264AG 256MB DS 32 Meg x 72 2.5V Gold (18) 16 Meg x 8 TSOP MT18VDDT3272AG 64MB SS 8 Meg x 72 2.5V Gold (9) 8 Meg x 8 TSOP MT9VDDT872G 128MB DS 16 Meg x 72 2.5V Gold (18) 8 Meg x 8 TSOP MT18VDDT1672DG 128MB DS 16 Meg x 72 2.5V Gold (18) 16 Meg x 4 TSOP MT18VDDT1672G 128MB SS 16 Meg x 72 2.5V Gold (9) 16 Meg x 8 TSOP MT9VDDT1672G 256MB DS 32 Meg x 72 2.5V Gold (18) 16 Meg x 8 TSOP MT18VDDT3272DG 256MB DS 32 Meg x 72 2.5V Gold (18) 32 Meg x 4 TSOP MT18VDDT3272G 512MB DS 64 Meg x 72 2.5V Gold (36) 32 Meg x 4 TSOP MT36VDDT6472G Family Density 184-pin DIMM Unbuffered 184-pin DIMM Registered Module Part Number Speed Die Rev. -202A2 -265A2 -262A2 -202A2 -265A2 -262A2 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 A = T84 2 = 0161 (1.25") PCB (Height) A = T84 2 = 0161 (1.25") A = T85 1 = 0161 (1.25") A = T85 1 = 0161 (1.25") A = T85 1 = 0116B (1.25") A = T85 1 = 0116B (1.25") -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 A = T84 1 = 0162 (1.80") A = T84 1 = 0162 (1.80") A = T84 1 = 0163 (1.80") A = T85 1 = 0162 (1.80") A = T85 1 = 0162 (1.80") A = T85 1 = 0163 (1.80") A = T85 1 = 0163 (1.80") M ICRON. A W ORLD M EMORY L EADER MHz Sample Production 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 Now Now TBD Now Now TBD Now Now TBD Now Now TBD Now Now TBD Now Now TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 Now Now TBD Now Now TBD Now Now TBD Now Now TBD Now Now TBD Now Now TBD TBD TBD TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD 4Q00 4Q00 TBD TBD TBD TBD RDRAM(R) MODULES (RIMMTM MODULES) Module Components Description Module Part Number Pins Density 184-pin 128MB SS 64 Meg x 16 non-ECC (4) 16 Meg x 16 MT4VR6416AG 128MB SS 64 Meg x 18 ECC (4) 16 Meg x 18 MT4VR6418AG 256MB SS 128 Meg x 16 non-ECC (8) 16 Meg x 16 MT8VR12816AG 256MB SS 128 Meg x 18 ECC (8) 16 Meg x 18 MT8VR12818AG 512MB DS 256 Meg x 16 non-ECC (16) 16 Meg x 16 MT16VR25616AG 512MB DS 256 Meg x 18 ECC (16) 16 Meg x 18 MT16VR25618AG Speed Die Rev. PCB (Height) -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 A = R96 1 = TBD (1.25") A = R96 1 = TBD (1.25") A = R96 1 = TBD (1.25") A = R96 1 = TBD (1.25") A = R96 1 = TBD (1.25") A = R96 1 = TBD (1.25") M ICRON. A W ORLD M EMORY L EADER MHz Sample Prod. 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD