MT16LSDT1664AG-10EC7 - Micron Technology, Inc.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VSS 43 VSS 85 VSS 127 VSS

2 DQ0 44 DNU 86 DQ32 128 CKE0

3 DQ1 45 S2# 87 DQ33 129 S3#*

4 DQ2 46 DQMB2 88 DQ34 130 DQMB6

5 DQ3 47 DQMB3 89 DQ35 131 DQMB7

6VDD 48 DNU 90 VDD 132 RFU

7 DQ4 49 VDD 91 DQ36 133 VDD

8 DQ5 50 NC 92 DQ37 134 NC

9 DQ6 51 NC 93 DQ38 135 NC

10 DQ7 52 NC 94 DQ39 136 NC

11 DQ8 53 NC 95 DQ40 137 NC

12 VSS 54 VSS 96 VSS 138 VSS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 VDD 101 DQ45 143 VDD

18 VDD 60 DQ20 102 VDD 144 DQ52

19 DQ14 61 NC 103 DQ46 145 NC

20 DQ15 62 NC 104 DQ47 146 NC

21 NC 63 CKE1* 105 NC 147 NC

22 NC 64 VSS 106 NC 148 VSS

23 VSS 65 DQ21 107 VSS 149 DQ53

24 NC 66 DQ22 108 NC 150 DQ54

25 NC 67 DQ23 109 NC 151 DQ55

26 VDD 68 VSS 110 VDD 152 VSS

27 WE# 69 DQ24 111 CAS# 153 DQ56

28 DQMB0 70 DQ25 112 DQMB4 154 DQ57

29 DQMB1 71 DQ26 113 DQMB5 155 DQ58

30 S0# 72 DQ27 114 S1#* 156 DQ59

31 DNU 73 VDD 115 RAS# 157 VDD

32 VSS 74 DQ28 116 VSS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 VSS 120 A7 162 VSS

37 A8 79 CK2 121 A9 163 CK3

38 A10 80 NC 122 BA0 164 NC

39 BA1 81 NC/WP** 123 A11 165 SA0

40 VDD 82 SDA 124 VDD 166 SA1

41 VDD 83 SCL 125 CK1 167 SA2

42 CK0 84 VDD 126 RFU 168 VDD

*128MB version only **-133/-10E versions only

PIN ASSIGNMENT (Front View)

SYNCHRONOUS

DRAM MODULE MT8LSDT864A, MT16LSDT1664A

For the latest data sheet, please refer to the Micron Web

site: www.micron.com/mti/msp/html/datasheet.html

FEATURES

• PC66-, PC100- and PC133-compliant

• JEDEC-standard 168-pin, dual in-line memory

module (DIMM)

• Utilizes 100 MHz, 125 MHz and 133 MHz SDRAM

components

• Unbuffered

• 64MB (8 Meg x 64) and 128MB (16 Meg x 64)

• Single +3.3V ±0.3V power supply

• Fully synchronous; all signals registered on

positive edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal SDRAM banks for hiding row access/

precharge

• Programmable burst lengths: 1, 2, 4, 8 or full page

• Auto Precharge, includes CONCURRENT AUTO

PRECHARGE, and Auto Refresh Modes

• Self Refresh Mode

• 64ms, 4,096-cycle refresh

• LVTTL-compatible inputs and outputs

• Serial Presence-Detect (SPD)

OPTIONS MARKING

• Operating Temperature Range

Commercial (-0oC to +70oC) G

Extended (-40oC to +85oC) I

• Frequency/CAS Latency

133 MHz/CL = 2 (7.5, 133MHz SDRAMs) -13E

133 MHz/CL = 3 (7.5ns, 133 MHz SDRAMs) -133

100 MHz/CL = 2 (8ns, 125 MHz SDRAMs) -10E

66 MHz/CL = 2 (10ns, 100 MHz SDRAMs) -662

168-Pin DIMM

64MB, 66 MHz; 64MB, 100 MHz; 128MB

KEY SDRAM COMPONENT

TIMING PARAMETERS

MODULE SPEED CAS ACCESS SETUP HOLD

MARKING GRADE LATENCY TIME TIME TIME

-13E -7E 2 5.4ns 1.5ns 0.8ns

-133 -75 3 5.4ns 1.5ns 0.8ns

-10E -8E 2 6ns 2ns 1ns

-662 -10 2 9ns 3ns 1ns

Micron is a registered trademark of Micron Technology, Inc.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

GENERAL DESCRIPTION

The MT8LSDT864A and MT16LSDT1664A are high-

speed CMOS, dynamic random-access, 64MB and 128MB

memories organized in a x64 configuration. These

modules use internally configured quad-bank SDRAMs

with a synchronous interface (all signals are registered

on the positive edge of the clock signals CK0-CK3).

Read and write accesses to the SDRAM modules are

burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a

programmed sequence. Accesses begin with the regis-

tration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address bits

registered coincident with the ACTIVE command are

used to select the bank and row to be accessed (BA0, BA1

select the bank, A0-A11 select the row). The address bits

registered coincident with the READ or WRITE com-

mand are used to select the starting column location for

the burst access.

These modules provide for programmable READ or

WRITE burst lengths of 1, 2, 4 or 8 locations, or the full

page, with a burst terminate option. An auto precharge

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst

sequence.

These modules use an internal pipelined architec-

ture to achieve high-speed operation. This architecture

is compatible with the 2n rule of prefetch architectures,

but it also allows the column address to be changed on

every clock cycle to achieve a high-speed, fully random

access. Precharging one bank while accessing one of the

other three banks will hide the precharge cycles and

provide seamless, high-speed, random-access opera-

tion.

These modules are designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is pro-

vided, along with a power-saving, power-down mode.

All inputs and outputs are LVTTL-compatible.

SDRAM modules offer substantial advances in DRAM

operating performance, including the ability to syn-

chronously burst data at a high data rate with auto-

matic column-address generation, the ability to inter-

leave between internal banks in order to hide precharge

time and the capability to randomly change column

addresses on each clock cycle during a burst access. For

more information regarding SDRAM operation, refer to

the 64Mb x4, x8, x16 SDRAM data sheet.

SERIAL PRESENCE-DETECT OPERATION

These modules incorporate serial presence-detect

(SPD). The SPD function is implemented using a 2,048-

bit EEPROM. This nonvolatile storage device contains

256 bytes. The first 128 bytes can be programmed by

Micron to identify the module type and various SDRAM

organizations and timing parameters. The remaining

128 bytes of storage are available for use by the cus-

tomer. System READ/WRITE operations between the

master (system logic) and the slave EEPROM device

(DIMM) occur via a standard IIC bus using the DIMM’s

SCL (clock) and SDA (data) signals, together with SA(2:0),

which provide eight unique DIMM/EEPROM addresses.

PART NUMBERS

PART NUMBER CONFIG BUS SPEED TEMP

MT8LSDT864AG-13E_ 8 Meg x 64 133 MHz 0

to +70

MT8LSDT864AG-133_ 8 Meg x 64 133 MHz 0

to +70

MT8LSDT864AG-10E_ 8 Meg x 64 100 MHz 0

to +70

MT8LSDT864AG-662_ 8 Meg x 64 66 MHz 0

to +70

MT16LSDT1664AG-13E_ 16 Meg x 64 133MHz 0

to +70

MT16LSDT1664AG-133_ 16 Meg x 64 133 MHz 0

to +70

MT16LSDT1664AG-10E_ 16 Meg x 64 100 MHz 0

to +70

MT16LSDT1664AG-662_ 16 Meg x 64 66 MHz 0

to +70

MT8LSDT864AI-133_ 8 Meg x 64 133 MHz -40

to +85

MT8LSDT864AI-10E_ 8 Meg x 64 100 MHz -40

to +85

MT8LSDT864AI-662_ 8 Meg x 64 66 MHz -40

to +85

MT16LSDT1664AI-133_ 16 Meg x 64 133 MHz -40

to +85

MT16LSDT1664AI-10E_ 16 Meg x 64 100 MHz -40

to +85

MT16LSDT1664AI-662_ 16 Meg x 64 66 MHz -40

to +85

NOTE: All part numbers end with a two-place code (not

shown), designating component and PCB revisions.

Consult factory for current revision codes. Example:

MT8LSDT864AG-10EB4.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

MT8LSDT864A (64MB)

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQMB7

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQMB6

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQMB5

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQMB4

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQMB3

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB2

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQMB1

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB0

S2#

S0#

U0-U7 = MT48LC8M8A2GT SDRAMs

SA0

SPD

SDA

SA1

SA2

RAS#

CAS#

CKE0

WE#

RAS#: SDRAMs U0-U7

CAS#: SDRAMs U0-U7

CKE0: SDRAMs U0-U7

WE#: SDRAMs U0-U7

A0-A11: SDRAMs U0-U7

BA0: SDRAMs U0-U7

BA1: SDRAMs U0-U7

A0-A11

BA0

BA1

SDRAMs U0-U7

10pF

CK2, CK3

CK0

CK1

10pF

CK1, CK3

SDRAM

CK0

SDRAM

CK2

3.3pF

66 MHz VERSION

100 MHz/133 MHz VERSIONS

SCL

47K

U10

NOTE: All resistor values are 10 ohms.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

MT16LSDT1664A (128MB)

DQM CS#

U0-U15 = MT48LC8M8A2TG SDRAMs

SA0

SPD

SDA

SA1

SA2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQMB7

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQMB6

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQMB5

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQMB4

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQMB3

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB2

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQMB1

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB0

S2#

S0#

CKE1

CKE0

CAS#

RAS#

WE#

CKE: SDRAMs U8-U15

CKE: SDRAMs U0-U7

CAS#: SDRAMs U0-U15

RAS#: SDRAMs U0-U15

WE#: SDRAMs U0-U15

A0-A11: SDRAMs U0-U15

BA0: SDRAMs U0-U15

BA1: SDRAMs U0-U15

A0-A11

BA0

BA1

VDD

VSS

SDRAMs U0-U15

DQM CS#

U12

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM CS#

U14

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM CS#

U16

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM CS#

U18

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

S1#

DQM CS#

U11

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM CS#

U13

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM CS#

U17

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM CS#

U19

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

S3#

VDD

10K

SDRAM

CK0

3.3pF

SDRAM

CK1

3.3pF

SDRAM

CK2

3.3pF

SDRAM

CK3

3.3pF

SCL

47K

NOTE: All resistor values are 10 ohms unless otherwise specified.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

115, 111, 27 RAS#, CAS#, Input Command Inputs: RAS#, CAS# and WE# (along with

WE# S0#-S3#) define the command being entered.

42, 79, 125, 163 CK0-CK3 Input Clock: CK0-CK3 are driven by the system clock. All SDRAM

input signals are sampled on the positive edge of CK. CK

also increments the internal burst counter and controls

the output registers.

63, 128 CKE1, CKE0 Input Clock Enable: CKE0-CKE1 activate (HIGH) and deactivate

(LOW) the CK0-CK3 signals. Deactivating the clock provides

PRECHARGE POWER-DOWN and SELF REFRESH operation

(all banks idle), ACTIVE POWER-DOWN (row ACTIVE in any

bank) or CLOCK SUSPEND operation (burst access in

progress). CKE0-CKE1 are synchronous except after the

device enters power-down and self refresh modes, where

CKE0-CKE1 become asynchronous until after exiting the

same mode. The input buffers, including CK0-CK3, are

disabled during power-down and self refresh modes,

providing low standby power.

30, 45, 114, 129 S0#-S3# Input Chip Select: S0#-S3# enable (registered LOW) and disable

(registered HIGH) the command decoder. All commands are

masked when S0#-S3# are registered HIGH. S0#-S3# are

considered part of the command code.

28-29, 46-47, DQMB0-DQMB7 Input Input/Output Mask: DQMB is an input mask signal for write

112-113, 130-131 accesses and an output enable signal for read accesses.

Input data is masked when DQMB is sampled HIGH during

a WRITE cycle. The output buffers are placed in a High-Z

state (two-clock latency) when DQMB is sampled HIGH

during a READ cycle.

39, 122 BA0, BA1 Input Bank Address: BA0 and BA1 define to which bank the

ACTIVE, READ, WRITE or PRECHARGE command is being

applied.

33-38, 117-121, 123 A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE

command (row-address A0-A11) and READ/WRITE com-

mand (column-address A0-A8, with A10 defining AUTO

PRECHARGE) to select one location out of the memory

array in the respective bank. A10 is sampled during a

PRECHARGE command to determine if all banks are to be

precharged (A10 HIGH) or bank selected by BA0, BA1

(LOW). The address inputs also provide the op-code during

a LOAD MODE REGISTER command.

81 WP Input Write Protect: Serial presence-detect hardware write

protect. Applies to -10E/-10C versions only.

83 SCL Input Serial Clock for Presence-Detect: SCL is used to synchro-

nize the presence-detect data transfer to and from the

module.

165-167 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to

configure the presence-detect device.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

PIN DESCRIPTIONS (continued)

PIN NUMBERS SYMBOL TYPE DESCRIPTION

2-5, 7-11, 13-17, 19-20, DQ0-DQ63 Input/ Data I/Os: Data bus.

55-58, 60, 65-67, 69-72, Output

74-77, 86-89, 91-95,

97-101, 103-104, 139-142,

144, 149-151, 153-156,

158-161

82 SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin

Output used to transfer addresses and data into and data out of

the presence-detect portion of the module.

6, 18, 26, 40, 41, 49, 59, VDD Supply Power Supply: +3.3V ±0.3V.

73, 84, 90, 102, 110,

124, 133, 143, 157, 168

1, 12, 23, 32, 43, 54, 64, VSS Supply Ground.

68, 78, 85, 96, 107, 116,

127, 138, 148, 152, 162

126, 132 RFU –Reserved for Future Use: These pins should be left

unconnected.

31, 44, 48 DNU –Do Not Use: These pins are not connected on these

modules but are assigned pins on the compatible DRAM

version.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions

(Figures 1 and 2).

SPD START CONDITION

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has been

met.

SPD STOP CONDITION

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the SPD device into standby power mode.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (Figure 3).

The SPD device will always respond with an ac-

knowledge after recognition of a start condition and its

slave address. If both the device and a WRITE operation

have been selected, the SPD device will respond with an

acknowledge after the receipt of each subsequent eight

bit word. In the read mode the SPD device will transmit

eight bits of data, release the SDA line and monitor the

line for an acknowledge. If an acknowledge is detected

and no stop condition is generated by the master, the

slave will continue to transmit data. If an acknowledge

is not detected, the slave will terminate further data

transmissions and await the stop condition to return to

standby power mode.

Figure 1

Data Validity

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

SCL

SDA

START

BIT

STOP

BIT

Figure 2

Definition of Start and Stop

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

Figure 3

Acknowledge Response From Receiver

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

SERIAL PRESENCE-DETECT MATRIX

BYTE DESCRIPTION ENTRY (VERSION) SYMBOL MT8LSDT864A MT16LSDT1664A

0 NUMBER OF BYTES USED BY MICRON 128 80 80

1 TOTAL NUMBER OF SPD MEMORY BYTES 256 08 08

2 MEMORY TYPE SDRAM 04 04

3 NUMBER OF ROW ADDRESSES 12 0C 0C

4 NUMBER OF COLUMN ADDRESSES 9 09 09

5 NUMBER OF BANKS 1 or 2 01 02

6 MODULE DATA WIDTH 64 40 40

7 MODULE DATA WIDTH (continued) 0 00 00

8 MODULE VOLTAGE INTERFACE LEVELS LVTTL 01 01

9 SDRAM CYCLE TIME 7 (-13E) tCK 70 70

(CAS LATENCY = 3) 7.5 (-133) 75 75

8 (-10E) 80 80

10 (-662) A0 A0

10 SDRAM ACCESS FROM CLOCK 5.4 (-13E/-133) tAC 54 54

(CAS LATENCY = 3) 6 (-10E) 60 60

7.5 (-662) 75 75

11 MODULE CONFIGURATION TYPE NONPARITY 00 00

12 REFRESH RATE/TYPE 15.6µs/SELF 80 80

13 SDRAM WIDTH (PRIMARY SDRAM) 8 08 08

14 ERROR-CHECKING SDRAM DATA WIDTH NONE 00 00

15 MINIMUM CLOCK DELAY FROM BACK-TO- 1 tCCD 01 01

BACK RANDOM COLUMN ADDRESSES

16 BURST LENGTHS SUPPORTED 1, 2, 4, 8, PAGE 8F 8F

17 NUMBER OF BANKS ON SDRAM DEVICE 4 04 04

18 CAS LATENCIES SUPPORTED 2, 3 06 06

19 CS LATENCY 0 01 01

20 WE LATENCY 0 01 01

21 SDRAM MODULE ATTRIBUTES UNBUFFERED 00 00

22 SDRAM DEVICE ATTRIBUTES: GENERAL 0E 0E 0E

23 SDRAM CYCLE TIME 7.5 (-13E) tCK 75 75

(CAS LATENCY = 2) 10 (-133/-10E) A0 A0

15 (-662) F0 F0

24 SDRAM ACCESS FROM CK 5.4 (-13E) tAC 54 54

(CAS LATENCY = 2) 6 (-133/-10E) 60 60

9 (-662) 90 90

25 SDRAM CYCLE TIME – tCK 00 00

(CAS LATENCY = 1)

26 SDRAM ACCESS FROM CK –tAC 00 00

(CAS LATENCY = 1)

27 MINIMUM ROW PRECHARGE TIME 15 (-13E) tRP 0F 0F

20 (-133/-10E) 14 14

30 (-662) 1E 1E

28 MINIMUM ROW ACTIVE TO ROW ACTIVE 14 (-13E) tRRD 0E 0E

15 (-133) 0F 0F

20 (-10E/-662) 14 14

NOTE: “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

SERIAL PRESENCE-DETECT MATRIX (continued)

BYTE DESCRIPTION ENTRY (VERSION) SYMBOL MT8LSDT864A MT16LSDT1664A

29 MINIMUM RAS# TO CAS# DELAY 15 (-13E) tRCD 0F 0F

20 (-133/-10E) 14 14

30 (-662) 1E 1E

30 MINIMUM RAS# PULSE WIDTH 37 (-13E) tRAS 25 25

44 (-133) 2C 2C

50 (-10E) 32 32

60 (-662) 3C 3C

31 MODULE BANK DENSITY 64MB 10 10

32 COMMAND AND ADDRESS SETUP TIME 1.5 (-13E/-133)

AS,

CMS

15 15

2 (-10E/-662) 20 20

33 COMMAND AND ADDRESS HOLD TIME 0.8 (-13E/-133)

AH,

CMH

08 08

1 (-10E/-662) 10 10

34 DATA SIGNAL INPUT SETUP TIME 1.5 (-13E/-133) tDS 15 15

2 (-10E/-662) 20 20

35 DATA SIGNAL INPUT HOLD TIME` 0.8(-13E/-133) tDH 08 08

1 (-10E/-662) 10 10

36-61 RESERVED 00 00

62 SPD REVISION REV. 1.2 12 12

63 CHECKSUM FOR BYTES 0-62 (-13E) 4F 50

(-133) 9D 9E

(-10E) E5 E6

(-662) B8 B9

64 MANUFACTURER’S JEDEC ID CODE MICRON 2C 2C

65-71 MANUFACTURER’S JEDEC ID CODE FF FF

(continued)

72 MANUFACTURING LOCATION 01 01

02 02

03 03

04 04

05 05

06 06

07 07

08 08

09 09

73-90 MODULE PART NUMBER (ASCII) xx xx

91 PCB IDENTIFICATION CODE 1 01 01

20202

30303

40404

50505

NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

2. x = Variable Data.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

SERIAL PRESENCE-DETECT MATRIX (continued)

BYTE DESCRIPTION ENTRY (VERSION) SYMBOL MT8LSDT864A MT16LSDT1664A

91 PCB IDENTIFICATION CODE (continued) 6 06 06

70707

80808

90909

92 IDENTIFICATION CODE (continued) 0 00 00

93 YEAR OF MANUFACTURE IN BCD xx xx

94 WEEK OF MANUFACTURE IN BCD xx xx

95-98 MODULE SERIAL NUMBER xx xx

99-125 MANUFACTURER-SPECIFIC DATA (RSVD) ––

126 SYSTEM FREQUENCY 100 MHz

(-13E/-133/-10E) 64 64

66 MHz (-662) 66 66

127 SDRAM COMPONENT AND CLOCK DETAIL (-13E/-133/-10E) AF FF

(-662) CF FF

NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

2. x = Variable Data.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

COMMANDS

Truth Table 1 provides a general reference of avail-

able commands. For a more detailed description of

TRUTH TABLE 1 – COMMANDS AND DQMB OPERATION

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQs NOTES

COMMAND INHIBIT (NOP) H XXXX X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3

READ (Select bank and column, and start READ burst) L H L H L/H8Bank/Col X 4

WRITE (Select bank and column, and start WRITE burst) L H L L L/H8Bank/Col Valid 4

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or L L L H X X X 6, 7

SELF REFRESH (Enter self refresh mode)

LOAD MODE REGISTER L L L L X Op-Code X 2

Write Enable/Output Enable ––––L–Active 8

Write Inhibit/Output High-Z ––––H–High-Z 8

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A11 define the op-code written to the Mode Register.

3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.

4. A0-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables

the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine which bank is being precharged. A10 HIGH: all banks are precharged and BA0, BA1 are

“Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

commands and operations, refer to the 64Mb x4, x8,

x16 SDRAM data sheet.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

200-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

40 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

80 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0-A8 Cn, Cn + 1, Cn + 2

Page Cn + 3, Cn + 4... Not supported

(y) (location 0-y) …Cn - 1,

Cn…

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Op Mode

A10

A11

Reserved* WB

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M11, M10 = “0, 0”

to ensure compatibility

with future devices.

Figure 4

Mode Register Definition

NOTE: 1. For full-page accesses: y = 512.

2. For a burst length of two, A1-A8 select the block-

of-two burst; A0 selects the starting column

within the block.

3. For a burst length of four, A2-A8 select the block-

of-four burst; A0-A1 select the starting column

within the block.

4. For a burst length of eight, A3-A8 select the

block-of-eight burst; A0-A2 select the starting

column within the block.

5. For a full-page burst, the full row is selected, and

A0-A8 select the starting column.

6. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

7. For a burst length of one, A0-A8 select the unique

column to be accessed, and Mode Register bit M3

is ignored.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD Supply Relative to VSS .... -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to VSS ..................................... -1V to +4.6V

Operating Temperature, TA (ambient) ... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +125°C

Power Dissipation ................................................... 8W

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1,2) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SUPPLY VOLTAGE VDD 3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2VDD + 0.3 V 3

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.5 0.8 V 3

INPUT LEAKAGE CURRENT: DQMB0-DQMB7 II1-10 10 µA 4

Any input 0V ≤ VIN ≤ VDD CK0-CK3, S0#-S3# II2-20 20 µA

(All other pins not under test = 0V) CKE0-CKE1 II3-40 40 µA

RAS#, CAS#, A0-A11, II4-80 80 µA 4

BA0-BA1, WE#

OUTPUT LEAKAGE CURRENT: DQ0-DQ63 IOZ -10 10 µA 4

DQs are disabled; 0V ≤ VOUT ≤ VDD

OUTPUT LEVELS: VOH 2.4 –V

Output High Voltage (IOUT = -4mA)

Output Low Voltage (IOUT = 4mA) VOL –0.4 V

NOTE: 1. All voltages referenced to VSS.

2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper

device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF

refresh requirement is exceeded.

3. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of

the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than

one third of the cycle rate.

4. 64MB module values will be half of those shown.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

IDD SPECIFICATIONS AND CONDITIONS

(Notes: 1-4) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL SIZE -13E -133 -10E -662 UNITS NOTES

OPERATING CURRENT: Active Mode; 64MB 1,000 920 760 720 5, 6,

Burst = 2; READ or WRITE; tRC = tRC (MIN); IDD1mA 7, 8

CAS latency = 3 128MB 1,360 1,280 1,040 960

STANDBY CURRENT: Power-Down Mode; IDD264MB 16 16 16 24 mA 8

CKE = LOW; All banks idle 128MB 32 32 32 48

STANDBY CURRENT: Active Mode; S0#-S3# = HIGH; 64MB 360 360 280 240 5, 9,

CKE = HIGH; All banks active after tRCD met; IDD3mA 7, 8

No accesses in progress 128MB 720 720 560 480

OPERATING CURRENT: Burst Mode; Continuous burst; 64MB 1,200 1,120 960 840 5, 6,

READ or WRITE; All banks active; IDD4mA 7, 8

CAS latency = 3 128MB 1,560 1,480 1,240 1,080

AUTO REFRESH CURRENT: IDD564MB 1,840 1,680 1,520 1,360 mA 5, 6,

CKE = HIGH; S0#-S3# = HIGH tRC = tRC (MIN); CL = 3 128MB 2,200 2,040 1,800 1,600 7, 8,

IDD664MB 24 24 24 24 mA 9, 10

tRC = 15.625µs; CL = 3 128MB 48 48 48 48

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD764MB 8 8 8 16 mA 11

128MB 16 16 16 32

MAX

NOTE: 1. All voltages referenced to VSS.

2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper

device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF

refresh requirement is exceeded.

3. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input

transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V

crosspover point.

4. IDD specifications are tested after the device is properly initialized.

5. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the

outputs open.

6. The IDD current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is

slower as the CAS latency is reduced.

7. Address transitions average one transition every two clocks.

8. tCK = 7.5ns for -133, 10ns for -10E and 15ns for -662.

9. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL

levels.

10. CKE is high during refresh command period (tRFC [MIN]) else CKE is low. The IDD6 limit is actually a nominal value and

does not result in a fail value.

11. Enables on-chip refresh and address counters.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

CAPACITANCE

(Note: 1)

PARAMETER SYMBOL MIN MAX MIN MAX UNITS

Input Capacitance: A0-A11, BA0, BA1, RAS#, CAS#, WE# CI122 30 44 60 pF

Input Capacitance: CK0-CK3 CI212 18 12 18 pF

Input Capacitance: S0#-S3# CI312 16 12 16 pF

Input Capacitance: CKE0, CKE1 CI422 30 22 30 pF

Input Capacitance: DQMB0#-DQMB7# CI54679pF

Input Capacitance: SCL, SA0-SA2 CI6–6–6pF

Input/Output Capacitance: DQ0-DQ63, SDA CIO 6 8 10 14 pF

64MB 128MB

NOTE: This parameter is sampled. VDD = +3.3V; f = 1 MHz.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

SDRAM COMPONENT* AC ELECTRICAL CHARACTERISTICS

(Notes: 1-6; notes appear below and on next page)

AC CHARACTERISTICS -13E (PC133) -133 (PC133) -10E (PC100) -662 (PC66)

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES

Access time from CK (pos. edge) CL = 3 tAC 5.4 5.4 6 7.5 ns 7

CL = 2 tAC 5.4 6 6 9 ns

Address hold time tAH 0.8 0.8 1 1 ns

Address setup time tAS 1.5 1.5 2 2 ns

CK high-level width tCH 2.5 2.5 3 3 ns

CK low-level width tCL 2.5 2.5 3 3 ns

Clock cycle time CL = 3 tCK 7 7.5 8 10 ns 8

CL = 2 tCK 7.5 10 10 15 ns 8

CKE hold time tCKH 0.8 0.8 1 1 ns

CKE setup time tCKS 1.5 1.5 2 2 ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 1 1 ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 2 2 ns

Data-in hold time tDH 0.8 0.8 1 1 ns

Data-in setup time tDS 1.5 1.5 2 2 ns

Data-out high-impedance time CL = 3 tHZ 5.4 5.4 6 8 ns 9

CL = 2 tHZ 5.4 7 7 10 ns 9

Data-out low-impedance time tLZ 1 1 1 2 ns

Data-out hold time (load) tOH 2.7 2.7 3 3 ns

Data-out hold time (no load) tOHN1.8 1.8 1.8 n/a ns 10

ACTIVE to PRECHARGE command tRAS 37 120,000 44 120,000 50 120,000 60 120,000 ns

ACTIVE to ACTIVE command period tRC 60 66 70 90 ns

AUTO REFRESH period tRCAR 15 66 70 90 ns

ACTIVE to READ or WRITE delay tRCD 64 20 20 30 ns

Refresh period (4,096 cycles) tREF 66 64 64 64 ms

PRECHARGE command period tRP 15 20 20 30 ns

ACTIVE bank A to ACTIVE bank B command tRRD 14 15 20 20 ns

Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 1 1.2 ns 11

WRITE recovery time tWR 1 CK + 1 CK + 1 CK + 1 CK + –12

7ns 7.5ns 8ns 8ns

14 15 15 15 ns 13

Exit SELF REFRESH to ACTIVE command tXSR 67 75 80 90 ns 14

*Specifications for the SDRAM components used on the module.

NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature

range (0°C ≤ TA ≤ +70°C) is ensured.

2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper

device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF

refresh requirement is exceeded.

3. AC characteristics assume tT = 1ns.

4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or

between VIL and VIH) in a monotonic manner.

5. Outputs measured at 1.5V with equivalent load:

50pF

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

NOTES: (continued)

6. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input

transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V

crosspover point.

7. tAC for -133 at CL = 3 with no load is 4.6ns and is guaranteed by design.

8. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints

specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE com-

mands). CKE may be used to reduce the data rate.

9. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The

last valid data element will meet tOH before going High-Z.

10. Parameter guaranteed by design.

11. AC characteristics assume tT = 1ns.

12. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/8ns after the first clock delay, after the

last WRITE is executed.

13. Precharge mode only.

14. CK must be toggled a minimum of two times during this period.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

AC FUNCTIONAL CHARACTERISTICS

(Notes: 1-6)

PARAMETER SYMBOL -133 -13E/ -10E -662 UNITS NOTES

READ/WRITE command to READ/WRITE command tCCD 1 1 1 tCK 7

CKE to clock disable or power-down entry mode tCKED 1 1 1 tCK 8

CKE to clock enable or power-down exit setup mode tPED 1 1 1 tCK 8

DQM to input data delay tDQD000

tCK 7

DQM to data mask during WRITEs tDQM 0 0 0 tCK 7

DQM to data high-impedance during READs tDQZ 2 2 2 tCK 7

WRITE command to input data delay tDWD 0 0 0 tCK 7

Data-in to ACTIVE command tDAL 5 4 4 tCK 9, 10

Data-in to PRECHARGE command tDPL 2 2 2 tCK 10, 11

Last data-in to burst STOP command tBDL 1 1 1 tCK 7

Last data-in to new READ/WRITE command tCDL 1 1 1 tCK 7

Last data-in to PRECHARGE command tRDL 2 2 2 tCK 10, 11

LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 2 tCK 12

Data-out to high-impedance from PRECHARGE command CL = 3 tROH 3 3 3 tCK 7

CL = 2 tROH 2 2 2 tCK 7

NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature

range (0°C ≤ TA ≤ +70°C) is ensured.

2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper

device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF

refresh requirement is exceeded.

3. AC characteristics assume tT = 1ns.

4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or

between VIL and VIH) in a monotonic manner.

5. Outputs measured at 1.5V with equivalent load:

6. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input

transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V

crosspover point.

7. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.

8. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.

9. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate.

10. Based on tCK = 143 MHz for 13E, tCK = 133 MHz for -75, 100 MHz for -10E and 66 MHz for -662.

11. Timing actually specified by tWR.

12. JEDEC and PC100 specify three clocks.

50pF

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS

(Note: 1) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.3 3.5 µs

Time the bus must be free before a new transition can start tBUF 4.7 µs

Data-out hold time tDH 300 ns

SDA and SCL fall time tF 300 ns

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 4 µs

Clock HIGH period tHIGH 4 µs

Noise suppression time constant at SCL, SDA inputs tI 100 ns

Clock LOW period tLOW 4.7 µs

SDA and SCL rise time tR1µs

SCL clock frequency tSCL 100 KHz

Data-in setup time tSU:DAT 250 ns

Start condition setup time tSU:STA 4.7 µs

Stop condition setup time tSU:STO 4.7 µs

WRITE cycle time tWRC 10 ms 2

SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS

(Note: 1) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SUPPLY VOLTAGE VDD 3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD x 0.7 VDD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4 V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10 µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10 µA

STANDBY CURRENT: ISB –30 µA

SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10%

POWER SUPPLY CURRENT: IDD –2mA

SCL clock frequency = 100 KHz

NOTE: 1. All voltages referenced to VSS.

2. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA

remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

SERIAL PRESENCE-DETECT EEPROM

TIMING PARAMETERS

SYMBOL MIN MAX UNITS

tAA 0.3 3.5 µs

tBUF 4.7 µs

tDH 300 ns

tF 300 ns

tHD:DAT 0 µs

tHD:STA 4 µs

SPD EEPROM

SYMBOL MIN MAX UNITS

tHIGH 4 µs

tLOW 4.7 µs

tR1µs

tSU:DAT 250 ns

tSU:STA 4.7 µs

tSU:STO 4.7 µs

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

168-PIN DIMM

(64MB, 66 MHz)

.125 (3.18)

MAX

.054 (1.37)

.046 (1.17)

PIN 1 (PIN 85 ON BACKSIDE)

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

4.550 (115.57)

.050 (1.27)

TYP

.118 (3.00)

TYP .039 (1.00)

TYP

.079 (2.00) R

(2X)

.039 (1.00)R (2X)

FRONT VIEW

.128 (3.25)

.118 (3.00)

PIN 84 (PIN 168 ON BACKSIDE)

(2X)

1.255 (31.88)

1.245 (31.62)

.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

5.256 (133.50)

5.244 (133.20)

168-PIN DIMM

(64MB, 100 MHz)

.125 (3.18)

MAX

.054 (1.37)

.046 (1.17)

PIN 1 (PIN 85 ON BACKSIDE)

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

4.550 (115.57)

.050 (1.27)

TYP

.118 (3.00)

TYP .039 (1.00)

TYP

.079 (2.00) R

(2X)

.039 (1.00)R (2X)

FRONT VIEW

.128 (3.25)

.118 (3.00)

PIN 84 (PIN 168 ON BACKSIDE)

(2X)

1.380 (35.05)

1.370 (34.80)

.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

5.256 (133.50)

5.244 (133.20)

NOTE: All dimensions in inches (millimeters) MAX or typical where noted.

MIN

8, 16 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

8, 16 MEG x 64

SDRAM DIMMs

NOTE: All dimensions in inches (millimeters) MAX or typical where noted.

MIN

168-PIN DIMM

(128MB)

.157 (4.00)

MAX

.054 (1.37)

.046 (1.17)

PIN 1 (PIN 85 ON BACKSIDE)

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

4.550 (115.57)

.050 (1.27)

TYP

.118 (3.00)

TYP .039 (1.00)

TYP

.079 (2.00) R

(2X)

.039 (1.00)R (2X)

FRONT VIEW

.128 (3.25)

.118 (3.00)

PIN 84 (PIN 168 ON BACKSIDE)

(2X)

.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

1.380 (35.05)

1.370 (34.80)

5.256 (133.50)

5.244 (133.20)

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

PRODUCT GUIDE

M3Q00

PART NUMBERING GUIDESPART SELECTOR ORDER INFORMATION

MICRON. A WORLD MEMORY LEADER

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MODULE

ORDER INFORMATION

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Tel: 44-1344-750750 • Fax: 44-1344-750710

Micron Semiconductor (Deutschland) GmbH

Sternstrasse 20 • D-85609 Aschheim • Germany • Tel: 49-89-904-8720 • Fax: 49-89-904-87250

Micron Semiconductor Asia, Pte. Ltd.

5 Upper Aljunied Link #06-06 • Quartz Industrial Bldg. • Singapore 367903 • Tel: 65-287-6006 • Fax: 65-287-6556

Micron Technology Asia Pacific, Inc., Taiwan Branch

Suite 1010, 10th Floor • 333 Keelung Road, Sec 1 • Taipei, 110 Taiwan, ROC • Tel: 886-2-2757-6622 • Fax: 886-2-2757-6656

Micron Technology Italia, Srl

Via Antonio Pacinotti 5/7 • Nucleo Industriale (AQ), Building 2 • Avezzano (AQ) Italia 67051 • Tel: 39-0863-423206 • Fax: 39-0863-423283

Micron Technology Japan, K.K.

4-30 Shiba-Koen 3-chome • 32 Mori Building 8F • Minato-ku • Tokyo 105, Japan • Tel: 81-3-3436-5666 • Fax: 81-3-3436-1444

Micron is a registered trademark of Micron Technology, Inc.

Rambus and RDRAM are registered trademarks and RIMM is a

trademark of Rambus Inc. Products and specifications are

subject to change without notice.

Rev. 8/00

PART NUMBERING GUIDES

MICRON. A WORLD MEMORY LEADER

DRAM MODULE NUMBERING

SDRAM/DDR SDRAM/RDRAM® MODULE NUMBERING

MT18LD1672 A G-5 X

Micron Technology

Product Family

D = DRAM

DT = DRAM TSOP

Process Technology

L = Low Voltage (3.3V)

Module Special Designator

Blank = Fast Page Mode

X = Extended Data-Out

L = Extended Refresh

S = Self Refresh

Package Code

G = Gold-Plated SIMM/DIMM

M = Tin/Lead-Plated SIMM

HG = Small-Outline Gold DIMM

DG = Low-Profile, Double-Sided SIMM

(gold-plated)

DM = Low-Profile, Double-Sided SIMM

(tin/lead-plated)

Access Time

50ns = -5

60ns = -6

70ns = -7

Number of

Memory Components

Depth

Width

Module Version

A = 168-pin DIMM; unbuffered,

serial presence-detect

MT18L SDT1672 AG-10EC 7

Micron Technology

Product Family

SD = SDRAM

SDT = SDRAM TSOP

DDT = DDR SDRAM TSOP

VR = Rambus®

Process Technology

L = 3.3V

V = 2.5V

Printed Circuit Board

Revision Designator

Package Code

G = Gold-Plated SIMM/DIMM

HG = Small-Outline Gold DIMM

DG = Low-Profile, Double-Sided DIMM

Memory Bus Speed

66 MHz CAS Latency 2 (-10 SDRAMs) = -662

100 MHz CAS Latency 3 (-8C SDRAMs) = -10C

100 MHz CAS Latency 2 (-8E SDRAMs) = -10E

133 MHz CAS Latency 3 (-75 SDRAMs) = -133

133 MHz CAS Latency 2 (-7E SDRAMs) = -13E

200 MHz data rate, CAS Latency 2 (-8 DDR SDRAMs) = -202

266 MHz data rate, CAS Latency 2.5 (-75 DDR SDRAMs) = -265

266 MHz data rate, CAS Latency 2 (-7 DDR SDRAMs) = -262

700 MHz data rate, 53ns access time = -750

700 MHz data rate, 45ns access time = -745

800 MHz data rate, 53ns access time = -850

800 MHz data rate, 45ns access time = -845

800 MHz data rate, 40ns access time = -840

Number of

Memory Components

Depth

Width

Module Version

SDRAM

A = 168-pin/184-pin DIMM and 184-pin RIMM™;

unbuffered, serial presence-detect

U = 100-pin DIMM; unbuffered,

serial presence-detect

G = 144-pin graphics SODIMM

Die Revision Designator

MICRON. A WORLD MEMORY LEADER

DRAM MODULE PART SELECTOR

Data sheets are available at

www.micronsemi.com/datasheets/datasheet.html.

DRAM MODULES

DS = Double Sided, SS = Single Sided; M = Tin Plated, G = Gold Plated; U = 100-pin DIMM,

H = Small-Outline DIMM (SODIMM), (A) = see footnote references below,

(X) = EDO, no X = FPM version

MODULE KEY

72-pin SODIMM 4MB SS 1 Meg x 32 3.3V Gold (2) 1 Meg x 16 TSOP MT2LDT132HG 60 1.000" Now Now

8MB SS 2 Meg x 32 3.3V Gold (4) 1 Meg x 16 TSOP MT4LDT232HG 60 1.000" Now Now

16MB SS 4 Meg x 32 3.3V Gold (2) 4 Meg x 16 TSOP MT2LDT432HG 60 1.000" Now Now

16MB DS 4 Meg x 32 3.3V Gold (8) 4 Meg x 4 TSOP MT8LDT432HG 60 1.000" Now Now

32MB DS 8 Meg x 32 3.3V Gold (4) 4 Meg x 16 TSOP MT4LDT832HG 60 1.000" Now Now

72-pin SIMM 4MB SS 1 Meg x 32 Gold/Tin (2) 1 Meg x 16 MT2D132G/M 50, 60 .800" Now Now

8MB DS 2 Meg x 32 Gold/Tin (4) 1 Meg x 16 MT4D232DG/M 50, 60 .800" Now Now

16MB SS 4 Meg x 32 Gold/Tin (8) 4 Meg x 4 MT8D432G/M 50, 60 1.000" Now Now

16MB SS 4 Meg x 36 ECC Gold/Tin (9) 4 Meg x 4 MT9D436G/M 50, 60 1.000" Now Now

32MB DS 8 Meg x 36 ECC Gold/Tin (18) 4 Meg x 4 MT18D836G/M 50, 60 1.000" Now Now

32MB DS 8 Meg x 32 Gold/Tin (16) 4 Meg x 4 MT16D832G/M 50, 60 1.000" Now Now

100-pin DIMM 4MB SS 1 Meg x 32 3.3V Gold (2) 1 Meg x 16 MT2LD132UG 60 1.000" Now Now

8MB SS 2 Meg x 32 3.3V Gold (4) 1 Meg x 16 MT4LD232UG 60 1.000" Now Now

16MB SS 4 Meg x 32 3.3V Gold (2) 4 Meg x 16 TSOP MT2LDT432UG 60 1.000" Now Now

32MB DS 8 Meg x 32 3.3V Gold (4) 4 Meg x 16 TSOP MT4LDT832UG 60 1.000" Now Now

144-pin SODIMM 32MB DS 4 Meg x 64 3.3V Gold (4) 4 Meg x 16 TSOP MT4LDT464HG (S) 50, 60 1.000" Now Now

64MB DS 8 Meg x 64 3.3V Gold (8) 8 Meg x 8 TSOP MT8LDT864HG (S) 60 1.050" Now Now

168-pin DIMM 8MB DS 1 Meg x 64 3.3V Gold (4) 1 Meg x 16 TSOP MT4LDT164AG 60 1.000" Now Now

32MB SS 4 Meg x 64 3.3V Gold (4) 4 Meg x 16 TSOP MT4LDT464AG 50, 60 1.000" Now Now

32MB DS 4 Meg x 64 3.3V Gold (16) 4 Meg x 4 MT16LD464AG 60 1.000" Now Now

32MB DS 4 Meg x 72 3.3V ECC Gold (18) 4 Meg x 4 MT18LD472(A)G 60 UB = 1.000" Now Now

B = 1.000"

32MB SS 4 Meg x 72 3.3V ECC Gold (5) 4 Meg x 16 TSOP MT5LDT472(A)G 60 UB = 1.000" Now Now

B = 1.050"

64MB SS 8 Meg x 64 3.3V Gold (8) 8 Meg x 8 MT8LD864AG 50, 60 1.100" Now Now

64MB DS 8 Meg x 72 3.3V ECC Gold (36) 4 Meg x 4 MT36LD872(A)G 60 UB = 1.500" Now Now

B = 1.500"

64MB SS 8 Meg x 72 3.3V ECC Gold (9) 8 Meg x 8 MT9LD872(A)G 50, 60 UB = 1.100" Now Now

B = 1.250"

64MB SS 8 Meg x 72 3.3V ECC Gold (9) 8 Meg x 8 TSOP MT9LDT872G 50, 60 1.350" Now Now

128MB DS 16 Meg x 64 3.3V Gold (16) 16 Meg x 4 MT16LD1664AG 50, 60 1.250" Now Now

128MB DS 16 Meg x 72 3.3V ECC Gold (18) 16 Meg x 4 MT18LD1672(A)G 50, 60 UB = 1.250" Now Now

B = 1.100"

128MB DS 16 Meg x 72 3.3V ECC Gold (18) 16 Meg x 4 TSOP MT18LDT1672G 50, 60 2.000" Now Now

256MB DS 32 Meg x 72 3.3V ECC Gold (36) 16 Meg x 4 MT36LD3272G 50, 60 2.000" Now Now

256MB DS 32 Meg x 72 3.3V ECC Gold (36) 16 Meg x 4 TSOP MT36LDT3272G 50, 60 2.000" Now Now

*All DRAM modules are available in EDO or Fast Page Mode.

DS = Double Sided; SS = Single Sided; (A) = 8 CAS, SPD version, unbuffered; no A = Buffered version for x72 DIMMs; UB = Unbuffered; B = Buffered.

Highlighted parts are not recommended for new designs.

Module Module Speed

Family Density Description Components Part Number (ns) Height Sample Prod.

MICRON. A WORLD MEMORY LEADER

DS = Double Sided, SS = Single Sided; M = Tin Plated, G = Gold Plated; U = 100-pin DIMM,

UDG = Double-sided, dual-bank 100-pin DIMM, H = Small-Outline DIMM (SODIMM),

(A) = see footnote references below

MODULE KEY

SDRAM MODULES

Module Module

Family Density Description Components Part Number Speed Die Rev. PCB (Height) MHz Samp. Prod. Note

100-pin DIMM 4MB SS 1 Meg x 32 3.3V Gold (2)1 Meg x 16 TSOP MT2LSDT132UG -10E1 E = Y72G 1 = 6649 (1")100 Now Now

-8E1 125 Now Now

8MB DS 2 Meg x 32 3.3V Gold (4)1 Meg x 16 TSOP MT4LSDT232UDG -10E1 E = Y72G 1 = 6649 (1")100 Now Now

-8E1 125 Now Now

16MB SS 4 Meg x 32 3.3V Gold (2)4 Meg x 16 TSOP MT2LSDT432UG -10C1 C = Y84 1 = 6660 (1")100 Now Now

-8C1 125 Now Now

32MB DS 8 Meg x 32 3.3V Gold (4)4 Meg x 16 TSOP MT4LSDT832UDG -10C1 C = Y84 1 = 6660 (1")100 Now Now

-8C1 125 Now Now

64MB DS 16 Meg x 32 3.3V Gold (4)16 Meg x 8 TSOP MT4LSDT1632UG -10B1 B = Y85B 1 = 6692 (1.15”) 100 Now Now

-8B1 125 Now Now

128MB DS 32 Meg x 32 3.3V Gold (8) 16 Meg x 8 TSOP MT8LSDT3232UG -10B1 B = Y85B 1 = 6692 (1.15”) 100 Now Now

-8B1 125 Now Now

144-pin SODIMM 32MB DS 4 Meg x 64 3.3V Gold (4)4 Meg x 16 TSOP MT4LSDT464(L)HG -662C1 C = Y84 1 = 6645 (1.15 " )66 Now Now

-662C2 2 = 6669 (1")66 Now Now

-10EC3 3 = 0118B (1")100 Now Now PC100

64MB DS 8 Meg x 64 3.3V Gold (8)8 Meg x 8 TSOP MT8LSDT864(L)HG -662C3 C = Y84 3 = 6678 (1.05")66 Now Now

4 Meg x 16 TSOP MT8LSDT864(L)HG -10EC5 5 = 0115C (1.25")100 Now Now PC100

64MB DS 8 Meg x 64 3.3V Gold (4)8 Meg x 16 TSOP MT4LSDT864(L)HG -10EB1 B = Y85B 1 = 0118B (1")100 Now Now

-133B1 133 Now Now

128MB DS 16 Meg x 64 3.3V Gold (8)16 Meg x 8 TSOP MT8LSDT1664(L)HG -662B2 B = Y85B 1 = 0115C (1.25")66 Now Now

(8) 8 Meg x 16 TSOP -10EB1 2 = 6678 (1.05")100 Now Now PC100

168-pin DIMM 32MB SS 4 Meg x 64 3.3V Gold (4)4 Meg x 16 TSOP MT4LSDT464AG -662C1 C = Y84 1 = 6652 (1")66 Now Now

Unbuffered -662C6 6 = 0134 (1”) 66 Now Now

-10EC6 100 Now Now

-133C6 133 Now Now CL3

-13EC6 133 Now Now CL2

64MB SS 8 Meg x 64 3.3V Gold (8)8 Meg x 8 TSOP MT8LSDT864AG -662C7 C = Y84 7 = 0104B (1.375")66 Now Now

-10EC7 100 Now Now

-133C7 133 Now Now CL3

-13EC7 133 Now Now CL2

64MB SS 8 Meg x 64 3.3V Gold (4)8 Meg x 16 TSOP MT4LSDT864AG -662B1 B = Y85B 1 = 0134 (1")66 Now Now

-10EB1 100 Now Now

-133B1 133 Now Now CL3

-13EB1 133 Now Now CL2

64MB SS 8 Meg x 72 3.3V ECC Gold (9)8 Meg x 8 TSOP MT9LSDT872AG -662C7 C = Y84 7 = 0104B (1.375”) 66 Now Now

-10EC7 100 Now Now

-133C7 133 Now Now CL3

-13EC7 133 Now Now CL2

128MB DS 16 Meg x 64 3.3V Gold (16)8 Meg x 8 TSOP MT16LSDT1664AG -662C7 C = Y84 7 = 0104B (1.375")66 Now Now

-10EC7 100 Now Now

-133C7 133 Now Now CL3

-13EC7 133 Now Now CL2

128MB SS 16 Meg x 64 3.3V Gold (8)16 Meg x 8 TSOP MT8LSDT1664AG -662B1 B = Y85B 1 = 0104 (1.375")66 Now Now

-10EB1 100 Now Now

-133B1 133 Now Now CL3

-13EB1 133 Now Now CL2

128MB DS 16 Meg x 72 3.3V ECC Gold (18)8 Meg x 8 TSOP MT18LSDT1672AG -662C7 C = Y84 7 = 0104B (1.375")66 Now Now

-10EC7 100 Now Now

-133C7 133 Now Now CL3

-13EC7 133 Now Now CL2

128MB SS 16 Meg x 72 3.3V Gold (9)16 Meg x 8 TSOP MT9LSDT1672AG -662B1 B = Y85B 1 = 0104 (1.375")66 Now Now

-10EB1 100 Now Now

-133B1 133 Now Now CL3

-13EB1 133 Now Now CL2

256MB DS 32 Meg x 64 3.3V Gold (16)16 Meg x 8 TSOP MT16LSDT3264AG -10EB1 B = Y85B 1 = 0104B (1.375")100 Now Now

-133B1 133 Now Now CL3

-13EB1 133 Now Now CL2

256MB DS 32 Meg x 72 3.3V ECC Gold (18)16 Meg x 8 TSOP MT18LSDT3272AG -10EB1 B = Y85B 1 = 0104B (1.375")100 Now Now

-133B1 133 Now Now CL3

-13EB1 133 Now Now CL2

(A) = SPD version, unbuffered; no A = registered version for x72 DIMMs. 144- and 168-pin DIMMs (66 MHz/100 MHz) adhere to Intel’s 4-clock SDRAM module specs (66 MHz uses -10

components,100 MHz uses -8, 133 MHz uses -75). For 100-pin DIMMs, 100 MHz uses -10 components; adheres to JEDEC standard. Highlighted parts are available in PC133.

MICRON. A WORLD MEMORY LEADER

We’re ready with DDR. See below . . .

SDRAM MODULES (continued)

Module Module

Family Density Description Components Part Number Speed Die Rev. PCB (Height) MHz Samp. Prod. Note

168-pin DIMM 64MB SS 8 Meg x 72 3.3V ECC Gold (9)8 Meg x 8 TSOP MT9LSDT872G -10EC3 C = Y84 3 = 0144 (1.5”) 100 Now Now

Registered

-133C3 133 Now Now CL3

-13EC3 133 Now Now

CL2

128MB DS 16 Meg x 72 3.3V ECC Gold (18)16 Meg x 4 TSOP MT18LSDT1672G -10EC2 C = Y84 2 = 0129 (1.7")100 Now Now

-133C2 133 Now Now CL3

-13EC2 133 Now Now CL2

128MB SS 16 Meg x 72 3.3V Gold (9)16 Meg x 8 TSOP MT9LSDT1672G -10EB1 B = Y85B 1 = 0144 (1.7")100 Now Now

-133B1 133 Now Now CL3

-13EB1 133 Now Now CL2

256MB DS 32 Meg x 72 3.3V ECC Gold (18)32 Meg x 4 TSOP MT18LSDT3272G -10EB1 B = Y85B 1 = 0129 (1.7”) 100 Now Now

-133B1 133 Now Now CL3

-13EB1 133 Now Now CL2

512MB DS 64 Meg x 72 3.3V ECC Gold (36)32 Meg x 4 FBGA MT36LSDF6472G -10EB1 B = Y85B 1 = 0123 (1.6")100 Now Now 11x13 pkg.

-133B2

2 = TBD (1.6”)

133 Now Now CL3

-13EB2 133 Now Now CL2

1GB DS 128 Meg x 72 3.3V Gold (36)32 Meg x 4 TSOP MT36LSDT12872G -10EA1 A = Y86 1 = TBD (1.7")100 9/00 4Q00

-133A1 133 9/00 4Q00 CL3

o A = registered version for x72 DIMMs. 144- and 168-pin DIMMs (66 MHz/100 MHz) adhere to Intel’s 4-clock SDRAM module specs (66 MHz uses -10 components,100 MHz uses -8,

133 MHz uses -75). Highlighted parts are available in PC133.

DDR SDRAM MODULES (PC1600 and PC2100)

Module Module

Family Density Description Components Part Number Speed Die Rev. PCB (Height) MHz Sample Production

184-pin DIMM 64MB SS 8 Meg x 64 2.5V Gold (8)8 Meg x 8 TSOP MT8VDDT864AG -202A2 A = T84 2 = 0161 (1.25")200 Now 4Q00

Unbuffered -265A2 266 Now 4Q00

-262A2 266 TBD TBD

64MB SS 8 Meg x 72 2.5V Gold (9)8 Meg x 8 TSOP MT9VDDT872AG -202A2 A = T84 2 = 0161 (1.25")200 Now 4Q00

-265A2 266 Now 4Q00

-262A2 266 TBD TBD

128MB SS 16 Meg x 64 2.5V Gold (8)16 Meg x 8 TSOP MT8VDDT1664AG -202A1 A = T85 1 = 0161 (1.25")200 Now 4Q00

-265A1 266 Now 4Q00

-262A1 266 TBD TBD

128MB SS 16 Meg x 72 2.5V Gold (9)16 Meg x 8 TSOP MT9VDDT1672AG -202A1 A = T85 1 = 0161 (1.25")200 Now 4Q00

-265A1 266 Now 4Q00

-262A1 266 TBD TBD

256MB DS 32 Meg x 64 2.5V Gold (16)16 Meg x 8 TSOP MT16VDDT3264AG -202A1 A = T85 1 = 0116B (1.25") 200 Now 4Q00

-265A1 266 Now 4Q00

-262A1 266 TBD TBD

256MB DS 32 Meg x 72 2.5V Gold (18)16 Meg x 8 TSOP MT18VDDT3272AG -202A1 A = T85 1 = 0116B (1.25") 200 Now 4Q00

-265A1 266 Now 4Q00

-262A1 266 TBD TBD

184-pin DIMM 64MB SS 8 Meg x 72 2.5V Gold (9)8 Meg x 8 TSOP MT9VDDT872G -202A1 A = T84 1 = 0162 (1.80")200 Now 4Q00

Registered -265A1 266 Now 4Q00

-262A1 266 TBD TBD

128MB DS 16 Meg x 72 2.5V Gold (18)8 Meg x 8 TSOP MT18VDDT1672DG -202A1 A = T84 1 = 0162 (1.80")200 Now 4Q00

-265A1 266 Now 4Q00

-262A1 266 TBD TBD

128MB DS 16 Meg x 72 2.5V Gold (18)16 Meg x 4 TSOP MT18VDDT1672G -202A1 A = T84 1 = 0163 (1.80")200 Now 4Q00

-265A1 266 Now 4Q00

-262A1 266 TBD TBD

128MB SS 16 Meg x 72 2.5V Gold (9)16 Meg x 8 TSOP MT9VDDT1672G -202A1 A = T85 1 = 0162 (1.80”) 200 Now 4Q00

-265A1 266 Now 4Q00

-262A1 266 TBD TBD

256MB DS 32 Meg x 72 2.5V Gold (18)16 Meg x 8 TSOP MT18VDDT3272DG -202A1 A = T85 1 = 0162 (1.80”) 200 Now 4Q00

-265A1 266 Now 4Q00

-262A1 266 TBD TBD

256MB DS 32 Meg x 72 2.5V Gold (18)32 Meg x 4 TSOP MT18VDDT3272G -202A1 A = T85 1 = 0163 (1.80”) 200 Now 4Q00

-265A1 266 Now 4Q00

-262A1 266 TBD TBD

512MB DS 64 Meg x 72 2.5V Gold (36)32 Meg x 4 TSOP MT36VDDT6472G -202A1 A = T85 1 = 0163 (1.80”) 200 TBD TBD

-265A1 266 TBD TBD

-262A1 266 TBD TBD

DS = Double Sided, SS = Single Sided; M = Tin Plated, G = Gold Plated; U = 100-pin DIMM,

UDG = Double-sided, dual-bank 100-pin DIMM, H = Small-Outline DIMM (SODIMM),

(A) = see footnote references below

MODULE KEY

MICRON. A WORLD MEMORY LEADER

RDRAM® MODULES (RIMM™ MODULES)

Module Module PCB

Pins Density Description Components Part Number Speed Die Rev. (Height) MHz Sample Prod.

184-pin 128MB SS 64 Meg x 16 non-ECC (4) 16 Meg x 16 MT4VR6416AG -653A1 A = R96 1 = TBD (1.25”) 600 TBD TBD

-750A1 700 TBD TBD

-745A1 700 TBD TBD

-845A1 800 TBD TBD

-840A1 800 TBD TBD

128MB SS 64 Meg x 18 ECC (4) 16 Meg x 18 MT4VR6418AG -653A1 A = R96 1 = TBD (1.25”) 600 TBD TBD

-750A1 700 TBD TBD

-745A1 700 TBD TBD

-845A1 800 TBD TBD

-840A1 800 TBD TBD

256MB SS 128 Meg x 16 non-ECC (8) 16 Meg x 16 MT8VR12816AG -653A1 A = R96 1 = TBD (1.25”) 600 TBD TBD

-750A1 700 TBD TBD

-745A1 700 TBD TBD

-845A1 800 TBD TBD

-840A1 800 TBD TBD

256MB SS 128 Meg x 18 ECC (8) 16 Meg x 18 MT8VR12818AG -653A1 A = R96 1 = TBD (1.25”) 600 TBD TBD

-750A1 700 TBD TBD

-745A1 700 TBD TBD

-845A1 800 TBD TBD

-840A1 800 TBD TBD

512MB DS 256 Meg x 16 non-ECC (16) 16 Meg x 16 MT16VR25616AG -653A1 A = R96 1 = TBD (1.25”) 600 TBD TBD

-750A1 700 TBD TBD

-745A1 700 TBD TBD

-845A1 800 TBD TBD

-840A1 800 TBD TBD

512MB DS 256 Meg x 18 ECC (16) 16 Meg x 18 MT16VR25618AG -653A1 A = R96 1 = TBD (1.25”) 600 TBD TBD

-750A1 700 TBD TBD

-745A1 700 TBD TBD

-845A1 800 TBD TBD

-840A1 800 TBD TBD