7/99 Microchip Technology Inc. Preliminary DS39026B-page 1
High Performance RISC CPU:
C-compiler optimized architecture/instruction set
- Source code compatible with the PIC16CXX
instructi on set
Linear program memory addressing to 2M bytes
Linear data memory addressing to 4K bytes
Up to 10 MIPs operation:
- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz osc./clock input with PLL active
16-bit wide instructions, 8-bit wide data path
Priority levels for interrupts
8 x 8 Single Cycle Hardware Multiplier
Peripheral Features:
High curre nt sin k/ sou rce 25 mA/25 mA
Three external interrupt pins
Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
Timer1 module: 16-bit timer/counter
Timer2 module: 8-bit timer/counter with 8-bit
period register (time-base for PWM)
Timer3 module: 16-bit timer/counter
Secondary oscillator clock option - Timer1/Timer3
•Two Capture/Compare/PWM (CCP) modules . CCP
pins that can be configured as:
- Capture input: capture is 16-bit,
max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit.
Max. PWM freq. @:8-bit resolution = 156 kHz
10-bit resolution= 39 kHz
Master Sync h r ono us Seria l Port (MSSP) module.
Two modes of operation:
- 3-wire SPI™ (supports all 4 SPI modes)
-I
2C™ master and slave mode
Addressable USART module:
- Supports interrupt on Address bit
Parallel Slav e Port (PSP) module
Pin Diagrams
Analog Features:
10-bit Analog-to-Digital Converter module (A/D)
with:
- Fast sampling rate
- Con version av ailable during sl eep
- DNL = ±1 LSb, INL = ±1 LSb
Programmable Low-Voltage Detection (LVD)
module
- Supports interrupt on low voltage detection
Programmable Brown-out Reset (BOR)
Special Microc ontroller Features:
Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Programmable code-protection
Power sa v ing SLEEP mode
Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
In-Circuit Serial Programming (ICSP™) via two pins
CMOS Technology:
Low-power, high-speed EPROM technology
Fully static design
Wide operating voltage range (2.5V to 5.5V)
Industrial and Extended temperature ranges
Low-power consumption
Device On-Chip Program Memory On-Chip
RAM
(bytes)
EPROM
(bytes) # Single Wor d
Instructions
PIC18C242 16K 8192 512
PIC18C252 32K 16384 1536
PIC18C442 16K 8192 512
PIC18C452 32K 16384 1536
*
*
*
*
*
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18C4X2
* RB3 is the alternate pin for the CCP2 pin multiplexing.
DIP, Windowed CERDIP
NOTE: Pin compatible with 40-pin PIC16C7X devices
PIC18CXX2
High-Performance Microcontrollers with 10-Bit A/D
DS39026B-page 2 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
Pin Diagrams
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
PIC18C4X2
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
OSC2/CLKO/RA6
NC
RE1/WR/AN6
RE2/CS/AN7
VDD
OSC1/CLKI
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18C4X2
37
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
NC
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2*
PLCC
TQFP
* RB3 is the alternate pin for the CCP2 pin multiplexing.
NOTE: Pin compatible with 44-pin PIC16C7X devices
VSS
RC0/T1OSO/T1CKI
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 3
Pin Diagrams (Cont.d)
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18C4X2
PIC18C2X2
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
* RB3 is the alternate pin for the CCP2 pin multiple xing.
DIP, JW
DIP, SOIC, JW
NOTE: Pin compatible with 40-pin PIC16C7X devices
NOTE: Pin compatible with 28-pin PIC16C7X devices
DS39026B-page 4 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Oscillator Configurations............................................................................................................................................................ 15
3.0 Reset.......................................................................................................................................................................................... 23
4.0 Memory O rganization. ................................................................................................................................................................ 33
5.0 Table Reads/Table Writes.......................................................................................................................................................... 53
6.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 61
7.0 Interrupts.................................................................................................................................................................................... 65
8.0 I/O Ports................. ..................... ..................... ........... ...... ........... ...... .......... ............. ...... ........... ...... ........... ...... .......... ....... ........ 77
9.0 Timer0 Module ........................................................................................................................................................................... 93
10.0 Timer1 Module ........................................................................................................................................................................... 97
11.0 Timer2 Module ......................................................................................................................................................................... 102
12.0 Timer3 Module ......................................................................................................................................................................... 105
13.0 Capture/Compare/PWM (CCP) Modules ............................ ............. ...... ...... ............. .... ............. ...... ........................................ 109
14.0 Master Synchronous Serial Port (M SSP ) Module .................................................................................................................... 117
15.0 Addr essable Universal Synchronous Asynchronous Receiv er Transmitter (USA RT ).............................................................. 151
16.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 167
17.0 Low Voltage Detect . ................................................................................................................................................................. 175
18.0 Special Features of the CPU.................................................................................................................................................... 181
19.0 Instruction Set Summary.......................................................................................................................................................... 191
20.0 Development Support . .............................................................................................................................................................. 235
21.0 Electrical Characteristics.......................................................................................................................................................... 241
22.0 DC and AC Characteristics Graphs and Tables............................... .... .. .... ......... .... .. .... .... ......... .... .. ........................................ 273
23.0 Packagin g In fo rmation........... ...... ........... ...... ........... ...... .......... ....... .......... ....... .......... ...... ..... ..................... ...... .......... ............... 275
Appendix A: Revision History.. .... ...... ........... .... .... .... ........... .... .... ........... ...... .... ........... .... .... .... ....................................................... 283
Appendix B: Device Differences........................................ .... .. .... ....... .... .. .... .... .. ....... .... .... .. .... ....................................................... 283
Appendix C: Conversion Considerations........................... .. .... .. .... ....... .. .. .... .. .... ..... .... .. .... .. .. ....... .... .............................................. 284
Appendix D: Migration from Baseline to Enhanced Devices......................................... .. .... .... ....... .. .... .... .. .................................... 284
Appendix E: Migration from Midrange to Enhanced Devices.... .... ....... .. .... .. .. .... ....... .. .... .. .... .. ....... .... .. .... .. .. .................................. 285
Appendix F: Migration from High-end to Enhanced Devices ..................... .... .... ....... .... .... .... .. ......... .... .... .... .................................. 285
Index................................................................................................................................................................................................. 287
On-Line Support............................ .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. .... .... .. ......... ................................................................... 293
Reader Response.............................................................................................................................................................................. 294
PIC18CXX2 Product Identification System ........................................................................................................................................ 295
To Our Valued Customers
Most Current Data Sheet
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An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recomm ended
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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Corrections to this Data Sheet
We constantly strive to improve the quality of all our product s and documentation. We have spent a great deal of time t o ensure
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We appreciate your assistance in making this a better document.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 5
PIC18CXX2
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following four devices:
1. PIC18C242
2. PIC18C252
3. PIC18C442
4. PIC18C452
These devices come in 28 and 40-pin packages. The
28-pin devices do not have a Parallel Slave Port (PSP)
implemen ted and the number of Analog-to-Digital (A/D)
conver ter input channels is reduced to 5. An overview
of features is shown in Table 1 -1.
The following two figures are device block diagrams
sorted b y pin coun t; 28-pin f or Figure 1-1 and 40-p in for
Figure 1-2. The 28-pin and 40-pin pinouts are listed in
Table 1-2 and Table 1 -3 respectively.
TABLE 1-1: DEVICE FEATURES
Features PIC18C242 PIC18C252 PIC18C442 PIC18C452
Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz
Progr am Mem ory (Bytes) 16K 32K 16K 32K
Program Memory (Instructions) 8192 16384 8192 16384
Data Memory (Bytes) 512 1536 512 1536
Interrupt sources 16 16 17 17
I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Captu re/C ompa r e/PW M mod ul es 2 2 2 2
Serial Communications MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
Parallel Communications PSP PSP
10-bit Analog-to-Digital Module 5 input channels 5 input channels 8 input channels 8 input channels
Resets (and Delays) POR, BOR,
Reset Instruction,
Sta ck Full ,
Stack Underflow
(PWRT, OST)
POR, BOR,
Reset Instruction,
Sta ck Full ,
Stack Underflow
(PWRT, OST)
POR, BOR,
Reset Instruction,
Stack Full,
Stac k Unde rflow
(PWRT, OST)
POR, BOR,
Reset Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Programmabl e Low Voltage Detect Yes Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions
Packages 28-pin DIP
28-pin SOIC
28-pin JW
28-pin DI P
28-pin SOIC
28-pin JW
40-pin DIP
40-pin PLCC
40-pin TQFP
40-pin JW
40-pin DI P
40-pin PLCC
40-pin TQ FP
40-pin JW
PIC18CXX2
DS39026B-page 6 Preliminary 7/99 Microchip Technology Inc.
FIGURE 1-1: PIC18C2X2 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS/LVDIN
RB0/INT0
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Brown-out
Reset
Note1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF
instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The
multiplexing combinations are device dependent.
Addressable
CCP1 Synchronous
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Timing
Generation
4X PLL
A/D Converter
Precision
Reference
RB1/INT1
Data Latch
Data RAM
Address Latch
Address<12>
12(2)
BSR FSR0
FSR1
FSR2
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BIT OP 8
8
ALU<8>
8
Address Latch
Program Memory
(up to 2M Bytes)
Data Latch
20
21
21
16
8
8
8
inc/dec logic
21 8
Data Bus<8>
8
Instruction
12
3
ROMLATCH
Timer3
CCP2
RB2/INT2
RB3/CCP2(1)
T1OSI
T1OSO
Bank0, F
PCLATU
PCU
RA6
Voltage
USART
Master
8
Register
TABLELATCH
Table Pointer <2>
inc/dec
logic
Decode
7/99 Microchip Technology Inc. Preliminary DS39026B-page 7
PIC18CXX2
FIGURE 1-2: PIC18C4X2 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS/LVDIN
RB0/INT0
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Brown-out
Reset
Note1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direc t Address for the RAM are from the BSR registe r (e x cept f or the M OVFF
instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions.
The multiplexing combinations are device dependent.
Addressable
CCP1 Master
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Parallel Slave Port
Timing
Generation
4X PLL
A/D Conver ter
RB1/INT1
Data Latch
Data RAM
(up to 4K
addres s reac h)
Address Latch
Address<12>
12(2)
Bank0, F
BSR FSR0
FSR1
FSR2
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BIT OP 8
8
ALU<8>
8
Address Lat ch
Program Memory
(up to 2M B yt es)
Data Latch
20
21
21
16
8
8
8
inc/dec logic
21 8
Data Bus<8>
TABLELATCH
8
Instruction
12
3
ROMLATCH
Timer3
PORTD
PORTE
RD7/PSP7:RD0/PSP0
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
CCP2
RB2/INT2
RB3/CCP2(1)
T1OSI
T1OSO
PCLATU
PCU
RA6
Precision
Reference
Voltage
Synchronous USART
Register
8
Table Pointer <2>
inc/dec
logic
Decode
PIC18CXX2
DS39026B-page 8 Preliminary 7/99 Microchip Technology Inc.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type
DIP SOIC Description
MCLR/VPP
MCLR
VPP
11I
P
ST Master clear (reset) input. This pin is an active low reset
to the device.
Programming voltage input.
NC These pins should be left unconnected.
OSC1/CLKI
OSC1
CLKI
99I
I
ST
CMOS
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2 /CLKOUT pins).
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10 10 O
O
I/O
TTL
Oscillator crystal output. Connects to crystal or
resonator in crystal oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT which has 1/4
the frequency of OSC1, and denotes the instruction
cycle rate.
General Purpose I/O pin .
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
22
I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
33
I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
44
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
55
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
RA4/T0CKI
RA4
T0CKI
66
I/O
IST/OD
ST Digital I/O. Open drain when configured as output.
Timer0 e x ternal cl ock input .
RA5/AN4/SS/LVDIN
RA5
AN4
SS
LVDIN
77
I/O
I
I
I
TTL
Analog
ST
Analog
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Input.
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
7/99 Microchip Technology Inc. Preliminary DS39026B-page 9
PIC18CXX2
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
21 21 I/O
ITTL
ST Digital I/O.
External Interrupt 0.
RB1/INT1
RB1
INT1
22 22 I/O
ITTL
ST External Interrupt 1.
RB2/INT2
RB2
INT2
23 23 I/O
ITTL
ST Digital I/O.
External Interrupt 2.
RB3/CCP2
RB3
CCP2
24 24 I/O
I/O TTL
ST Digital I/O.
Capture2 input, Compare2 output, PWM2 output.
RB4 25 25 I/O TTL Digital I/O.
Interrupt on change pin.
RB5 26 26 I/O TTL Digital I/O.
Interrupt on change pin.
RB6 27 27 I/O
I
TTL
ST
Digital I/O.
Interrupt on change pin.
ICSP programming clock.
RB7 28 28 I/O
I/O
TTL
ST
Digital I/O.
Interrupt on change pin.
ICSP programming data.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (Cont.d)
Pin Name Pin Number Pin
Type Buffer
Type
DIP SOIC Description
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
PIC18CXX2
DS39026B-page 10 Preliminary 7/99 Microchip Technology Inc.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11 11 I/O
O
I
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
12 12 I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
13 13 I/O
I/O ST
ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
14 14 I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode
RC4/SDI/SDA
RC4
SDI
SDA
15 15 I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI Data In.
I2C Data I/O.
RC5/SDO
RC5
SDO
16 16 I/O
OST
Digital I/O.
SPI Data Out.
RC6/TX/CK
RC6
TX
CK
17 17 I/O
O
I/O
ST
ST
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock.
(See related RX/DT)
RC7/RX/DT
RC7
RX
DT
18 18 I/O
I
I/O
ST
ST
ST
Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data.
(See related TX/CK)
VSS 8, 19 8, 19 P Ground reference for logic and I/O pins.
VDD 20 20 P Positive supply for logic and I/O pins.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (Cont.d)
Pin Name Pin Number Pin
Type Buffer
Type
DIP SOIC Description
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
7/99 Microchip Technology Inc. Preliminary DS39026B-page 11
PIC18CXX2
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type
DIP PLCC TQFP Description
MCLR/VPP
MCLR
VPP
1218
I
P
ST Master clear (reset) input. This pin is an active
low reset to the device.
Programming voltage input.
NC These pins should be left unconnected.
OSC1/CLKI
OSC1
CLKI
13 14 30 I
I
ST
CMOS
Oscillator crystal inpu t or external clock
source input. ST buffer when configured in
RC mode. CMOS otherwise.
External clock source input. Always
associated with pin function OSC1. (See
related OSC1/CLKIN, OSC2/CLKOUT pins).
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 15 31 O
O
I/O
TTL
Oscillator crystal output. Connects to crystal
or resonator in crystal oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT,
which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
2319
I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3420
I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
4521
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
5622
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
RA4/T0CKI
RA4
T0CKI
6723
I/O
IST/OD
ST Digital I/O. Op en drai n when con fig ured as ou tput.
Timer0 external clock input.
RA5/AN4/SS/LVDIN
RA5
AN4
SS
LVDIN
7824
I/O
I
I
I
TTL
Analog
ST
Analog
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Vo ltage Detect Input.
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS leve ls
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
PIC18CXX2
DS39026B-page 12 Preliminary 7/99 Microchip Technology Inc.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0
RB0
INT0
33 36 8 I/O
ITTL
ST Digital I/O.
External Interrupt 0.
RB1/INT1
RB1
INT1
34 37 9 I/O
ITTL
ST External Interrupt 1.
RB2/INT2
RB2
INT2
35 38 10 I/O
ITTL
ST Digital I/O.
External Interrupt 2.
RB3/CCP2
RB3
CCP2
36 39 11 I/O
I/O TTL
ST Digital I/O.
Capture2 input, Compare2 output, PWM2 output.
RB4 3 7 41 14 I/O TTL Digital I/O.
Interrupt on change pin.
RB5 3 8 42 15 I/O TTL Digital I/O.
Interrupt on change pin.
RB6 39 43 16 I/O
I
TTL
ST
Digital I/O.
Interrupt on change pin.
ICSP programming clock.
RB7 40 44 17 I/O
I/O
TTL
ST
Digital I/O.
Interrupt on change pin.
ICSP programming data.
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (Cont.d)
Pin Name Pin Number Pin
Type Buffer
Type
DIP PLCC TQFP Description
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
7/99 Microchip Technology Inc. Preliminary DS39026B-page 13
PIC18CXX2
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15 16 32 I/O
O
I
ST
ST
Digital I/O.
Timer1 oscillator output.
Tim er1/ Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
16 18 35 I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
17 19 36 I/O
I/O ST
ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
18 20 37 I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I2C mode.
RC4/SDI/SDA
RC4
SDI
SDA
23 25 42 I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI Data In.
I2C Data I/O.
RC5/SDO
RC5
SDO
24 26 43 I/O
OST
Digital I/O.
SPI Data Out.
RC6/TX/CK
RC6
TX
CK
25 27 44 I/O
O
I/O
ST
ST
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock.
(See related RX/DT)
RC7/RX/DT
RC7
RX
DT
26 29 1 I/O
I
I/O
ST
ST
ST
Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data.
(See related TX/CK)
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (Cont.d)
Pin Name Pin Number Pin
Type Buffer
Type
DIP PLCC TQFP Description
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS leve ls
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
PIC18CXX2
DS39026B-page 14 Preliminary 7/99 Microchip Technology Inc.
PORTD is a bi-directional I/O port.
Pa rallel Slave Port (PSP) for interfacing to a micropro-
cessor port. These pins have TTL input buffers when
PSP module is enabled.
RD0/PSP0 19 21 38 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD1/PSP1 20 22 39 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD2/PSP2 21 23 40 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD3/PSP3 22 24 41 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD4/PSP4 27 30 2 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD5/PSP5 28 31 3 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD6/PSP6 29 32 4 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD7/PSP7 30 33 5 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
PORTE is a bi-directional I/O port.
RE0/RD/AN5
RE0
RD
AN5
8 9 25 I/O ST
TTL
Analog
Digital I/O.
Read control for parallel slave port.
(See also WR and CS pins)
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
9 10 26 I/O ST
TTL
Analog
Digital I/O.
Write control for parallel slave port.
(See CS and RD pins)
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 11 27 I/O ST
TTL
Analog
Digital I/O.
Chip Select control for parallel slave port.
(See related RD and WR)
Analog input 7.
VSS 12, 31 13, 34 6, 29 P Ground reference for logic and I/O pins.
VDD 11, 32 12, 35 7, 28 P Positive supply for logic and I/O pins.
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (Cont.d)
Pin Name Pin Number Pin
Type Buffer
Type
DIP PLCC TQFP Description
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 15
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Oscillator Types
The PIC18CXX2 can be operated in eight different
oscillator modes. The user can program three configu-
rat ion bits (FOSC2, FOSC1, and F OSC0) to sel ect on e
of these eight modes:
1. LP Low Power Crystal
2. XT Crystal/Resonator
3. HS High Speed Crystal/Resonator
4. HS + PLL High Speed Crystal/Resonator with
PLL enabled
5. RC External Resistor/Capacitor
6. RCIO External Resistor/Capacitor with
I/O pin enabled
7. EC External Clock
8. ECIO External Clock with I/O pin enabled
2.2 Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HS-PLL oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connectio ns. An external c lock source ma y als o
be connected to the OSC1 pin in these modes, as
shown in Figure 2-2.
The PIC1 8CXX2 osc illat or desi gn requ ires th e use o f a
parallel cut crystal.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers
specifications.
Note 1: See Table 2 -1 and Table 2-2 for recom-
mended values of C1 and C2.
Note 2: A series resistor (RS) may be required
for AT strip cut crys tals.
Note 3: RF varies with the crystal chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
SLEEP
To
logic
PIC18CXXX
RS(2)
internal
OSC1
OSC2
Open
Clock from
ext. system PIC18CXXX
PIC18CXX2
DS39026B-page 16 Preliminary 7/99 Microchip Technology Inc.
TABLE 2-1: CERAMIC RESONATORS
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
2.3 RC Oscillator
For timing insensitive applications, the “RC” and
"RCIO" device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscillator frequency will var y from unit to unit due
to normal process parameter variation. Furthermore,
the difference in lead frame capacitance between
package types will also aff ect the oscillation frequency,
especially for low CEXT v alues . The user also needs to
take into account v ariation due to tolerance of external
R and C components used. Figure 2-3 shows how the
R/C combination is connected.
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
FIGURE 2-3: RC OSCILLATOR MODE
The RCIO oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
POR TA (RA6).
2.4 External Clock Input
The EC and ECIO os cilla tor mode s require an e xternal
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to sav e c urrent. There is no oscill a-
tor startup time required after a Power-On-Reset or
after a recovery from SLEEP mode.
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Fi gure 2-4 shows the pin co nne cti ons for the EC
oscillator mode.
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
Resonators Used:
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.0 0MG ± 0.5%
4.0 MHz Murata Erie CSA4.0 0MG ± 0.5%
8.0 MHz Murata Erie CSA8.0 0MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
All resonators used did not have built-in capacitors.
Osc Type Crystal
Freq Cap. Range
C1
Cap.
Range
C2
LP 32.0 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1.0 MHz 15 pF 15 pF
4.0 MHz 15 pF 15 pF
HS 4.0 MHz 15 pF 15 pF
8.0 MHz 15-33 pF 15-33 pF
20.0 MHz 15-33 pF 15-33 pF
25.0 MHz TBD TBD
These values are for design g uidance onl y. See
notes at bottom of page.
Crystals Used
32.0 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1.0 MHz ECS ECS-10-13-1 ± 50 PPM
4.0 MHz ECS ECS-40-20-1 ± 50 PPM
8.0 MHz EPSON CA-301 8.000M-C ± 30 PPM
20.0 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
2: Higher capacitance increases the stability
of the osci llator, b ut als o inc reases the st art-
up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonato r /c rystal man ufacturer f or app ropri -
ate values of external components.
4: Rs may be required in HS mode, as well as
XT mode, to avoid overdriving crystals with
low drive level specification.
OSC2/CLKO
CEXT
REXT
PIC18CXXX
OSC1
FOSC/4
Internal
clock
VDD
VSS
Recommended values: 3 k REXT 100 k
CEXT > 20pF
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 17
FIGURE 2-4: EXTERNAL CLOCK INPUT
OPERATION
(EC OSC CONFIGURATION)
The ECIO oscillator mode functions like the EC mode,
exce pt that the OSC2 pin be comes an addit ional g en-
eral purpose I/O pin. The I/O pin becomes Bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO oscillator mode.
FIGURE 2-5: EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
2.5 HS/PLL
A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the fre-
quency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they
are programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes of the FOSC<2:0> con-
figuration bits. The oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
FIGURE 2-6: PLL BLOCK DIAGRAM
OSC1
OSC2
FOSC/4
Clock from
ext. system PIC18CXXX
OSC1
I/O (OSC2)
RA6
Clock from
ext. system PIC18CXXX
MUX
VCO
Loop
Filter
Divide by 4
Crystal
Osc
OSC2
OSC1
PLL Enable
FIN
FOUT SYSCLK
Phase
Comparator
(from configuration HS Osc
bit regist er)
PIC18CXX2
DS39026B-page 18 Preliminary 7/99 Microchip Technology Inc.
2.6 Oscillator Switching Feature
The PIC18CXX2 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For the PIC18CXX2 devices, this alternate clock
source is the Timer1 oscilla tor . If a lo w-frequency crys-
tal (32 KHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low power
execution mode. Figure 2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enab le (OSCSEN) bi t in C on fig uration Reg is ter1 H to a
’0’. Clock switching is disabled in an erased device.
See Section 9 f or further details of t he Timer1 oscillator .
See Section 18.0 for Configuration Register details.
FIGURE 2-7: DEVICE CLOCK SOURCES
2.6.1 SYSTEM CLOCK SWITCH BIT
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON<0>) contro ls the c loc k s wi tching. When th e
SCS bit is ’0’, the system clock source comes from the
main os cil la tor tha t is sel ect ed by the FOSC config ur a-
tion bits in Configuration Register1H. When the SCS
bit is set, the system clock source will come from the
Timer1 oscillator. The SCS bit is cleared on all forms
of reset.
Register 2-1: OSCCON Register
PIC18CXXX
TOSC
4 x PLL
TT1P
TSCLK
Clock
Source
MUX
Tosc/4
Timer1 Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source option
for other modules
OSC1
OSC2
Sleep
Main Oscillator
Note: The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer 1 oscil lator is enabled by set ting t he
T1OSCEN bit in the Timer1 control regist er
(T1CON). If the Timer1 oscillator is not
enabled, then any write to the SCS bit will
be ignored (SCS bit forced cleared) and
the main oscillator will continue to be the
system clock source.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
SCS
bit 7 bit 0
bit 7-1 Unimplemented: Read as '0'
bit 0 SCS: System Clock Switch bit
when OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:
1 = Switch to Timer1 Oscillator/Clock pin
0 = Use primary Oscillator/Clock input pin
when OSCSEN and T1OSCEN are in other states:
bit is forced clear
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is clear ed x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 19
2.6.2 OSCILLATOR TRANSITIONS
The PIC18CXX2 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essen tially, th e circui tr y waits for ei ght ri sing ed ges of
the cl ock s ource that the pro cessor is s witch ing to . This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
A timing diagram indicating the transition from the
main oscillator to the Timer1 oscillator is shown in
Figure 2-8. The Timer1 oscillator is assumed to be
running all the time. After the SCS bit is set, the pro-
cessor is frozen at the next occurring Q1 cycle. After
eight synchronization cycles are counted from the
Timer1 oscillator, operation resumes. No additional
delays are required after the synchronization cycles.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external crys-
tal (HS , XT, LP), then th e transit ion will take place after
an oscil lator startup time (TOST) has occu rred. A timing
diagra m indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS, XT and LP modes is
shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS,XT,LP)
Q3Q2Q1Q4Q3Q2
OSC1
Internal
SCS
(OSCCON<0>)
Program PC + 2PC
Note1: Delay on internal system clock is eight oscillator cycles for synchronization.
Q1
T1OSI
Q4 Q1
PC + 4
Q1
Tscs
Clock
Counter
System
Q2 Q3 Q4 Q1
TDLY
TT1P
TOSC
21 34 5678
Q3
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter PC PC + 2
Note1: TOST = 1024TOSC (drawing not to scale).
T1OSI
Clock
OSC2
TOST
Q1
PC + 6
TT1P
TOSC
TSCS
1234 5678
PIC18CXX2
DS39026B-page 20 Preliminary 7/99 Microchip Technology Inc.
If the main oscillator is con figured f or HS-PLL mode , an
oscillator startup time (TOST) plus an additional PLL
timeout (TPLL) will occu r . Th e PLL time out is ty pically 2
ms and al lows the PLL to loc k to the ma in oscillato r fre-
quency. A timing di agr am in dicati ng the tr ansi tion from
the Timer1 oscillator to the main oscillator for HS-PLL
mode is shown in Figure 2 -10.
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
If the main os ci lla tor is c on figured i n t he R C, RCIO, EC
or ECIO modes, there is no oscillator startup timeout.
Operation will resume after eight cycles of the main
oscillator ha ve been counted. A timing diagr am indicat-
ing the transition from the Timer1 oscillator to the main
oscill ator f or RC , RCIO , EC an d ECIO modes is shown
in Figure 2-11.
FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter PC PC + 2
Note 1: TOST = 1024TOSC (drawing not to scale).
T1OSI
Clock
TOST
Q3
PC + 4
TPLL
TOSC
TT1P
TSCS
Q4
OSC2
PLL Clock
Input 1 234 5678
Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter PC PC + 2
Note 1: RC oscillator mode assumed.
PC + 4
T1OSI
Clock
OSC2
Q4
TT1P
TOSC
TSCS
123
45678
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 21
2.7 Effects of Sleep Mode on the On-chip
Oscillator
When the de vice executes a SLEEP instruction, the on-
chip clocks and oscillator are turned off and the device
is held at the beginning of an instruction cycle (Q1
state) . Wit h the o sc ill ato r off, the OSC1 and OS C2 si g-
nals will stop oscillating. Since all the transistor switch-
ing currents have be en rem o ved, slee p m od e a ch ieve s
the lowest current consumption of the device (only
leakage currents). Enabling any on-chip feature that
will operate during sleep will increase the current con-
sumed during sleep. The user can wake from SLEEP
through external reset, Watchdog Timer Reset or
through an interr upt.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
2.8 Power-up Delays
P ower up delays are controlled b y two timers , so that no
e xternal reset circuitry is required f or most applications .
The delays ensure that the device is kept in RESET
until the device power supply and clock are stable. For
additional information on RESET operation, see the
“Reset” section.
The first timer is the Power-up Timer (PWRT), which
optionally provides a f ixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Os cillator St art-up Timer O ST, intended to kee p the
chip in RESET until the crystal oscillator is stable.
With the PLL enabled (HS/PLL oscillator mode), the
time-out sequence follow ing a power-on reset is differ-
ent from other osci llator modes . The time-out se quence
is as f ollow s: First the PWR T tim e-out is in vok ed aft er a
POR time delay has expired. Then the Oscillator Start-
up Timer (OST) is invoked. However, this is still not a
suffici ent amount o f time to al low the PL L to loc k at high
frequencies. The PWRT timer is used to provide an
addition al fix ed 2ms (n ominal) ti me-out to a llow the PLL
ample time to lock to the incoming clock frequency.
OSC Mode OSC1 Pin OSC2 Pin
RC Floating, external resistor should pull
high At logic low
RCIO Floating, external resistor should pull
high Confi gu red as Port A, bit 6
ECIO Floating Configured as Port A, bit 6
EC Floating At logic low
LP, XT, and HS Feedback inverter disabled, at quies-
cent voltage level Feedback inverter disabled, at quies-
cent voltage level
See Table 3-1, in the Reset” section, for time-outs due to Sleep and MCLR reset.
PIC18CXX2
DS39026B-page 22 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 23
3.0 RESET
The PIC18CXXX differentiates between various kinds
of reset:
a) Power-on Reset (POR)
b) MCLR reset during normal operation
c) MCLR reset during SLEEP
d) Watchdog Timer (WDT) Reset (during normal
operation)
e) P rogrammable Brown-out Reset (BOR)
f) Reset Instruction
g) Stack Full res et
h) Stack Underflow reset
Most regi sters are un aff ected b y a reset. Th eir status i s
unknown on POR and unchanged by all other resets.
The other registers are forced to a “reset state” on
Power-on Reset, MCLR, WDT reset, Brown-out Reset,
MCLR reset during SLEEP and by the RESET instruc-
tion.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
atio n. Stat us bit s from the RCON r egiste r, RI, TO, PD,
POR and BOR, a re set or c leared dif fer ently in d iff erent
reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
reset. See Table 3-3 for a full description of the reset
states of all registers.
A simplifi ed b loc k diag ram of the on-ch ip res et circui t is
shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR reset pat h. The filter w ill detect a nd ignore
small pulses.
A WDT reset
does not drive MCLR pin low.
FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External Reset
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
On-chip
RC OSC
(
1
)
WDT
Time-out
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Reset
Enable OST(2)
Enable PWRT
SLEEP
Note1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
Brown-out
Reset BOREN
RESET
Instruction
Stack
Pointer Stack Full/Underflow Reset
PIC18CXX2
DS39026B-page 24 Preliminary 7/99 Microchip Technology Inc.
3.1 Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detec ted. To tak e adv antage of the POR cir-
cuitry, just tie the MCLR pin directly (or th rough a resi s-
tor) to VDD. T his wi ll elimina te e xternal RC component s
usually needed to create a Power-on Reset delay. A
maximum rise time for VDD is specified (parameter
D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
reset co ndi tion), device operati ng p aramete rs (voltage,
frequency, temper ature,...) must be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the voltage
start-up condition.
FIGURE 3-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
3.2 Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chi p is k e pt in reset a s long as the PW R T i s act iv e .
The PWR T s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/dis-
able the PWRT.
The po wer-up ti me dela y will v ary from ch ip-to-chip du e
to VDD, temperature and process variation. See DC
parameter #33 for details.
3.3 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWR T dela y is ov er (parameter #3 2). This ensures th at
the crystal osci llator or resonato r has started and stabi-
lized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4 PLL Lock Timeout
With the PLL enabled, the timeout sequence following
a power-on reset is different from other oscillator
modes . A portion of the Power-up Ti mer is used to pro-
vide a fixed timeout that is sufficient for the PLL to lock
to the mai n os ci lla tor fre que nc y. This PLL lock timeo ut
(TPLL) is typically 2 ms and f ollows the oscillator startup
timeout (OST).
3.5 Brown-Out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A reset may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The P ow er-up Timer wi ll then be in voked and will
keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brow n-out Reset and the P ow er-up Ti mer will b e initial-
ized. Once VDD rises abo v e BV DD, the Pow er-up T imer
will execute the additional time delay.
Note1: Exte rnal P ower-on Reset cir cuit is required
only if the VDD po wer-up s lop e i s too s low .
The diode D hel ps d isch arge th e ca pacito r
quickl y when V DD powers down.
2: R < 40 k is recommended to make sure
that the voltage drop across R does not
violate the device’s electrical specification.
3: R1 = 100 to 1 k will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break -
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC18CXXX
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 25
3.6 Time-out Sequence
On power-up , the time-out sequence is as follows: First,
PWRT time-out is invok ed after the POR time delay has
expired. Then, OST is activated. The total time-out will
v ary based on oscil lator con fig urati on and the s tatus of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 3-3,
Figure 3-4, Figure 3-5, Figure 3-6 and Figure 3-7
depict time-out sequences on power-up.
Since the time-outs occu r from the POR puls e, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18CXXX de vice operat-
ing in parallel.
Table 3-2 sh ows the rese t co ndit ions for some S peci al
Function Registers, while Table 3-3 shows the reset
conditions for all the registers.
TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS
Register 3-1: RCON Register Bits and Positions
TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Oscillator
Configuration
Power-up (2)
Brown-out (2)
Wake-up from
SLEEP or
Oscillato r Swi tc hPWRTE = 0 PWRTE = 1
HS with PLL enabled (1) 72 m s + 10 24 Tosc + 2m s 1024Tosc + 2 ms 72 ms + 1024Tosc + 2ms 1024Tosc + 2 ms
HS, XT, LP 72 ms + 1024Tosc 1024Tosc 72 ms + 1024Tosc 1024Tosc
EC 72 ms —72 ms
External RC 72 ms 72 m s
Note1: 2 ms = Nominal time required for the 4x PLL to lock.
2: 72 ms is the nominal power-up timer delay
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
Condition Program
Counter RCON
Register RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 00-1 1100 1 1 1 0 0 u u
MCLR Reset during normal
operation 0000h 00-u uuuu u u u u u u u
Software Reset during normal
operation 0000h 0u-0 uuuu 0 u u u u u u
Stack Full Reset during normal
operation 0000h 0u-u uu11 u u u u u u 1
Stack Underflow Reset during
normal operation 0000h 0u-u uu11 u u u u u 1 u
MCLR Reset during SLEEP 0000h 00-u 10uu u 1 0 u u u u
WDT Reset 0000h 0u-u 01uu 1 0 1 u u u u
WDT Wake-up PC + 2 uu-u 00uu u 0 0 u u u u
Brown-out Reset 0000h 0u-1 11u0 1 1 1 1 0 u u
Interrupt wake-up from SLEEP PC + 2(1)uu-u 0 0uu u 1 0 u u u u
Legend: u = unchanged, x = unknown, — = unimplemented bit read as '0'.
Note1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
PIC18CXX2
DS39026B-page 26 Preliminary 7/99 Microchip Technology Inc.
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Reset Instru ction
Stack Resets Wake-up via WDT
or Interrupt
TOSU 242 442 252 452 ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3)
TOSL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR 242 442 252 452 00-0 0000 00-0 0000 uu-u uuuu(3)
PCLATU 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu
PCLATH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PCL 242 442 252 452 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TBLPTRH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TABLAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PRODH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 242 442 252 452 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 242 442 252 452 1111 -1-1 1111 -1-1 uuuu -u-u(1)
INTCON3 242 442 252 452 11-0 0-00 11-0 0-00 uu-u u-uu(1)
INDF0 242 442 252 452 N/A N/A N/A
POSTINC0 242 442 252 452 N/A N/A N/A
POSTDEC0 242 442 252 452 N/A N/A N/A
PREINC0 242 442 252 452 N/A N/A N/A
PLUSW0 242 442 252 452 N/A N/A N/A
FSR0H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 242 442 252 452 N/A N/A N/A
POSTINC1 242 442 252 452 N/A N/A N/A
POSTDEC1 242 442 252 452 N/A N/A N/A
PREINC1 242 442 252 452 N/A N/A N/A
PLUSW1 242 442 252 452 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset va lue for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 27
FSR1H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
INDF2 242 442 252 452 N/A N/A N/A
POSTINC2 242 442 252 452 N/A N/A N/A
POSTDEC2 242 442 252 452 N/A N/A N/A
PREINC2 242 442 252 452 N/A N/A N/A
PLUSW2 242 442 252 452 N/A N/A N/A
FSR2H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 242 442 252 452 ---x xxxx ---u uuuu ---u uuuu
TMR0H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
OSCCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
LVDCON 242 442 252 452 --00 0101 --00 0101 --uu uuuu
WDTCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
RCON(4, 6) 242 442 252 452 00-1 11q0 00-1 qquu uu-u qquu
TMR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 242 442 252 452 0-00 0000 u-uu uuuu u-uu uuuu
TMR2 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PR2 242 442 252 452 1111 1111 1111 1111 1111 1111
T2CON 242 442 252 452 -000 0000 -000 0000 -uuu uuuu
SSPBUF 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.d)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Reset Instru ction
Stack Resets Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset va lue for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
PIC18CXX2
DS39026B-page 28 Preliminary 7/99 Microchip Technology Inc.
ADRESH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
ADCON1 242 442 252 452 --0- 0000 --0- 0000 --u- uuuu
CCPR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
CCPR2H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TMR3H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu
SPBRG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
RCREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA 242 442 252 452 0000 -01x 0000 -01u uuuu -uuu
RCSTA 242 442 252 452 0000 000x 0000 000u uuuu uuuu
IPR2 242 442 252 452 ---- 1111 ---- 1111 ---- uuuu
PIR2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu(1)
PIE2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
IPR1 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
242 442 252 452 -111 1111 -111 1111 -uuu uuuu
PIR1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(1)
242 442 252 452 -000 0000 -000 0000 -uuu uuuu(1)
PIE1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
242 442 252 452 -000 0000 -000 0000 -uuu uuuu
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.d)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Reset Instru ction
Stack Resets Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset va lue for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 29
TRISE 242 442 252 452 0000 -111 0000 -111 uuuu -uuu
TRISD 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISC 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISB 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISA(5, 7) 242 442 252 452 -111 1111(5) -111 1111(5) -uuu uuuu(5)
LATE 242 442 252 452 ---- -xxx ---- -uuu ---- -uuu
LATD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5, 7) 242 442 252 452 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)
PORTE 242 442 252 452 ---- -000 ---- -000 ---- -uuu
PORTD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5, 7) 242 442 252 452 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.d)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Reset Instru ction
Stack Resets Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset va lue for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
PIC18CXX2
DS39026B-page 30 Preliminary 7/99 Microchip Technology Inc.
FIGURE 3-3: TIME-OUT SEQUENCE ON P OWER-UP (MCLR TIED TO VDD)
FIGURE 3-4: TIME-OUT SEQUENCE ON P OWER-UP (MCLR NO T TIED TO VDD): CASE 1
FIGURE 3-5: TIME-OUT SEQUENCE ON P OWER-UP (MCLR NO T TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 31
FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD)
FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V 1V 5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
IINTERNAL POR
PWRT TIME-OUT
OST TIME-O UT
INTERNAL RESET
PLL TIME-OUT
TPLL
TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
PIC18CXX2
DS39026B-page 32 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 33
4.0 MEMORY ORGANIZATION
There are two memory blocks in Enhanced MCU
devices. These memory blocks are:
Program Memory
Data Memory
Each block has its own bus so that concurrent access
can occur.
4.1 Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mby t e pr og ram memory space . Ac ce ss in g a locatio n
between the physically implemented memory and the
2-Mbyte address will cause a read of all ’0’s (a NOP
instruction).
PIC18C252 and PIC18C452 have 32-KBytes of
EPROM, while PIC18C242 and PIC18C442 have
16-KBytes of EPROM. This means that PIC18CX52
devices can store up to 16K of single word instruc-
tions, and PIC18CX42 devices can store up to 8K of
single wor d i nst r u ct ions.
The reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
Figure 4-1 shows the Program Memory Map for
PIC18C242/442 devices and Figure 4-2 shows the
Program Memory Map for PIC18C252/452 devices.
DS39026B-page 34 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR PIC18C442/
242
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR PIC18C452/
252
PC<20:0>
Stack Level 1
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
CALL,BSUB,RETURN
RETFIE,RETLW 21
0000h
0018h
On-chip
Program Memor y
High Priority Interr upt Vector 0008h
User Memory Space
1FFFFFh
4000h
3FFFh
Read ’ 0’
200000h
PC<20:0>
Stack Level 1
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
CALL,BSUB,RETURN
RETFIE,RETLW 21
0000h
0018h
8000h
7FFFh
On-chip
Program Memor y
High Priority Interr upt Vector 0008h
User Memory Space
Read ’0’
1FFFFFh
200000h
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 35
4.2 Return Address Stack
The r eturn addre ss s tack allows a n y c om bin ati on of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is ex ecute d or an interrupt is
acknowledged. The PC val ue is pulled off t he stack on
a RETURN, RETLW or a RETFIE in struct ion. PCLATU
and PCLATH are not affected by any of the return
instructions.
The stack operates as a 31 word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all resets. There is no RAM associated
with stack pointer 00000b. This is only a reset value.
During a CALL type instruction causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction causing a pop from the stack, the contents
of the R AM locati on pointe d to b y the STKPTR is trans-
ferred to the PC and then the stack pointer is decre-
mented.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the addre ss on the top o f the stac k is read able and writ-
able through SFR registers. Data can also be pushed
to or popped from the stack using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at or
beyond the 31 levels provided.
4.2.1 TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
v alues can b e pla ced on a us er defi ned softw ar e stac k.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
during this time to pre vent inadv ertent stac k operations.
4.2.2 RETURN STACK POINTER (STKPTR)
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR re gister . The v alue o f the stac k p ointer can b e
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At reset, the stack
pointer va lue wil l be 0. The use r ma y read and w rite the
stac k po inter value. T his f e atur e can be u sed b y a Rea l
Time Operating System for return stack maintenance.
After the PC is push ed on to the stac k 31 tim es (wi thout
popping any values off the stack), the STKFUL bit is
set. The ST KFUL bi t can only be cle ared in softw are or
by a POR .
The action that takes place when the stack becomes
full depends on the state of the STVREN (stack over-
flow rese t enab l e) con figur ation bit. R ef er to Sec tion 1 8
for a description of the device configuration bits. If
STVREN is set (def ault) the 31st push will push the (PC
+ 2) v alue onto th e stack, s et the STKFUL bit, a nd reset
the device. The STKFUL bit will remain set and the
stack pointer will be set to 0.
If STVREN is clea red, the STKFUL bit will b e set on the
31st push and the stack pointer will increment to 31.
The 32nd push will o verwrite the 31 st push (and s o on),
while STKPTR remains at 31.
When the stack has been popped enough times to
unload the stac k, the ne xt pop will re turn a v alue of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note: Return ing a value of zero t o t he PC o n an
underflow has the effect of vectoring the
program to the reset vector, where the
stac k condition s can be v erifie d and appro-
priate actions can be taken.
DS39026B-page 36 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
Register 4-1: STKPTR - Stack Point er Register
FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
4.2.3 P USH AND POP INSTRUCTIONS
Since the Top-of-Stack (TOS) is readable and writable,
the abi lit y to p ush values onto the s tac k a nd pu ll v a lues
off the stack without disturbing normal program execu-
tion is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increm ent t he sta ck point er and load the cu r-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a retur n address on the
stack.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the st ack, withou t distur bing nor mal execu tio n, is
achie v ed by u sing the POP instruction. The POP instruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
4.2.4 STACK FULL/UNDERFLOW RESETS
These resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disab led, a ful l or unde rflow cond ition will se t the appro-
priate STKFUL or STKUNF bit, but not caus e a device
reset. Whe n the STVREN bit i s enabled, a full or under-
flow will set the appropriate STKFUL or STKUNF bit
and then cause a device reset. The STKFUL or
STK UNF bit s are only cl eared by the us er sof tware or
a POR reset.
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL STKUNF - S P4 SP3 SP2 SP1 SP0 R = Readable bit
W = Writeable bit
C = Clearable bit
U = Unimplemented bit,
Read as ‘0’
- n = Value at POR reset
bit7 6 5 4 3 2 1 bit0
bit 7(1):STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6(1):STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5: Unimplemented: Read as ’0’
bit 4-0: SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and Bit 6 can only be cleared in user software or by a POR.
00011
0x001A34
11111
11110
11101
00010
00001
00000
00010
Return Address Stack
Top of Stack 0x000D58
TOSLTOSHTOSU 0x340x1A0x00 STKPTR<4:0>
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 37
4.3 Fast Register Stack
A "f ast interrupt return" option is av ailable f or interrupts .
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers and are only one in depth.
The stac k is n ot reada b le or writ ab le and is lo aded wi th
the current value of the corresponding register when
the proces sor vectors for an interrupt . The v alues in the
registers are then loaded back into the working regis-
ters if the fast return instruction is used to return from
the interrupt.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stac k regis ter va lve s stored b y the lo w priority inter-
rupt will be overwritten.
If high priority int errupts are n ot disab led during lo w pri-
ority interrupts, users must save the key registers in
software during a low priority interrupt.
If no in t er r up t s a r e us ed, t he fast r eg is t er s t ack ca n be
used to restore the STATUS, WREG and BSR registers
at the end of a sub rou tine call . To us e the fast r egist er
stack for a subroutine call, a fast call instruction must be
executed.
Examp le 4- 1 shows a sou rce cod e exam ple that uses
the fast register stack.
EXAMPLE 4-1: FAST REGISTER STACK
CODE EXAMPLE
4.4 PCL, PCLATH and PCLATU
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register c ontai ns the PC<20:16> bits a nd is n ot directl y
readable or writable. Updates to the PCU register may
be perfor med through the PCLATU register.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ’0’.
The PC incre me nts by 2 to address se que ntial instruc-
tions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is us eful
for computed offsets to the PC. (See Section 4.8.1)
4.5 Clocking Scheme/Instruction Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 4-4.
FIGURE 4-4: CLOCK/I NSTRUC TION CYCLE
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC+2 PC+4
Fetch INST (PC)
Execute INST (PC-2) Fetch INST (PC+2)
Execute INST (PC) Fetch INST (PC+4)
Execute INST (PC+2)
Internal
phase
clock
DS39026B-page 38 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.6 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then tw o cycles ar e required to c omplete the instruction
(Example 4-2).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the e x ecu tion cy cle, t he f etche d instructio n is latche d
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles . Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW
4.7 Instructions in Program Memory
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The least significant byte of an instruction
word is always stored in a program memory location
with an even address (LSB = ’0’). Figure 4-5 shows an
e xamp le of ho w in struction w ords a re sto red in th e pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’. (See Section 4.4)
The CALL and GOTO instructions have an absolute
progr am memory address embedded in to the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to
PC<20:1>, which accesses the desired byte address
in program memory. Instruction #2 in Figure 4-5
shows how the instruction "GOTO 000006h’ is
encoded in the program memory. Program branch
instructions which encode a relative address offset
operate in the same manner. The offset value stored
in a branch instruction represents the number of sin-
gle word instructions that the PC will be offset by.
Section 19.0 pro vides further details of the instruction
set.
FIGURE 4-5: INSTRUCTIONS IN PROGRAM MEM OR Y
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
Word Address
LSB = 1 LSB = 0
Program Memor y
Byte Locations 000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 000006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 39
4.7.1 TWO-W ORD INSTRUCTIONS
The PIC 18CXX2 devices ha v e 4 tw o-w ord in structions :
MOVFF, CALL, GOTO and LFSR. The second word of
these instructions has the 4 MSB’s set to 1’s and is a
specia l k in d of NOP instructi on. The low er 12 bits o f th e
second word c ontain d ata to b e used by the instructio n.
If the first word of the instruction is executed, the data
in the second word is accessed. If the second word of
the instruction is executed by itself (first word was
skipped), it will execute as a NOP. This action is neces-
sary when the two word instruction is preceded by a
conditi ona l i ns truction that ch ang es the PC . A program
example that demonstrates this concept is shown in
Example 4-3. Ref er to Section 19.0 for further details of
the instruction set.
EXAMP L E 4- 3: TWO-WO RD INST RU C TIONS
4.8 Lookup Tables
Look-up tables are implemented two ways. These are:
Computed GOTO
•Table Reads
4.8.1 COMPUTED GOTO
A comput ed GOTO i s a cc om pli sh ed by adding an o ffs et
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
The offse t va lue (v alue in WREG) spec ifies the n umber
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
4.8.2 TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored 2 bytes per program
word by using ta ble reads and w rites. The table pointer
(TBLPTR) specifies the byte address and the table
latch (TABLAT) contains the data that is read from or
written to program memory. Data is transferred to/from
program memory one byte at a time.
A description of the Table Read/Table Write operation
is shown in Section 5.0.
CASE 1:
Object code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction
1111 0100 0101 0110 ; 2nd operand holds address of REG2
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes
1111 0100 0101 0110 ; 2nd operand becomes NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
DS39026B-page 40 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.9 Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-6
and Figure 4-7 show the data memory organization for
the PIC18CXX2 devices.
Banking is requ ire d to all o w mo re tha n 256 b y tes to be
accessed. The data memory map is divided into as
many as 16 banks that contain 256 bytes each. The
lower 4 bits of the Bank Select Register (BSR<3:0>)
select which bank will be accessed. The upper 4 bits
for the BSR are not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and periphe ral fu nctio ns , whi le GPRs are us ed f o r data
storage and scratch pad operations in the users appli-
cation. The SFRs star t at the last location of Bank 15
(OxFFF) and grow downwards. Any remaining space
beyond the S FRs in the Ban k may be im plem ente d as
GPRs. GPRs start at the first location of Bank 0 and
gro w upw ards. An y rea d of an unimpl emented l ocation
will read as ’0s.
The entire data memory may be accessed directly or
indirec tly. Direct addres sing ma y require the use of the
BSR register. Indirect addressing requires the use of
the File Select Register (FSR). Each FSR holds a 12-
bit address value that can be used to access any loca-
tion in the Data Memory map without banking.
The instruction set and architecture allow operations
across all ban ks. This ma y be accomplished b y indirect
addressing or by the use of the MOVFF instruction.
The MOVFF in struction is a tw o word /two c ycle instruc-
tion that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed i n a single c ycle regard-
less of the current BSR values, an Access Bank is
implemented. A segment of Bank 0 and a segment of
Bank 15 com prise the Acc es s RAM. Section 4.10 pro-
vides a detailed description of the Access RAM.
4.9.1 GENERAL PURPOSE REGISTER FILE
The regis ter file c an be ac cess ed eith er direct ly or ind i-
rectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other resets.
Data RAM is available for use as GPR registers by all
instr u ctio ns. The top ha lf of ba nk 15 (0xF8 0 to 0x FFF )
contain s SFRs. All ot her banks of data me mory contai n
GPR registers starting with bank 0.
4.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used b y the CPU and P eripheral Modules f or controlling
the desi red oper ation of the de vice . These regis ters are
implemented as static RAM. A list of these registers is
given in Table 4-1 and Table 4-2.
The SFRs can be classified into two sets; those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” ar e described in this sect ion , while thos e relate d
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are ty pically distri buted among the peripher-
als whose functions they control.
The unused SFR locations will be unimplemented and
read as '0's . See Tab le 4-1 f or addre sses f or the SFRs .
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 41
FIGURE 4-6: DATA MEMORY MAP FOR PIC18C242/442
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000b
= 0001b
= 1111b
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are
General Purpose RAM
(from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify
the RAM location that the
instru ction uses.
F7Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Unused
Access RAM high
Acce ss RAM low
Bank 2
to
200h
Unused
Read ’00h’
= 1110b
= 0010b (SFR’s)
DS39026B-page 42 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 4-7: DATA MEMORY MAP FOR PIC18C252/452
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000b
= 0001b
= 1110b
= 1111b
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are
General Purpose RAM
(from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify
the RAM location that the
instru ction uses.
Bank 4
Bank 3
Bank 2
F7Fh
F00h
EFFh
3FFh
300h
2FFh
200h
1FFh
100h
0FFh
000h
= 0110b
= 0101b
= 0011b
= 0010b
Access RAM
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
GPR
GPR
SFR
Unused
Access RAM high
Acce ss RAM low
Bank 5
GPR
GPR
Bank 6
to
4FFh
400h
5FFh
500h
600h
Unused
Read ’00h’
= 0100b
(SFR’s)
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 43
TABLE 4-1: SPECIAL FUNCTION REGISTER MAP
FFFh TOSU FDFh INDF2 (3) FBFh CCPR1H F9Fh IPR1
FFEh TOSH FDEh POSTINC2 (3) FBEh CCPR1L F9Eh PIR1
FFDh TOSL FDDh POSTDEC2 (3) FBDh CCP1CON F9Dh PIE1
FFCh STKPTR FDCh PREINC2 (3) FBCh CCPR2H F9Ch
FFBh PCLATU FDBh PLUSW2 (3) FBBh CCPR2L F9Bh
FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah
FF9h PCL FD9h FSR2L FB9h F99h
FF8h TBLPTRU FD8h STATUS FB8h F98h
FF7h TBLPTRH FD7h TMR0H FB7h F97h
FF6h TBLPTRL FD6h TMR0L FB6h F96h TRISE (2)
FF5h TABLAT FD5h T0CON FB5h F95h TRISD (2)
FF4h PRODH FD4h FB4h F94h TRISC
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB
FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h
FF0h INTCON3 FD0h RCON FB0h F90h
FEFh INDF0 (3) FCFh TMR1H FAFh SPBRG F8Fh
FEEh POSTINC0 (3) FCEh TMR1L FAEh RCREG F8Eh
FEDh POSTDEC0 (3) FCDh T1CON FADh TXREG F8Dh LATE (2)
FECh PREINC0 (3) FCCh TMR2 FACh TXSTA F8Ch LATD (2)
FEBh PLUSW0 (3) FCBh PR2 FABh RCSTA F8Bh LATC
FEAh FSR0H FCAh T2CON FAAh F8Ah LATB
FE9h FSR0L FC9h SSPBUF FA9h F89h LATA
FE8h WREG FC8h SSPADD FA8h F88h
FE7h INDF1 (3) FC7h SSPSTAT FA7h F87h
FE6h POSTINC1 (3) FC6h SSPCON1 FA6h F86h
FE5h POSTDEC1 (3) FC5h SSPCON2 FA5h F85h
FE4h PREINC1 (3) FC4h ADRESH FA4h F84h PORTE (2)
FE3h PLUSW1 (3) FC3h ADRESL FA3h F83h PORTD (2)
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB
FE0h BSR FC0h FA0h PIE2 F80h PORTA
Note 1: Unimplemented registers are read as ’0’
2: This registers is not available on PIC18C2X2 devices
3: This is no t a physical regi ster
DS39026B-page 44 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 4-2: REGISTER FILE SUMMARY
Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
resets
(note 3)
TOSU Top-of-Stack upper Byte (TOS<20:16>) ---0 0000 ---0 0000
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 0000 0000
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 0000 0000
STKPTR STKFUL STKUNF Return Stack Pointer 00-0 0000 00-0 0000
PCLATU Holding Regi st er for PC<20:16 > ---0 0000 ---0 0000
PCLATH Holdi ng Regi st er for PC<15:8> 0000 0000 0000 0000
PCL PC Low Byte (PC<7:0>) 0000 0000 0000 0000
TBLPTRU bit21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 ---0 0000
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 0000 0000
TABLAT Progr am Memory Table Latch 0000 0000 0000 0000
PRODH Product Register High Byte xxxx xxxx uuuu uuuu
PRODL Product Register Low Byte xxxx xxxx uuuu uuuu
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP 1111 -1-1 1111 -1-1
INTCON3 INT2IP INT1IP INT2IE INT1IE —INT2IFINT1IF11-0 0-00 11-0 0-00
INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) n/a n/a
POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) n/a n/a
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) n/a n/a
PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) n/a n/a
PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) -
value of FSR0 offset by value in WREG n/a n/a
FSR0H Indirect Data Memory Address Pointer 0 High Byte ---- 0000 ---- 0000
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx uuuu uuuu
WREG W orking Register xxxx xxxx uuuu uuuu
INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) n/a n/a
POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) n/a n/a
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) n/a n/a
PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) n/a n/a
PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) -
value of FSR1 offset by value in WREG n/a n/a
FSR1H Indirect Data Memory Address Pointer 1 High Byte ---- 0000 ---- 0000
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx uuuu uuuu
BSR Bank Select Register ---- 0000 ---- 0000
INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) n/a n/a
POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a n/a
POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) n/a n/a
PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a n/a
PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) -
value of FSR2 offset by value in WREG n/a n/a
FSR2H Indirect Data Memory Address Pointer 2 High Byte ---- 0000 ---- 0000
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx uuuu uuuu
STATUS —N OV Z DC C ---x xxxx ---u uuuu
TMR0H Timer0 register high byte 0000 0000 0000 0000
TMR0L Timer0 register low byte xxxx xxxx uuuu uuuu
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only and read ’0 in all
other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) resets include external reset through MCLR and Watchdog Timer Reset.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 45
OSCCON —SCS ---- ---0 ---- ---0
LVDCON IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 --00 0101
WDTCON —SWDTE---- ---0 ---- ---0
RCON IPEN LWRT —RI TO PD POR BOR 0q-1 11qq 0q-q qquu
TMR1H Timer1 Register High Byte xxxx xxxx uuuu uuuu
TMR1L Timer1 Register Low Byte xxxx xxxx uuuu uuuu
T1CON RD16 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR2 Timer2 R egister 0000 0000 0000 0000
PR2 Timer2 Period Register 1111 1111 1111 1111
T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPADD SSP Addr ess R egist er in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 0000 0000
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx uuuu uuuu
CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx uuuu uuuu
CCP1CON DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2H Capture/Compare/PWM Register2 High Byte xxxx xxxx uuuu uuuu
CCPR2L Capture/Compare/PWM Register2 Low Byte xxxx xxxx uuuu uuuu
CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
TMR3H Timer3 Register High Byte xxxx xxxx uuuu uuuu
TMR3L Timer3 Register Low Byte xxxx xxxx uuuu uuuu
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
SPBRG USART1 Baud Rate Generator 0000 0000 0000 0000
RCREG USART1 Receive Register 0000 0000 0000 0000
TXREG USART1 Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
TABLE 4-2: REGISTER FILE SUMMARY (Cont.d)
Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
resets
(note 3)
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only and read ’0 in all
other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) resets include external reset through MCLR and Watchdog Timer Reset.
DS39026B-page 46 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.10 Access Bank
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Comm on variables
Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-6
and Figure 4-7 indicate the Access RAM areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ’a’ bit (for
access bit) .
When forced in the Access Bank (a = ’0’), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function registers so that these registers
can be accessed without any software overhead. This
is useful for testing status flags and modifying control
bits.
IPR2 BCLIP LVDIP TMR3IP CCP2IP ---- 1111 ---- 1111
PIR2 BCLIF LVDIF TMR3IF CCP2IF ---- 0000 ---- 0000
PIE2 BCLIE LVDIE TMR3IE CCP2IE ---- 0000 ---- 0000
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISE IBF OBF IBOV PSP-
MODE Data Direction bits f or PORTE 0000 -111 0000 -111
TRISD Data Direction Control Register for PORT D 1111 1111 1111 1111
TRISC Data Direction Control Register for PORT C 1111 1111 1111 1111
TRISB Data Direction Control Register for PORT B 1111 1111 1111 1111
TRISA TRISA6(1) Data Direction C ont rol R egist er for PORTA -111 1111 -111 1111
LATE Read PORTE Data Latch, Write
PORTE Data Latch ---- -xxx ---- -uuu
LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx uuuu uuuu
LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx uuuu uuuu
LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx uuuu uuuu
LATA LATA6(1) Read POR TA Data Latch, Write PORTA Data Latch(1) -xxx xxxx -uuu uuuu
PORTE Read PORTE pins, Write POR TE Data Latch ---- -000 ---- -000
PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx uuuu uuuu
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx uuuu uuuu
PORTB Read PORTB pins, Write POR TB Data Latch xxxx xxxx uuuu uuuu
PORTA RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 -u0u 0000
TABLE 4-2: REGISTER FILE SUMMARY (Cont.d)
Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
resets
(note 3)
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only and read ’0 in all
other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) resets include external reset through MCLR and Watchdog Timer Reset.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 47
4.11 Bank Sel ect Regist er (BSR )
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
des i red bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
A MOVLB instructio n has been pro vided in the in struc-
tion set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleare d as appro priate
for the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is imp lemented as static RAM.
A MOVFF inst ruction ig nore s t he BSR , si nc e th e 1 2-b it
addresses are embedded into the instruction word.
Section 4.12 provi des a descriptio n of indirect addr ess-
ing, which allows linear addressing of the entire RAM
space.
FIGURE 4-8: DIRECT ADDRESSING
Note 1: For register file map detail, see Table 4-1.
2: The access bit of the instruction can be used to force an override of the selected bank
(BSR<3:0>) to the registers of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data
Memory(1)
Direct Addressing
bank select(2)location select(3)
BSR<3:0> 7 0
from opcode(3)
00h 01h 0Eh 0Fh
Bank 0 Bank 1 Bank 14 Bank 15
1FFh
100h
0FFh
000h
EFFh
E00h
FFFh
F00h
DS39026B-page 48 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.12 Indirect Addressing, INDF and FSR
Registers
Indir ect addressin g is a mode of address ing data mem-
ory, where the data memory address in the instruction
is not fixed. An SFR register is use d as a pointer to th e
data memory location that is to be read or written.
Since this pointer is in RAM, the contents can be mod-
ified by the program. This can be useful for data tables
in the data me mory and f or softw are stac ks . Figu re 4-9
sho ws the oper ation of indire ct address ing. This sho ws
the moving of the value to the data memory address
specified by the value of the FSR register.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself
indirectly (FSR = ’0’) will read 00h. Writing to the INDF
register indirectly results in a no-operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer) . This is indi rect addressing.
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-4: HOW TO CLEAR RAM
(BANK1) USING INDIRECT
ADDRESSING
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required . These indire ct add res si ng regi ste r s are:
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data.
If an instruction writes a value to INDF0, the value will
be written to th e add res s poi nte d t o b y F S R0H :FSR0 L.
A read from INDF1 reads the data from the address
pointed to by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ’0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
oper ation will be equiv alent to a NOP instruction and the
STATUS bits are not affected.
4.12.1 INDIRECT ADDRESSING OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Per-
forming an operation on one of these five registers
determines how the FSR will be modified during indi-
rect addressing.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
Do nothing to FSRn after an indirect access (no
change) - INDFn
Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn
Auto-increment FSRn after an indirect access
(post-increment) - POSTINCn
Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn
Use the value in the WREG register as an offset
to FSRn. Do not m odify the v alue of the W REG or
the FSRn register after an indirect access (no
change) - PLUSWn
When using the auto-increment or auto-decrement
feat ures, the effect on the FS R is not refle cted in th e
STATUS regist er. For example, if t he in direc t addre ss
causes the FSR to equal '0', the Z bit will not be set.
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL ov erflows from an increment,
FSRnH will be incremented automatically.
Adding thes e fe atures allo ws the FSRn to be used as a
stack pointer in addition to its uses for table operations
in data memory.
Each FSR has an address associated with it that per-
forms an indexed ind irec t ac cess . Wh en a da ta a cc es s
to this INDFn location (PLUSWn) occurs, the FSRn is
configu r ed to a dd the si gned value in the WREG re gis -
ter and the value in FSR to form the address before an
indirect access. The FSR value is not changed.
If an FSR regis ter contains a value tha t points to on e of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(STATUS bits are not affected).
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or post-
increment/decrement functions.
LFSR 0x100, FSR0 ;
NEXT CLRF POSTINC0 ; Clear INDF register
; & inc pointer
BTFSS FSR0H, 1 ; All done w/ Bank1?
GOTO NEXT ; NO, clear next
CONTINUE ;
: ; YES, continue
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 49
FIGURE 4-9: INDIRECT ADDRESSING OPERATION
FIGURE 4-10: INDIRECT ADDRESSING
Opcode Address
File Address = access of an indirect addressing register
FSR
Instruction
Executed
Instruction
Fetched
RAM
Opcode File
12
12
12
BSR<3:0>
8
4
0h
FFFh
Note 1: For register file map detail, see Table 4-1.
Data
Memory(1)
Indirect Addressing
FSR register11 0
0FFFh
0000h
location select
DS39026B-page 50 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.13 STATUS Register
The STATUS register, shown in Register 4-2, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled. These bits
are set or clea red a cc ord ing to the device logic. The r e-
fore , th e result of an in stru cti on with the STATUS regi s-
ter as destination may be different than intended.
For example, CLRF STATUS will cl ea r t h e up per - th r ee
bits an d set the Z bi t. T his l ea ve s the STATUS regist er
as 000u u1uu (where u = unchanged).
It is recommended, t herefore, that only BCF, BSF,
SWAPF, MO VFF and MOVWF instructions ar e used to
alter the STATUS register, because these instruc-
tions do not affect the Z, C, DC, OV or N bits from
the STATUS register. For other instructions not
affecting any status bits, see Table 19-2.
Register 4-2: STATUS Register
Note: The C and DC b its operat e as a bo rrow and
digit borrow bit respectively, in subtraction.
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
—— NOVZDCC
bit 7 bit 0
bit 7:5 Unimpl emented: Read as0’
bit 4 N: Negative bit
This bit is use d for sign ed arithmatic (2’ s com plement). It indicate s whether the resu lt was neg-
ative, (ALU MSB = 1)
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used f or signed arithmetic (2’ s complement). It indicates an over flow of the 7-bit mag-
nitude, which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmatic (in this arithmetic operation)
0 = No overflow occurred
bit2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. Fo r rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.
bit 0 C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 51
4.13.1 RCON REGISTER
The Reset Control (RCON) register contains flag bits,
that allow differentiation between the sources of a
device reset. These flags include the TO, PD, POR,
BOR and RI bits . This regis ter is readab le and writable .
Register 4-3: RCON Register
Note 1: If the BOREN configu ration bit is set, BOR
is ’1’ on Power-on Reset. If the BOREN
configu r a tio n b it i s c lea r, BOR is unknown
on Power-on Reset.
The BOR sta tus bi t is a "d on't c are" an d is
not necessarily predictable if the brown-
out circuit is disabled (the BOREN config-
ura tion bi t is clear). BOR mu st then b e set
by the user and checked on subsequent
resets to see if it is clear, indicating a
brown -out has occurred.
2: It is recomme nded that the PO R bit be set
after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable pr ior ity levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enable bit
1 = Enable TBLWT to internal program memory
Once this bit is set, it can only be cleared by a POR or MCLR reset.
0 = Disable TBLWT to internal program memory; TBLWT only to external program memory
bit 5 Unimplemented: Read as ’0
bit 4 RI: Reset In struction Flag bit
1 = The Reset instruction was not executed
0 = The Reset instruction was executed causing a device reset
(must be set in software after a Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = After power-up, CLRWDT instruction, or SLEEP instr uction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP inst ruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred
0 = A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown- out Reset has not occurr ed
0 = A Brown-out Reset o c curred
(must be set in softwa re after a Brown-out Reset occurs)
Legend:
R = Reada ble bit W = Wri table bi t U = Unimplemented bit, read as ‘0’
- n = Value at POR reset 1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS39026B-page 52 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 53
5.0 TABLE READS/TA BLE WRITES
Enhanced devices have two memory spaces: the pro-
gr am me mo ry space and t he da ta m em ory space . Th e
program memory space is 16 bits wide, while the data
memory space is 8 bits wide. Table Reads and Table
Writes have been provided to move data between
these two memory spaces through an 8 bit register
(TABLAT).
The operations that allow the processor to move data
between the data and program memory spaces are:
•Table Read (TBLRD)
Table Write (TBLWT)
Table Read operations retrieve data from program
memory and place it into the Data memory space.
Figure 5-1 shows the operation of a Table Read with
program and data memory.
Table Write operations store data from the data mem-
ory space into program memory. Figure 5-2 shows the
oper ation of a Table Write with progra m and da ta mem-
ory.
Table operations work with byte entities. A table block
contain ing dat a is no t require d to be wo rd align ed, so a
table block can start an d en d at any byte add res s. If a
table write is being used to write an e xecutable program
to program memory, program instructions will need to
be word aligned.
FIGURE 5-1: TABLE READ OPERATION
FIGURE 5-2: TABLE WRITE OPERATION
TABL E PO INTER (1) TABLE LATCH (8-bit)
PROGRAM MEMORY
TBLPTRH TBLPTRL TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer points to a byte in
program memory
Program Memory
(TBLPTR)
TABL E PO INTER (1) TABLE LATCH (8-bit)
PROGRAM MEMORY
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: Table Pointer points to a byte in
program memory
DS39026B-page 54 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
5.1 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
TBLPTR registers
TABLAT register
RCON register
5.1.1 RCON REGISTER
The LWRT bit specifies the operati on of Table Writes to
internal mem ory when the VPP voltage is appli ed to th e
MCLR pin. When the LWRT bit is set, the controller
continues to execute user code, but long table writes
are allowed (for programming internal program mem-
ory) from user mode. The L WR T bit can be cleared only
by perfo rming either a POR or MCLR reset.
Register 5-1: RCON Register (Address: 08h)
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable
1 = Enable priority levels on interrupts
0 = Disable pr iority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enable
1 = Enable TBLWT to internal program memory
0 = Disable TBLWT to internal program memory.
Note 1: Only cleared on a POR or MCLR reset.
This bit has no effect on TBLWTs to external program memory.
bit 5 Unimplemented: Re ad as ’0’
bit 4 RI: Reset Instruction Flag bit
1 = No Reset instruction occur red
0 = A Reset instruction occurred
bit 3 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instr uction
0 = A WDT time-out occurred
bit 2 PD: Powe r-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset nor POR reset occurred
0 = A Brown-out Reset nor POR reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Reada ble bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 55
5.1.2 TABLAT - TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data memor y.
5.1.3 TBLPTR - TABLE POINTER REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper byte, High
byte and Low byte). These three registers (TBLP-
TRU:TBLPTRH:TBLPTRL) join to form a 22-bit wide
pointer. The low order 21-bits allow the device to
address up to 2M b ytes of progr am memory space. The
22nd bit allows access to the Device ID, the User ID
and the Configuration bits.
The ta ble poin te r TBL PT R is use d by the TB LR D an d
TBLWT instructions. These instructions can update
the TBLPTR in one of four ways based on the table
operation. These operations are shown in Table 5-1.
These o perations on the TBL PTR only af fe ct the low
order 21 -b it s.
TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLWT* TBLPTR is not modified
TBLRD*+
TBLWT*+ TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*- TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+* TBLPTR is incremented before the read/write
DS39026B-page 56 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
5.2 Internal Program Memory Read/
Writes
5.2.1 TABLE READ OVERVIEW (TBLRD)
The TBLRD instruct ions are used to read d ata from pro-
gram memory to data memory.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into TAB-
LAT. In addition, TBLPTR can be modified automati-
cally for the next Table Read operation.
Table R eads from p rogr am memo ry are perf o rmed one
by te at a tim e. The instruction will load TABLAT with the
one b yte from progr am memory point ed to b y TBLP TR.
5.2.2 INTERNAL PROGRAM MEMORY WRITE
BLOCK SIZE
The internal program memory of PIC18CXXX devices
is written in blocks. For PIC18CXX2 devices, the write
block size is 2 bytes. Consequently, Table Write oper-
ations to internal program memory are performed in
pairs, one byte at a time.
When a Table Write occurs to an even program mem-
ory address (TBLPTR <0> = 0 ), the co ntents of TABLAT
are transferred to an internal holding register. This is
performed as a short write and the program memory
blo ck is not actually prog rammed at th is time. T he hold-
ing register is not accessible by the user.
When a Table Write o ccurs to an odd pro gr am me mory
address (TBLPTR,)>=1), a long write is started. During
the lon g write, th e contents of TABLAT are written to the
high byte of the program memory block and the con-
tents of the holding register are transferred to the low
byte of the program memory block.
Figure 5-3 shows the holding register and the program
memory write blocks.
If a single b yte is to be prog rammed, the low (eve n) byte
of the destination program word should be read using
TBLRD*, modified or changed, if required, and written
back to the same address using TBLWT*+. The high
(odd) byte should be read using TBLRD*, modified or
changed if required, and written back to the same
address using TBLWT. The write to an odd address will
cause a long write to begin. This process ensures that
existing data in either byte will not be changed unless
desired.
FIGURE 5-3: HOLDING REGISTER AND THE WRITE BLOCK
Block n
Block n + 1
Block n + 2
MSB
The write to the MSB of the Write Block
causes the entire block to be written to pro-
gram memory. The program memory block
that is written depends on the address that is
written to in the MSB of the Write Block.
Holding Register
Program Memory (x 2-bits)
Write Block
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 57
5.2.2.1 OPERATION
The long w rite is wh at ac tua ll y pro g r am s w o rds of da ta
into the internal mem ory. When a TBLWT to the MSB of
the write block occurs, instruction execution is halted.
During this time, programming voltage and the data
stored in internal latches is applied to program memory .
For a long write to occur:
1. MCLR/VPP pin must be at the pro grammin g volt-
age
2. LWRT bit must be set
3. TBLWT to the address of the MSB of the write
block
If the LWRT bit is clear , a short write will occur and pro-
gram memory will not be changed. If the TBLWT is not
to the MSB of the write block, then the programming
phase is not initiated.
Setting the LWRT bit enables long writes when the
MCLR pin is taken to VPP volta ge. Once the LW RT bit
is set, it can be cleared only by performing a POR or
MCLR reset.
To ensure that the m em ory location has been well pro-
grammed, a minimum programming time is required.
The long write can be terminated after the program-
ming time has expired by a reset or an interrupt. Having
only on e inte rrupt so urce e nab led to terminate the lon g
write ensures that no unintended interrupts will prema-
turely terminate the long write.
5.2.2.2 SEQUENCE OF EVENTS
The sequence of events for programming an internal
program memory location should be:
1. Enable the interrupt that terminates the long
write. Disable al l other interrupts.
2. Clear the source interrupt flag.
3. If Interrupt Service Routine execution is desired
when the device wakes, enable global inter-
rupts.
4. Set LWRT bit in the RCON register.
5. Raise MCLR/VPP pin to the programming volt-
age, VPP.
6. Clear the WDT (if enabled).
7. Set the interrupt source to interrupt at the
required tim e .
8. Exec ute the tab le write f or the low er (ev en) b yte.
This will be a short write.
9. Execute the table write for the upper (odd) byte.
This w ill be a lo ng write. The control ler will go to
sleep while programming. The interrupt wakes
the controller.
10. If GIE was set, service the interrupt request.
11. Lower MCLR/VPP pin to VDD.
12. Verify the memory location (table read).
DS39026B-page 58 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
5.2.3 INTERRUPTS
The long write must be terminated by a reset or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur regardless of the
setting s of interrupt priority bits , the GIE/GIEH bit or th e
PIE/GIEL bit.
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR) or continue execution from
where programming commenced.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
TABLE 5-2: SLEEP MODE, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
GIE/
GIEH PIE/
GIEL Priority Interrupt
Enable Interrupt
Flag Action
XX X 0
(default) X Long write continues even if interrupt
flag becomes set during sleep.
X X X 1 0 Long write continues, will wake when
the interrupt flag is set.
0
(default) 0
(default) X 1 1 Terminates long write,
executes next instruction. Interrupt flag
not cleared.
0
(default) 11
high priority
(default)
1 1 Terminates long write,
executes next instruction. Interrupt flag
not cleared.
10
(default) 0
low 1 1 Terminates long write, executes next
instruction. Interrupt flag not cleared.
0
(default) 10
low 1 1 Terminates long write, branches to low
priority interrupt vector.
Interrupt flag can be cleared by ISR.
10
(default) 1
high priority
(default)
1 1 Terminates long write, branches to high
priority interrupt vector.
Interrupt flag can be cleared by ISR.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 59
5.2.4 UNEXPECTED TERMINATION OF WR ITE
OPERATIONS
If a write is terminated by an unplanned event such as
loss o f power, an unexpected res et, o r an in terrupt th at
was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
DS39026B-page 60 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 61
6.0 8 X 8 HARDWARE MULTIPLIER
6.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18CXX2 devices. By making the multiply a
hardw a re o peration, it compl ete s in a sing le ins tructio n
cycle. This is an unsigned multiply that gives a 16-bit
result. Th e resul t is store d into th e 16-bit product regi s-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
Higher computational throughput
Reduc es co de si z e requirem ents for mult ipl y alg o-
rithms
The perf ormance inc rease allo ws the de vice to be used
in applications previously reserved for Digital Signal
Processors.
Table 6-1 shows a performance comparison between
enhance d devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 6-1: PERFORMANCE COMPARISON
Routine Multiply Method Program
Memory
(Words)
Cycles
(Max) Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned Without hardwa re multiply 13 69 6.9 µs27.6 µs69 µs
Hardware multiply 1 1 100 ns 400 ns 1 µs
8 x 8 signed Without hardware multiply 33 91 9.1 µs36.4 µs91 µs
Hardware multiply 6 6 600 ns 2.4 µs6 µs
16 x 16 unsigned Without hardware multiply 21 242 24.2 µs96.8 µs242 µs
Hardware multiply 24 24 2.4 µs9.6 µs24 µs
16 x 16 signed Without hardwa re multiply 52 254 25.4 µs 102.6 µs254 µs
Hardware multiply 36 36 3.6 µs14.4 µs36 µs
PIC18CXX2
DS39026B-page 62 Preliminary 7/99 Microchip Technology Inc.
6.2 Operation
Example 6-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argumen t of the m u lti ply i s alre ady l oaded in
the WREG regist er.
Exampl e 6-2 shows th e sequence t o do an 8 x 8 s igned
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 6-1: 8 x 8 UNSIGNED MULTIPLY
ROUTINE
EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
Example 6-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EQUATION 6-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)
EXAMPLE 6-3 : 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 6-4 shows the sequence to do an 16 x 16
signed multiply. Equation 6-2 shows the algorithm
used. The 32-bit result is stored in four registers
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 6-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
= ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)+
(-1 ARG2H<7> ARG1H:ARG1L 216)+
(-1 ARG1H<7> ARG2H:ARG2L 216)
MOVFF ARG1, WREG ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVFF ARG1, WREG
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVFF ARG2, WREG
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
MOVFF ARG1L, WREG
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVFF ARG1H, WREG
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVFF ARG1L, WREG
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVFF PRODL, WREG ;
ADDWF RES1, F ; Add cross
MOVFF PRODH, WREG ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
MOVFF ARG1H, WREG ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVFF PRODL, WREG ;
ADDWF RES1, F ; Add cross
MOVFF PRODH, WREG ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 63
EXAMPLE 6-4: 16 x 16 SIGNED MULTIPLY
ROUTINE
MOVFF ARG1L, WREG
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVFF ARG1H, WREG
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVFF ARG1L, WREG
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVFF PRODL, WREG ;
ADDWF RES1, F ; Add cross
MOVFF PRODH, WREG ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
MOVFF ARG1H, WREG ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVFF PRODL, WREG ;
ADDWF RES1, F ; Add cross
MOVFF PRODH, WREG ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
GOTO SIGN_ARG1 ; no, check ARG1
MOVFF ARG1L, WREG ;
SUBWF RES2 ;
MOVFF ARG1H, WREG ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
GOTO CONT_CODE ; no, done
MOVFF ARG2L, WREG ;
SUBWF RES2 ;
MOVFF ARG2H, WREG ;
SUBWFB RES3
;
CONT_CODE
:
PIC18CXX2
DS39026B-page 64 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 65
7.0 INTERRUPTS
The PIC18CXX2 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 0 00008h and the low priority interrupt v ector
is at 000018h. High priority interrupt events will over-
ride any low priority interrupts that may be in progress.
There are ten registers which are used to control inter-
rupt operation. These registers are:
RCON
•INTCON
INTCON2
INTCON3
PIR1, PIR2
PIE1, PIE2
IPR1, IPR2
It is recommended that the Microchip header files sup-
plied with MPLAB be used for the symbolic bit names
in these registers. This allows the assembler/compiler
to automatically take care of the placement of these bits
within the specified register.
Each interrupt source has three bits to control its oper-
ation. The functions of these bits are:
Flag bit to indicate that an interrupt event
occurred
Enable bit that allows program execution to
branch to the interrupt vector address when
the flag bit is set
Priority bit to sel ect hig h priority or lo w priority
The interr upt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enab led, the re are tw o bits wh ich e nab le in terrupts gl o-
bally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that hav e the priority bit set. Setting the GIEL
bit (INTCON<6>) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable it are set, the
inter rupt will v e cto r imme diatel y to a ddress 00000 8h or
000018h depending on the priority level. Individual
interr upts can be disabled through their corresponding
enable bits.
When the IPEN bit is cleared (default state), the inter-
rupt priority feature is disabled and interrupts are com-
patible with PICmicro mid-range devices. In
compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enab les/dis able s all perip heral i nterrupt sourc es.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in compatibility mode.
When an in terrupt is respo nde d to, the Global In terrupt
Enab le bit is cle ared t o disable f urther interrupts. If the
IPEN bit is c leared, this is the GIE bit. If interrupt prior-
ity levels are used, this will be either the GIEH or GIEL
bit. High priority interrupt sources can interrupt a low
priority interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the interrupt service
routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bi ts m ust b e cle ared i n soft ware bef ore re-ena b ling
interrupts to avoid recursive interrupts.
The "return from interrupt" instruction, RETFIE, exits
the interru pt routine and se ts the GIE bit (GIE H or GI EL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the POR TB input c hange interrupt, the in terrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
PIC18CXX2
DS39026B-page 66 Preliminary 7/99 Microchip Technology Inc.
FIGURE 7-1: INTERRUPT LOGIC
T0IE
GIEH/GIE
GIEL/PEIE
W ak e- up if in SLEEP mode
Interrupt to CPU
Vector to location
0008h
INT2F
INT2E
INT2P
INT1F
INT1E
INT1P
T0IF
T0IE
T0IP
INT0F
INT0E
RBIF
RBIE
RBIP
IPE
T0IF
T0IP
INT1F
INT1E
INT1P
INT2F
INT2E
INT2P
RBIF
RBIE
RBIP
INT0F
INT0E
GIEL\PEIE
Interrupt to CPU
Vector to Location
IPE
IPE
0018h
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
XXXXIF
XXXXIE
XXXXIP
Additional Peripheral Interrupts
TMR1IF
TMR1IE
TMR1IP
High Priority Interrupt Generation
Low Priority Interrupt Generation
XXXXIF
XXXXIE
XXXXIP
Additional Peripheral Interrupts
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 67
7.0.1 INTC ON REGISTERS
The INTCON Registers are readable and writable
registers, which contains various enable, priority and
flag bits.
Register 7-1: INTCON Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all un-masked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all interrupts
0 = Disables all interrupts
bit 6 PEIE/GEIL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 exter n al interrupt
0 = Disables the INT0 exter nal interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its co rres po ndi ng enab l e bi t or t he global e na b l e bi t. U s er s oftw a r e should ens ure
the app ropriate interrupt fl ag bi ts are clear prior to e nab ling an in terrupt. Thi s f ea ture
allows for software polling.
PIC18CXX2
DS39026B-page 68 Preliminary 7/99 Microchip Technology Inc.
Register 7-2: INTCON2 Register
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 TMR0IP RBIP
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0:External Interrupt0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Re ad as '0'
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Re ad as '0'
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset 1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its co rres po ndi ng enab l e bi t or t he global e na b l e bi t. U s er s oftw a r e should ens ure
the app ropriate interrupt f lag bi ts are clear prior to e nab ling an in terrupt. Thi s f ea ture
allows for software polling.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 69
Register 7-3: INTCON3 Register
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF
bit 7 bit 0
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 =High priority
0 =Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 =High priority
0 =Low priority
bit 5 Unimplemented: Read as '0'
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 =Enables the INT2 exter n al interrupt
0 =Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 =Enables the INT1 exter n al interrupt
0 =Disables the INT1 external interrupt
bit 2 Unimplemented: Read as '0'
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 =The INT2 external interrupt occurred
(must be cleared in software)
0 =The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 =The INT1 external interrupt occurred
(must be cleared in software)
0 =The INT1 ex ternal interrupt did not occur
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its co rres po ndi ng enab l e bi t or t he global e na b l e bi t. U s er s oftw a r e should ens ure
the app ropriate interrupt fl ag bi ts are clear prior to e nab ling an in terrupt. Thi s f ea ture
allows for software polling.
PIC18CXX2
DS39026B-page 70 Preliminary 7/99 Microchip Technology Inc.
7.0.2 PIR REGISTERS
The PIR registe rs conta in the ind ividu al flag bi ts f or the
peripheral interrupts. Due to he number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag Registers (PIR1, PIR2).
7.0.3 PIE REGISTERS
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Enable Registers (PIE1, PIE2). When IPEN = 0,
the PEIE bi t must be set to e na b l e an y o f th es e p eriph-
eral interrupts.
7.0.4 IPR REGISTERS
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to on the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority Register s (IPR1, IPR2). The opera tion
of the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
7.0.5 RCON REGISTER
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN).
Register 7-4: RCON Register
Note 1: Interrupt flag bi ts get s et when an in terrupt
conditi on occurs , regardles s of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
Note 2: User softwa re shou ld ens ure the ap propri-
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable pr ior ity levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enab l e
For details of bit operation see Register 4-1
bit 5 Unimplemented: Read as ’0’
bit 4 RI: Reset In struction Flag bit
For details of bit operation see Register 4-1
bit 3 TO: Watchdog Time-out Flag bit
For details of bit operation see Register 4-1
bit 2 PD: Power-down Detection Flag bit
For details of bit operation see Register 4-1
bit 1 POR: Power-on Reset Status bit
For details of bit operation see Register 4-1
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation see Register 4-1
Legend:
R = Reada ble bit W = Wri table bi t U = Unimplemented bit, read as ‘0’
- n = Value at POR reset 1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 71
Register 7-5: Peripheral Interrupt Request (Flag) Registers
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
PIR2 BCLIF LVDIF TMR3IF CCP2IF
bit 7 bit 0
PIR1 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place
(must be cleared in software)
0 = No read or write has occurred
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
(must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer, RCREG, is full
(cleared when RCREG is read)
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer, TXREG, is empty
(cleared when TXREG is written)
0 = The USART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete
(must be cleared in software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred
(must be cleared in software)
0 = No TMR1 register capture occurred
Compar e Mode
1 = A TMR1 register com pare m atch occurred
(must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred
(must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed
(must be cleared in software)
0 = TMR1 re gister did not overflow
PIC18CXX2
DS39026B-page 72 Preliminary 7/99 Microchip Technology Inc.
Register 7-5: Peripheral Interrupt Request (Flag) Registers (cont’d)
PIR2 bit 7-4 Unimplemented: Read as ’0’
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A Bus Collision occurred
(must be cleared in software)
0 = No Bus Collision occurred
bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low voltage condition occurred
(must be cleared in software)
0 = The device voltage is above the Low Voltage Detect trip point
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 regi ster overflowed
(must be cleared in software)
0 = TMR3 register did not overflow
bit 0 CCP2IF: CCPx Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred
(must be cleared in software)
0 = No TMR1 register capture occurred
Comp are Mod e
1 = A TMR1 register compare match occurred
(must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 73
Register 7-6: Peripheral Interrupt Enable Registers
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
PIE2 BCLIE LVDIE TMR3IE CCP2IE
bit 7 bit 0
PIE1 bit 7 PSPIE: Parallel Slave Port Read/Write Interr upt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Po rt Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP inte rrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PIE2 bit 7-4 Unimplemented: Read as '0'
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 LVDIE: Low-voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enables the TMR3 overflow interrupt
0 = Disables the TMR3 overflow interrupt
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026B-page 74 Preliminary 7/99 Microchip Technology Inc.
Register 7-7: Peripheral Interrupt Priority Registers
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
IPR2 BCLIP LVDIP TMR3IP CCP2IP
bit 7 bit 0
IPR1 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RCIP: USART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TXIP: USART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
IPR2 bit 7-4 Unimplemented: Read as '0'
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 LVDIP: Low-voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 75
7.0.6 INT0 INTERRUPT
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising if the
corresp onding INTEDGx b it is set in the INTCON2 re g-
ister, or falling, if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit INTxF is set. This interrupt can be disabled by
clear ing t he corr espondi ng enable b it INTx E. Flag bit
INTxF must be cleared in software in the interrupt ser-
vice routine before re-enabling the interrupt. All exter-
nal interrupts (INT0, INT1 and INT2) can wake-up the
processor from SLEEP, if bit INTxE was set prior to
going into SL EEP. If the gl ob al in terrup t ena b l e bit G IE
set, the proce ssor will bran ch to the i nter rupt v ector f ol-
lowing wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
7.0.7 TMR0 INTERRUPT
In 8-bit mo de (which is the d efault ), an ov erflo w (FFh
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh 0000h) in the
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit T0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2<2 >). See Sec-
tion 8.0 for further details on the Timer0 module.
7.0.8 PORTB INTERRUPT ON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>).
Interrupt priority for PORTB Interrupt on change is
determined by the value contained in the interrupt pri-
ority bit RBIP (INTCON2<0>).
7.1 Context Saving During Interrupts
During an interrupt, the re turn PC v alu e is sa ve d on the
stack. Additionally, the WREG, STATUS and BSR reg-
isters are sav ed on the f ast retu rn stac k. If a f ast return
from interrupt is not used (See Section 4.3), the user
ma y n eed t o s ave the WR EG, STATUS and BSR regis -
ters in software. Depending on the user’s application,
other registers ma y also n eed to be sav ed. Example 6-
1 saves and restores the WREG, STATUS and BSR
register s during an inter rupt service routine.
EXAMPLE 7-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
PIC18CXX2
DS39026B-page 76 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 77
8.0 I/O PORTS
Depen ding on the de vic e selected , there are either five
ports or three ports available. Some pins of the I/O
ports are multiplexed with an alternate function from
the peripheral features on the device. In general, when
a peripheral is enabled, that pin may not be used as a
general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
TRIS register (Data Direction register)
PORT register (rea ds the levels o n th e pi ns of th e
device)
LAT register (output latch)
The data latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are driv-
ing.
8.1 PORTA, TRISA and LATA Registers
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA b it (=1 ) wi ll m ake the correspo ndi ng PORTA pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
mak e the corresp onding POR TA pin an output, (i.e ., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the por t latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register reads and writes the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open drain
output. Al l other R A port pin s ha ve TTL inpu t le ve ls and
full CMOS output drivers.
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
oper ation of ea ch pin is selected by c learing/settin g the
control bits in the ADCON1 register (A/D Control
Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user m ust ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 8-1: INITIALIZING PORTA
Note: On a Power-on Reset, these pins are con-
figured as inputs and read as '0'.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 0x07 ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
PIC18CXX2
DS39026B-page 78 Preliminary 7/99 Microchip Technology Inc.
FIGURE 8-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 8-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
FIGURE 8-3: BLOC K DIAGRAM OF RA6
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR LATA
WR TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins hav e protection diodes to VDD and VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter and LVD Modules
RD LATA
or
PORTA
SS input (RA5 only)
Data
Bus
WR TRISA
RD PORTA
Data Latch
TRIS Latch
RD TRISA
Schmitt
Trigger
input
buffer
N
VSS
I/O pin(1)
TMR0 Cock Input
Note 1: I/O pin has protection diodes to VSS only.
QD
Q
CK
QD
Q
CK
EN
QD
EN
RD LATA
WR LATA
or
PORTA
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR LATA
WR
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins hav e protection diodes to VDD and VSS.
or
PORTA
RD LATA
ECRA6 or
Data Bus
ECRA6 or
enable
Data Bus
TTL
input
buffer
RCRA6
RCRA6 enable
TRISA
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 79
TABLE 8-1: PORTA FUNCTIONS
TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input
RA1/AN1 bit1 TTL Input/output or analog input
RA2/AN2/VREF- bit2 TTL Input/output or analog input or VREF-
RA3/AN3/VREF+ bit3 TTL Input/output or analog input or VREF+
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4/LVDIN bit5 TTL Input/output or slave select input for synchronous serial port or analog
input, or low voltage detect input
OSC2/CLKO/RA6 bit6 O SC2 or clock output or I/O pin
Legend: TTL = TTL input, ST = Schmitt Trigger input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other
resets
PORTA RA6 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
LATA Latch A Data Output Register --xx xxxx --uu uuuu
TRISA PORTA Data Direction Register --11 1111 --11 1111
ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unk nown , u = un ch anged, - = uni mplemen ted loc ations read a s ’ 0 . Shad ed ce lls are not us ed b y PORTA.
PIC18CXX2
DS39026B-page 80 Preliminary 7/99 Microchip Technology Inc.
8.2 PORTB, TRISB and LATB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will mak e the corres ponding POR TB pi n
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, ( i.e. put
the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register reads and writes the latched output value for
PORTB.
EXAMPLE 8- 2: INITIALIZING PORTB
Each o f the PO RTB pins h as a weak internal pull -up. A
single control bi t can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2<7>). The
weak pu ll-up i s automa tically tur ned off when t he por t
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause t his interrupt to occur (i.e . an y RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compar ed w ith th e o ld value latc he d o n the la st read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user , in th e interrupt service routine , can clear the in ter-
rupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 8-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
FIGURE 8-5: BLOCK DIAGRAM OF
RB2:RB0 PINS
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Data Latch
From other
RBPU(2) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR LATB
WR TRISB
Set RBIF
TRIS Latch
RD TRISB
RD PORTB
RB7:RB4 pins
weak
pull-up
RD PORTB
Latch
TTL
Input
Buffer
pin(1)
ST
Buffer
RBx/INTx Q3
Q1
RD LATB
or
PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2<7>).
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBP U bit (OPTION_REG<7>).
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 81
FIGURE 8-6: BLOCK DIAGRAM OF RB3
Data Latch
P
VDD
QD
CK
QD
EN
Data Bus
WR LATB or
WR TRISB
RD TRISB
RD PORTB
weak
pull-up
CCP2 input(3)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
RD LATB
WR PORT B
RBPU(2)
CK
D
Enable (3)
CCP Output
RD PORTB
CCP Output(3) 1
0P
N
VDD
VSS
I/O
Pin(1)
Q
CCP2MX
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register.
PIC18CXX2
DS39026B-page 82 Preliminary 7/99 Microchip Technology Inc.
TABLE 8-3: PORTB FUNCTIONS
TABLE 8-4: SUMMARY OF REGISTERS
ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT0 bit0 TTL/ST(1) Input/output pin or external interrupt input1. Internal software
programmable weak pull-up.
RB1/INT1 bit1 TTL/ST(1) Input/output pin or external interrupt input2. Internal software programma-
ble weak pull-up.
RB2/INT2 bit2 TTL/ST(1) Input/output pin or external interrupt input3. Internal software programma-
ble weak pull-up.
RB3/CCP2 (3) bit3 TTL/ST(4) Input/output pin. Capture2 input/Compare2 output/PWM output when
CCP2MX configuration bit is enabled. Internal software programmable
weak pul l-u p.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up. Serial programming clo ck.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note1: This buffer is a Schmitt Tr igger input when configured as the ex ternal interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other resets
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
LATB LATB Data Output Register
TRISB PORTB Data Direction Register 1111 1111 1111 1111
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 TMR0IP RBIP 1111 -1-1 1111 -1-1
INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF 11-0 0-00 11-0 0-00
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 83
8.3 PORTC, TRISC and LATC Registers
PORTC is an 8 bit wide bi-directional port. The corre-
sponding Data Direction Register is TRISC. Setting a
TRISC bit (=1) w ill mak e the correspondin g PORTC pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output, (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register reads and writes the latched output value for
PORTC.
POR TC is m ultiple x ed with se ver al periphera l function s
(Table 8-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TR IS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
mak e a pin an inp ut. The user shoul d ref er to the corre-
sponding peripheral section f or the correct TRIS bit set-
tings.
The pin override value is not loaded into the TRIS reg-
ister . This allows read-modify-write of the TRIS register ,
without concern due to peripheral overrides.
EXAMPLE 8-3: INITIALIZING PORTC
FIGURE 8-7: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
Data Bus
WR LATC or
WR TRISC
RD TRISC
QD
Q
CK
QD
CK
Peripheral Data Out
1
0
QD
Q
CK
RD PORTC
Peripheral Data In
WR PORT C
RD LATC
Q
Peripheral Out
Select
Peripheral Output Enable
RC7: RC0
ST Buffer
PIC18CXX2
DS39026B-page 84 Preliminary 7/99 Microchip Technology Inc.
TABLE 8-5: PORTC FUNCTIONS
TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/ Timer1 clock input
RC1/T1OSI/CCP2 bit1 ST Input/output port pin, Timer1 oscillator input, or Capture2 input/
Compare2 output/PWM output when CCP2MX configuration bit is
disabled.
RC 2/CCP1 bit2 ST I nput/output port pin or Capture 1 input/Compare1 output/PWM1
output
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output
RC6/TX/CK bit6 ST Input/outp ut port pin, Add ressab le USAR T Asynchro nous Transm it, or
Addressable USA RT Synchronous Clock
RC7/RX/DT bit7 ST Input/output port pin, Addressable USART Asynchronous Receive, or
Address able USA RT Synchronous Data
Legend: ST = Schmitt Trigger input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
V a lue on all
other resets
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
LAT C LATC Data Output Register xxxx xxxx uuuu uuuu
TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 85
8.4 PORTD, TRISD and LATD Registers
This section is applicable to only the PIC18C4X2
devices.
PORTD is an 8 bit wide bi-directional port. The corre-
sponding Data Direction Register is TRISD. Setting a
TRISD bit (=1) w ill mak e the correspondin g PORTD pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISD bit (=0) will
make the corresponding PORTD pin an output, (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch Register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register reads and writes the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In th is mode, the in put bu ffe rs
are TTL. See Section 8.6 for additional inform ation on
the Parallel Slave Port (PSP).
EXAMPLE 8-4: INITIALIZING PORTD
FIGURE 8-8: PORTD BLOCK DIAGRAM
IN I/O PORT MODE
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method
; to clear output
; data latches
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Data
Bus
WR LATD
WR TRISD
RD PORTD
Data Latch
TRIS Latch
RD TRISD
Schmitt
Trigger
input
buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
RD LATD
or
PORTD
PIC18CXX2
DS39026B-page 86 Preliminary 7/99 Microchip Technology Inc.
TABLE 8-7: PORTD FUNCTIONS
TABLE 8-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit# Buffer Type Function
RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0
RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1
RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2
RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3
RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4
RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5
RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6
RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR Value on all
other resets
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
LATD LATD Data Output Register xxxx xxxx uuuu uuuu
TRISD PORTD Data Direction Register 1111 1111 1111 1111
TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by PORTD.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 87
8.5 PORTE, TRISE and LATE Registers
This section is only applicable to the PIC18C4X2
devices.
PORTE is an 3 bit wide bi-directional port. The corre-
sponding Data Direction Register is TRISE. Setting a
TRISE bit (= 1) will mak e the corres ponding POR TE pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISE bit (=0) will
make the corresponding PORTE pin an output, (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch Register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register reads and writes the latched output value for
PORTE.
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
Figure 8-1 shows the TRISE register, which also con-
trols the parallel slave por t operation. Capture2 input/
Compare2 output/PWM output when CCP2MX config-
uration bit is enabled.
PORTE pins are multiplexed with analog inputs. When
select ed as an analo g input, these pins will r ead as ’ 0’s .
TRISE control s the direction of th e RE pins, e v en when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
EXAMPLE 8-5: INITIALIZING PORTE
FIGURE 8-9: PORTE BLOCK DIAGRAM
IN I/O PORT MODE
Note: On a Power-on Reset, these pins are con-
figured as analog inputs.
CLRF PORTE ; Initialize PORTE by
; clearing output
; data latches
CLRF LATE ; Alternate method
; to clear output
; data latches
MOVLW 0x07 ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 0x03 ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
Data
Bus
WR LATE
WR TRISE
RD PORTE
Data Latch
TRIS Latch
RD TRISE
Schmitt
Trigger
input
buffer
QD
CK
QD
CK
EN
QD
EN
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
RD LATE
or
PORTE
To Analog Converter
PIC18CXX2
DS39026B-page 88 Preliminary 7/99 Microchip Technology Inc.
Register 8 -1: TRISE Register
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE TRISE2TRISE1TRISE0
bit 7 bit 0
bit 7 IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3 Unimplemented: Read as ’0’
bit 2 TRISE2: RE2 direction control bit
1 = Input
0 = Output
bit 1 TRISE1: RE1 direction control bit
1 = Input
0 = Output
bit 0 TRISE0: RE0 direction control bit
1 = Input
0 = Output
Legend:
R = Readable bit W = Writable bit
U = Unimplemented bit, read as ‘0’ - n = Value at POR reset
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 89
TABLE 8-9: PORTE FUNCTIONS
TABLE 8-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name Bit# Buffer Type Function
RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in parallel slave port mode
or analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in parallel slave port mode
or analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
V alue on all
other
resets
PORTE —RE2RE1RE0---- -000 ---- -000
LATE LATE Data Outpu t Register ---- -xxx ---- -uuu
TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 0000 -111
ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFG0 --0- -000 --0- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by PORTE.
PIC18CXX2
DS39026B-page 90 Preliminary 7/99 Microchip Technology Inc.
8.6 Parallel Slave Port
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC18C4X2).
PORTD operates as an 8-bit wide Parallel Slave Por t,
or microprocessor port when control bit PSPMODE
(TRIS E<4>) i s set. In slave mode it is asynch ronous ly
readab le and writab le by the e xternal world thro ugh RD
control input pin RE0/RD and WR control input pin
RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus . Th e e xte rnal microproc esso r can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables por t pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port con-
figuration bits PCFG2:PCFG0 (ADCON1<2:0>) must
be set, which will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines a re first de tected lo w . A read from t he PSP occu rs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>)
is set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O . In
this mode, the input buffers are TTL.
FIGURE 8-10: PORTD AND POR TE BLOCK
DIAGRAM
(PARALLEL SLAVE PORT)
FIGURE 8-11: PARALLEL SLAVE PORT WRITE WAVEFORMS
Data Bus
WR LATD RDx
QD
CK
EN
QD
EN
RD PORTD
Pin
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL
or
PORTD
RD LATD
Data Latch
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 91
FIGURE 8-12: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 8-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on all
other resets
PORTD Port data latch when written; port pins when read xxxx xxxx uuuu uuuu
LATD LATD Data Output Bits xxxx xxxx uuuu uuuu
TRISD PORTD Data Direction Bits 1111 1111 1111 1111
PORTE —RE2RE1RE0---- -000 ---- -000
LATE LATE Data Output Bits ---- -xxx ---- -uuu
TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 -111 0000 -111
INTCON GIE/
GIEH PEIE/
GIEL TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFG0 --0- -000 --0- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’.
Shaded cells are not used by the Parallel Slave Port.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
PIC18CXX2
DS39026B-page 92 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 93
9.0 T IMER0 MODULE
The Timer0 module has the following features:
Software selectable as an 8-bit or 16-bit timer/
counter
Readable and writable
Dedicated 8-bit software programmable prescaler
Clock source selectable to be external or internal
Interrupt on overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
Edge select for external clock
Figure 9-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 9-1 shows a
simpli fie d block di agram of the Timer 0 m od ule i n 16-bit
mode.
The T0C ON reg ister i s a re adab le and writ ab le reg ister
that controls all the aspects of Timer0, including the
prescale selection.
Register 9-1: T0CON: Timer0 Control Register
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cyc le clock (CLKOUT)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increm ent on high-to-low transition on T0C KI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler As signment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output
bit 2:0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026B-page 94 Preliminary 7/99 Microchip Technology Inc.
FIGURE 9-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
FIGURE 9-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
Note: Upon reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
RA4/T0CKI
T0SE
0
1
0
1
Pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
clocks TMR0
(2 Tcy delay)
Data Bus
8
PSA
T0PS2, T0PS1, T0PS0 Set Interrupt
Flag bit TMR0IF
on overflow
3
Note: Upon reset, Timer0 is enabled in 8-bit mode with cloc k input from T0CKI max. prescale.
T0CKI pin
T0SE
0
10
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0L
(2 Tcy delay)
Data Bus<7:0>
8
PSA
T0PS2, T0PS1, T0PS0
Set Interrupt
Flag bit TMR0IF
on overflow
3
TMR0
TMR0H
High Byte
88
8
Read TMR0L
Write TMR0L
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 95
9.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing the T0CS bit. In
timer mode, the Timer0 module will increment every
instruction cycl e (w ith out p res caler). If the TMR0 regis-
ter is written , the incr ement is in hibite d f or the follow ing
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit. In
counter mode, Timer0 will increment either on every
rising or falling e dge o f pin RA4/T0 CKI. The in creme nt-
ing edge is determined by the Timer0 Source Edge
Select bi t (T0SE). Clearing th e T0SE bit sel ects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When an e xternal clock inp ut is used f or Timer0 , it must
meet certain requirements. The requirements ensure
the e xternal cloc k can b e synchron ized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
9.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or writ-
able.
The PSA and T0PS2:T0PS0 bits determine the pres-
caler assignment and prescale ratio.
Clearing bit PSA will assign the pre scaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
When as signed to t he Ti mer0 mo dul e, all in str u cti on s
writing to the TMR0 register (e.g. CLRF TMR0,
MOVWF TMR0, BSF TMR0, x....etc.) will clear the
prescaler count.
9.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol, (i.e ., it can be change d “on-the -fly ” during pr ogr am
e x ecu tio n).
9.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister o v erflo ws from FFh to 00h in 8-bit mod e or FFFFh
to 0000 h in 16-bit mode. This ove rflow s ets the T MR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IE bit must be cleared in soft-
ware by the Timer0 module interrupt service routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut off during SLEEP.
9.4 16-Bit Mode Timer Reads and Writes
TMR0H is not the high byte of the timer/counter in 16-
bit mode, but is actually a buffered version of the high
byte of Timer0 (refer to Figure 9-1). The high byte of
the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TM R0L. This pro-
vides the ability to read all 16-bits of Timer0 without
having t o ver ify th at the r ead of th e high a nd low byte
were valid due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through th e TMR0H buff er reg ister . T imer0 high b yte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to
be updated at once.
TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on a ll
other resets
TMR0L Timer0 Module’s Low Byte Register xxxx xxxx uuuu uuuu
TMR0H Timer0 Module’s High Byte Register 0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111
TRISA PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by Timer0.
PIC18CXX2
DS39026B-page 96 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 97
10.0 TIMER1 MODULE
The Tim er1 module timer/count er has the f ollo wing f ea-
tures:
16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
Readable and writable (Both registers)
Internal or external clock select
Interrupt on overflow from FFFFh to 0000h
Reset from CCP module special event trigger
Figure 10-1 is a simplified block diagram of the Timer1
module.
Register 10-1 shows the Timer1 control register. This
register controls the operating mode of the Timer1
module as wel l as contai ns the Timer1 oscillator e nabl e
bit (T1OSCEN). Timer1 can be enabled/disabled by
setting/clearing control bit TMR1ON (T1CON<0>).
Register 10-1: T1CON: Timer1 Control Register
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register Read/Write of TImer1 in one 16-bit operation
0 = Enables register Read/Write of Timer1 in two 8-bit operations
bit 6 Unimplemented: Read as '0'
bit 5:4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 P rescale value
10 = 1:4 P rescale value
01 = 1:2 P rescale value
00 = 1:1 P rescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 Oscillator is enabled
0 = Timer1 Oscillator is shut off.
The oscillator inverter and feedback resistor are turned off to eliminate power drain
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026B-page 98 Preliminary 7/99 Microchip Technology Inc.
10.1 Timer1 Operation
Timer1 can operate in one of these modes:
•As a timer
As a synchronous counter
As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments ever y instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 a lso has an in ternal “reset input ”. This reset can
be generated by the CCP module (Section 13.0).
FIGURE 10-1: TIMER1 BLOCK DIAGRAM
FIGURE 10-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
TMR1H TMR1L
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 SLEEP input
FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
TMR1IF
Overflow TMR1 CLR
CCP Special Event Trigger
T1OSCEN
Enable
Oscillator(1)
T1OSC
Interrupt
Flag Bit
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This
eliminates power drain.
T1OSI
T1CKI/T1OSO
Timer 1 TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
SLEEP input
T1OSCEN
Enable
Oscillator(1)
TMR1IF
Overflow
Interrupt
Fosc/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
T13CKI/T1OSO
T1OSI
TMR1
flag bit
Note1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates
power drain.
high byte
Data bus<7:0>
8
TMR1H 8
8
8
Read TMR1L
Write TMR1L
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 99
10.2 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The osc illa-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 10-1 shows the capacitor
selection for the Timer1 o scilla tor.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillat or.
10.3 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR1IF (PI R1<0>).
This inte rrupt can be enab led/d isab led by setting/c lear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
10.4 Resetting Timer1 using a CCP Trigger
Output
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either timer or synchro-
niz ed counter m ode to tak e adv antage of th is f eature . If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the e v ent that a write to Timer1 coi ncides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of oper ation, the CCPR1H:CC PR1L regis -
ters pair effectively becomes the period register for
Timer1.
10.5 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 10-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high by te buffer. This provides
the user with the ability to accurately read all 16-bits of
Timer1 without having to determine whether a read of
the high byte followed by a read of the low byte is valid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through th e TMR1H buff er reg ister . T imer1 high b yte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This a llow s a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high b y te of Timer1 i s n ot d irect ly readab l e or w rit-
abl e in t his m ode . All rea ds and w rites m ust tak e pl ace
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The pres-
caler is only cleared on writes to TMR1L.
TABLE 10-1: CAPACITOR SELECTION FOR
THE ALTERNATE OSCILLATOR
Osc Type Freq C1 C2
LP 32 kHz TBD (1) TBD
(1)
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A ± 20
PPM
Note1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
4: Capacitor values are for design guidance
only.
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
PIC18CXX2
DS39026B-page 100 Preliminary 7/99 Microchip Technology Inc.
TABLE 10-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Value on
all other
resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as0’.
Shaded cells are not used by the Timer1 module.
Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 101
NOTES:
PIC18CXX2
DS39026B-page 102 Preliminary 7/99 Microchip Technology Inc.
11.0 TIMER2 MODULE
The Timer2 module timer has the following features:
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrup t on T MR2 match o f PR2
SSP module optional use of TMR2 output to gen-
erate clock shift
Timer2 has a control register shown in Register 11-1.
Timer2 can be s hut off by cleari ng co ntrol b it TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 11-1 is a simplified block diagra m of the Timer2
module. Figure 11-1 shows the Timer2 control register .
The prescaler and postscaler selection of Timer2 are
controlled by this register.
11.1 Timer2 Operation
Timer2 can be used as the PWM time-base for the
PWM mode o f t he CC P mo dul e . The TMR2 regis ter i s
readable and writable, and is cleared on any device
reset. The input cloc k (F OSC/4) has a prescale o ption of
1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 inte rrupt (latched in flag bi t TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
a write to the TMR2 register
a write to the T2CON register
any device reset (Power-on Reset, MCLR reset,
Watchdog Timer reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
Register 11-1: T2CON: Timer2 Control Register
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit
7bit 0
bit 7 Unimplemented: Read as '0'
bit 6:3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer 2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1:0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 103
11.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readab le and writable register . The PR2 register is ini-
tialized to FFh upon reset.
11.3 Output of TMR2
The outpu t of TMR2 (bef ore th e postscaler) i s fed t o the
Synchron ous Serial P ort module, w hich option ally uses
it to generate the shift clock.
FIGURE 11-1: TIMER2 BLOCK DIAGRAM
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Comparator
TMR2 Sets flag
TMR2
output (1)
Reset
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note1: TMR2 register output can be software selected by the SSP Module as a baud clock.
to
TOUTPS3:TOUTPS0
T2CKPS1:T2CKPS0
Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 B it 2 B it 1 Bit 0 Value on
POR, BOR
Value on
all other
resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TMR2 Timer2 modules register 0000 0000 0000 0000
T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer2 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
PIC18CXX2
DS39026B-page 104 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 105
12.0 TIMER3 MODULE
The Tim er3 module timer/count er has the f ollo wing f ea-
tures:
16-bit timer/counter
(Two 8-bit registers; TMR3H and TMR3L)
Readable and writable (both registers)
Internal or external clock select
Interrupt on overflow from FFFFh to 0000h
Reset from CCP module trigger
Figure 12-1 is a simplified block diagram of the Timer3
module.
Register 12-1 shows the Timer3 control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
Register 10-1 shows the Timer1 control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enab le bit (T1OSCEN), which c an be a clock source f or
Timer3.
Register 12-1: T3CON: Timer3 Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable
1 = Enables register Read/Write of Timer3 in one 16-bit operation
0 = Enables register Read/Write of Timer3 in two 8-bit operations
bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the clock source for compare/capture CCP modules
01 = Timer3 is the clock source for compare/capture of CCP2,
Timer1 is the clock source for compare/capture of CCP1
00 = Timer1 is the clock source for compare/capture CCP modules
bit 5:4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 P rescale value
10 = 1:4 P rescale value
01 = 1:2 P rescale value
00 = 1:1 Prescale value
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling
edge)
0 = Internal clock (Fosc/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026B-page 106 Preliminary 7/99 Microchip Technology Inc.
12.1 Timer3 Operation
Timer3 can operate in one of these modes:
•As a timer
As a synchronous counter
As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
When TMR3CS = 0, Timer3 increments ever y instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer3 a lso has an in ternal “reset input ”. This reset can
be generated by the CCP module (Section 12.0).
FIGURE 12-1: TIMER3 BLOCK DIAGRAM
FIGURE 12-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT MODE
TMR3H TMR3L
T1OSC T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
SLEEP input
T1OSCEN
Enable
Oscillator(1)
TMR3IF
Overflow
Interrupt
Fosc/4
Internal
Clock
TMR3ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
T1OSO/
T1OSI
flag bit
(3)
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T13CKI
Timer3
TMR3L
T1OSC T3SYNC
TMR3CS
T3CKPS1:T3CKPS0 SLEEP input
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR3ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
T1OSO/
T1OSI
TMR3
T13CKI
CLR
CCP Special Trigger
T3CCPx
To Timer1 Clock Input
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resist or are turned off. This eliminates power drain.
High Byte
Data bus<7:0>
8
TMR3H 8
8
8
Read TMR3L
Write TMR3L
Set TMR3IF flag bit
on ov erfl ow
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 107
12.2 Timer1 Oscillator
The Timer1 osc ill ato r may be used a s th e c lock source
fo r Timer3. The Timer1 oscillator is enabled by setting
the T1O SC EN (T1CO N<3 >) b it. The osci lla tor is a l o w
pow er oscillat or rated up to 200 KHz. See Section 10.0
for further details.
12.3 Timer3 Interrupt
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 Interrupt, if enabled, is generated on overflow
which is latched in interrupt fl ag bit TMR3IF ( PIR2<1>).
This inte rrupt can be enab led/d isab led b y setting/cle ar-
ing TMR3 interrupt enable bit TMR3IE (PIE2<1>).
12.4 Resetting Timer3 Using a CCP Trigger
Output
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Timer3 must be configured for either timer or synchro-
niz ed counter m ode to tak e adv antage of th is f eature . If
Timer3 is running in asynchronous counter mode, this
reset operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation, the CCPR1H:CCPR1L registers pair effec-
tively becomes the period register for Timer3.
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note: The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR1<0>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR2 BCLIF LVDIF TMR3IF CCP2IF 0000 0000 0000 0000
PIE2 BCLIE LVDIE TMR3IE CCP2IE 0000 0000 0000 0000
IPR2 BCLIP LVDIP TMR3IP CCP2IP 0000 0000 0000 0000
TMR3L Holding register for the Least Significant Byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu
TMR3H Holding register for the Most Significant Byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu
T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
T3CON T3CKPS2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer1 module.
PIC18CXX2
DS39026B-page 108 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 109
13.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/ slav e Dut y Cycle register. Tabl e 13-1 sho ws the
timer resources of the CCP module modes.
The opera tion of CCP1 is identical to that of CCP2, with
the exception of the special event trigger. Therefore,
operation of a CCP module in the following sections is
described with respect to CCP1.
Table 13-2 shows the interaction of the CCP modul es.
Register 13-1: CCP1CON Register/CCP2CON Register
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7:6 Unimplemented: Read as '0'
bit 5:4 DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
Capture Mode:
Unused
Compare Mode:
Unused
PWM Mode:
These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3:0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mo de, ever y 16th rising edge
1000 = Compare mode,
Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)
1001 = Compare mode,
Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)
1010 = Compare mode,
Generate software interrupt on compare match
(CCPIF bit is set, CCP pin is unaffected)
1011 = Compare mode,
Trigger special event (CCPIF bit is set)
11xx =PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026B-page 110 Preliminary 7/99 Microchip Technology Inc.
13.1 CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register co ntrols
the operation of CCP1. All are readable and writable.
13.2 CCP2 Module
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
TABLE 13-1: CCP MODE - TIMER RESOURCE
TABLE 13-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
CCPx Mode CCPy Mode Interaction
Capture C apture TMR1 or TMR3 time-base. Time base can be different for each CCP.
Capture Compare The compare co ul d be conf igu red f or the special event trigger, which cl ears ei the r TM R1
or TMR3 depending upon which time base is used.
Compare Compare The compare(s) could be configured for the special event trigger, which clears TMR1 or
TMR3 depending upon which time base is used.
PWM PWM The PWMs will have the same frequency and update rate
(TMR2 interrupt).
PWM Capture None
PWM Compare None
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 111
13.3 Captu re Mod e
In Capture mode, CCPR1H:CCPR1L captures the 16-
bit v alue of the TMR1 or T MR3 regis ters when an e v ent
occurs on pin RC2/CCP1. An event is defined as:
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be clea red in softw are. If anot her capture occu rs befo re
the value in register CCPR1 is read, the old captured
value will be lost.
13.3.1 CCP PIN CONFIGURATION
In Captu re m ode, the RC2/CCP1 p in s hou ld b e co nfi g-
ured as an input by setting the TRISC<2> bit.
13.3.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(either Tim er1 an d/o r Time r3) m us t be runnin g in tim er
mode or s yn chr oni z e d co un ter m ode. In asynchronou s
counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the T3CON register.
13.3.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
13.3.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 13-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 13-1: CHANGIN G BETWEEN
CAPTURE PRESCALERS
FIGURE 13-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If the RC2/CCP1 is configured as an out-
put, a write to th e port can cause a ca pture
conditi on.
CLRF CCP1CON, F ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF TMR3
Enable
Q’s CCP1CON<3:0>
CCP1 Pin
Prescaler
÷ 1, 4, 16
and
edge detect
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP2
CCPR2H CCPR2L
TMR1H TMR1L
Set flag bit CCP2IF
TMR3
Enable
Q’s CCP2CON<3:0>
CCP2 Pin
Prescaler
÷ 1, 4, 16
and
edge detect
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
PIC18CXX2
DS39026B-page 112 Preliminary 7/99 Microchip Technology Inc.
13.4 Compare Mode
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value or the TMR3 register pair value.
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin
is:
driven High
driven Low
toggle output (High to Low or Low to High)
remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit CCP1IF (CCP2IF) is set.
13.4.1 CCP PIN CONFIGURATION
The user mus t configure the CCPx pi n as an output by
clearing the appropriate TRISC bit.
13.4.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
13.4.3 SOFTWARE INTERRUPT MODE
When gen er ate s oftwa re inte rrupt is ch osen, the C CP1
pin is not aff ec ted. Onl y a CCP interrupt is gener ated (if
enabled).
13.4.4 SPECIAL EVENT TRIGGER
In this mod e, an in ternal hardw a re trigger is g ener ated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
eff ec tiv el y be a 16-b it prog ram mab le period register f or
Timer1.
The special trigger output of CCPx resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will s tart an A/D c onversion if the
A/D module is enabled.
FIGURE 13-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP1CON register will force
the RC2/ CCP1 compare output latch to the
default low level. This is not the data latch.
Note: The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Ev ent Trigger
Set flag bit CCP1IF
match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special Event Trigger will:
Reset Timer1or Timer3, but not set Timer1 or Timer3 interrupt flag bit,
and set bit GO/DONE (ADCON0<2>)
which starts an A/D conversion (CCP2 only)
TMR3H TMR3L
T3CCP2
CCPR2H CCPR2L
Comparator
1
0
T3CCP2
T3CCP1
QS
ROutput
Logic
Special Ev ent Trigger
Set flag bit CCP2IF
match
RC1/CCP2
TRISC<1> CCP2CON<3:0>
Mode Select
Output Enable
Pin
01
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 113
TABLE 13-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPI F (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 000 0 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 00 00 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 111 1 1111
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
TMR1H Hold i ng register for the Most Significant Byte of the 16 -bit TMR1regist er xxxx xxxx uuu u uuuu
T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuu u uuuu
CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuu u uuuu
CCP1CON DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 -- 00 0000
CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuu u uuuu
CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuu u uuuu
CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 -- 00 0000
PIR2 BCLIF LVDIF TMR3IF CCP2IF 0000 0000 0000 0000
PIE2 BCLIE LVDIE TMR3IE CCP2IE 0000 0000 0000 0000
IPR2 BCLIP LVDIP TMR3IP CCP2IP 0000 0000 0000 0000
TMR3L Holding register for the Least Significant Byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu
TMR3H Hold i ng register for the Most Significant Byte of the 16 -bit TMR3 register xxxx xxxx uuu u uuuu
T3CON T3CKPS2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’ .
Shaded cells are not used by Capture and Timer1.
Note 1: The PS PIF, PSP IE and PSPI P bits are reserved on the PIC18C2x2 devices. Always maintain these bits clear.
PIC18CXX2
DS39026B-page 114 Preliminary 7/99 Microchip Technology Inc.
13.5 PWM Mod e
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is m ultiplex ed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
F or a step by step pro cedure on ho w t o set up the CCP
module for PWM operation, see Section 13.5.3.
FIGURE 13-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 13-4) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period ( 1/pe riod ).
FIGURE 13-4: PWM OUTPUT
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty cycle registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 115
13.5.1 PWM PERIOD
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formul a:
PWM pe riod = (PR2) + 1] • 4 • TOSC
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR 2 is equal to PR2, th e follo wing three e v ents
occur on the next increment cycle:
TMR2 is cl eare d
The CCP1 pin is set (exception: if PWM duty
cycl e = 0%, the CCP1 pin will not be set)
The PWM dut y cycl e is latche d from CCPR1L i nto
CCPR1H
13.5.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM du t y cy c l e = (CCPR1L :CCP1CON<5:4>) •
TOSC • (TMR2 pre scale value)
CCPR1L and CC P1CON <5:4> c an be writ ten to at an y
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to d ouble buffer the PWM duty c yc le. This doub l e
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM reso lution ( bits) for a given PWM fr e-
quency:
Note: The Timer2 postscaler (see Section 10.0)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a ser vo update rate at a dif-
ferent frequency than the PWM output.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
FOSC
FPWM
---------------


log
2()log
----------------------------- bits=
PIC18CXX2
DS39026B-page 116 Preliminary 7/99 Microchip Technology Inc.
13.5.3 SET-UP FOR PWM OPERATION
The followi ng steps shou ld be taken w hen confi guri ng
the CCP module for PWM operation:
1. Set the PWM period b y writing to the PR 2 regi s-
ter.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC< 2> bit.
4. Set the TMR2 prescale value and ena ble Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 13-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
TABLE 13-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
PWM Frequency 2.44 kHz 9.76 kHz 19.53 kHz 39.06 kHz 78.12 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 5.5
Name Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all othe r
resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
TMR2 Timer2 modules register 0000 0000 0000 0000
PR2 Timer2 module’s period register 1111 1111 1111 1111
T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM reg ister1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Captu r e/Compare/PWM registe r1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM reg ister2 (LSB) xxxx xxxx uuuu uuuu
CCPR2H Captu r e/Compare/PWM registe r 2 (MSB) xxxx xxxx uuuu uuuu
CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, = unimplemented read as ’0’.
Shaded cells are not used by PWM and Timer2.
Note 1: The PS PIF, PSP IE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 117
14.0 MASTER SYNCHRONOUS
SERIAL POR T (MSSP)
MODULE
14.1 Master SSP (MSSP) Module Overview
The Master Synchronous Serial P ort (MSSP) module is
a serial interface useful for communicating with other
peripher al or mi crocontro ller devices. Th ese peri phera l
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two mode s:
Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I2C)
- Full Mast er Mode
- Slave mode (with general address call)
The I2C i nterf ace su pports the f ollo wing mod es in ha rd-
ware:
•Master mode
Multi-master mode
•Slave mode
PIC18CXX2
DS39026B-page 118 Preliminary 7/99 Microchip Technology Inc.
14.2 Control Registers
The MSSP module has three associated registers.
These include a status register and two control regis-
ters.
Register 14-1: SSPSTAT: MSSP Status Register
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data out put time
SPI Slave Mode
SMP must be cl eared when SPI is used in slave mode
In I2C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabl ed f or high speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select
CKP = 0
1 = Data tr ansmitt ed on rising edge of SC K
0 = Data tr ansmitted on f alling edge of SCK
CKP = 1
1 = Data tr ansmitted on f alling edge of SCK
0 = Data tr ansmitt ed on rising edge of SC K
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last b yte received or trans m itted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSS P module is disabled, SS PEN is cleared)
1 = Indicat es that a st op bit has been detected last (this bit is ’0’ on RESET)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSS P module is disabled, SSPEN is cleared)
1 = Indicat es that a st art bit has been detecte d l ast (this bit is ’0’ on RESET)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address
match to the ne xt start bit, stop bit , or not ACK bit.
In I2C slave mode:
1 = Read
0 = Write
In I2C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
OR-ing this bit with SEN, RSEN, PEN, RCEN, or A CKEN will ind icate if the MSSP is in IDLE mode.
bit 1 UA: Update Address (10-bit I2C mode only)
1 = Indicat e s that the us er needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Rec e i ve (SPI and I2C modes)
1 = Receive co mplete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimpl e m ente d bi t , re ad as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cl eared x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 119
Register 14-2: SSPCON1: MSSP Control Register1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
Master Mode:
1 = A write to the SSPBUF regist er was at tempted while the I2C conditions were not valid for a transmission
to be started
0 = No collision
Slave Mode:
1 = The SSPB UF r egister is written while it is st ill transmitting th e previous word mus t be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in slave mode. In slave mode the user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not
set since each new reception (and transmission) is init iated by writing to the SSPBUF register. (Must be
cleared in software)
0 = No overflow
In I2C mode:
1 = A byte is received while the SSPBUF register is still holding the pre vi ous byte. SSPOV is a "don’t care"
in transmit mode. (Must be cleared in software)
0 = No overflow
bit 5 SSPEN: Synchronou s Serial Port Enable bit
In both modes, when enabled , these pins m ust be properly con figured as input or output.
In SPI mode:
1 = Enab les serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode:
1 = Enab les the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state f or clock is a low le vel
In I2C slave mode:
SCK release control
1 = Enable cl ock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I2C master mode
Unused in this mode
bit 3 - 0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SC K pi n . SS pin control enabled.
0101 = SPI slave mode, clock = SC K pi n . SS pin control disabled. SS can be used as I/O pin
0110 = I2C sla ve mode, 7-bi t address
0111 = I2C sla ve mode, 10-bit address
1000 = I2C master mode, clock = FOSC / (4 * (SSPADD+1) )
1001 = Reser ved
1010 = Reser ved
1011 = I2C firmware controlled Master mode (Sla ve idle)
1100 = Reser ved
1101 = Reser ved
1110 = I2C sla ve mode, 7-bi t address with start and stop bit interrupt s enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cl eared x = Bit is unknown
PIC18CXX2
DS39026B-page 120 Preliminary 7/99 Microchip Technology Inc.
Register 14-3: SSPCON2: MSSP Control Register2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (In I2C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (In I2C master mo de onl y)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowle dge was received from slave
bit 5 ACKDT: Acknowledge Data bit (In I2C master mode only)
In master re ceive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (In I2C master mode only)
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (In I2C master mo de onl y)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (In I2C master mode only)
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
bit 1 RSEN: Repeated Start Condition Enabled bit (In I2C master mode onl y)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
bit 0 SEN: Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle
Note: F or bits A CKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in th e idle mode ,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
R = Reada ble bit W = Wri table bi t U = Unimplemented bit, read as ‘0’
- n = Value at POR reset 1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 121
14.2.1 SPI Mode
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish com-
munication, typically three pins are used:
Serial Data Out (SDO) - RC5/SDO
Serial Data In (SDI) - RC4/SDI/SDA
Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
Additionally a four th pin may be used when in a slave
mode of operation:
•Slave Select (SS
) - RA5/SS/AN4
14.2.1.1 OPERATION
When initializing the SPI, several options need to be
specif ied. This is don e by prog ramming the ap propriate
control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.
These control bits allow the following to be specified:
Master Mode (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data input sample phase (middle or end of data
output time)
Clock edge (output data on rising/falling edge of
SCK)
Clock Rate (Master mode only)
Slave Select Mode (Slave mode only)
Figure 14-1 shows the block diagram of the MSSP
module, when in SPI mode.
FIGURE 14-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The MSSP consis ts of a transmit/re ceive Shift Register
(SSPSR) and a buffer regis ter (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF hold s the data that w as written to the SSPSR,
until the received data is ready. Once the 8 bits of data
hav e bee n receiv ed, that b yte is mov ed to the SSPB UF
register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double buffering of the received data (SSP-
BUF) allows the next byte to start reception before
reading th e data that w as just receiv ed. An y write to the
SSPBUF re gister during transmis sion/reception o f data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the W COL bi t s o that it c an be determined if the follow -
ing write(s) to the SSPBUF register completed suc-
cessfully.
Read Write
Internal
data bus
SSPSR reg
SSPBU F reg
SSPM3:SSPM0
bit0 shift
clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
SDI
SDO
SS
SCK
( )
PIC18CXX2
DS39026B-page 122 Preliminary 7/99 Microchip Technology Inc.
When the application software is expecting to receive
v alid da ta, the SS PBUF s hould be read bef ore the ne x t
by te of dat a to tra nsf e r is written to t he SSPB UF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
determine when the transmission/reception has
completed. The SSPBUF must be read and/or written.
If the interrupt method is not going to be used, then
software polling can be done to ensure that a write
collision does not occur. Example 14-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
EXAMPLE 14-1: LOADING THE SSPBUF (SSP SR) REGISTER
The SSPSR is not directly readable or writable, and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP status register (SSPSTAT) indi-
cates the various status conditions.
14.2.1.2 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the SSP-
CON registers, and then set the SSPEN bit. This con-
figures the SDI, SDO, SCK, and SS pins as serial port
pins. Fo r the pins to behave as the serial port function,
some must have their data direction bits (in the TRIS
register) appropriately programmed. That is:
SDI is au tom ati ca lly co ntro lle d by the SPI module
SDO must have TRISC<5> bit cleared
SCK (Master mode) must have TRISC<3> bit
cleared
SCK (Slave mode) must have TRISC<3> bit set
•SS
must have TRISC<4> bit set
Any s erial port function that is not desired ma y be ov er-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
14.2.1.3 TYPICAL CONNECTION
Figure 14-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite edge
of the cloc k. Both processors shoul d be progr ammed to
same Clo ck Polarity (CKP), the n both contro llers w ould
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data tr ans m iss io n:
Master sends data Slave sends dummy data
Master sends data Slave sends data
Master sends dummy data Slave sends data
LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
GOTO LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 123
FIGURE 14-2: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM3: SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slav e SSPM3:SSPM0 = 010xb
Serial Clock
PIC18CXX2
DS39026B-page 124 Preliminary 7/99 Microchip Technology Inc.
14.2.1.4 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 14-2) is to broad-
cast data by the software protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO ou tput could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the prog r amme d cloc k r ate . As each b y te is rec eiv ed , it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
The cloc k polarity is selected b y appropriately progr am-
ming the CKP bit (SSPCON1<4>). Thi s then would give
waveforms for SPI communication as shown in
Figure 14-3, Figure 14-5, and Figure 14-6 where the
MSB is tr ans m itte d fi rst. In m aster m ode, the SPI cloc k
rate (bi t rat e) is user pro gramm abl e to be on e of the f ol-
lowing:
•F
OSC/4 (or TCY)
•F
OSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum data rate (at 40 MHz) of 10.00
Mbps.
Figure 14-3 Shows the waveforms for master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. Th e
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 14-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 clock
modes
Input
Sample
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Wr it e to
SSPBUF
SSPSR to
SSPBUF
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(CKE = 0)
(CKE = 1)
Next Q4 cycle
after Q2
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 125
14.2.1.5 SLAVE MODE
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in slave mode the external clock is supplied by
the e x ternal cloc k sour ce o n the SCK pin. This e xt ernal
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in sleep mode, the slave can transmit/receive
data. When a byte is receive the device will wake-up
from sleep.
14.2.1.6 SLAVE SELECT SYNCHRONIZATION
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode with SS pin control
enabled (SSPCON1<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The Data Latch must be high. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. External pull-up/ pull-down resistors may be
desira ble, depending on the application.
When the SPI module resets, the bit counter is forced
to 0. Thi s can be done b y either b y f orcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiv er the SDO pin can be conf igured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 14-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slav e Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is
set to VDD.
Note 2: If the SPI is used in Slave Mo de wit h C KE
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7
SDO bit7 bit6 bit7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit0
bit7 bit0
Next Q4 cycle
after Q2
PIC18CXX2
DS39026B-page 126 Preliminary 7/99 Microchip Technology Inc.
FIGURE 14-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 14-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
optional
Next Q4 cycle
after Q2
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
not optional
Next Q4 cycle
after Q2
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 127
14.2.1.7 SLEEP OPERATION
In master mode all module clocks are halted, and the
tra nsmiss ion/rec eption will re main i n that sta te unti l the
device wakes from sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In slave mode, the SPI transmit/receive shift register
oper at es as y nch ron ous ly to the device . This all o w s the
device to be placed in sleep mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits ha ve been received, the MSSP interrupt
flag bit will be set and if enabled will wake the device
from sleep.
14.2.1.8 EFFECTS OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
14.2.1.9 BUS MODE COMPATIBILITY
Table 14-1 shows the compatibility between the stan-
dard SPI modes and the states the the CKP and CKE
control bits.
TABLE 14-1: SPI BUS MODES
There is also a SMP bit w hich control s when th e data i s
sampled.
Standard SPI Mode
Terminology Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
PIC18CXX2
DS39026B-page 128 Preliminary 7/99 Microchip Technology Inc.
TABLE 14-2: REGISTERS ASSOCIATED WITH SPI OPERATION
14.3 MSSP I2C Operation
The MSSP module in I2C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pin s are used f or data trans fer . T hese are the RC 3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The MSSP module functions are enabled by setting
MSSP Enable bit SSPEN (SSPCON<5>).
FIGURE 14-7: MSSP BLOCK DIAGRAM
(I2C MODE)
The MSSP module has six registers for I2C operation.
These are the:
MSSP Control Register1 (SSPCON1)
MSSP Control Register2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) - Not directly
accessible
MSSP Address Register (SSPADD)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA PORTA Data Direction Register --11 1111 --11 1111
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = uni m plem ented read as '0'.
Shaded cells are not used by the MSSP in SPI mode.
Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
Read Write
SSPSR reg
Match detect
SSPADD reg
Start and
Stop bit detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
Shift
Clock
MSb
SDI/ LSb
SDA
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 129
The SSPCON1 register allows control of the I2C oper-
ation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
•I
2C Master mode, clock = OSC/4 (SSPADD +1)
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit address), with start and
stop bit interrupts enabled
•I
2C Slave mode (10-bit address), with start and
stop bit interrupts enabled
•I
2C Firmware controlled master operation, slave
is id le
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
14.3.1 SLAVE MODE
In slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-trans mi tter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse and
load the SSPBUF register with the received value cur-
rently in the SSPSR register.
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before t he transfer was r eceived.
b) The ov erflo w bit SSPO V (SSPCON<6>) w as set
before t he transfer was r eceived.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit i s cleared by r eading th e SSPBUF re gister , while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP modul e , is sho w n in ti mi ng pa ra meter #100 and
parameter #101.
14.3.1.1 ADDRESSING
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, th e 8-bits are shifted in to the SSPSR register . All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit BF is set.
c) An ACK pulse is generated.
d) MSSP interrupt flag bit SSPIF (PIR1<3>) is set
(interr upt is generated if enabled) on the falling
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte sp ecify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for 10-bit
address is as follows with steps 7- 9 for slave-transmit-
ter:
1. Receive first (high) byte of Address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD regis ter with the fir st (hig h)
byte of Address. If match releases SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
PIC18CXX2
DS39026B-page 130 Preliminary 7/99 Microchip Technology Inc.
14.3.1.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is clea red. The re ce ive d ad dress is lo aded in to
the SSPBUF register.
When the address byte overflow condition exists, then
no ac knowled ge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
by te. Fla g bit SSPIF ( PIR1<3>) m ust be clea red in soft-
ware. The SSPSTAT register is used to deter mine the
status of the byte.
14.3.1.3 TRANSMISSION
When the R/W bit of t he incomi ng addr ess byte is se t
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the n inth bit and pin RC3/SC K/SCL is held
low. The transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
sla v e de vi ces m a y b e h olding off the m aster b y st retch-
ing the clock. The eight data bits are shifted out on the
f alling edge of the SCL input. This ensure s that the SDA
signal is valid during the SCL high time (Figure 14-9).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the ma s-
ter-receiver is latched on the r ising edge of the nint h
SCL input pulse. If the SDA line is high (not ACK),
then the da ta transfer is comple te. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave monitors for
another occurren ce of the START bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register, which also loads the SSPSR
register. Pin RC3/SCK/SCL should be enabled by
setting bit C KP.
FIGURE 14-8: I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 14-9: I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
P
9
8
765
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 1234567891234567891234
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Ad dr ess
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Not ACK
ACK is not sent.
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON1<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 Not ACKTransmitting DataR/W = 1Receiving Address
123456789 123456789 P
Cleared in software
SSPBUF is written in software From SSP interrupt
service routine
Set bit after writing to SSPBUF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written-to
before the CKP bit can be set)
R/W = 0
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 131
FIGURE 14-10 : I2C SLAVE MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
11110A9A8 A7 A6A5A4A3A2A1A0 11110 A8
R/W=1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Master sends NACK
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated.
UA (SSPSTAT<1 >)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Transmit is complete
CKP has to be set for clock to be released
Bus Master
terminates
transfer
PIC18CXX2
DS39026B-page 132 Preliminary 7/99 Microchip Technology Inc.
FIGURE 14-11 : I2C SLAVE MODE WAVEFORM (RECEPTION 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456 789 1 23456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus Master
terminates
transfer
D2
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
R/W = 1
Cleared in software
Dummy read of SSPBUF
to clear BF flag Read of SSPBUF
clears BF flag
Cleared by hardware when
SSPADD is updated with
low byte of address. high byte of address.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 133
14.3.2 GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master . The e xception is the gener al call address which
can ad dres s al l devices. Whe n t his a ddress is used, al l
devices should, in theory, respond with an acknowl-
edge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Ca ll En able bit (GCEN) is enabled (SSPCON2<7>
set). Following a start-bit detect, 8-bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eight
bit), and on the fa lling edge of th e ninth bit (A CK bit), the
SSPIF interrupt flag bit is set.
When the i nte rrupt is serviced, the so urc e for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
f or the se cond half of the addres s to match, a nd the U A
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
acknowledge (Figure 14-12).
FIGURE 14-12: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS
MODE)
SDA
SCL S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared in software
SSPBUF is read
R/W = 0ACK
General Call Address
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
’0’
’1’
PIC18CXX2
DS39026B-page 134 Preliminary 7/99 Microchip Technology Inc.
14.3.3 MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abl ed . C ont rol of the I2C bus may be taken when the P
bit is set or the bus is idle with both the S and P bits
clear.
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
START condition
STOP condition
Data transfer byte transmitted/received
Ac k nowledge Transmit
Repea ted Start
14.3.4 I2C MASTER MODE SUPPOR T
Master Mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once master mode is enab led, the user has
six opt ions.
1. Assert a start condition on SDA and SCL.
2. Assert a Repeated Star t condition on SDA and
SCL.
3. Write to the SSPB UF register initi ating transmis -
sion of data/address.
4. Generate a stop Condition on SDA and SCL.
5. Configure the I2C port to receive data.
6. Generate an acknowledge condition at the end
of a received byte of data.
FIGURE 14-13: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Note: The MSSP Modul e, when configu red in I2C
Master Mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a start condition and
immediately write the SSPBUF register to
imitate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit wil l be set, indi catin g that a write
to the SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
Start bit detect
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
Receive Enable
clo ck cntl
clock arbitrate/WCOL detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 135
14.3.4.1 I2C MASTER MODE OPERATION
The master device generates all of the serial clock
pulses an d t he START and STOP condition s . A tran s-
fer is ended with a STOP condition or with a repeated
START conditio n. Since the repeated STA RT condition
is also the beginning of the next serial transfer, the I2C
bus will not be rele ased.
In Master transmitter mode serial data is output through
SDA, while SCL outputs the serial clock. The first byte
transmitted contains the slave address of the receiving
device (7 bits) and the Read/Write (R/W) bit. In this
case, the R/W bit w ill be l ogic ’0’. Ser ial data is trans -
mitted 8 bits at a ti me. After e ach byte is transm itted, an
acknowledge bit is received. START and STOP condi-
tion s are out put to indi cate th e beginn ing and t he end
of a serial transfer.
In Master receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R /W bit. In t his cas e, the R/W bit wil l be
logic ’1’. Thus, t h e fi rs t byte t ransm i tt e d is a 7- b it s lave
addr ess followed by a ’1’ to ind icate recei ve bit. S eri al
data is received via SDA, while SCL outputs the serial
cloc k. Serial data is receiv ed 8 bi ts at a time . After eac h
byte is received, an acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmissio n.
The baud rate ge ner ator used for the SPI mode opera-
tion is now used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. The
baud rate generator reload value is contained in the
low er 7 bits of the SSPADD register . The baud rat e gen-
erator will automatically begin counting on a write to the
SSPBUF. Once the given operation is complete, (i.e.
tra nsmission of t he last data b it is f ollowe d by A CK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
A typical transmit sequence would go as follows:
a) The user generates a Start Condition by setting
the START enable bit SEN (SSPCON2<0>).
b) SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
c) The user load s the SSPB UF with th e address to
transmit.
d) Addres s is s hif ted ou t th e SDA pin u nti l all 8 bit s
are transmitted.
e) The MSSP Modu le shifts in the A CK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) The MSSP modul e gen erate s an interrupt a t the
end of the n inth cloc k cycl e by set ting the SSPIF
bit.
g) The user loads the SSPBUF with eight bits of
data.
h) D ATA is shifted out the SD A pin until all 8 bits are
transmitted.
i) The MSSP Module sh ifts in the A CK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
j) The MSSP modul e gener ates an int errupt at th e
end of the n inth cloc k cycl e by set ting the SSPIF
bit.
k) The user gener ates a ST OP condit ion by setting
the STOP enable bit PEN (SSPCON2<2>).
l) Inter rupt is generated once the stop condition is
complete.
PIC18CXX2
DS39026B-page 136 Preliminary 7/99 Microchip Technology Inc.
14.3.5 BAUD RATE GENERATOR
In I2C master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 14-14). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
remented twice per instruction cycle (TCY) on the Q2
and Q4 clocks. In I2C master mode, the BRG is
reloaded automatically. If Clock Arbitration is taking
place for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 14-15).
FIGURE 14-14: BAUD RATE GENERATOR BLOCK DIAGRAM
FIGURE 14-15: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SSPM3:SSPM0
BRG Down Counter
CLKOUT Fosc/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control Reload
SDA
SCL
SCL de-asserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count.
03h 02h 01h 00h (hold off) 03h 02h
reload
BRG
value
SCL low (clock arbitration) SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 137
14.3.6 I2C MASTER MODE START CONDITION
TIMING
To initiate a START condition, the user sets the start
condition enable bit SEN (SSPCON2<0>). If the SDA
and SCL p ins are sam ple d hi gh, the baud r ate genera-
tor is re-l oaded with th e content s of SSPADD<6:0> an d
starts its count. If SCL and SDA are both sample d high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
dri ven low, wh ile SCL i s high, i s the STA RT c onditi on,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended
lea vi ng the SDA line h eld low and the STAR T co nd itio n
is complete.
14.3.6.1 WCOL STATUS FLAG
If the user writes the SSPBUF when an START
sequenc e is i n p r og re ss, the WCOL is s et an d the co n-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 14-16: FIRST START BIT TIMING
Note: If at the beginning of the START condition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition
the SCL line is sampled lo w before the SD A
line is driven lo w , a b us coll ision occu rs, the
Bus Collision Interrupt Flag BCLIF is set,
the START condition is aborted, and the
I2C module is reset into its IDLE state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
conditi on is complete.
SDA
SCL
S
TBRG
1st Bit 2nd Bit
TBRG
SDA = 1, At completion of start bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
Hardware clears SEN bit
TBRG
Write to SEN bit occurs here. Set S bit (SSPSTAT<3>)
and sets SSPIF bit
PIC18CXX2
DS39026B-page 138 Preliminary 7/99 Microchip Technology Inc.
14.3.7 I2C MASTER MODE REPEATED START
CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the idle state. When the RSEN bit is set,
the SCL pi n is asserted low. When the SCL pin is sam -
pled low, the baud rate generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
genera tor count (TBRG). Whe n the baud r ate ge nera tor
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled
high, the ba ud rate generator is re-loaded with the con-
tents of SSPADD<6:0> and begins counting. SDA and
SCL must be sampled high f or one TBRG. Th is acti on i s
then followed by asse rtion of t he SDA pin (SD A = 0) for
one TBRG, while SCL is high. Following this, the RSEN
bit (SSPCON2<1>) will be automatically cleared and
the baud rate generator will not be reloaded, leaving
the SDA pin held low. As soon as a start condition is
detected on the SDA and SCL pins, the S bit (SSP-
STAT<3>) will be set. The SSPIF bi t will not be se t until
the baud rate generator has timed-out.
Immediately following the SSPIF bit getting set, the
user may wr ite the SSPBUF wi th the 7- bit ad dress in
7-bit mode, or the def ault first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
14.3.7.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a Repeated Star t
sequenc e is i n p r og re ss, the WCOL is s et an d the co n-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 14-17: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
Note 2: A bus collision during the Repeated Start
condition occurs if:
SDA is sampled low when SCL goes
from low to high.
SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
Write to SSPBUF occurs here.
Falling edge of ninth clock
End of Xmit
At completion of start bit,
hardwar e cle ar RSEN bit
1st Bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SD A = 1,
SCL(no chan ge ) SCL = 1
occurs here.
TBRG TBRG TBRG
and set SSPIF
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 139
14.3.8 I2C MASTER MODE TRANSMISSION
Transmission of a data b yte, a 7-bit address or the other
half of a 10-bit address is accomplished by simply writ-
ing a v a lue to the SSPBUF register. This action will set
the buffer full flag bit, BF, and allow the baud rate gen-
erator to begin counting and start the next transmis-
sion. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter 106). SCL
is held low for one baud rate generator roll over count
(TBRG). Data should be valid before SCL is released
high (see Data setup time specification parameter
107). W hen the SCL p in i s rel eas ed high , it i s he ld th at
way for TBRG. The data on the SDA pin must remain
stable for that duration and some hold time after the
next falling edge of SCL. Af ter th e eighth bit is s hifted
out (the falling edge of the eighth clock), the BF flag is
cleared and the master releases SDA. allowing the
slave device being addressed to respond with an ACK
bit during the ni nth bit tim e, i f an addres s match oc curs
or if data was received properly. The status of ACK is
written into the ACKDT bit on the falling edge of the
ninth clock. If the master receives an acknowledge, the
ac knowledge status bit, A CKSTAT, is clear ed. If not, the
bit is set. After the ninth clock, the SSPIF bit is set and
the master clock (baud rate generator) is suspended
until the ne xt data byte is loaded into the SSPBUF, leav-
ing SCL low and SDA unchanged (Figure 14-18).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and t he R/W bit are complet ed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin allowing the slave to respond with an
ac know ledge . On the fa lling ed ge of the ninth cl ock , the
master will sample the SDA pin to see if the address
wa s recog niz ed b y a sl ave. The st atus of th e A CK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another writ e to th e SS PBU F takes place , ho ldi ng SCL
low and allowing SDA to float.
14.3.8.1 BF STATUS FLAG
In tran smit mode, the BF bit (SSPSTAT<0>) is se t when
the CPU writes to SSPBUF and is cleared when all 8
bits are shifted out.
14.3.8.2 WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress, (i.e. SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
14.3.8.3 ACKSTAT STATUS FLAG
In transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge
(ACK = 0), and is set when the s lave does not acknowl-
edge (ACK = 1). A slave sends an acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
14.3.9 I2C MASTER MODE RECEPTION
Master m ode re ce ption is e na b l ed by programming the
receive enable bit, RCEN (SSPCON2<3>).
The baud rate generat or be gin s c oun tin g, an d on eac h
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF fla g bit is set and t he ba ud r ate gene r a-
tor is suspended from counting, holding SCL low. The
MSSP is now in IDLE state, awaiting the next com-
mand. When the buffer is read by the CPU, the BF flag
bit is aut om atic al ly c lea red. The u se r c an the n s en d a n
acknowledge bit at the end of reception, by setting the
acknowledge sequence enable bit ACKEN
(SSPCON2<4>).
14.3.9.1 BF STATUS FLAG
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
14.3.9.2 SSPOV STATUS FLAG
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
14.3.9.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e . SSPSR is still sh ifting in a da ta
byte), the the WCOL bit is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Note: The MSSP Module must be in an IDLE
STATE before the RCEN bit is set, or the
RCEN bit will be disregarded.
PIC18CXX2
DS39026B-page 140 Preliminary 7/99 Microchip Technology Inc.
FIGURE 14-18 : I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7D6D5D4D3D2D1D0
ACK
Transmitting Data or Second Half
R/W = 0Transmi t Addr ess to Slave
123456789 123456789 P
cleared in software service routine
SSPBUF is written in software
From SSP inter rupt
After start condition SEN cleared by hardware.
S
SSPBUF written with 7 bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Addr ess
Write SSPCON2<0> SEN = 1
START condition be gins From slave clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
cleared in software
SSPBUF written
PEN
Cleared in software
R/W
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 141
FIGURE 14-19 : I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus Master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1)
Write to SSPBUF occurs here ACK from Slave
Master configured as a receiver
by programming SSPCON2<3>, (RCEN = 1) PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
Start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Cleared in software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SSPIF at end
Set SSPIF interrupt
at end of acknowledge
sequence
Set SSPIF interrupt
at end of acknow-
ledge sequence
of receive
Set ACKEN start acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = ACKDT = 1
RCEN cleared
automatically
RCEN = 1 start
next receive
Write to SSPCON2<4>
to start acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
Begin Start Condition
Cleared in software
SDA = ACK DT = 0
PIC18CXX2
DS39026B-page 142 Preliminary 7/99 Microchip Technology Inc.
14.3.10 ACKNOWLEDGE SEQUENCE TIMING
An acknowledge sequence is enabled by setting the
acknowledge sequence enable bit ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the ac knowled ge data bit
is prese nte d on the SDA pin. If the u se r w ish es to gen-
erate an acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
(TBRG) and the SCL pin is de-asserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the baud rate generator counts for T BRG. The SCL pin
is then pulled lo w . Following this , the ACKEN bi t is auto-
matically cleared, the baud rate generator is turned off
and the MSSP module then goes into IDLE mode
(Figure 14-20).
14.3.10.1 WCOL STATUS FLAG
If the user writes the SSPBUF when an acknowledge
sequence is in progress, then WCOL is set and the
content s of th e b uff er are unchan ged (the w rite doesn ’t
occur).
14.3.11 STOP CONDITION TIMING
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop sequence enable
bit, PEN (SSPCON2<2 >). At the end of a receive /trans-
mit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SD A line lo w. When the SDA line is sample d
low, the baud rate generator is reloaded and counts
dow n to 0. When the baud rate gene rator times out, the
SCL pin will be brought high, and one TBRG (baud rate
generator rollover count) later, the SDA pin will be de-
asserted. When the SD A pin is sampled high while SCL
is high, the P bit (SSPSTAT<4>) is set. A TBRG later , the
PEN bit is cleared and the SSPIF bit is set (Figure 14-
21).
14.3.11.1 WCOL STATUS FLAG
If the use r writes the SSPBUF when a ST OP sequenc e
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 14-20: AC KNOWLEDGE SEQUENCE WAVEFORM
Note: TBRG= one baud rate generator period.
SDA
SCL
Set SSPIF at the end
Ackno wledge sequence starts here,
Write to SS PCO N 2 A CKEN automatically cleared
Cleared in
TBRG TBRG
of receive
ACK
8
ACK EN = 1 , ACKDT = 0
D0
9
SSPIF
software Set SSPIF at the end
of acknowledge sequence
Cleared in
software
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 143
FIGURE 14-21: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2
Set PEN
Falling edge of
SCL = 1 for Tbrg, followed by SDA = 1 for Tbrg
9th clock
SCL brought high after TBRG
Note: TBRG = one baud rate generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set
TBRG
to setup stop condition.
ACK
P
TBRG
PEN bit (SSPCON2<2>) is clea red by
hard ware and the SSPIF bit is set
PIC18CXX2
DS39026B-page 144 Preliminary 7/99 Microchip Technology Inc.
14.3.12 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or repeated start/stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the baud rate gen-
era tor (BRG) is susp ended from co unting u ntil th e SCL
pin is ac tually sam pled high. When the SCL pin is sam -
pled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time will always be at least
one BRG rollover count in the event that the clock is
held low by an external device (Figure 14-22).
14.3.13 SLEEP OPERATION
While in sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, w ake the processor from
sleep (if the MSSP interrupt is enabled).
14.3.14 EFFECT OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
FIGURE 14-22: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
SCL
SDA
BRG over f l ow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count B R G overfl ow occur s,
Release SCL, Slave device holds SCL low. SCL = 1 BRG star ts counting
clock high interval.
SCL line sampled once every machine cycle (TOSC² 4).
Hold off BRG until SCL is sampled high.
TBRG TBRG TBRG
to measure high time interval
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 145
14.3.15 MULTI-MASTER MODE
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the MSSP module is disabled. Control of the I2C
bus ma y b e tak en when the P bit (SSPSTAT<4>) is set,
or the b us is idle with bot h the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored, for arbitration, to see if the signal level is the
expec ted ou tpu t le vel. This chec k is pe rformed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
14.3.16 MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another master as s erts a '0'. Wh en the SCL pin fl oat s
high, data should be stable. If the expected data on
SD A is a '1' and the da ta samp led on the SDA pin = '0',
then a bus c ollision has tak en place . The master will set
the Bus Collision Interrupt Flag BCLIF and rese t the I2C
port to its IDLE state. (Figure 14-23).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When th e user s ervices
the b us co lli sion i nterrupt service rou tine , an d if the I2C
bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated Start, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines a re d e-asserted, and t he resp ective control bit s in
the SSPCON2 registe r are cleared. When the user s er-
vices the bus collision interrupt service routine, and if
the I2C b us is free, the user can resume commun ication
by asserting a START condition.
The Master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be
set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In multi-master mode, the interrupt generation on the
detection of star t and stop conditions allows the deter-
minatio n of when the bus is free. Co ntrol of the I2C bus
can be tak en whe n the P bit is set in the SSPSTAT reg-
ister , or the b us is idle a nd the S and P bits are cleared.
FIGURE 14-23: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source Sample SDA. While SCL is high
data doesn’t match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLIF).
by the master.
by master
Data changes
while SCL = 0
PIC18CXX2
DS39026B-page 146 Preliminary 7/99 Microchip Technology Inc.
14.3.16.1 BUS COLLISION DUR ING A START
CONDITION
During a START condition, a bus collision occurs if:
a) SD A or SCL are sa mpled low at th e beginning of
the START condition (Figure 14-24).
b) S CL is sampled low before SDA is asserted low
(Figure 14-25).
During a START condition, both the SDA and the SCL
pins are monitored.
If: the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is abor ted,
and the BCLIF flag is set,
and the MSSP module is reset to its IDLE state
(Figure 14-24).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ’1’ during the START condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 14-26). If however a ’1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts dow n to 0, and during this time, if the SCL pins
is sampled as ’0’, a bus collision does not occur. At the
end of the BRG c oun t, th e SC L p in i s ass erted low.
FIGURE 14-24: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The rea son that bus co llision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition doe s not ca us e a b u s
collis ion, becaus e the tw o masters m ust be
allo wed to arbitrat e the first a ddress f oll ow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or STOP conditions.
SDA
SCL
SEN
SDA sampled low befor e
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable star t
condition if SDA = 1, SCL=1
SDA = 0, SCL = 1
BCLIF
S
SSPIF
SDA = 0, SC L = 1 SSPIF and BCLIF are
cleared in software.
SSPIF and BCLIF are
cleared in software.
. Set BCL I F,
Set BCLIF.
START condition.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 147
FIGURE 14-25: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 14-26: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN Bus collision occurs, Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Inte rru p t cl e a r e d
in software.
Bus collision occurs, Set BCLIF.
SCL = 0 before BRG time out,
’0’ ’0
’0’’0’
SDA
SCL
SEN
Set S
Set SEN, enab le start
sequence if SDA = 1, SCL = 1
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
in software.
Set SS PIF
SDA = 0, SCL = 1
SDA pulled low b y other master.
Reset BRG and assert SDA
SCL pulled low after BRG
Timeout
Set SS PIF
’0’
PIC18CXX2
DS39026B-page 148 Preliminary 7/99 Microchip Technology Inc.
14.3.16.2 BUS COLLISION DURING A REPEATED
START CONDITION
During a Repeated Start condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asser ted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and cou nts down to 0. The SCL pin is then de-a sserted,
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e. another
master, Figure 14-27, is attempting to transmit a data
’0’). If SDA is sampled high, the BRG is reloaded and
begins counting. If SDA goes from high to low before
the BRG ti mes ou t, no b us col lisio n occu rs becau se no
two m asters c an assert SD A at e xactl y the sam e time .
If SCL goes from high to low before the BRG times out
and SD A ha s not alrea dy been as serted, a b us collis ion
occurs. In this case, another master is attempting to
tran smit a data ’1 ’ during the Repe ated Start conditio n,
Figure 14-28.
If at the end of the BRG time out both SCL and SD A are
still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is com-
plete.
FIGURE 14-27: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 14-28: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
Cleared in software
'0'
'0'
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
TBRG TBRG
’0’
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 149
14.3.16.3 BUS COLLISION DURING A STOP
CONDITION
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ’0’ (Figure 14-29). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs . This is another case of another master attempt-
ing to drive a data ’0’ (Figure 14-30).
FIGURE 14-29: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 14-30: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
Set BCLIF
’0
’0
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SD A goes high
Set BCLIF
’0’
’0’
PIC18CXX2
DS39026B-page 150 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 151
15.0 ADDRESSABLE UNI VERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
muni cations I nterf ace or SCI ). The USAR T can b e con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CR T ter-
minals and person al compu ters, or it can b e configure d
as a half dup lex synchro nou s sy stem that ca n co mmu-
nicate w ith peripher al de vices , such as A/D or D /A inte-
grated circuits, Serial EEPROMs, etc.
The USART can be configured in the following modes:
Asynchronous (full duplex)
Synchronous - Master (half duplex)
Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Univ ersal Sync hronous Asynchro-
nous Receiver Transmitter.
Register 15-1: TXSTA: Transmit Status and Control Register
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Cloc k Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Read as '0'
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is clear ed x = Bit is unknown
PIC18CXX2
DS39026B-page 152 Preliminary 7/99 Microchip Technology Inc.
Register 15-2: RCSTA: Receive Status and Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is clea red after reception is c omplete.
Synchronous mode - slave
Unused in this mode
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1)
1 = Enables address detection, enable interrupt and load of the receive buffer
when RSR<8> is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2 FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of received data, can be Address/Data bit or a parity bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is clear ed x = Bit is unknown
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 153
15.1 USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate genera tor. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode, bit BRGH is ignored.
Table 15-1 shows the formula for computation of the
baud r ate f or diff erent USAR T mode s, whi ch only apply
in master mode (internal clock).
Giv en the desired baud r ate and Fo sc, the neare st inte-
ger value for the SPBRG register can be calculated
using the for mula in Table 15-1. From this, the error in
baud rate can be determined.
Example 15-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
becaus e the F OSC/(16(X + 1 )) eq uati on ca n red uc e th e
baud rate err or in some cases .
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a ti mer overflow be fo re out put-
ting the new baud rate.
15.1.1 SAMPLING
The data on th e RC7/RX/DT pi n is sampled three ti mes
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 15-1: CALCULATING BAUD RATE ERROR
TABLE 15-1: BAUD RATE FORMULA
TABLE 15-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1)) Baud Rate= FOSC/(16(X+1))
NA
X = value in SPBRG (0 to 255)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other resets
TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'.
Shaded cells are not used by the BRG.
Desired Baud rate = Fosc / (64 (X + 1))
Solving for X:
X = ( (Fosc / Desired Baud rate) / 64 ) - 1
X = ((16000000 / 9600) / 64) - 1
X = [25.042] = 25
Calculated Baud Rate = 16000000 / (64 (25 + 1))
= 9615
Error = (Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
= (9615 - 9600) / 9600
= 0.16%
PIC18CXX2
DS39026B-page 154 Preliminary 7/99 Microchip Technology Inc.
TABLE 15-3: BAUD RATES FOR SYNCHRONOUS MODE
BAUD
RATE
(K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPB R G
value
(decimal)
7.15909 MHz SPB R G
value
(decimal)
%% %%
0.3NA- - NA- - NA- - NA- -
1.2NA- - NA- - NA- - NA- -
2.4NA- - NA- - NA- - NA- -
9.6 NA - - NA - - 9.766 +1.73 255 9.622 +0.23 185
19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92
76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22
96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18
300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5
500 500 0 9 500 0 7 500 0 4 NA - -
HIGH 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0
LOW 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255
BAUD
RATE
(K)
FOSC = 5.0688 MHz 4 MHz SPBRG
value
(decimal)
3.579545 MHz SPBRG
value
(decimal)
1 MHz SPBRG
value
(decimal)
32.768 kHz SPBRG
value
(decimal)
% SPBRG % % % %
0.3 NA - - NA - - NA - - NA - - 0.303 +1.14 26
1.2 NA - - NA - - NA - - 1.202 +0.16 207 1.170 -2.48 6
2.4 NA - - NA - - NA - - 2.404 +0.16 103 NA - -
9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 NA - -
19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 NA - -
76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 NA - -
96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 NA - - NA - -
300 316.8 +5.60 3 NA - - 298.3 -0.57 2 NA - - NA - -
500 NA - - NA - - NA - - NA - - NA - -
HIGH 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0
LOW 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 155
TABLE 15-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
7.15909 MHz SPBRG
value
(decimal)
%% %%
0.3 NA - - NA - - NA - - NA - -
1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92
2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46
9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11
19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5
76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 NA - -
96 104.2 +8.51 2 NA - - NA - - NA - -
300 312.5 +4.17 0 NA - - NA - - NA - -
500 NA - - NA - - NA - - NA - -
HIGH 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0
LOW 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255
BAUD
RATE
(K)
FOSC = 5.0688 MHz 4 MHz SPBRG
value
(decimal)
3.579545 MHz SPBRG
value
(decimal)
1 MHz SPBRG
value
(decimal)
32.768 kHz SPBRG
value
(decimal)
% SPBRG % % % %
0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1
1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 NA - -
2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 NA - -
9.6 9.9 +3.13 7 NA - - 9.322 -2.90 5 NA - - NA - -
19.2 19.8 +3.13 3 NA - - 18.64 -2.90 2 NA - - NA - -
76.8 79.2 +3.13 0 NA - - NA - - NA - - NA - -
96 NA - - NA - - NA - - NA - - NA - -
300 NA - - NA - - NA - - NA - - NA - -
500 NA - - NA - - NA - - NA - - NA - -
HIGH 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0
LOW 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255
PIC18CXX2
DS39026B-page 156 Preliminary 7/99 Microchip Technology Inc.
TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
7.16 MHz SPBRG
value
(decimal)
%%%%
9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46
19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22
38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11
57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7
115.2 113.636 -1.36 10 11 1.111 -3.55 8 125 +8.51 4 111.860 -2.90 3
250 250 0 4 250 0 3 NA - - NA - -
625 625 0 1 NA - - 625 0 0 NA - -
1250 1250 0 0 NA - - NA - - NA - -
BAUD
RATE
(K)
FOSC = 5.068 SPBRG
value
(decimal)
4 MHz SPBRG
value
(decimal)
3.579 MHz SPBRG
value
(decimal)
1 MHz SPBRG
value
(decimal)
32.768 kHz SPBRG
value
(decimal)
%%%%%
9.6 9.6 0 32 NA - - 9.727 +1.32 22 8.928 -6.99 6 NA - -
19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 NA - -
38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 NA - -
57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 NA - -
115.2 105.6 -8.33 2 19.231 +0.16 12 111.86 -2.90 1 NA - - NA - -
250 NA - - NA - - 223.72 -10.51 0 NA - - NA - -
625 NA - - NA - - NA - - NA - - NA - -
1250 NA - - NA - - NA - - NA - - NA - -
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 157
15.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one start bit, eight or nine data bits
and one stop bit). The most common data format is
8-bits. An on-chip dedicated 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. Th e USAR T’ s transmit ter and receive r are
functio nally in dependent , but use the s ame data fo rmat
and baud rate. The baud rate generator produces a
clock, either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hard ware , b ut can be implem ented in s oftw are (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements :
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
15.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 15-1. The heart of the tra nsmit ter is the tr ansmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TX RE G r egi st e r is empty a nd
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
wa re. It will reset onl y when ne w data is load ed into the
TXREG register. While flag bit TXIF indicated the sta-
tus of the TXREG register, another bit TRMT
(TXSTA<1>) sho w s the statu s of the T SR regis ter. Sta-
tus bit TRMT is a read only bit, which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
Steps to f ollo w when se tting up an as ynchronous trans-
mission:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 15.1)
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 15-1: USART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
Note 2: Flag bit TXIF is set when enab le bi t TXEN
is set.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG register
TSR register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
• •
PIC18CXX2
DS39026B-page 158 Preliminary 7/99 Microchip Technology Inc.
FIGURE 15-2: ASYNCHRONOUS TRANSMISSION
FIGURE 15-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 15-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
TXREG USART Transmit R egister 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
WORD 1 Stop Bit
WORD 1
Transmit Shift Reg
Start Bit Bit 0 Bit 1 Bit 7/8
Write to TXREG Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT b it
(Tran s mit shi ft
reg. empty fl ag)
Transmit Shift Reg.
Write to TXREG
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. fla g)
TRMT bi t
(Transmit shift
reg. empty flag)
Word 1 Word 2
WORD 1 WORD 2
Start Bit Stop Bit Start Bit
Transmit Shift Reg.
WORD 1 WORD 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two consecutive transmissions.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 159
15.2.2 USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 15-4.
The data is re ceived on the RC7/RX/ DT pin and drives
the data recovery block. The data recovery block is
actuall y a h igh s pee d s hi fter ope rating a t x 16 tim es th e
baud r ate, wherea s the main recei ve serial shif ter oper-
ates at the bit rate or at FOSC. This mode would typi-
cally be used in RS-232 systems.
Steps to follow when setting up an Asynchronous
Reception:
1. Initializ e the SPBRG regis te r for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 15.1).
2. Enab le the a sy nchronous s erial po rt by clearin g
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is com-
plete an d an interrup t will be gen erated if enab le
bit RCIE was set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception .
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
15.2.3 SETTING UP 9-BIT MODE W ITH ADDRESS
DETECT
This m ode would typically b e used in RS -48 5 s y ste ms.
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enable:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is required,
set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select t he desired priority le vel with the RCIP bi t.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCIF bit will be set when reception is com-
plete. The interrupt will be acknowledged if the
RCIE and GIE bits are set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREG to determine if the de vice is being
addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
FIGURE 15-4: USART RECEIVE BLOC K DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷ 64
÷ 16
or Stop Start
(8) 710
RX9
• • •
PIC18CXX2
DS39026B-page 160 Preliminary 7/99 Microchip Technology Inc.
FIGURE 15-5: ASYNCHRONOUS RECEPTION
TABLE 15-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generat or Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Reception.
Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
Start
bit bit7/8
bit1bit0 bit7/8 bit0Stop
bit
Start
bit Start
bit
bit7/8 Stop
bit
RX (pin)
reg
Rcv buffer reg
Rcv shift
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
WORD 1
RCREG WORD 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 161
15.3 USART Synchr onous Master Mode
In Sync hronous Maste r mode, t he data i s transmitte d in
a half-duplex manner, (i.e. transmission and reception
do not occur at the same time). Whe n transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode in dicates that th e proces sor tran smits th e
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
15.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 15-1. The heart of the tra nsmit ter is the tr ansmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXRE G reg iste r tr ansfers t he data to th e TS R re giste r
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE, and cannot be cleared in soft-
wa re. It will reset onl y when ne w data is load ed into the
TXREG register . While fla g bit TXIF indicates the st atus
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit, which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 15.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
TABLE 15-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other Resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Master Transmission.
Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
PIC18CXX2
DS39026B-page 162 Preliminary 7/99 Microchip Technology Inc.
FIGURE 15-6: SYNCHRONOUS TRANSMISSION
FIGURE 15-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Bit 0 Bit 1 Bit 7
WORD 1
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 2 Bit 0 Bit 1 Bit 7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
(Inte rru pt flag)
TRMT
TXEN bit ’1’ ’1
Note: Sync master mode; SPBRG = ’ 0’. Continuous transmission of two 8-bit words
WORD 2
TRMT b it
Write word1 Write word2
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit0 bit1 bit2 bit6 bit7
TXEN b it
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 163
15.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once synchronous mode is selected, reception is
enab led by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 15.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will b e set when receptio n
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 15-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other
Resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented read as '0'.
Shaded cells are not used for Synchronous Master Reception.
Note1: Th e PSPIF, PSPIE and PSPIP bits are reserv ed on the PIC18C2X2 devices. Alw a ys mai ntain these bits clea r .
PIC18CXX2
DS39026B-page 164 Preliminary 7/99 Microchip Technology Inc.
FIGURE 15-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = ’1’ and bit BRGH = ’0’.
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
’0’
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
’0
Q1 Q2 Q3 Q4
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 165
15.4 USART Synchr onous Slave Mode
Synchron ous Slav e Mode diff ers from the Master Mode
in the fact that the shift clock is supplied externally at
the RC6/T X/CK pin (instead of being su pplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
15.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instructi on i s exec ute d, th e followin g wi ll o ccur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register .
c) Flag bit TXIF will not be set.
d) When the first w ord has been shifted o ut of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enab led, t he p rogr am w ill br anch to the in terrupt
vector.
Steps to follow when setting up a Synchronous Slave
Transmission:
1. Enab le the sync hronous sl av e serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
15.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the synchronous master and slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a "don’t care" in slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction , then a word may b e receive d during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enab le bit RCIE bit is set, the interrupt gener ated
will wake the chip from SLEEP. If the global interrupt is
enab led, the prog ram will br anch to the interrupt v ector .
Steps to follow when setting up a Synchronous Slave
Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RC IF wi ll b e se t w he n rec ept ion is com -
plete . An interrupt will be g ene ra ted if ena ble bit
RCIE w a s set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
PIC18CXX2
DS39026B-page 166 Preliminary 7/99 Microchip Technology Inc.
TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 15-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other Resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generat or Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented read as '0'.
Shaded cells are not used for Synchronous Slave Transmission.
Note1: Th e P SPIF, PSPIE and PSPIP bits a re reserved on th e PI C1 8C2X 2 d evices. Always maintain th ese bi ts cl ea r.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other
Resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Reg ister 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented read as '0'.
Shaded cells are not used for Synchronous Slave Reception.
Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 167
16.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has five
inputs for the PIC18C2x2 devices and eight for the
PIC18C4x2 devices. This module has the ADCON0
and ADCON1 register definitions that are compatible
with the mid-range A/D module.
The A/D allows con version of an analog input signal to
a corre spo ndi ng 10- bit digit al numb er.
The A/D module has four registers. These registers
are: A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 16-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 16-2, configures the func-
tions of the port pins.
Register 16-1: ADCON0 Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON
bit 7 bit 0
bit 7:6 ADCS1:ADCS0: A/D Conversion Clock Select bits (shown in bold)
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock derived from the internal A/D RC oscillator)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock derived from the internal A/D RC oscillator)
Note: The ADCS2 bit is located in the ADCO N1 regi ster
bit 5:3 CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (AN0)
001 = channel 1, (AN1)
010 = channel 2, (AN2)
011 = channel 3, (AN3)
100 = channel 4, (AN4)
101 = channel 5, (AN5)
110 = channel 6, (AN6)
111 = channel 7, (AN7)
Note: The PIC18C2X2 devices do not implement the full 8 A/D channels, the unimple-
mented selections are reserved. Do not select any unimplemented channel.
bit 2 GO/DONE: A/D Co nversi on Status bit
When ADON = 1
1 = A/D conv ersion in prog ress (setting thi s bit starts the A/D c onversion which is automatica lly
cleared by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
bit 1 Unimplemented: Read as ’0’
bit 0 ADON: A/D On bit
1 = A/D converter module is powered up
0 = A/D converter module is shut off and consumes no operating current
Legend:
R = R eadable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026B-page 168 Preliminary 7/99 Microchip Technology Inc.
Register 16-2: ADCON1 Register
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7:6 Unimplemented: Read as ’0’
bit 7 ADFM: A/D Re sult format select.
1 = Right justified. 6 Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ’0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (shown in bold)
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock derived from the internal A/D RC oscillator)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock derived from the internal A/D RC oscillator)
Note: The ADCS1:ADCS0 bits are located in the ADCON0 register
bit 5:4 Unimplemented: Read as ’0’
bit 3:0 PCFG3:PCFG0: A/D Port Configuration Control bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: On any device reset, the por t pins that are multiplexed with analog functions (ANx) are
forced to be an analog input.
A = Analog input D = Digital I/O
C/R = # of analog input channels / # of A/D voltage references
PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+VREF- C / R
0000 AAAAA A AAV
DD VSS 8 / 0
0001 AAAAVREF+A A A AN3 VSS 7 / 1
0010 DDDAA A AAVDD VSS 5 / 0
0011 DDDAV
REF+A A A AN3 VSS 4 / 1
0100 DDDDA D AAVDD VSS 3 / 0
0101 DDDDVREF+D A A AN3 VSS 2 / 1
011x DDDDD D DD 0 / 0
1000 AAAAV
REF+VREF-A AAN3AN26 / 2
1001 DDAAA A AAVDD VSS 6 / 0
1010 DDAAV
REF+A A A AN3 VSS 5 / 1
1011 DDAAVREF+VREF-A AAN3AN24 / 2
1100 DDDAVREF+VREF-A AAN3AN23 / 2
1101 DDDDV
REF+VREF-A AAN3AN22 / 2
1110 DDDDD D DAVDD VSS 1 / 0
1111 DDDDVREF+VREF-D AAN3AN21 / 2
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 169
The analog reference voltage is software selectable to
either the de vice’s positi ve and negativ e suppl y vo ltage
(VDD and VSS) or the voltage level on the RA3/AN3/
VREF+ pin and RA2/AN2/VREF-.
The A/D conv erter has a unique f eature of b eing ab le to
oper ate while the devic e is in SLEEP mode. To operate
in sleep, the A/D conversion clock must be derived from
the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
Each por t pin as sociat ed with the A/D conver ter c an
be configured as an analog input (RA3 can also be a
voltage reference) or as a digital I/O.
The ADRESH and ADRESL regist ers contain th e result
of the A/D conversion. When the A/D conversion is
complete, the result is loaded into the ADRESH/
ADRESL registers , the GO/DONE bit (ADCON0<2>) is
cleared , and A/D i nterrupt flag b it ADIF is set. The b loc k
diagram of the A/D module is shown in Figure 16-1.
FIGURE 16-1: A/D BLOCK DIAGRAM
(Input voltage)
VAIN
VREF+
Reference
voltage
VDD
PCFG0
CHS2:CHS0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
111
110
101
100
011
010
001
000
10-bit
Converter
VREF-
VSS
A/D
PIC18CXX2
DS39026B-page 170 Preliminary 7/99 Microchip Technology Inc.
The value that is in the ADRESH/ADRESL registers is
not modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Powe r-on Rese t.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 16.1.
After this acqui sitio n time has e lapse d, the A/D c on v er-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversion:
1. Configure the A/D module:
Config ure a nal og p in s , voltage reference and
digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D conversion clock (ADCON0)
Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3. Wait the required acquisiti on tim e .
4. Start conversion:
Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either :
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH/ADRESL);
clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
16.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The sour ce imped ance aff ects the offset volt age
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5k. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
FIGURE 16-2: ANALOG INPUT MODEL
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
VAIN CPIN
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I leakage
RIC 1k
Sampling
Switch
SS RSS
CHOLD = 120 pF
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
( k)
VDD
± 500 nA
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 171
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation assumes
that 1/2 LS b error is used (1024 step s f or th e A/D). Th e
1/2 LSb e rror i s t he m ax im um erro r al lo wed for the A/D
to meet its specified resolution.
Equation 16-1: Acquisition Time
Equation 16-2: A/D Minimum Charging Time
Example 16-3 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assump-
tions:
CHOLD = 120 pF
Rs = 2.5 k
Conversion Error 1/2 LSb
VDD = 5V Rss = 7 k
Temperature = 50°C (system max.)
VHOLD =0V @ time = 0
EXAMPLE 16-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ = Amplifier Settling Ti me +
Holding Capacitor Charging Time +
Temperature Coefficient
=TAMP + TC + TCOFF
VHOLD = (VREF - (VREF/2048)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))
or
Tc = -(120 pF)(1 k + RSS + RS) ln(1/2047)
TACQ =TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ =2 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]
TC =-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 k + 7 k + 2.5 k) ln(0.0004885)
-120 pF (10.5 k) ln(0.0004885)
-1.26 µs (-7.6241)
9.61 µs
TACQ =2 µs + 9.61 µs + [(50°C - 25°C)(0.05 µs/°C)]
11.61 µs + 1.25 µs
12.86 µs
PIC18CXX2
DS39026B-page 172 Preliminary 7/99 Microchip Technology Inc.
16.2 Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D co nve rsio n requi res 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. The seven possibl e options for TAD are:
•2T
OSC
•4TOSC
•8TOSC
•16TOSC
•32TOSC
•64T
OSC
Internal R C oscillat or
For c orrect A /D co nversio ns, the A/ D co nve rsio n clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 16- 1 shows th e res ultan t TAD times de r ived from
the device operating frequencies and the A/D clock
sour ce se lec ted .
16.3 Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must ha ve their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
TABLE 16-1: TAD vs. DEVICE OPERATING FREQUENCIES
TABLE 16-2: TAD vs. DE VICE OPERATING FREQUENCIES (FOR EXTENDED, LC, DEVICES)
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will conver t an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
Note 2: Analog le vels on an y pin t hat is d efined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to con-
sume current that is out of the devices
specification.
AD Clock Source (TAD) Device Frequency
Operation ADCS2:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz
2TOSC 000 100 ns(2) 400 ns(2) 1.6 µs6
µs
4TOSC 100 200 ns(2) 800 ns(2) 3.2 µs 12 µs
8TOSC 001 400 ns(2) 1.6 µs6.4
µs24 µs(3)
16TOSC 101 800 ns(2) 3.2 µs 1 2.8 µs48 µs(3)
32TOSC 010 1.6 µs6.4
µs25.6 µs(3) 96 µs(3)
64TOSC 110 3.2 µs 12.8 µs51.2 µs(3) 192 µs(3)
RC 011 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time .
3: For faster conversion times, the selection of another cloc k source is recommended.
4: For de vice frequencies abov e 1 MHz, the de vice must be in SLEEP for the entire conversion or the A/D accuracy may be
out of specification.
AD Clock Source (TAD) Device Frequency
Operation ADCS2:ADCS0 4 MHz 2 MHz 1.25 MHz 333.33 kHz
2TOSC 000 500 ns(2) 1.0 µs(2) 1.6 µs(2) 6 µs
4TOSC 100 1.0 µs(2) 2.0 µs(2) 3.2 µs(2) 12 µs
8TOSC 001 2.0 µs(2) 4.0 µs6.4
µs24 µs(3)
16TOSC 101 4.0 µs(2) 8.0 µs 1 2.8 µs48 µs(3)
32TOSC 010 8.0 µs 16.0 µs25.6 µs(3) 96 µs(3)
64TOSC 110 16.0 µs 32.0 µs51.2 µs(3) 192 µs(3)
RC 011 3 - 9 µs(1,4) 3 - 9 µs(1,4) 3 - 9 µs(1,4) 3 - 9 µs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 6 µs.
2: These values violate the minimum required TAD time .
3: For faster conversion times, the selection of another cloc k source is recommended.
4: For de vice frequencies abov e 1 MHz, the de vice must be in SLEEP for the entire conversion or the A/D accuracy may be
out of specification.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 173
16.4 A/D Conversions
Figure 16-3 shows the operation of the A/D conver ter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the l as t value written to th e ADRESH: AD RES L re g-
isters). After the A/D con v ersion is aborted, a 2TAD wait
is required before the next acquisition is star ted. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
16.5 Use of the CCP2 Trigger
An A/D co n v ersion c an be s tarted by th e “spec ial event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion, and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appro priate analog input chann el must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a conver-
sion).
If the A/ D module is no t enable d (ADON is cleare d), the
“special event trigger” will be ignored by the A/D mod-
ule, but will still reset the Timer1 (or Timer3) counter.
FIGURE 16-3: A/D CONVERSION TAD CYCLES
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1TAD2TAD3TAD4 TAD5TAD6 TAD7TAD8 TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2 TAD9 TAD10
b1 b0
Tcy - TAD
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion Start s
b0
PIC18CXX2
DS39026B-page 174 Preliminary 7/99 Microchip Technology Inc.
TABLE 16-3: SUMMARY OF A/D REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
PIR2 BCLIF LVDIF TMR3IF CCP2IF ---- 0000 ---- 0000
PIE2 BCLIE LVDIE TMR3IE CCP2IE ---- 0000 ---- 0000
IPR2 BCLIP LVDIP TMR3IP CCP2IP ---- 0000 ---- 0000
ADRESH A/D Result Register xxxx xxxx uuuu uuuu
ADRESL A/D Result Register xxxx xxxx uuuu uuuu
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/
DONE —ADON0000 00-0 0000 00-0
ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
PORTA RA6 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
TRISA PORTA Data Direction Register --11 1111 --11 1111
PORTE —RE2RE1RE0---- -000 ---- -000
LATE LATE2 LATE1 LATE0 ---- -xxx ---- -uuu
TRISE IBF OBF IBOV PSPMODE POR TE Da ta Di rection Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, = unimplemented read as ’0. Shaded cells are not used for A/D conversion.
Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 175
17.0 LOW VOLTAGE DETECT
In many applications, the ability to determine if the
device voltag e (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do "housekeeping tasks" before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When th e volt age of the d evic e becomes l ower then the
specif ied poi nt, an in terrupt flag is set. If the i nterrupt is
enab led, th e prog ra m e x ec ution will br anch to th e int er-
rupt ve ctor addres s and the so ftw are can then res pond
to that interrupt source.
The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be "turned
off" by the software, which minimizes the current con-
sumption for the device.
Figure 17-1 shows a possible application voltage curv e
(typically for batteries). Over time, the device voltage
decreas es. When the de vice vo ltage equals v oltage V A,
the LVD logic generates an interrupt. This occurs at
time TA. The application so ftware then has the time until
the device vo lta ge is no lon ger in valid operati ng r ange
to shut down the system. Voltage point VB i s t he mini -
mum valid operating voltage specification. This occurs
at time TB. TB - TA is the total time for shutdown.
FIGURE 17-1: TYPICAL LOW VOLTAGE DETECT APPLICATION
Time
Voltage
VA
VB
TATB
VA = LVD trip point
VB = Minimu m valid device
operating voltage
Legend:
PIC18CXX2
DS39026B-page 176 Preliminary 7/99 Microchip Technology Inc.
Figure 17-2 shows the block diagram for the LVD mod-
ule. A comparator uses an internally generated refer-
ence voltage as the set point. When the selected tap
output of the device voltage crosses the set point (is
lower than), the LVDIF bit is set.
Each node in the resister divider represents a “trip
point ” volt age. The “t ri p poi nt” volta ge is the mi nimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the voltage
generated by the internal voltage reference module.
The comp ar ator then gene rates an interrupt si gnal se t-
ting the LVDIF bi t. This v ol tage i s so ftwar e p rogr amm a-
ble to any one of 16 values (See Figure 17-2). The trip
point is selected by programming the LVDL3:LVDL0
bits (LVDCON<3:0>).
FIGURE 17-2: LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM
LVDIF
VDD
16 to 1 MUX
LVDEN
LVD Control
Register
Internally generated
reference vo ltage
LVDIN
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 177
17.1 Control Register
The Low Voltage Detect Control register controls the
operation of the Low Voltage Detect circuitry.
Register 17-1: LVDCON Register
U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0
bit 7 bit 0
bit 7:6 Unimplemented: Read as ’0’
bit 5 IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the
specified voltage range.
0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4 LVDEN: Low-voltage Detect Power Enable bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 3:0 LVDL3:LVDL0: Low Voltage Detection Limit bits
1111 = External analog input is used (input comes from the LVDIN pin)
1110 = 4.5V min - 4.77V max.
1101 = 4.2V min - 4.45V max.
1100 = 4.0V min - 4.24V max.
1011 = 3.8V min - 4.03V max.
1010 = 3.6V min - 3.82V max.
1001 = 3.5V min - 3.71V max.
1000 = 3.3V min - 3.50V max.
0111 = 3.0V min - 3.18V max.
0110 = 2.8V min - 2.97V max.
0101 = 2.7V min - 2.86V max.
0100 = 2.5V min - 2.65V max.
0011 = 2.4V min - 2.54V max.
0010 = 2.2V min - 2.33V max.
0001 = 2.0V min - 2.12V max.
0000 = 1.8V min - 1.91V max.
Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage
of the device are not tested.
Legend:
R = Readable bit W = Writable bit
U = Unimplemented bit, read as ‘0’ - n = Value at POR reset
PIC18CXX2
DS39026B-page 178 Preliminary 7/99 Microchip Technology Inc.
17.2 Operation
Depen din g on the p o wer source f or th e device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be con-
stantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods, where the voltage is checked. After
doing the check, the LVD module may be disabled.
Each tim e that the LVD module is e nab led, the circ uitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
The following steps are needed to setup the LVD
module:
1. Write the value to the LVDL3:LVDL0 bits (LVD-
CON register), which selects the desired LVD
Trip Point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
3. Enable the LVD module (Set the LVDEN bit in
the LVDCON register).
4. Wait for th e LVD m o dule t o s ta bi li ze (t he IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
f alsely become set until the LVD module has st a-
bilized (clear the LVDIF bit).
6. Enab le the LVD interrupt (s et t he LVDIE an d th e
GIE bits).
Figure 17-3 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 17-3: LOW VOLTAGE DETECT WAVEFORMS
.
VLVD
VDD
LVDIF
VLVD
VDD
Enable LVD
Internally Generated 50 ms
LVDIF may not be set
Enable LVD
50 ms
LVDIF
LVDIF cleared in software
LVDIF cleared in software
LVDIF cleared in software,
CASE 1:
CASE 2:
LVDIF remains set since LVD condition still exists
Reference stable
Internally Generated
Reference stable
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 179
17.2.1 REFERENCE VOLTAGE SET POINT
The Internal Ref erence Voltage of the LVD module ma y
be used by other internal circuitry (the programmable
brown-out reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low voltage
conditi on can be rel iably d etected. This time is in v ariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low-voltage
inter rupt flag wil l not be enab led until a stab le ref erence
v oltage is reac hed . Re f er to the w a v eform in Figu re 17-
3.
17.2.2 CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divid er are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
17.3 Operation During Sleep
When enabled, the LVD circuitry continues to operate
during sleep . If the de vice voltage crosses t he trip point,
the LVDIF bit will be set and the device will wake-up
from sleep. Device execution will continue from the
interrupt v ector a ddress if int errupts ha v e been globa lly
enabled.
17.4 Effects of a Reset
A device reset forces all registers to their reset state.
This forces the LVD module to be turned off.
PIC18CXX2
DS39026B-page 180 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 181
18.0 SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
OSC Selection
Reset
- Power-on Reset (POR)
- P o wer-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID locations
In-circuit serial programming
These devices have a Watchdog Timer, which is per-
manently enab led via the configuration bits or software-
controlled. It runs off its own RC oscillator for added
reliability. There are two timers that offer necessary
delays on power-up. One is the Oscillator Start-up
Timer (O ST), intended to ke ep the chip in reset until the
crystal oscillator is stable. The other is the Power-up
Timer (PWRT), which provides a fixed dela y on p o wer-
up only, designed to keep the part in reset while the
power supply stab ili z e s . Wit h th es e two timers on-ch ip,
most applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
pow er-down m ode. The user can w ake-up from SLEEP
through external reset, Watchdog Timer Wake-up or
through an interrupt. Se veral oscill ator opti ons are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
18.1 Configuration Bits
The con figur ati on bits c an be progr a mmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped star ting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
TABLE 18-1: CONFIGURATION BITS AND DEVICE IDS
Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/
unprogrammed
value
300000h CONFIG1L CP CP CP CP CP CP CP CP 1111 1111
300001h CONFIG1H OSCSEN FOSC2 FOSC1 FOSC0 111- -111
300002h CONFIG2L BORV1 BORV0 BODEN PWRTEN ---- 1111
300003h CONFIG2H WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111
300005h CONFIG3H —CCP2MX---- ---1
300006h CONFIG4L —LVENSTVREN---- --11
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 0000 0000
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0010
Legend: x = unknown, u = unchanged , - = unimplement ed, q = value depends on c ondition, grayed cells are unimp l emented read as 0
PIC18CXX2
DS39026B-page 182 Preliminary 7/99 Microchip Technology Inc.
Register 18-1: Configuration Register 1 High (CONFIG1H: Byte Address 300001h)
Register 18-2: Configuration Register 1 Low (CONFIG1L: Byte Address 300000h)
R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1
Reserved Reserved OSCSEN FOSC2 FOSC1 FOSC0
bit 7 bit 0
bit 7-6 Reserved: Read as ’1
bit 5 OSCSEN: Oscillator System Clock Switch Enable bit
1 = Oscillator system clock switch option is disabled (Main oscillator is source)
0 = Oscillator system clock switch option is enabled
(Oscillator switching is enabled)
bit 4-3 Reserved: Read as ’0
bit 2-0 FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator w/ OSC2 configured as RA6
110 = HS oscillator with PLL enabled/CLock frequency = (4 x Fosc)
101 = EC oscillator w/ OSC2 configured as RA6
100 = EC oscillator w/ OSC2 configured as divide by 4 clock output
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0
- n = Value when device is unprogrammed u = Unchanged from programmed state
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP CP CP CP CP CP CP CP
bit 7 bit 0
CP: Code Protection bits (apply when in Code Protected Microcontroller Mode)
1 = Program memory code protection off
0 = All of program memory code protected
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0
- n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 183
Register 18-3: Configuration Register 2 High (CONFIG2H: Byte Address 300003h)
Register 18-4: Configuration Register 2 Low (CONFIG2L: Byte Address 300002h)
U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7 bit 0
bit 7-4 Reserved: Read as ’0
bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Sele ct bits
000 = 1:128
001 = 1:64
010 = 1:32
011 = 1:16
100 = 1:8
101 = 1:4
110 = 1:2
111 = 1:1
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit P = Programmable bit U = Unim plemented bit, read a s 0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
BORV1 BORV0 BOREN PWRTEN
bit 7 bit 0
bit 7-4 Reserved: Read as ’0
bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits
11 = VBOR set to 2.5V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 1 BOREN: Brown-out Reset Enable bit (1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
Note: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardless of the v alue of bit PWR TEN. En sure t he P o wer-up Timer i s enabl ed an y-
time Brown-out Reset is enabled.
bit 0 PWRTEN: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
Note: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any-
time Brown-out Reset is enabled.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, r ead as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18CXX2
DS39026B-page 184 Preliminary 7/99 Microchip Technology Inc.
Register 18-5: Configuration Register 3 High (CONFIG3H: Byte Address 300005h)
Register 18-6: Configuration Register 4 Low (CONFIG3H: Byte Address 300006h)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/P-1
CCP2MX
bit 7 bit 0
bit 7-1 Reserved: Read as ’0
bit 0 CCP2MX: CCP2 Mux bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0
- n = Value when device is unprogrammed u = Unchanged from programmed state
U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1
Reserved STVREN
bit 7 bit 0
bit 7-2 Reserved: Read as ’0
bit 1 Reserved: Maintain this bit set.
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack Full/Under flow wil l cause reset
0 = Stack Full/Underflow will not cause rese t
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 185
18.2 Watchdog Timer (WDT)
The W atchdog Timer is a free running on-chip RC oscil-
lator, whic h does not requ ire an y e x ternal comp onents .
This RC oscillator is separate from the RC oscillator of
the OSC1 /CLKI pin. Tha t means tha t the WDT will run,
even if the clock on the OSC1/CLKI and OSC2/CLKO/
RA6 pi ns of th e de v ic e has b een s top ped , for e x am ple,
by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (W atchdog Timer Reset). If the de vice is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the RCON re gister
will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software exe-
cution m ay not disabl e this functi on. When the WDTEN
configuration bit is cleared, the SWDTEN bit enables/
disables the operation of the WDT.
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits.
18.2.1 CONTROL REGISTER
Register 18-7 shows the WDTCON register. This is a
readable and writable register , which contains a control
bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.
Register 18-7 WDTCON Register
Note: The CLRWDT and SLEEP instructions clear
the WDT and the postscaler if assigned to
the WDT, and pre vent it fro m timing out and
generating a device RESET condition.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
presc al er ass ig nme nt is not changed.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
SWDTEN
bit 7 bit 0
bit 7:1 Unimplemented: Read as ’0
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable Bit
1 = Watchdog Timer is on
0 = Watchdog Timer is turned off if the WDTEN configuration bit in the configuration
register = ’0’
Legend:
R = Readable bit W = Writable bit
U = Unimplemented bit, read as ‘0’ - n = Value at POR reset
PIC18CXX2
DS39026B-page 186 Preliminary 7/99 Microchip Technology Inc.
18.2.2 WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
reset period. The postscaler is selected at the time of
the device programming, by the value written to the
CONFIG2H configuration register.
FIGURE 18-1: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 18-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2H WDTPS2 WDTPS2 WDTPS0 WDTEN
RCON IPEN LWRT RI TO PD POR BOR
WDTCON —SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
Postscaler
WDT Timer
WDTEN
8 - to - 1 MUX WDTPS2:WDTPS0
WDT
Time-out
8
SWDTEN bit
Note: WDPS2:WDPS0 are bits in a configuration register.
Configuration bit
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 187
18.3 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or hi-impedance).
Fo r lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switchin g c urre nts ca us ed by floating inp uts. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
18.3.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
The following peripheral interrupts can wake the device
from SLEEP:
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. TMR3 interrupt. Timer3 must be operating as
an asynchronous counter.
4. CCP capture mode interrupt.
5. Special event trigger (Timer1 in asynchronous
mode using an external clock).
6. MSSP (Start/Stop) bit detect interrupt.
7. MSSP transmit or receive in slave mode (SPI/
I2C).
8. USART RX or TX (synchronous slave mode).
9. A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and will cause a "wake-up". The TO and PD
bits i n the RCON registe r can be used to d etermine th e
cause of the device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
When th e SLEEP instruction is being ex ecuted, the ne xt
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
inte rrup t ena ble bit mus t be set (enabled ). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP inst ru ction . If the GIE bi t is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
PIC18CXX2
DS39026B-page 188 Preliminary 7/99 Microchip Technology Inc.
18.3.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit set, o ne of th e followin g will o ccur:
If an interru pt cond ition (in terrupt flag b it and in ter-
rupt enable bits are set) occurs before the execu-
tion of a SLEEP instruction, the SLEEP instruction
will complete as a NOP. Therefore, the WDT and
WDT pos tscal er will not be cl eared, th e T O bit will
not be set and PD bits will not be cleared.
If the interrupt condition occurs during or after
the execution of a SLEEP instruction, the device
will immediately wake up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
pos tscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instr uction executed , test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT in stru c-
tion should be executed before a SLEEP instruction.
FIGURE 18-3: WAKE-UP FR OM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIEH bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+2 PC+4
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 2)
SLEEP
Processor in
SLEEP
Interrupt Latency(3)
Inst(PC + 4)
Inst(PC + 2)
Inst(0008h) Inst(000Ah)
Inst(0008h)
Dummy cycle
PC + 4 0008h 000Ah
Dummy cycle
TOST(2)
PC+4
Note1: XT, HS or LP oscillator mode assumed.
2: GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = '0',
execution will continue in-line.
3: TOST = 1024TOSC (drawing not to scale) This delay will not occur for RC and EC osc modes.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 189
18.4 Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
18.5 ID Locations
Fiv e memory locations (20 0000h - 200004h) are desi g-
nated as ID locations, where the user can store che ck-
sum or other code-identification numbers. These
locations are accessible during normal execution
through the TBLRD instr uction or during program/ver-
ify. The ID locations can be read when the device is
code protected.
18.6 In-Circuit Serial Programming
PIC18CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply d one with two lin es f or cloc k a nd data, a nd three
other line s for pow er , ground and the prog ramming v olt-
age. This all ows c ustomers to manufacture bo ards with
unprogrammed devices, and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
Note: Microchip Technology does not recom-
mend code protect ing windowed devices.
PIC18CXX2
DS39026B-page 190 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 191
19.0 INSTRUCTION SET SUMMARY
The PIC18CXXX instruction set adds many enhance-
ments to the previous PICmicro instruction sets, while
maintaining an easy migration from these PICmicro
instruction sets.
Most instructions are a single program memory word
(16-bits), but there are three instructions that require
two program memory locations.
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
The ins truc ti o n se t is hig hl y ort h og on a l an d is group ed
into four basic categories:
Byte-oriented operations
Bit-oriented operations
Literal operations
Control ope rations
The PIC18CXXX instruction set summary in
Table 19-2 lists byte-oriented, bit-oriented, literal
and control operations. Table 19-1 shows the
opcode field descriptions.
Most byte-oriented instructions have three operands:
1. The file register (specified by the value of ’f’)
2. The destination of the result
(specified by the value of ’d’)
3. The accessed memory
(specified by the value of ’a’)
'f' represents a file register designator and 'd' repre-
sents a destination designator. The file register desig-
nator specifies which file register is to be used by the
instr ucti on.
The desti nation designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the WREG register. If 'd' is one, the result is
placed in the file register specified in the instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by the value of ’f’)
2. The bit in the file register
(specified by the value of ’b’)
3. The accessed memory
(specified by the value of ’a’)
'b' represents a bit field designator which selects the
number of the bit affected by the operation, while 'f' rep-
resents the numbe r of the file in which the b it is located.
The literal instructions may use some of the following
operands:
A literal value to be loaded into a file register
(specified by the value of ’k’)
The desired FS R register to load the literal value
into (specified by the value of ’f’)
No operand required
(specified by the value of ’—’)
The control i nstructio ns ma y us e some of the f oll owin g
operands:
A program memory address (specified by the
value of ’n’)
The mod e of the Call or Retu rn inst ructio ns (s pec -
ified by the v al ue of ’s’)
The mode of the Table Read and Table Write
ins tructio ns (specified by the val ue of ’ m )
No operand required
(specified by the value of ’—’)
All instructions are a single word, except for three dou-
ble word instructions. These three instructions were
made double word instructions so that all the required
information is available in these 32-bits. In the second
word, the 4-MSbs are 1’s. If this second word is exe-
cuted as an instruction (by itself), it will execute as a
NOP.
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these ca ses, the e x ecut ion tak es tw o instructio n
cycles with the additional instruction cycle(s) executed
as a NOP.
The doub l e w ord ins tructions e x e cute i n tw o ins truction
cycles.
One in struction cycle con sists o f f our oscil lator p eriods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction e xecution time is 1 µs. I f a con dition al tes t is
true or t he progr am counter is changed as a resul t of an
instruction, the instruction execution time is 2 µs. Two
word branch instructions (if true) would take 3 µs.
Figur e 19-1 shows the genera l fo rmats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
The Instruction Set Summary, shown in Table 19-2,
lists the instructions recognized by the Microchip
assembler (MPASM).
Section 19.1 pro vides a desc ription of each i nstructio n.
PIC18CXX2
DS39026B-page 192 Preliminary 7/99 Microchip Technology Inc.
TABLE 19-1: OPCODE FIELD DESCRIPTIONS
Field Description
aRAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7)
BSR Bank Select Register. Used to select the current RAM bank.
dDestination select bit;
d = 0: store result in WREG,
d = 1: store result in file regi ster f.
dest Destination either the WREG register or the specified register file location
f8-bit Register file address (0x00 to 0xFF)
fs 12-bit Register file address (0x000 to 0xFFF). This is the source address.
fd 12-bit Register file address (0x000 to 0xFFF). This is the destination address.
kLiteral field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
label Label name
mm The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
* No Change to register (such as TBLPTR with Table reads and writes)
*+ Post-Increment register (such as TBLPTR with Table reads and writes)
*- Post-Decrement register (such as TBLPTR with Table reads and writes)
+* Pre-Increment register (such as TBLPTR with Table reads and writes)
nThe relative address (2’s complement number) for relative branch instructions, or the direct
address for Call/Branch and Retur n instructions
PRODH Product of Multi ply high byte
PRODL Product of Multiply low byte
sFast Call / Return mode select bit.
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
uUnused or Unchang ed
WREG Working register (accumulator)
xDon't care (0 or 1)
The ass em b l er w il l gen erate co de w it h x = 0. I t is th e recom me nde d form of use for compa tibi li ty
with all Microchip software tools.
TBLPTR 21-bit Table Pointer (points to a Program Memory location)
TABLAT 8-bit Table Latch
TOS Top of Stack
PC Program Counter
PCL Program Counter Low Byte
PCH Program Counte r High Byte
PCLATH Program Counter High Byte Latch
PCLATU Program Counter Upper Byte Latc h
GIE Global Interrupt Enable bit
WDT Watchdog Timer
TO Time-out bit
PD Power-down bit
C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative
[ ] Optional
( ) Contents
Assigned to
< > Register bit field
In the set of
italics User defined term (font is courier)
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 193
FIGURE 19-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10 9 8 7 0
d = 0 for result destination to be WREG register
OPCODE d a f (FILE #)
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
Bit-oriented file register operations
15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #)
b = 3-bit position of bit in file register (f)
Literal operations
15 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Byte to Byte move operations (2-word)
15 12 11 0
OPCODE f (Source FILE #)
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal)
n = 20-bit immediate value
a = 1 for BSR to select bank
f = 8-bit file register address
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
15 12 11 0
1111 n<19:8> (literal)
15 12 11 0
1111 f (Destination FILE #)
f = 12-bit file register address
Control operations
Example Instruction
ADDWF MYREG, W, B
MOVFF MYREG1, MYREG2
BSF MYREG, bit, B
MOVLW 0x7F
GOTO Label
15 8 7 0
OPCODE n<7:0> (literal)
15 12 11 0
n<19:8> (literal)
CALL MYFUNC
15 11 10 0
OPCODE n<10:0> (literal)
S = Fast bit
BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
S
PIC18CXX2
DS39026B-page 194 Preliminary 7/99 Microchip Technology Inc.
TABLE 19-2: PIC18CXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Comple ment f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Incremen t f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination)2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1 (2 or 3)
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
0101
0101
0011
0110
0001
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
C, DC, Z, OV, N
C, DC, Z, OV, N
None
None
Z, N
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1, 2
1, 2
1, 2
1, 2
4
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
Note1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
val ue pres ent on the pi ns the mselv es . For e xam ple , if the data l atch i s ’ 1’ f or a pi n conf igured as inp ut and is driv en
low by an external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instruct ions a re 2 word instructions. The second word of these ins truction will be exec uted as a NOP, unless
the first wo rd of the instruction retrieves the information embedded in these 16-bits. This ensures that all program
memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 195
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
n
n
n
n
n
n
n
n
n
n, s
n
n
s
k
s
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1st word
2nd word
Clear Watchdog Timer
Deci mal Adjust WRE G
Go to address1st word
2nd word
No Operation
No Operation (Note 4)
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relativ e Call
Software device RESET
Return from interrupt enable
Return with liter al in WREG
Return from Subroutine
Go into stan dby mode
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
1
1
2
1
1
1
1
2
1
2
2
2
1
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO, PD
TABLE 19-2: PIC18CXXX INSTRUCTION SET (Cont.d)
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
val ue pres ent on the pi ns the mselv es . For e xam ple , if the data l atch i s ’ 1’ f or a pi n conf igured as inp ut and is driv en
low by an external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instruct ions are 2 word instr uctions. The second word of th ese instruction will be executed as a NOP, unless
the first wo rd of the instruction retrieves the information embedded in these 16-bits. This ensures that all program
memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
PIC18CXX2
DS39026B-page 196 Preliminary 7/99 Microchip Technology Inc.
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
f, k
k
k
k
k
k
k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit)1st word
to FSRx2nd word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY PRO GRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pr e-incremen t
2
2 (5)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
TABLE 19-2: PIC18CXXX INSTRUCTION SET (Cont.d)
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
val ue pres ent on the pi ns the mselv es . For e xam ple , if the data l atch i s ’ 1’ f or a pi n conf igured as inp ut and is driv en
low by an external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instruct ions a re 2 word instructions. The second word of these ins truction will be exec uted as a NOP, unless
the first wo rd of the instruction retrieves the information embedded in these 16-bits. This ensures that all program
memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 197
19.1 Instruction Set
ADDLW ADD literal to WREG
Syntax: [
label
] ADDLW k
Operands: 0 k 255
Operation: (WREG) + k WREG
Status Affected: N,OV, C, DC, Z
Encoding: 0000 1111 kkkk kkkk
Description: The contents of WREG are added
to the 8 -bit liter al ’k ’ an d the result i s
placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ’k’ Process
Data Write to
WREG
Example:ADDLW 0x15
Before Instruction
WREG = 0x10
After Instruction
WREG = 0x25
ADDWF ADD WREG to f
Syntax: [
label
] ADDWF f,d,a
Operands: 0 f 25 5
d [0,1]
a [0,1]
Operation: (WREG) + (f) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0010 01da ffff ffff
Description: Add WREG to register f’. If ’d’ is 0,
the result is stored in WREG. If ’d’
is 1, the res ult is sto red b ack in reg-
ister 'f' (default). If ’a’ is 0, the
Access Ba nk will be se lec ted. If ’a
is 1, the BSR will not be overridden
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:ADDWF REG, 0, 0
Before Instruction
WREG = 0x17
REG = 0xC2
After Instruction
WREG = 0xD9
REG = 0xC2
PIC18CXX2
DS39026B-page 198 Preliminary 7/99 Microchip Technology Inc.
ADDWFC ADD WREG and Carry bit to f
Syntax: [
label
] ADDWFC f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (WREG) + (f) + (C) des t
Status Affected: N,OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Description: Ad d WREG, the C arry Flag an d data
memory location ’f’. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in data memory
location 'f'. If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
BSR will not be overridden.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:ADDWFC REG, 0, 1
Before Instruction
Carry bit= 1
REG = 0x02
WREG = 0x4D
After Instruction
Carry bit= 0
REG = 0x02
WREG = 0x50
ANDLW AND literal with WREG
Syntax: [
label
] ANDLW k
Operands: 0 k 255
Operation: (WREG) .AND. k WREG
Status Affected: N,Z
Encoding: 0000 1011 kkkk kkkk
Description: The co ntents of WREG are AND’ed
with th e 8 -bit literal ' k '. The resu lt i s
placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
’k’ Proc ess
Data Write to
WREG
Example:ANDLW 0x5F
Before Instruction
WREG = 0xA3
After Instruction
WREG = 0x03
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 199
ANDWF AND WREG with f
Syntax: [
label
] ANDWF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (WREG) .AND. (f) dest
Status Affected: N,Z
Encoding: 0001 01da ffff ffff
Description: The contents of WREG are AND’e d
with register 'f'. If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank w ill be se lected. If ’a’ is 1, the
BSR will not be overridden
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:ANDWF REG, 0, 0
Before Instruction
WREG = 0x17
REG = 0xC2
After Instruction
WREG = 0x02
REG = 0xC2
BC Branch if Carry
Syntax: [
label
] BC n
Operands: -128 n 127
Operation: if carry bit is ’1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0010 nnnn nnnn
Description: If the Carry bit is ’1’, then the pro-
gram will branch.
The 2s complement number ’2n’ is
added t o th e PC . Since the PC w il l
have incremented to fetch the next
instructio n, the ne w add ress will be
PC+2+2n. This instruction is then
a two-cycle instr uction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jum p: Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data No
operation
Example:HERE BC 5
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 1;
PC = address (HERE+12)
If Carry = 0;
PC = address (HERE+2)
PIC18CXX2
DS39026B-page 200 Preliminary 7/99 Microchip Technology Inc.
BCF Bit Clear f
Syntax: [
label
] BCF f,b,a
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 0 f<b>
Status Affected: None
Encoding: 1001 bbba ffff ffff
Description: Bit 'b' in register 'f' is cleared. If ’a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write
register ’f
Example:BCF FLAG_REG, 7, 0
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
BN Branch if Negative
Syntax: [
label
] BN n
Operands: -128 n 127
Operation: if negative bit is ’1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0110 nnnn nnnn
Description: If the Negative bit is ’1’, then the
program will branch.
The 2s complement number ’2n’ is
added t o th e PC . Since the PC w il l
have incremented to fetch the next
instructio n, the ne w add ress will be
PC+2+2n. This instruction is then
a two-cycle instr uction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jum p: Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data No
operation
Example:HERE BN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative= 1;
PC = address (Jump)
If Negative= 0;
PC = address (HERE+2)
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 201
BNC Branch if Not Carry
Syntax: [
label
] BNC n
Operands: -128 n 127
Operation: if carry bit is ’0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0011 nnnn nnnn
Description: If the Carry bit is ’0’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC w il l
have incremented to fetch the next
instructio n, the ne w add ress will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data No
operation
Example:HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 0;
PC = address (Jump)
If Carry = 1;
PC = address (HERE+2)
BNN Branch if Not Negative
Syntax: [
label
] BNN n
Operands: -128 n 127
Operation: if negative bit is ’0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0111 nnnn nnnn
Description: If the Negative bit is ’0’, then the
program will branch.
The 2s complement number ’2n’ is
added t o th e PC . Since the PC w il l
have incremented to fetch the next
instructio n, the ne w add ress will be
PC+2+2n. This instruction is then
a two-cycle instr uction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jum p: Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data No
operation
Example:HERE BNN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative= 0;
PC = address (Jump)
If Negative= 1;
PC = address (HERE+2)
PIC18CXX2
DS39026B-page 202 Preliminary 7/99 Microchip Technology Inc.
BNOV Branch if Not Overflow
Syntax: [
label
] BNOV n
Operands: -128 n 127
Operation: if overflow bit is ’0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0101 nnnn nnnn
Description: If the Overflow bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC w il l
have incremented to fetch the next
instructio n, the ne w add ress will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data No
operation
Example:HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow= 0;
PC = address (Jump)
If Overflow= 1;
PC = address (HERE+2)
BNZ Branch if Not Zero
Syntax: [
label
] BNZ n
Operands: -128 n 127
Operation: if zero bit is ’0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0001 nnnn nnnn
Description: If the Zero bit is ’0’, then the pro-
gram will branch.
The 2s complement number ’2n’ is
added t o th e PC . Since the PC w il l
have incremented to fetch the next
instructio n, the ne w add ress will be
PC+2+2n. This instruction is then
a two-cycle instr uction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jum p: Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data No
operation
Example:HERE BNZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 0;
PC = address (Jump)
If Zero = 1;
PC = address (HERE+2)
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 203
BRA Unconditional Branch
Syntax: [
label
] BRA n
Operands: -1024 n 1023
Operation: (PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2’s complement number
’2n’ to the PC. Since the PC will
have incremented to fetch the next
instructio n, the ne w add ress will be
PC+2+2 n. This inst ruction is a tw o-
cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example:HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)
BSF Bit Set f
Syntax: [
label
] BSF f,b,a
Operands: 0 f 25 5
0 b 7
a [0,1]
Operation: 1 f<b>
Status Affected: None
Encoding: 1000 bbba ffff ffff
Description: Bit 'b' in register 'f' is set. If ’a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1,
then the bank will be selected as
per the BSR value.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write
register ’f’
Example:BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG= 0x0A
After Instruction
FLAG_REG= 0x8A
PIC18CXX2
DS39026B-page 204 Preliminary 7/99 Microchip Technology Inc.
BTFSC Bit Test File, Skip if Clear
Syntax: [
label
] BTFSC f,b,a
Operands: 0 f 255
0 b 7
a [0,1]
Operation: skip if (f<b> ) = 0
Status Affected: None
Encoding: 1011 bbba ffff ffff
Description: If bit 'b' in register ’f' is 0, then the
next instruction is skipped .
If bit 'b' is 0, then the next instruction
fetche d d uring th e c urre nt i nstructio n
execution is discarde d, and a NOP is
executed instead, making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1, then
the bank will be selected as per the
BSR v al ue (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-w ord ins tructio n
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)
BTFSS Bit Test File, Skip if Set
Syntax: [
label
] BTFSS f,b,a
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: skip if (f<b>) = 1
Status Affected: None
Encoding: 1010 bbba ffff ffff
Desc ription: If bit 'b' in reg ister 'f' is 1 then the ne xt
instruction is skipped.
If bit 'b' is 1, then the next instruction
fe tched during the current instruc-
tion execution, is discarded and an
NOP is exe cu ted instead , ma king th is
a tw o-cycle i nstructio n. If ’a’ is 0, t he
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1, then
the bank will be selected as per the
BSR val ue (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 205
BTG Bit Toggle f
Syntax: [
label
] BTG f,b,a
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: (f<b>) f<b>
Status Affected: None
Encoding: 0111 bbba ffff ffff
Description: Bit ’b’ in data memory location ’f’ is
inverted. If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write
register ’f’
Example:BTG PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [0x75]
After Instruction:
PORTC = 0110 0101 [0x65]
BOV Branch if Overflow
Syntax: [
label
] BOV n
Operands: -128 n 127
Operation: if overflow bit is ’1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0100 nnnn nnnn
Description: If the Overflow bit is ’1’, then the
program will branch.
The 2s complement number ’2n’ is
added t o th e PC . Since the PC w il l
have incremented to fetch the next
instructio n, the ne w add ress will be
PC+2+2n. This instruction is then
a two-cycle instr uction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jum p: Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data No
operation
Example:HERE BOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow= 1;
PC = address (Jump)
If Overflow= 0;
PC = address (HERE+2)
PIC18CXX2
DS39026B-page 206 Preliminary 7/99 Microchip Technology Inc.
BZ Branch if Zero
Syntax: [
label
] BZ n
Operands: -128 n 127
Operation: if Zero bit is ’1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0000 nnnn nnnn
Description: If the Zero bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC w il l
have incremented to fetch the next
instructio n, the ne w add ress will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
’n’ Process
Data No
operation
Example:HERE BZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 1;
PC = address (Jump)
If Zero = 0;
PC = address (HERE+2)
CALL Subroutine Call
Syntax: [
label
] CALL k,s
Operands: 0 k 1048575
s [0,1]
Operation: (PC) + 4 TOS,
k PC<20:1>,
if s = 1
(WREG) WS,
(STATUS) STATUSS,
(BSR) BSRS
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111 110s
k19kkk k7kkk
kkkk kkkk0
kkkk8
Description: Subroutine call of entire 2M byte
memory range. First, return
address (PC+ 4) is pushe d onto the
return stack. If ’s’ = 1, the W, STA-
TUS and BSR registers are also
pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If 's' = 0, no update
occu rs (default). Then the 20-bit
value ’k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
’k’<7:0>, Push PC to
stack Read literal
’k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example:HERE CALL THERE,1
Before Instruction
PC = Address(HERE)
After Instruction
PC = Address(THERE)
TOS = Address (HERE + 4)
WS = WREG
BSRS= BSR
STATUSS = STATUS
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 207
CLRF Clear f
Syntax: [
label
] CLRF f,a
Operands: 0 f 255
a [0,1]
Operat ion: 000h f
1 Z
Status Affected: Z
Encoding: 0110 101a ffff ffff
Desc ription: Clears th e contents of the spec ified
registe r . If ’a’ is 0 , the Access Bank
will b e selected, o ve rriding the BS R
value. If ’a’ = 1, then the bank will
be select ed as per the BSR v a lue
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write
register ’f’
Example:CLRF FLAG_REG,1
Before Instruction
FLAG_REG = 0x5A
After Instruction
FLAG_REG = 0x00
CLRWDT Clear Watchdog Tim er
Syntax: [
label
] CLRWDT
Operands: None
Operation: 000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data No
operation
Example:CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter = 0x00
WDT Postscaler = 0
TO =1
PD =1
PIC18CXX2
DS39026B-page 208 Preliminary 7/99 Microchip Technology Inc.
COMF Complement f
Syntax: [
label
] COMF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: dest
Status Affected: N,Z
Encoding: 0001 11da ffff ffff
Description: The contents of register ’f’ are com-
plemented. If ’d’ is 0 the result is
stored in WREG. If d’ is 1 th e result
is stored back in register ’f’
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR v al ue (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:COMF REG, 0, 0
Before Instruction
REG = 0x13
After Instruction
REG = 0x13
WREG = 0xEC
(f)
CPFSEQ Compare f with WREG, skip if f =
WREG
Syntax: [
label
] CPFSEQ f,a
Operands: 0 f 255
a [0,1]
Operation: (f) – (WREG),
skip if (f) = (WREG)
(unsign ed comparison)
Status Affected: None
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsign ed subtr ac tio n.
If 'f' = WREG, then the fetched
instruc tion is d iscar ded a nd an NOP
is executed instead making this a
two - cycle instructi on. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
WREG = ?
REG = ?
After Instruction
If REG = WREG;
PC = Address (EQUAL)
If REG WREG;
PC = Address (NEQUAL)
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 209
CPFSGT Compar e f with WREG, sk ip i f f >
WREG
Syntax: [
label
] CPFSGT f,a
Operands: 0 f 255
a [0,1]
Operation: (f) − (WREG),
skip if (f) > (WREG)
(unsigned comparison)
Status Affected: None
Encoding: 0110 010a ffff ffff
Description: Compares the contents of data
memory location ’f’ to the contents
of the WREG by performing an
unsign ed subtrac t io n.
If the contents of ’f ’ a re g reater than
the contents of , then the fetched
instruction is discarded and a NOP
is executed instead making this a
two - cycle instructi on. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1,
then the bank will be selected as
per the BSR v alue (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-w ord ins tructio n
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC = Address (HERE)
WREG = ?
After Instruction
If REG > WREG;
PC = Address (GREATER)
If REG WREG;
PC = Address (NGREATER)
CPFSLT Compare f with WREG, skip if f <
WREG
Syntax: [
label
] CPFSLT f,a
Operands: 0 f 25 5
a [0,1]
Operation: (f) – (WREG),
skip if (f) < (WREG)
(unsign ed comparison)
Status Affected: None
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsign ed subtr ac tio n.
If the contents of 'f' are less than
the contents of WREG, then the
f etched in struct ion is disc arded and
a NOP is executed instead making
this a two-cycle instruction. If ’a’ is
0, the Access Bank will be
selec ted. I f a’ is 1 the BSR will no t
be overridden (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSLT REG, 1
NLESS :
LESS :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG < WREG;
PC = Address (LESS)
If REG WREG;
PC = Address (NLESS)
PIC18CXX2
DS39026B-page 210 Preliminary 7/99 Microchip Technology Inc.
DAW Decimal Adjust WREG Register
Syntax: [
label
] DAW
Operands: None
Operat ion: If [WREG<3:0> >9] or [DC = 1]
then
(WREG<3:0>) + 6 WREG <3:0>;
else
(WREG<3:0>) WREG<3:0>;
If [WREG<7:4> >9] or [C = 1] then
(WREG<7:4>) + 6 WREG<7:4>;
else
(WREG<7:4>) WREG<7:4>;
Status Affected: C
Encoding: 0000 0000 0000 0111
Description: DAW adjusts the eight bit value in
WREG resulting from the earlier
addition of two variables (each in
packed BCD format) and produces
a corr ect packed BCD result.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register
WREG
Process
Data Write
WREG
Example1:DAW
Before Instruction
WREG = 0xA5
C=0
DC = 0
After Instruction
WREG = 0x05
C=1
DC = 0
Example 2:
Before Instruction
WREG = 0xCE
C=0
DC = 0
After Instruction
WREG = 0x34
C=1
DC = 0
DECF Decrement f
Syntax: [
label
] DECF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest
Status Affected: C,DC,N,OV,Z
Encoding: 0000 01da ffff ffff
Description: Decre ment regist er 'f'. If ' d' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR val ue (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:DECF CNT, 1, 0
Before Instruction
CNT = 0x01
Z=0
After Instruction
CNT = 0x00
Z=1
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 211
DECFSZ Decrement f, skip if 0
Syntax: [
label
] DECFSZ f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if resu lt = 0
Status Affected: None
Encoding: 0010 11da ffff ffff
Description: The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is pla ce d back in registe r 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOP is executed
instead making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR v al ue (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-w ord ins tructio n
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE DECFSZ CNT, 1, 1
GOTO LOOP
CONTINUE
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT - 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT 0;
PC = Address (HERE+2)
DCFSNZ Decrement f, skip if not 0
Syntax: [
label
] DCFSNZ f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 11da ffff ffff
Description: The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOP is
executed instead making it a two-
cycle instruction. If ’a’ is 0, the
Acce ss Ban k wil l be se lected , o v er-
riding the BSR value. If ’a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE DCFSNZ TEMP, 1, 0
ZERO :
NZERO :
Before Instruction
TEMP = ?
After Instruction
TEMP = TEMP - 1,
If TEMP = 0;
PC = Address (ZERO)
If TEMP 0;
PC = Address (NZERO)
PIC18CXX2
DS39026B-page 212 Preliminary 7/99 Microchip Technology Inc.
GOTO Unconditional Branch
Syntax: [
label
] GOTO k
Operands: 0 k 1048575
Operation: k PC<20:1>
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111 1111
k19kkk k7kkk
kkkk kkkk0
kkkk8
Description: GOTO allows an unconditional
branch anywhere within entire 2M
byte memory range. The 20-bit
value ’k’ is loaded into PC<20:1>.
GOTO is always a two-cycle instruc-
tion.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
’k’<7:0>, No
operation Read literal
’k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example:GOTO THERE
After Instruction
PC = Address (THERE)
INCF Increment f
Syntax: [
label
] INCF f,d,a
Operands: 0 f 25 5
d [0,1]
a [0,1]
Operation: (f) + 1 dest
Status Affected: C,DC,N,OV,Z
Encoding: 0010 10da ffff ffff
Description: The contents of registerf’ are
incremented. If ’d’ is 0, the result is
placed in WREG. If ’d is 1, the
result is placed back in register ’f’
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR val ue (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:INCF CNT, 1, 0
Before Instruction
CNT = 0xFF
Z=0
C=?
DC = ?
After Instruction
CNT = 0x00
Z=1
C=1
DC = 1
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 213
INCFSZ Increment f, skip if 0
Syntax: [
label
] INCFSZ f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if resu lt = 0
Status Affected: None
Encoding: 0011 11da ffff ffff
Description: The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in WREG. If ’dis 1, the
result is pla ce d back in registe r ’f’.
(default)
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOP is executed
instead making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR v al ue (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-w ord ins tructio n
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE INCFSZ CNT, 1, 0
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address(ZERO)
If CNT 0;
PC = Address(NZERO)
INFSNZ Increment f, skip if not 0
Syntax: [
label
] INFSNZ f,d,a
Operands: 0 f 25 5
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 10da ffff ffff
Description: The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOP is
executed instead making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE INFSNZ REG, 1, 0
ZERO
NZERO
Before Instruction
PC = Address (HERE)
After Instruction
REG = REG + 1
If REG 0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)
PIC18CXX2
DS39026B-page 214 Preliminary 7/99 Microchip Technology Inc.
IORLW Inclusive OR literal with WREG
Syntax: [
label
] IORLW k
Operands: 0 k 255
Operation: (WREG) .OR. k WREG
Status Affected: N,Z
Encoding: 0000 1001 kkkk kkkk
Description: The contents of WREG are OR’ed
with the eight bit literal 'k'. The
result is placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ’k’ Process
Data Write to
WREG
Example:IORLW 0x35
Before Instruction
WREG = 0x9A
After Instruction
WREG = 0xBF
IORWF Inclusive OR WREG with f
Syntax: [
label
] IORWF f,d,a
Operands: 0 f 25 5
d [0,1]
a [0,1]
Operation: (WREG) .OR. (f) dest
Status Affected: N,Z
Encoding: 0001 00da ffff ffff
Description: Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:IORWF RESULT, 0, 1
Before Instruction
RESULT = 0x13
WREG = 0x91
After Instruction
RESULT = 0x13
WREG = 0x93
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 215
LFSR Load FSR
Syntax: [
label
] LFSR f,k
Operands: 0 f 2
0 k 4095
Operation: k FSRf
Status Affected: None
Encoding: 1110
1111 1110
0000 00ff
k7kkk k11kkk
kkkk
Desc ription : The 12-bit liter al k’ is l oad ed i nto
the file select register pointed to
by ’f’
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
’k ’ M SB Process
Data Write
literal ’k’
MSB to
FSRfH
Decode Read literal
’k’ LSB Process
Data Wr ite literal
’k’ to FSRfL
Example:LFSR 2, 0x3AB
After Instruction
FSR2H = 0x03
FSR2L = 0xAB
MOVF Move f
Syntax: [
label
] MOVF f,d,a
Operands: 0 f 25 5
d [0,1]
a [0,1]
Operation: f dest
Status Affected: N,Z
Encoding: 0101 00da ffff ffff
Description: The conten ts of regi ster ’ f’ is m ov ed
to a destination dependent upon
the status of ’d’. If ' d' i s 0, the resu lt
is placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). Location 'f' can be any-
where in the 2 56 b yte bank. If ’a’ i s
0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Writ e
WREG
Example:MOVF REG, 0, 0
Before Instruction
REG = 0x22
WREG = 0xFF
After Instruction
REG = 0x22
WREG = 0x22
PIC18CXX2
DS39026B-page 216 Preliminary 7/99 Microchip Technology Inc.
MOVFF Move f to f
Syntax: [
label
] MOVFF fs,fd
Operands: 0 fs 4095
0 fd 4095
Operation: (fs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.) 1100
1111 ffff
ffff ffff
ffff ffffs
ffffd
Description: The contents of source register ’fs
are moved to destination register
’fd. Location of source ’fs’ can be
anywhere in the 4096 byte data
space (000h to FFFh) , and l ocati on
of destin ation ’fdcan also be any-
where from 000h to FFFh.
Either so urc e or de st ination ca n be
WREG (a usef ul spe ci al si tuation).
MOVFF is particularly useful for
transf erring a data memory location
to a peripher al register (such as the
transmit buffer or an I/O port).
The MOVFF instruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register
Words: 2
Cycles: 2 (3)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’
(src)
Process
Data No
operation
Decode No
operation
No dummy
read
No
operation Write
register ’f
(dest)
Example:MOVFF REG1, REG2
Before Instruction
REG1 = 0x33
REG2 = 0x11
After Instruction
REG1 = 0x33,
REG2 = 0x33
MOVLB Move literal to low nibble in BSR
Syntax: [
label
] MOVLB k
Operands: 0 k 255
Operat ion: k BSR
Status Affected: None
Encoding: 0000 0001 kkkk kkkk
Description: The 8-bit literal ’k’ is loaded into
the Bank Select Register (BSR).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
’k’ Proc ess
Data Write
lit eral ’k’ to
BSR
Example:MOVLB 5
Before Instruction
BSR register= 0x02
After Instruction
BSR register= 0x05
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 217
MOVLW Move literal to WREG
Syntax: [
label
] MOVLW k
Operands: 0 k 255
Operation: k WREG
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Desc ription : The eight bi t li teral ’k’ is loade d i nto
WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ’k’ Process
Data Write to
WREG
Example:MOVLW 0x5A
After Instruction
WREG = 0x5A
MOVWF Move WREG to f
Syntax: [
label
] MOVWF f,a
Operands: 0 f 25 5
a [0,1]
Operation: (WREG) f
Status Affected: None
Encoding: 0110 111a ffff ffff
Description: Move data from WREG to register
f’. Location ’f’ can be anywhere in
the 256 byte bank. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write
register ’f’
Example:MOVWF REG, 0
Before Instruction
WREG = 0x4F
REG = 0xFF
After Instruction
WREG = 0x4F
REG = 0x4F
PIC18CXX2
DS39026B-page 218 Preliminary 7/99 Microchip Technology Inc.
MULLW Multiply Literal with WREG
Syntax: [
label
] MULLW k
Operands: 0 k 255
Operation: (W REG) x k PRODH:PRODL
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Desc ription : An unsig ned m u lti pli ca tion is c ar-
ried out between the contents of
WREG and the 8-bit literal ’k’.
The 16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
WREG is unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possib le in this opera-
tion. A zero result is possible but
not detected.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ’k’ Process
Data Write
registers
PRODH:
PRODL
Example:MULLW 0xC4
Before Instruction
WREG = 0xE2
PRODH = ?
PRODL = ?
After Instruction
WREG = 0xE2
PRODH = 0xAD
PRODL = 0x08
MULWF Multiply WREG with f
Syntax: [
label
] MULWF f,a
Operands: 0 f 255
a [0,1]
Operation: (WREG) x (f) PR ODH:PR ODL
Status Affected: None
Encoding: 0000 001a ffff ffff
Description: An unsigned m u ltiplicat ion is c ar-
ried out between the contents of
WREG and the register file loca-
tion ’ f’. The 16-bit result is st ored
in the PRODH:PRODL register
pair. PRODH contains the high
byte.
Both WREG and ’f’ are
unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is po ssible in this opera-
tion. A z ero resu lt i s po ss ible but
not detected. If ’a’ is 0, the
Access Bank will be selecte d,
ov erridin g the BSR v al ue. If ’a’ =
1, then the bank will be selected
as per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write
registers
PRODH:
PRODL
Example:MULWF REG, 1
Before Instruction
WREG = 0xC4
REG = 0xB5
PRODH = ?
PRODL = ?
After Instruction
WREG = 0xC4
REG = 0xB5
PRODH = 0x8A
PRODL = 0x94
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 219
NEGF Negate f
Syntax: [
label
] NEGF f,a
Operands: 0 f 255
a [0,1]
Operation: ( f ) + 1 f
Status Affected: N,OV, C, DC, Z
Encoding: 0110 110a ffff ffff
Description: Location ’f’ is negated using twos
complement. The result is placed in
the d ata memory locatio n 'f'. If ’a’ i s
0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write
register ’f’
Example:NEGF REG, 1
Before Instruction
REG = 0011 1010 [0x3A]
After Instruction
REG = 1100 0110 [0xC6]
NOP No Operation
Syntax: [
label
] NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 0000
1111 0000
xxxx 0000
xxxx 0000
xxxx
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
Example:
None.
PIC18CXX2
DS39026B-page 220 Preliminary 7/99 Microchip Technology Inc.
POP Pop Top of Return Stack
Syntax: [
label
] POP
Operands: None
Operation: (T OS) bit bucket
Status Affected: None
Encoding: 0000 0000 0000 0110
Description: The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the previ-
ous v alu e that w as pu shed ont o the
return stack.
This instruction is provided to
enab le the user to properly manage
the return stack to incorporate a
software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation PO P TOS
value No
operation
Example:POP
GOTO NEW
Before Instruction
TOS = 0031A2h
Stack (1 level down)= 014332h
After Instruction
TOS = 014332h
PC = NEW
PUSH Push Top of Return Stack
Syntax: [
label
] PUSH
Operands: None
Operation: (PC+2) TOS
Status Affected: None
Encoding: 0000 0000 0000 0101
Description: The PC+2 is pus hed onto the top of
the return stac k. The pr e vious T OS
value is pushed down on the stack.
This instruction allows to implement
a sof tware stac k by modifyin g T OS,
and then push it onto the return
stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode PUSH PC+2
on to re tu rn
stack
No
operation No
operation
Example:PUSH
Before Instruction
TOS = 00345Ah
PC = 000124h
After Instruction
PC = 000126h
TOS = 000126h
Stack (1 level down)= 00345Ah
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 221
RCALL Relative Call
Syntax: [
label
] RCALL n
Operands: -1024 n 1023
Operat ion: ( PC) + 2 TOS,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 1nnn nnnn nnnn
Description: Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ’2n’ to the PC.
Since the PC will hav e incremen ted
to fetch the next instruction, the
ne w addres s will be PC+2+2n.
This instruction is a two-cycle
instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
’n’
Push PC to
stack
Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example:HERE RCALL Jump
Before Instruction
PC = Address(HERE)
After Instruction
PC = Address(Jump)
TOS = Address (HERE+2)
RESET Reset
Syntax: [
label
] RESET
Operands: None
Operation: Reset all registers and flags that
are affected by a MCLR reset.
Status Affected: All
Encoding: 0000 0000 1111 1111
Description: This instruction provides a way to
execute a MCLR reset in software.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Start
reset No
operation No
operation
Example:RESET
After Instruction
Registers= Reset Value
Flags* = Reset Value
PIC18CXX2
DS39026B-page 222 Preliminary 7/99 Microchip Technology Inc.
RETFIE Return from Interrupt
Syntax: [
label
] RETFIE s
Operands: s [0,1]
Operation: (T OS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) WREG,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH,PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from Interrupt. Stack is
popped and Top of Stack (TOS) is
loade d into the PC. Interrupts are
enabled by setting the either the
high or low pr ior i ty gl obal inte r-
rup t enable bi t. If ’s’ = 1, the con -
tents of the shadow registers WS,
STAT USS an d BSR S are lo aded
into the ir corr esponding registers ,
WREG, STATUS and BSR. If ’s’ =
0, no update of these registers
occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation pop PC from
stack
Set GIEH or
GIEL
No
operation No
operation No
operation No
operation
Example:RETFIE 1
After Interrupt
PC = TOS
W=WS
BSR = BSRS
STATUS = STATUSS
GIE/GIEH, PEIE/GIEL= 1
RETLW Return Literal to WREG
Syntax: [
label
] RETLW k
Operands: 0 k 255
Operation: k WREG,
(TOS) PC,
PCLATU, PCLATH are u nchanged
Status Affected: None
Encoding: 0000 1100 kkkk kkkk
Description: WREG is loaded with the eight bit
literal 'k'. The program counter is
loaded from the top of the stack
(the return address). The high
address latch (PCLATH) remains
unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ’k’ Process
Data pop PC from
stack, Write
to WREG
No
operation No
operation No
operation No
operation
Example:
CALL TABLE ; WREG contains table
; offset value
; WREG now has
; table value
:
TABLE
ADDWF PCL ; WREG = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
WREG = 0x07
After Instruction
WREG = value of kn
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 223
RETURN Return from Subroutine
Syntax: [
label
] RETURN s
Operands: s [0,1]
Operation: (T OS) PC,
if s = 1
(WS) WREG,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The
stack is popped and the top of the
stack (TOS) is loaded into the
program co unte r. If ’s’ = 1, the
conten ts o f t h e sh ad ow re gist e rs
WS, STATUSS and BSRS are
loaded into thei r cor respon ding
regi sters, WR EG, STAT US and
BSR. If ’s’ = 0, no upda te of
these registers occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data pop PC from
stack
No
operation No
operation No
operation No
operation
Example:RETURN
After Interrupt
PC = TOS
RLCF Rotate Left f through Carry
Syntax: [
label
] RLCF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n+1>,
(f<7>) C,
(C) dest<0>
Status Affected: C,N,Z
Encoding: 0011 01da ffff ffff
Description: The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If ' d' is 0 the resu lt is
placed in WREG. If 'd' is 1 the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:RLCF REG, 0, 0
Before Instruction
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
WREG = 1100 1100
C=1
Cregister f
PIC18CXX2
DS39026B-page 224 Preliminary 7/99 Microchip Technology Inc.
RLNCF Rotate Left f (no carry)
Syntax: [
label
] RLNCF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n+1>,
(f<7>) dest<0>
Status Affected: N,Z
Encoding: 0100 01da ffff ffff
Description: The contents of register ’f’ are
rotated one bit to the left. If ’d’ is 0
the result is placed in WREG. Ifd’
is 1, the res ult is s to r ed b ack in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:RLNCF REG, 1, 0
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
register f
RRCF Rotate Right f through Carry
Syntax: [
label
] RRCF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n-1>,
(f<0>) C,
(C) dest<7>
Status Affected: C,N,Z
Encoding: 0011 00da ffff ffff
Description: The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, then the
bank will be selected as per the
BSR val ue (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:RRCF REG, 0, 0
Before Instruction
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
WREG = 0111 0011
C=0
Cregister f
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 225
RRNCF Rotate Right f (no carry)
Syntax: [
label
] RRNCF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n-1>,
(f<0>) dest<7>
Status Affected: N,Z
Encoding: 0100 00da ffff ffff
Description: The contents of register ’f’ are
rotated on e bit to the right. If ’d ’ is 0,
the result is placed in WREG. If ’d’
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR v alue (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example 1:RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2:RRNCF REG, 0, 0
Before Instruction
WREG = ?
REG = 1101 0111
After Instruction
WREG = 1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: [
label
] SETF f,a
Operands: 0 f 25 5
a [0,1]
Operation: FFh f
Status Affected: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write
register ’f’
Example:SETF REG,1
Before Instruction
REG = 0x5A
After Instruction
REG = 0xFF
PIC18CXX2
DS39026B-page 226 Preliminary 7/99 Microchip Technology Inc.
SLEEP Enter SLEEP mode
Syntax: [
label
]SLEEP
Operands: None
Operation: 00h WDT,
0 WDT postscaler,
1 TO,
0 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0011
Description : The po wer-do wn status bit (PD ) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its postsc aler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data Go to
sleep
Example:SLEEP
Before Instruction
TO =?
PD =?
After Instruction
TO =1 †
PD =0
† If WDT causes wake-up, this bit is cleared
SUBFWB Subtract f from WREG with
borrow
Syntax: [
label
]SUBFWB f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operat ion: (WREG) – (f) – (C) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0101 01da ffff ffff
Description: Subtract register 'f' and carry flag
(borrow) fro m WREG (2’s comple-
ment m ethod). If ' d' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored in register ' f'
(default) . If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR v alue . If ’a’ i s 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 227
SUBFWB
Example 1:SUBFWB REG, 1, 0
Before Instruction
REG = 3
WREG = 2
C=1
After Instruction
REG = FF
WREG = 2
C=0
Z=0
N = 1 ; result is negative
Example 2:SUBFWB REG, 0, 0
Before Instruction
REG = 2
WREG = 5
C=1
After Instruction
REG = 2
WREG = 3
C=1
Z=0
N = 0 ; result is positive
Example 3:SUBFWB REG, 1, 0
Before Instruction
REG = 1
WREG = 2
C=0
After Instruction
REG = 0
WREG = 2
C=1
Z = 1 ; result is zero
N=0
SUBLW Subtract WREG from literal
Syntax: [
label
]SUBLW k
Operands: 0 k 255
Operation: k – ( WREG) WREG
Status Affected: N,OV, C, DC, Z
Encoding: 0000 1000 kkkk kkkk
Description: WREG is subtracted from the
eight bit literal 'k'. The result is
placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ’k’ Process
Data Write to
WREG
Example 1: SUBLW 0x02
Before Instruction
WREG = 1
C=?
After Instruction
WREG = 1
C = 1 ; result is positive
Z=0
N=0
Example 2:SUBLW 0x02
Before Instruction
WREG = 2
C=?
After Instruction
WREG = 0
C = 1 ; result is zero
Z=1
N=0
Example 3:SUBLW 0x02
Before Instruction
WREG = 3
C=?
After Instruction
WREG = FF ; (2’s complement)
C = 0 ; result is negative
Z=0
N=1
PIC18CXX2
DS39026B-page 228 Preliminary 7/99 Microchip Technology Inc.
SUBWF Subtract WREG from f
Syntax: [
label
]SUBWF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (WREG) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0101 11da ffff ffff
Description: Subtract WREG from register 'f'
(2’s complement method). If 'd' is
0, the result is stored in WREG. If
'd' is 1, t he resul t is s tore d back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected,
overr iding the BSR value. If ’a’ is
1, then the bank will be selected
as per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
SUBWF Subtract WREG from f (cont’d)
Example 1:SUBWF REG, 1, 0
Before Instruction
REG = 3
WREG = 2
C=?
After Instruction
REG = 1
WREG = 2
C = 1 ; result is positive
Z=0
N=0
Example 2:SUBWF REG, 0, 0
Before Instruction
REG = 2
WREG = 2
C=?
After Instruction
REG = 2
WREG = 0
C = 1 ; result is zero
Z=1
N=0
Example 3:SUBWF REG, 1, 0
Before Instruction
REG = 1
WREG = 2
C=?
After Instruction
REG = FFh ;(2’s complement)
WREG = 2
C = 0 ; result is negative
Z=0
N=1
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 229
SUBWFB Subtract WREG from f with
Borrow
Syntax: [
label
]SUBWFB f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (WREG) – (C) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0101 10da ffff ffff
Description: Subtract WREG and the carry flag
(borrow) from register 'f' (2’s com-
plement method). If 'd' is 0, the
result is stored in WREG. If 'd' is
1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected,
overr iding the BSR value. If ’a’ is
1, then the bank will be selected
as per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
SUBWFB Subtract WREG from f with
Borrow (cont’d)
Example 1:SUBWFB REG, 1, 0
Before Instruction
REG = 0x19 (0001 1001)
WREG = 0x0D (0000 1101)
C=1
After Instruction
REG = 0x0C (0000 1011)
WREG = 0x0D (0000 1101)
C=1
Z=0
N = 0 ; result is positive
Example2: SUBWFBREG, 0, 0
Before Instruction
REG = 0x1B (0001 1011)
WREG = 0x1A (0001 1010)
C=0
After Instruction
REG = 0x1B (0001 1011)
WREG = 0x00
C=1
Z = 1 ; result is zero
N=0
Example3: SUBWFBREG, 1, 0
Before Instruction
REG = 0x03 (0000 0011)
WREG = 0x0E (0000 1101)
C=1
After Instruction
REG = 0xF5 (1111 0100) [2’s
comp]
WREG = 0x0E (0000 1101)
C=0
Z=0
N = 1 ; result is negative
PIC18CXX2
DS39026B-page 230 Preliminary 7/99 Microchip Technology Inc.
SWAPF Swap f
Syntax: [
label
] SWAPF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<3:0>) dest<7:4>,
(f<7:4>) dest<3 :0>
Status Affected: None
Encoding: 0011 10da ffff ffff
Desc ription : The upper and lower nib bles of reg-
ister ’ f’ are e xchan ged. If ’ d’ is 0, the
result is p lac ed in W R EG. If d’ is 1 ,
the resu lt is pla ce d in regis ter ’f’
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, then the
bank will be selected as per the
BSR v al ue (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example:SWAPF REG, 1, 0
Before Instruction
REG = 0x53
After Instruction
REG = 0x35
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 231
TBLRD Table Read
Syntax: [
label
] TBLRD ( *; *+; *-; +*)
Operands: None
Operation: if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR - No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) +1 TBLPT R;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) -1 TBLPTR;
if TBLRD +*,
(TBLPTR) +1 TBLPT R;
(Prog Mem (TBLPTR)) TABLAT;
Status Affected: None
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the
content s of Prog ram Mem ory (P.M.). To
address the progr am me mory a po inter
called Table Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR ha s a 2 Mbyt e address ran ge.
TBLPTR[0] = 0:Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program
Memory Word
The TBLRD instruction can modify the
value of TBLPTR as follows:
no change
post-increment
post-decrement
pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No
operation
(Read
Program
Memory)
No
operation No
operation
(Write
TABLAT)
TBLRD Table Read (cont’d)
Example1:TBLRD *+ ;
Before Instruction
TABLAT = 0x55
TBLPTR = 0x00A356
MEMORY(0x00A356) = 0x34
After Instruction
TABLAT = 0x34
TBLPTR = 0x00A357
Example2:TBLRD +* ;
Before Instruction
TABLAT = 0xAA
TBLPTR = 0x01A357
MEMORY(0x01A357) = 0x12
MEMORY(0x01A358) = 0x34
After Instruction
TABLAT = 0x34
TBLPTR = 0x01A358
PIC18CXX2
DS39026B-page 232 Preliminary 7/99 Microchip Technology Inc.
TBLWT Table Write
Syntax: [
label
] TBLWT ( *; *+; *-; +*)
Operands: None
Operation: if TBLWT*,
(TABLAT) Prog Mem (TBLPTR) or
Holding Re gister ;
TBLPTR - No Change;
if TBLWT*+,
(TABLAT) Prog Mem (TBLPTR) or
Holding Re gister ;
(TBLPTR) +1 TBLPTR;
if TBLWT*-,
(TABLAT) Prog Mem (TBLPTR) or
Holding Re gister ;
(TBLPTR) -1 TBLPTR;
if TBLWT+*,
(TBLPTR) +1 TBLPTR;
(TABLAT) Prog Mem (TBLPTR) or
Holding Re gister ;
Status Affected: None
Encoding: 0000 0000 0000 11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Desc ription : This inst ruction is used to p rogram the
contents of Program Memory (P.M.).
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 MBtye address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
TBLPTR[0] = 0:Least Significant
Byte of Progr am
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Progr am
Memory Word
The TBL WT instruction can m odify the
value of TBLPTR as follows:
no change
post-increment
post-decrement
pre-increment
Words: 1
Cycles: 2 (many if long write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No
operation
(Read
TABLAT)
No
operation No
operation
(Write to Holding
Register or Memory)
TBLWT Table Write (cont.’d)
Example1:TBLWT *+;
Before Instruction
TABLAT = 0x55
TBLPTR = 0x00A356
MEMORY(0x00A356) = 0xFF
After Instructions (table write completion)
TABLAT = 0x55
TBLPTR = 0x00A357
MEMORY(0x00A356) = 0x55
Example 2:TBLWT +*;
Before Instruction
TABLAT = 0x34
TBLPTR = 0x01389A
MEMORY(0x01389A) = 0xFF
MEMORY(0x01389B) = 0xFF
After Instruction (table wr ite completion)
TABLAT = 0x34
TBLPTR = 0x01389B
MEMORY(0x01389A) = 0xFF
MEMORY(0x01389B) = 0x34
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 233
TSTFSZ Test f, skip if 0
Syntax: [
label
] TSTFSZ f,a
Operands: 0 f 255
a [0,1]
Operat ion: skip if f = 0
Status Affected: None
Encoding: 0110 011a ffff ffff
Description: If ’f’ = 0, the next instruction,
fetched during the current instruc-
tion execution, is discarded and a
NOP is executed making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR v alue (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-w ord ins tructio n
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE TSTFSZ CNT, 1
NZERO :
ZERO :
Before Instruction
PC = Address(HERE)
After Instruction
If CNT = 0x00,
PC = Address (ZERO)
If CNT 0x00,
PC = Address (NZERO)
XORLW Exclusive OR literal with WREG
Syntax: [
label
]XORLW k
Operands: 0 k 255
Operation: (WREG) .XOR. k WREG
Status Affected: N,Z
Encoding: 0000 1010 kkkk kkkk
Description: The contents of WREG are
XOR’ed with the 8-bit literal 'k'.
The result is placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ’k’ Process
Data Write to
WREG
Example:XORLW0xAF
Before Instruction
WREG = 0xB5
After Instruction
WREG = 0x1A
PIC18CXX2
DS39026B-page 234 Preliminary 7/99 Microchip Technology Inc.
XORWF Exclusive OR WREG with f
Syntax: [
label
] XORWF f,d,a
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (WREG) .XOR. (f) dest
Status Affected: N,Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of
WREG with registerf. If ’d’ is 0, the
result is stored in WREG. If ’d’ is 1,
the result is stored back in the reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ’f’ Process
Data Write to
destination
Example: XORWF REG, 1, 0
Before Instruction
REG = 0xAF
WREG = 0xB5
After Instruction
REG = 0x1A
WREG = 0xB5
1999 Microchip Technology Inc. Preliminary DS39026B-page 235
PIC18CXX2
20.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full r an ge of hardw are and softw are d e velopment to ols:
Integrated Development Environment
- MPLAB™ IDE Software
Assemblers/Compilers/Linkers
- MPASM Assembler
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
Simulators
- MPLAB-SIM Software Simulator
•Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circui t
Emulator
-ICEPIC™
In-Circuit Debugger
- MPLAB-ICD for PIC16F877
Device Programmers
-PRO MATE
II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- SEEVAL
-KEELOQ
20.1 MPLAB Integrated Development
Environment Software
- The MPLAB IDE software brings an ease of
software development previously unseen in
the 8-bit micr ocontroller market. MPLAB is a
Windows-based application which contains:
Multiple functionality
-editor
- simulator
- programmer (sold separately)
- emulator (sold separately)
A full featured editor
A project manager
Customizable tool bar and key mapping
A status bar
On-line help
MPLAB allows you to:
Edit your source files (either assembly or ‘C’)
One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
proje ct information)
Debug using:
- source files
- absolute listing file
- object co de
The ability to use MPLAB with Microchips simulator,
MPLAB-SIM, allo ws a c on si ste nt pl atform and the abi l-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
20.2 MPASM Assembler
MPASM is a ful l f eatured univ ersal m acro assemb ler f or
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
MPASM has a command line interface and a Windows
shell and c an be u sed a s a stand alone appli catio n o n a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which con tains so urce li nes an d gen-
erated machine code, and a COD file for MPLAB
debugging.
MPASM fea ture s inc lud e:
MPASM and MPLINK are integrated into MPLAB
projects.
MPASM allows user defined macros to be created
for streamlined assembly.
MPASM allows conditional assembly for multi pur-
pose source files.
MPASM directi ve s allo w comple te control ov er the
assem b l y proces s .
20.3 MPLAB-C17 an d MPLAB-C18
C Compilers
The MPLAB-C 17 and MPLAB -C18 Code De v elop ment
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other co mpi le rs .
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
PIC18CXX2
DS39026B-page 236 Preliminary 1999 Microchip Technology Inc.
20.4 MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file , only the modules that contains
that routine will be linked in with the application. This
allows l arg e li brarie s to b e u se d e ff i cien t l y i n ma ny di f -
ferent applications. MPLIB manages the creation and
modification of library files.
MPLINK features include:
MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
MPLIB features include:
MPLIB makes linking easier bec au se singl e li brar-
ies can be included instead of many smaller files.
MPLIB hel ps k ee p code maintai nab l e b y g roupin g
related modules together.
MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
20.5 MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given in struct ion, th e data areas ca n be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
e xecution can be perf ormed in singl e step, e xecute until
break, or trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
deb ug code outside of the laboratory environment ma k-
ing it an excellent multi-project software development
tool.
20.6 MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
inte nded to provi de t he pr oduc t developm ent en gin eer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive dev el-
opment tools. The PC platf orm an d Microsoft® Windows
3.x/95/98 en vironment were chos en to best make th ese
features available to you, the end user.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, tr igger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
20.7 PICMASTER/PICMAST ER CE
The PICMASTER system from Microchip Technolog y is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
20.8 ICEPIC
ICEPIC is a lo w-cost in-circ uit emula tion solution f o r the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX fam ilies of 8-bit on e-time-
progr amma b le (OTP) microcontrollers. The modula r
system can suppo rt different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeab le persona lity modules or daughter
boards. The em ulator is capable of emulating without
target application circuitry being present.
20.9 MPLAB-ICD In-Circuit Debugger
Microc hip’s In-C ircuit Deb ugger , MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F8 7X. This f eature, alon g with Microchip’ s In-C ir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
de velop and deb ug so urce c ode b y w atc hing variables ,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
1999 Microchip Technology Inc. Preliminary DS39026B-page 237
PIC18CXX2
20.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
ture d programme r capable of operati ng in stand -alo ne
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-al on e m ode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
20.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supp o rts a ll PI Cmicr o devices wi th up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
20.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Microchip’s PIC1 2C5XX, PIC12CE5 XX, an d
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to pro-
vide non-real-time I/O po rt emulation. SIMICE ena bles
a developer to run simulator code for driving the target
system . In addition, the target system can provi de input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
20.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and downl o a d t h e
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
20.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTAR T-P lus , and eas ily test firmware .
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional ha rdware and connectin g it to the mic rocontroll er
soc ket (s). Some of the f eatures include a RS-232 int er-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of th e I2C bu s and separ ate hea ders f or connec -
tion to an LCD module and a keypad.
20.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microc ont roll ers wi th a LCD Mo dul e . All the ne ces -
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PI CDEM -3 bo ar d, on a P RO MATE II pro gram-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional protot ype a rea h as bee n provided to
the us er for adding ha rdware and con necti ng it to the
microcontroller socket(s). Some of the f eatures i nclude
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a k e y pad. Als o pro vide d on th e PICDEM -3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week . The PIC DE M-3 provides an add i-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplex ed LCD signals on a PC . A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
PIC18CXX2
DS39026B-page 238 Preliminary 1999 Microchip Technology Inc.
20.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers, including PIC17C752, PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is incl uded to run bas ic demo prog rams, which are su p-
plied on a 3.5-inch disk. A programmed sample is
includ ed, and the us er ma y eras e it an d prog ram it wi th
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code . In additio n, PICDEM-17 su p-
ports down-loa ding of progr ams to and e xec uting out of
e xt ernal FLASH memory on board. The PICD EM -17 i s
also usab le with th e MPL AB-ICE or PI CMASTER em u-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
20.17 SEEV AL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analy sis a nd relia bility calc ulatio ns . The tota l kit ca n
significantly reduce time-to-market and result in an
optimized system.
20.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microc hips HCS Secure D ata Product s. The HC S ev al-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
1999 Microchip Technology Inc. Preliminary DS39026B-page 239
PIC18CXX2
TABLE 20-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Soft w ar e To ol s
MPLABIntegrated
Develo pm en t Envi ro nm e nt
á
á
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB C17 Compiler
á
á
MPLAB C18 Compiler
á
MPASM/MPLINK
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Emulators
MPLAB™-ICE
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PICMASTER/PICMASTER-CE
á
á
á
á
á
á
á
á
á
á
á
ICEPICLow-Cost
In-Circuit Emulator
á
á
á
á
á
á
á
á
Debugger
MPLAB-ICD In-Circuit Debugger
á
*
á
*
á
Programmers
PICSTARTPlus
Low-Cost Universal Dev. Kit
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PRO MATE II
Universal Programmer
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
á
á
Demo Boards an d Eval Kits
SIMICE
á
á
PICDEM-1
á
á
á
á
á
PICDEM-2
á
á
á
PICDEM-3
á
PICDEM-14A
á
PICDEM-17
á
KEELOQ® Evaluation Kit
á
KEELOQ Transponder Kit
á
microID™ Programmer’s Kit
á
125 kHz microID Developer’s Kit
á
125 kHz Anticollision microID
Developer’s Kit
á
13.56 MHz Anticollision microID
Developer’s Kit
á
MCP2510 CAN Developer’s Kit
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for a vailability date.
Development tool is available on select devices.
PIC18CXX2
DS39026B-page 240 Preliminary 1999 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 241
21.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2)..........................................................................................0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin...........................................................................................................................300 mA
Maximum current into VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20 mA
Maximu m out put current sunk by any I/O pin........... ...... ..... ...... ................. ..... ................. ...... ............ .....................25 mA
Maximu m out put current sourced by an y I/O pin ................ ...... ...... ..... ................. ...... ................ ...... ......................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined) .............................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
Note 2: Voltage s pi kes below V SS at the MCLR/VPP pin, inducin g c urren ts greater than 80 m A , may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin, ra ther
than pulling this pin directly to VSS.
Note 3: PORTD and PORTE n ot available on the PIC18C2X2 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
de vic e. Th is is a s tress r ating o nly and functional oper atio n of the device at thos e or an y other c onditi ons abo v e those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC18CXX2
DS39026B-page 242 Preliminary 7/99 Microchip Technology Inc.
FIGURE 21-1: PIC18CXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
FIGURE 21-2: PIC18LCXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
40 MHz
5.0 V
3.5 V
3.0 V
2.5 V
PIC18CXXX
4.2V
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
40 MHz
5.0 V
3.5 V
3.0 V
2.5 V
PIC18LCXXX
FMAX = (20.0 MHz/V) (VDDAPPMIN - 2.5 V) + 6 MHz
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application
6 MHz
4.2V
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 243
21.1 DC Characteristics: PIC18CXX2 (Industrial, Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
VDD Supply Voltage
D001 4.2 5.5 V
D002 VDR RAM Data Retention
Voltage(1) 1.5 V
D003 VPOR VDD Start Voltage to
ensure internal Power-
on Reset signal
0.7 V See section on Power-on Reset for details
D004 SVDD VDD Rise Rate to
ensure internal Power-
on Reset signal
0.05 V/ms See section on Power-on Reset for details
VBOR Brown-out Reset
Voltage
D005 B ORV1:BO RV0 = 1x N.A. N.A. V Not in operating voltage range of device
BORV1:BORV0 = 01 4.2 4.46 V
BORV1:BORV0 = 00 4.5 4.78 V
D010 IDD Supply Current(2,4) ——TBDmA
XT, RC, RCIO osc configurations
FOSC = 4 MHz, VDD = 4.2V
D010A TBD µALP osc configuration
FOSC = 32 kHz, VDD = 4.2V
D010C 45 mA EC, ECIO osc configurations,
Fosc = 40 MHz, VDD = 5.5V
D013 50 mA HS osc configu r ations
Fosc = 25 MHz, VDD = 5.5V
D013 50 mA HS + PLL osc configuration
Fosc = 10 MHz, VDD = 5.5V
D014
TBD
TBD µA
µA
OSCB osc configuration
FOSC = 32 kHz, VDD = 4.2V
FOSC = 32 kHz, VDD = 4.2V, 25°C
Legend: Shading of rows is to assist in readability of the table.
Note1: This is the limit to which VDD can be lowered in SLEEP mode or during a device reset without losing RAM
data.
2: The supply cur r ent is ma inl y a fun cti on of th e operating voltage and frequency. Other factors, s uc h as I/O p in
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The po w er-do wn curre nt in SLEEP m ode do es no t depen d on th e oscil lator ty pe . Power-d own curren t is mea-
sured with the part in SLEEP mode , wit h all I/ O pins in hi-im pedanc e sta te and ti ed to VDD or VSS, and al l f ea-
tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
PIC18CXX2
DS39026B-page 244 Preliminary 7/99 Microchip Technology Inc.
21.1 DC Characteristics: PIC18CXX2 (Industrial, Extended) (contd)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
IPD Power-down Current(3)
D020
<1
TBD
36 µA
µAVDD = 4.2V, -40°C to +85°C
VDD = 5.5V, -40°C to +85°C
D020A TBD µAVDD = 4.2V, 25°C
D021B
<TBD
TBD
42 µAVDD = 4.2V, -40°C to +125°C
VDD = 5.5V, -40°C to +125°C
Module Differential
Current
D022 IWDT Watchdog Timer
25
TBD
TBD
µA
µA
µA
VDD = 5.5V, -40°C to +85°C
VDD = 5.5V, -40°C to +125°C
VDD = 4.2V, 25°C
D022A IBOR Brown-ou t Reset
50
TBD
TBD
µA
µA
µA
VDD = 5.5V, -40°C to +85°C
VDD = 5.5V, -40°C to +125°
VDD = 4.2V, 25°C
D022B ILVD Low Voltage Detect
TBD
TBD
TBD
µA
µA
µA
VDD = 4.2V, -40°C to +85°C
VDD = 4.2V, -40°C to +125°C
VDD = 4.2V, 25°C
D025 IOSCB Timer1 Oscillator
TBD
TBD
TBD
µA
µA
µA
VDD = 4.2V, -40°C to +85°C
VDD = 4.2V, -40°C to +125°C
VDD = 4.2V, 25°C
Legend: Shading of rows is to assist in readability of the table.
Note1: This is the limit to which VDD can be lowered in SLEEP mode or during a device reset without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumptio n.
The test condi t ion s for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The po w er-do wn curre nt in SLEEP mode do es no t depen d on th e oscil lator ty pe . Power-d own curren t is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS, and all
features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 245
21.2 DC Characteristics: PIC18LCXX2 (Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Symbol Characteristic Min Typ Max Units Conditions
VDD Supply Voltage
D001 2.5 5.5 V HS, XT, RC and LP osc mode
D002 VDR RAM Data Retention
Voltage(1) 1.5 V
D003 VPOR VDD Start Voltage to
ensure internal Power-
on Reset signal
0.7 V See section on Power-on Reset for details
D004 SVDD VDD Rise Rate to
ensure internal Power-
on Reset signal
0.05 V/ms See section on Power-on Reset for details
VBOR Brown-out Reset
Voltage
D005 B ORV1:BO RV0 = 11 2.5 2.66 V
BORV1:BORV0 = 10 2.7 2.86 V
BORV1:BORV0 = 01 4.2 4.46 V
BORV1:BORV0 = 00 4.5 4.78 V
D010 IDD Supply Current(2,4) ——4mA
XT, RC, RCIO osc configurations
FOSC = 4 MHz, VDD = 2.5V
D010A 48 µALP osc configuration
FOSC = 32 kHz, VDD = 2.5V
D010C 45 mA EC, ECIO osc configurations,
Fosc = 40 MHz, VDD = 5.5V
D013
TBD
50 mA
mA
HS osc conf igu rations
Fosc = 6 M Hz, VDD = 2.5V
Fosc = 25 MHz, VDD = 5.5V
D013 50 mA HS + PLL osc configuration
Fosc = 10 MHz, VDD = 5.5V
D014
48
TBD µA
µA
Timer1 osc configuration
FOSC = 32 kHz, VDD = 2.5V
FOSC = 32 kHz, VDD = 2.5V, 25°C
Legend: Shading of rows is to assist in readability of the table.
Note1: This is the limit to which VDD can be lowered in SLEEP mode or during a device reset without losing RAM
data.
2: The supply cur r ent is ma inl y a fun cti on of th e operating voltage and frequency. Other factors, s uc h as I/O p in
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The po w er-do wn curre nt in SLEEP m ode do es no t depen d on th e oscil lator ty pe . Power-d own curren t is mea-
sured with the part in SLEEP mode , wit h all I/ O pins in hi-im pedanc e sta te and ti ed to VDD or VSS, and al l f ea-
tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
PIC18CXX2
DS39026B-page 246 Preliminary 7/99 Microchip Technology Inc.
21.2 DC Characteristics: PIC18LCXX2 (Industrial) (cont’d)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Symbol Characteristic Min Typ Max Units Conditions
D020 IPD P o wer -down Current(3)
<2.5
5
36
TBD
µA
µA
µA
VDD = 2.5V, -40°C to +85°C
VDD = 5.5V, -40°C to +85°C
VDD = 2.5V, 25°C
Module Differential
Current
D022 IWDT Watchdog Timer
12
25
TBD
µA
µA
µA
VDD = 2.5V
VDD = 5.5V
VDD = 2.5V, 25°C
D022A IBOR Brown-ou t Reset
50
TBD µA
µAVDD = 5. 5V
VDD = 2.5V, 25°C
D022B ILVD Low Voltage Detect
50
TBD µA
µAVDD = 2.5V
VDD = 2.5V, 25°C
D025 IOSCB Timer1 oscillator
3
TBD µA
µAVDD = 2.5V
VDD = 2.5V, 25°C
Legend: Shading of rows is to assist in readability of the table.
Note1: This is the limit to which VDD can be lowered in SLEEP mode or during a device reset without losing RAM
data.
2: The supp ly cur rent i s mainly a func tion of t he oper ating v oltag e and fre que ncy. Other f actors , s uch as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurem en ts in act ive operation mo de are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measure d with th e part in SLEEP mode, with all I/O pins in hi-impe dance st ate and tied to VDD and VSS, and
all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 247
21.3 DC Characteristics: PIC18CXX2 (Industrial, Extended) and PIC18LCXX2 (Industrial)
DC CHARA CTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Max Units Conditions
VIL Input Low Voltage
I/O ports:
D030 with TTL buffer VSS 0.15VDD VVDD < 4.5V
D030A 0.8 V 4.5V VDD 5.5V
D031 with Schmitt Trigger buffer
RC3 and RC4 VSS
VSS 0.2VDD
0.3VDD V
V
D032 MCLR VSS 0.2VDD V
D032A OSC1 (in XT, HS and LP modes)
and T1OSI VSS 0.3VDD V
D033 OSC1(in RC mo de)(1) VSS 0.2VDD V
VIH Input High Voltage
I/O ports:
D040 with TTL buffer 0.25VDD +
0.8V VDD VVDD < 4.5V
D040A 2.0 VDD V4.5V VDD 5.5V
D041 with Schmitt Trigger buffer
RC3 and RC4 0.8VDD
0.7VDD VDD
VDD V
V
D042 MCLR 0.8VDD VDD V
D042A OSC1 (in XT, HS and LP modes)
and T1OSI 0.7VDD VDD V
D043 OSC1 (RC mode)(1) 0.9VDD VDD V
D050 VHYS Hysteresis of Schmitt Trigger Inputs TBD TBD V
IIL Input Leakage Current(2,3)
D060 I/O ports ±1µAVSS VPIN VDD,
Pin at hi-impeda nc e
D061 MCLR ±5µAVss VPIN VDD
D063 OSC1 ±5µAVss VPIN VDD
IPU Weak Pull-up Current
D070 IPURB PORTB weak pull-up current 50 400 µAVDD = 5V, VPIN = VSS
Note1: I n RC o scillato r conf igura tion, t he OSC1/CLKIN p in is a Schm itt Trigger in put. It i s not recomme nded th at the
PICmicro be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied volt age level. The specified
leve ls repr es ent normal ope rat ing cond it ion s. Higher leak age cur rent may be measured at different inp ut
voltages.
3: Negative current is defined as current sourced by the pin.
PIC18CXX2
DS39026B-page 248 Preliminary 7/99 Microchip Technology Inc.
21.3 DC Characteristics: PIC18CXX2 (Industrial, Extend ed) and PIC18LCXX2 (Industr ial) (cont’d)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Max Units Conditions
VOL Output Low Voltage
D080 I/O ports 0.6 V I OL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D080A 0.6 V IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D083 OSC2/CLKOUT
(RC mode) —0.6VI
OL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
D083A 0.6 V IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
VOH Output High Voltage(3)
D090 I/O ports VDD - 0.7 V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D090A VDD - 0.7 V IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
D092 OSC2/CLKOUT
(RC mode) VDD - 0.7 V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D092A VDD - 0.7 V IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D150 VOD Open-drain High Voltage 7.5 V RA4 pin
Capacit ive Load ing Specs
on Output Pins
D101 CIO All I/O pins and OSC2
(in RC mode) 50 pF To meet the AC Timing Specifications
D102 CBSCL, SDA 400 pF In I2C mode
Note1: In RC osci llator config urati on, the OSC1 /CLKIN pin is a Schm itt Trigger input. It is not reco mmended that the
PICm icro be driven with an external clock while in RC mod e.
2: The leak age cur r ent on t he MCLR pin is str on gly dep enden t on t he ap pli ed voltage level. The specifie d
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 249
FIGURE 21-3: LOW-VOLTAGE DETECT CHARACTERISTICS
TABLE 21-1: LOW VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Max Units Conditions
D420 VLVD LVD Voltage LVV<3:0> = 0100 2.5 2.66 V
LVV<3:0> = 0101 2.7 2.86 V
LVV<3:0> = 0110 2.8 2.98 V
LVV<3:0> = 0111 3.0 3.2 V
LVV<3:0> = 1000 3.3 3.52 V
LVV<3:0> = 1001 3.5 3.72 V
LVV<3:0> = 1010 3.6 3.84 V
LVV<3:0> = 1011 3.8 4.04 V
LVV<3:0> = 1100 4.0 4.26 V
LVV<3:0> = 1101 4.2 4.46 V
LVV<3:0> = 1110 4.5 4.78 V
VLVD
LVDIF
VDD
(LVDIF set by hardware)
(LVDIF can be
cleared in software)
PIC18CXX2
DS39026B-page 250 Preliminary 7/99 Microchip Technology Inc.
TABLE 21-2: EPROM PROGRAMMING REQUIREMENTS
DC CHARACTERI STICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +40°C
Param.
No. Sym Characteristic Min Max Units Conditions
Internal Program Memory
Programmi ng Specs (Note 1)
D110
D111
D112
D113
D114
D115
VPP
VDDP
IPP
IDDP
TPROG
TERASE
Voltage on MCLR/VPP pin
Supply voltage during
programming
Current into MCLR/VPP pin
Supply current during
programming
Programming pulse width
EPROM erase time
Device operation 3V
Device operation 3V
12.75
4.75
100
4
TBD
13.25
5.25
50
30
1000
V
V
mA
mA
µs
hrs
hrs
Note 2
Terminated via internal/external
interrupt or a reset
Note1: These spe cifications are f or the prog rammin g of the on-c hip progr am mem ory EPR OM throug h the use of t he
table write instructions. The complete programming specifications can be found in: PIC18CXXX Program-
ming Specifications (Literature number TBD).
2: The MCL R/VPP pin may be kept in this range at times other than programming, but is not recommended.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 251
21.4 AC (Timing) Characteristics
21.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TFFrequency TTime
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters an d their meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
PIC18CXX2
DS39026B-page 252 Preliminary 7/99 Microchip Technology Inc.
21.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 21-3
apply to all timing specifications unless otherwise
noted. Figure 21-4 specifies the load conditions for the
timing specific ati ons.
TABLE 21-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
FIGURE 21-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for indust rial
-40°C TA +125°C for extended
Opera ting v oltag e VDD range as described in DC sp ec Se ction 21.1 and Sec tion 21.2.
LC parts operate for industrial temp’s only.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464
CL= 50 pF for all pins except OSC2/CLKOUT
and including D and E outputs as ports
Load condition 1 Load condition 2
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 253
21.4.3 TIMING DIAG RAMS AND SPECIFICATIONS
FIGURE 21-5: EXTERNAL CLOCK TIMING
TABLE 21-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Pa ram. No. Symbol Characteristic Min Max Units Conditions
1A Fosc External CLKIN
Frequency(1) DC 40 MHz XT 0osc
DC 40 MHz HS osc
4 10 MHz HS + PLL osc
DC
DC 40
40 kHz
MHz LP osc
EC
Oscillator Frequency(1) DC 4 MHz RC osc
0.1 4 MHz XT osc
4 25 MHz HS osc
4 10 MHz HS + PLL osc
5 200 kHz LP osc mode
1Tosc
External CLKIN Period(1) 250 ns XT and RC osc
40 ns HS osc
100 ns HS + PLL osc
5
5
µs
ns LP osc
EC
Oscillator Period(1) 250 ns RC osc
250 10,000 ns XT osc
100
40 10,000
100 ns
ns HS osc
HS + PLL osc
5—µsLP osc
2T
CY Instruction Cycle Time(1) 100 ns TCY = 4/FOSC
3 TosL,
TosH External Clock in (OSC1)
High or Low Time
30 ns XT osc
2.5 µsLP osc
10 ns HS osc
4TosR,
TosF External Clock in (OSC1)
Rise or Fall Time 20 ns XT osc
50 ns LP osc
7.5 ns HS osc
Note1: I nstruction cy cl e period (T CY) equals four times the in put oscillator time -bas e p eriod. Al l s pe cif ied v a lue s a re
based o n char acte rization d ata f or t hat particular os cilla tor type under s tandard oper ating c ondit ions w ith th e
devic e exec uti ng code . Exc eed ing thes e s pec ifi ed lim it s m ay result i n a n unstable oscilla tor ope ra tio n and/or
higher th an e x pecte d curren t cons umpti on. All d e vices are tes ted to o per ate at "min. " v alue s with a n e xte rnal
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is
"DC" (no clock) for all devices.
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
PIC18CXX2
DS39026B-page 254 Preliminary 7/99 Microchip Technology Inc.
TABLE 21-5: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V)
Param
No. Symbol Characteristic Min Max Units Conditions
TRC PLL Start-up Time
(Loc k Tim e) —2ms
CLK CLKOUT Stability (Jitter) using PLL -2 +2 %
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 255
FIGURE 21-6: CLKOUT AND I/O TIMING
TABLE 21-6: CLKOUT AND I/O TIMING REQUIREMENTS
Param.
No. Symbol Characteristic Min Typ Max Units Conditions
10 TosH2ckL OSC1 to CLKOUT 75 200 ns (1)
11 TosH2ckH OSC1 to CLKOUT 75 200 ns (1)
12 TckR CLKOUT rise time 35 100 ns (1)
13 TckF CLKOUT fall time 35 100 ns (1)
14 TckL2ioV CLKOUT to Port out valid 0.5TCY + 20 ns (1)
15 TioV2ckH Port in valid before CLKOUT 0.25TCY + 25 ns (1)
16 TckH2ioI Por t in hold after CLKOUT 0—ns
(1)
17 TosH2ioV OSC1 (Q1 cycle) to Port out valid 50 150 ns
18 TosH2ioI OSC1 (Q2 cycle) to
Port input invalid
(I/O in hold time)
PIC18CXXX 100 ns
18A PIC18LCXXX 200 ns
19 TioV2osH Port input valid to OSC1
(I/O in setup time) 0—ns
20 TioR Port output rise time PIC18CXXX 10 25 ns
20A PIC18LCXXX 60 ns
21 TioF Port output fall time PIC18CXXX 10 25 ns
21A PIC18LCXXX 60 ns
22†† TINP INT pin high or low time TCY ——ns
23†† TRBP RB7:RB4 change INT high or low time TCY ——ns
24†† TRCP RC7:RC4 change INT high or low time 20 ns
††These parameters are asynchronous events not related to any internal clock edges.
Note1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 21-4 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12
16
old value new value
PIC18CXX2
DS39026B-page 256 Preliminary 7/99 Microchip Technology Inc.
FIGURE 21-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 21-8: BROWN-OUT RESET TIMING
TABLE 21-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No. Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 —— µs
31 TWDT Watchdog Timer Time-out Period
(No Prescaler) 71833ms
32 TOST Oscillation Start-up Timer Period 1024TOSC 1024TOSC —TOSC = OSC1 period
33 TPWRT Power up Timer Period 28 72 132 ms
34 TIOZ I/O H i -im ped anc e fro m M CLR Lo w
or Watchdog Timer Reset —2µs
35 TBOR Brown -out R eset Pulse W idth 200 µsVDD BVDD (See
D005)
36 TIVRST Time for Internal Reference
Voltage to become stable —2050 µs
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 21-4 for load conditions.
VDD BVDD
35 VBGAP = 1.2V
VIRVST
Enable Internal Reference Voltage
Internal Reference Voltage stable 36
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 257
FIGURE 21-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 21-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Symbol Characteristic Min Max Units Conditions
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 2 0 —ns
With Prescaler 10 ns
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 ns
With Prescaler 10 ns
42 Tt0P T0CKI Period No Prescaler TCY + 10 ns
With Prescaler Greater of:
20 nS or TCY + 40
N
ns N = prescale
value
(1, 2, 4,..., 256)
45 Tt1H T1CKI
High
Time
Synchro nou s , no pres ca le r 0.5TCY + 20 ns
Synchronous,
with prescaler PIC18CXXX 10 ns
PIC18LCXXX 25 ns
Asynchronous PIC18CXXX 30 ns
PIC18LCXXX 50 ns
46 Tt1L T1CKI
Low
Time
Synchro nou s , no pres ca le r 0.5TCY + 5 ns
Synchro nou s,
with prescaler PIC18CXXX 10 ns
PIC18LCXXX 25 ns
Asynchronous PIC18CXXX 30 ns
PIC18LCXXX TBD TBD ns
47 Tt1P T1CKI
input
period
Synchronous Greater of:
20 nS or TCY + 40
N
ns N = prescale
value
(1, 2, 4, 8)
Asynchronous 60 ns
Ft1 T1CKI oscillator input frequency range DC 50 kHz
48 Tcke2tmrI Delay from external T1CKI clock edge to
timer inc rement 2Tosc 7Tosc
Note: Refer to Figure 21-4 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T1CKI
TMR0 o r
TMR1
PIC18CXX2
DS39026B-page 258 Preliminary 7/99 Microchip Technology Inc.
FIGURE 21-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 21-9: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param.
No. Symbol Characteristic Min Max Units Conditions
50 TccL CCPx input low
time No Prescaler 0.5TCY + 20 —ns
With
Prescaler PIC18CXXX 10 ns
PIC18LCXXX 20 ns
51 TccH CCPx input
high time No Prescaler 0.5TCY + 20 ns
With
Prescaler PIC18CXXX 10 ns
PIC18LCXXX 20 ns
52 TccP CCPx input period 3TCY + 40
N ns N = prescale
value (1,4 or 16)
53 TccR CCPx output fall time PIC18CXXX 25 ns
PIC18LCXXX 45 ns
54 TccF CCPx output fall time PIC18CXXX 25 ns
PIC18LCXXX 45 ns
Note: Refer to Figure 21-4 for load conditions.
CCPx
(Capture Mode)
50 51
52
CCPx
53 54
(Compare or PWM Mode)
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 259
FIGURE 21-11: PARALLEL SLAVE PORT TIMING (PIC18C4X2)
TABLE 21-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18C4X2)
Param.
No. Symbol Characteristic Min Max Units Conditions
62 TdtV2wrH Data in valid before WR or CS
(setup time) 20
25
ns
ns Extended Temp range
63 TwrH2dtI WR or CS to data–in invalid
(hold time) PIC18CXXX 20 ns
PIC18LCXXX 35 ns
64 TrdL2dtV RD and CS to data–out valid
80
90 ns
ns Extended Temp range
65 TrdH2dtI RD or CS to data–out invalid 10 30 ns
66 TibfINH Inhibit of the IBF flag bit being cleared from
WR or CS—3T
CY
Note: Refer to Figure 21-4 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
PIC18CXX2
DS39026B-page 260 Preliminary 7/99 Microchip Technology Inc.
FIGURE 21-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 21-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK input TCY —ns
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 ns
71A Single Byte 40 ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 ns
72A Single Byte 40 ns Note 1
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 ns
73A TB2BLast cloc k edge of Byte 1 to the 1st cloc k edge of
Byte2 1.5TCY + 40 ns Note 2
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 ns
75 TdoR SDO data output rise time PIC18CXXX 25 ns
PIC18LCXXX 45 ns
76 TdoF SDO data output fall time 25 ns
78 TscR SCK output rise time
(master mo de) PIC18CXXX 25 ns
PIC18LCXXX 45 ns
79 TscF SCK output fall time (master mode) 25 ns
80 TscH2doV,
TscL2doV SDO data output valid after
SCK edge PIC18CXXX 50 ns
PIC18LCXXX 100 ns
Note1: Requires the use of Parameter # 73A.
2: Only if Parameter #s 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
BIT6 - - - - - -1
MSb IN LSb IN
BIT6 - - - -1
Note: Refer to Figure 21- 4 for load conditions.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 261
FIGURE 21-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 21-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No. Symbol Characteristic Min Max Units Conditions
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 —ns
71A Single Byte 40 ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 ns
72A Single Byte 40 ns Note 1
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 ns
73A TB2BLast cloc k edge of Byte 1 to the 1st cloc k edge of
Byte2 1.5TCY + 40 ns Note 2
74 TscH2d iL,
TscL2diL Hold time of SDI data input to SCK edge 100 ns
75 TdoR SDO data output rise time PIC18CXXX 25 ns
PIC18LCXXX 45 ns
76 TdoF SDO data output fall time 25 ns
78 TscR SCK output rise time
(master mo de) PIC18CXXX 25 ns
PIC18LCXXX 45 ns
79 TscF SCK output fall time (master mode) 25 ns
80 TscH2doV,
TscL2doV SDO data output valid after
SCK edge PIC18CXXX 50 ns
PIC18LCXXX 100 ns
81 TdoV2scH,
TdoV2scL SDO data output setup to SCK edge TCY —ns
Note1: Requires the use of Parameter # 73A.
2: Only if Parameter #s 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb IN
BIT6 - - - - - -1
LSb IN
BIT6 - - - -1
LSb
Note: Refer to Figure 21-4 for load conditions.
PIC18CXX2
DS39026B-page 262 Preliminary 7/99 Microchip Technology Inc.
FIGURE 21-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 21-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Parm.
No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK input TCY —ns
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 ns
71A Single Byte 40 ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 ns
72A Single Byte 40 ns Note 1
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 ns
73A TB2BLast clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 ns Note 2
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 ns
75 TdoR SDO data output rise time PIC18CXXX 25 ns
PIC18LCXXX 45 ns
76 TdoF SDO data output fall time 25 ns
77 TssH2doZ SS to SDO output hi-impedance 10 50 ns
78 TscR SCK output rise time
(master mode) PIC18CXXX 25 ns
PIC18LCXXX 45 ns
79 TscF SCK output fall time (master mode) 25 n s
80 TscH2doV,
TscL2doV SDO data output valid after SCK
edge PIC18CXXX 50 ns
PIC18LCXXX 100 ns
83 TscH2ssH,
TscL2ssH SS after SCK edge 1.5TCY + 40 ns
Note1: Requires the use of Parameter # 73A.
2: Only if Parameter #s 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
BIT6 - - - - - -1
MSb IN BIT6 - - - -1 LSb IN
83
Note: Refer to Figure 21- 4 for load conditions.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 263
FIGURE 21-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 21-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Parm.
No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK input TCY —ns
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 ns
71A Single Byte 40 ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 ns
72A Single Byte 40 ns Note 1
73A TB2BLast clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 ns Note 2
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 ns
75 TdoR SDO data output rise time PIC18CXXX 25 ns
PIC18LCXXX 45 ns
76 TdoF SDO data output fall time 25 ns
77 TssH2doZ SS to SDO output hi-impedance 10 50 ns
78 TscR SCK output rise time
(master mode) PIC18CXXX 25 ns
PIC18LCXXX 45 ns
79 TscF SCK output fall time (master mode) 25 ns
80 TscH2doV,
TscL2doV SDO data output valid after SCK
edge PIC18CXXX 50 ns
PIC18LCXXX 100 ns
82 TssL2doV SDO data output valid after SS
edge PIC18CXXX 50 ns
PIC18LCXXX 100 ns
83 TscH2ssH,
TscL2ssH SS after SCK edge 1.5TCY + 40 ns
Note1: Requires the use of Parameter # 73A.
2: Only if Parameter #s 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb BI T 6 - - - - - -1 LSb
77
MSb IN BIT6 - - - -1 LSb IN
80
83
Note: Refer to Figure 21-4 for load conditions.
PIC18CXX2
DS39026B-page 264 Preliminary 7/99 Microchip Technology Inc.
FIGURE 21-16 : I2C BUS START/STOP BITS TIMING
TABLE 21-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Parm.
No. Symbol Characteristic Min Max Units Conditions
90 TSU:STA START condition 100 kHz mode 4700 ns Only relevant for repeated
START condition
Setup time 400 kHz mode 600
91 THD:STA START condition 100 kHz mode 4000 ns After this period the first
clock pulse is generated
Hold time 400 kHz mode 600
92 TSU:STO STOP condition 100 kHz mode 4700 ns
Setup time 400 kHz mode 600
93 THD:STO STOP condition 100 kHz mode 4000 ns
Hold time 400 kHz mode 600
Note: Refer to Figure 21-4 for load conditions.
91
92
93
SCL
SDA
START
Condition STOP
Condition
90
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 265
FIGURE 21-17 : I2C BUS DATA TIMING
TABLE 21-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No. Symbol Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 4.0 µs PIC18CXXX must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 µs PIC18CXXX must operate at a
minimum of 10 MHz
SSP Module 1.5TCY
101 TLOW Clock low time 100 kHz mode 4.7 µs PIC18CXXX must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 µs PIC18CXXX must operate at a
minimum of 10 MHz
SSP Module 1.5TCY
102 TRSD A and SCL rise
time 100 kHz mode 1000 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
103 TFSDA and SCL fall
time 100 kHz mode 300 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
90 TSU:STA START condition
setup time 100 kHz mode 4.7 µs Only relevant for repeated
START condition
400 kHz mode 0.6 µs
91 THD:STA START condition hold
time 100 kHz mode 4.0 µs A fter this period the first clock
pulse is generated
400 kHz mode 0.6 µs
106 THD:DAT Data input hold time 100 kHz mode 0 ns
400 kHz mode 0 0.9 µs
107 TSU:DAT Data input setup time 100 kHz mode 250 ns Note 2
400 kHz mode 100 ns
92 TSU:STO STOP condition
setup time 100 kHz mode 4.7 µs
400 kHz mode 0.6 µs
109 TAA Output valid from
clock 100 kHz mode 3500 ns Note 1
400 kHz mode ns
110 TBUF Bus free time 100 kHz mode 4.7 µs T ime the bus must be free
before a ne w transmission can
start
400 kHz mode 1.3 µs
D102 Cb Bus capacitive loading 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STO P conditions.
2: A fast-mode I2C b us device can be used in a standard-mode I2C bus system, but the requirement tsu;DAT 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
TR max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
Note: Refer to Figure 21-4 for load conditions.
90
91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC18CXX2
DS39026B-page 266 Preliminary 7/99 Microchip Technology Inc.
FIGURE 21-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
TABLE 21-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
90 TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) ns Only relevant for
repeated START
condition
Setup time 400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode (1) 2(TOSC)(BRG + 1)
91 THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) ns After this period the
first clock pulse is
generated
Hold time 400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode (1) 2(TOSC)(BRG + 1)
92 TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) ns
Setup time 400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode (1) 2(TOSC)(BRG + 1)
93 THD:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) ns
Hold time 400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode (1) 2(TOSC)(BRG + 1)
Note1: Maximum pin capacitance = 10 pF for all I2C pins.
Note: Refer to Figure 21-4 for load conditions.
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 267
FIGURE 21-19: MASTER SSP I2C BUS DATA TIMING
TABLE 21-18: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) —ms
400 kHz mode 2(TOSC)(BRG + 1) ms
1 MHz mode (1) 2(TOSC)(BRG + 1) ms
101 TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) ms
400 kHz mode 2(TOSC)(BRG + 1) ms
1 MHz mode (1) 2(TOSC)(BRG + 1) ms
102 TRSDA and SCL
rise time 100 kHz mode 1000 ns Cb is specified to be from
10 to 400 pF 400 kHz mode 20 + 0.1Cb 300 ns
1 MHz mode (1) 300 ns
103 TFSDA and SCL
f a ll tim e 100 kHz mode 300 ns Cb is specified to be from
10 to 400 pF 400 kHz mode 20 + 0.1Cb 300 ns
1 MHz mode (1) 100 ns
90 TSU:STA START condition
setup time 100 kHz mode 2(TOSC)(BRG + 1) ms Only relevant for repeated
START condition400 kHz mode 2(TOSC)(BRG + 1) ms
1 MHz mode (1) 2(TOSC)(BRG + 1) ms
91 THD:STA START condition
hold time 100 kHz mode 2(TOSC)(BRG + 1) ms After this period the first
clock pulse is generated400 kHz mode 2(TOSC)(BRG + 1) ms
1 MHz mode (1) 2(TOSC)(BRG + 1) ms
106 THD:DAT Data input
hold time 100 kHz mode 0 ns
400 kHz mode 0 0.9 ms
1 MHz mode (1) TBD ns
107 TSU:DAT Data input
setup time 100 kHz mode 250 ns Note 2
400 kHz mode 100 ns
1 MHz mode (1) TBD ns
92 TSU:STO STOP condition
setup time 100 kHz mode 2(TOSC)(BRG + 1) ms
400 kHz mode 2(TOSC)(BRG + 1) ms
1 MHz mode (1) 2(TOSC)(BRG + 1) ms
109 TAA Output valid from
clock 100 kHz mode 3500 ns
400 kHz mode 1000 ns
1 MHz mode (1) ——ns
110 TBUF Bus f ree time 100 kHz mode 4. 7 ms Time the bus must be free
before a new transmis-
sion can start
400 kHz mode 1.3 ms
1 MHz mode (1) TBD ms
D102 Cb Bus capacitive loading 400 pF
Note1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fas t-m ode I 2C bus dev ic e c an be used in a st andard-mod e I2C b us sy st em , but parameter #107 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
parameter #102.+ parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz-mode) before the SCL line is released.
Note: Refer to Figure 21-4 for load conditions.
90 91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC18CXX2
DS39026B-page 268 Preliminary 7/99 Microchip Technology Inc.
FIGURE 21-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 21-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid PIC18CXXX —40ns
PIC18LCXXX 100 ns
121 Tckrf Clock out rise time and fall time
(Master Mo de) PIC18CXXX 20 ns
PIC18LCXXX 50 ns
122 Tdtrf Data out rise time and fall time PIC18CXXX 20 ns
PIC18LCXXX 50 ns
Note: Refer to Figure 21-4 for load conditions.
121 121
120 122
RC6/TX/CK
RC7/RX/DT
pin
pin
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 269
FIGURE 21-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 21-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data hold before CK (DT hold tim e) 10 —ns
126 TckL2dtl Data hold after CK (DT hold time) 15 ns
Note: Refer to Figure 21-4 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
PIC18CXX2
DS39026B-page 270 Preliminary 7/99 Microchip Technology Inc.
TABLE 21-21: A/D CONVERTER CHARACTERISTICS: PIC18CXX2 (INDUSTRIAL, EXTENDED)
PIC18LCXX2 (INDUSTRIAL)
Param
No. Symbol Characteristic Min Typ Max Units Conditions
A01 NRResolution
10
TBD bit
bit VREF = VDD 3.0V
VREF = VDD < 3.0V
A03 EIL Integral linearity error
<±1
TBD LSb
LSb VREF = VDD 3.0V
VREF = VDD < 3.0V
A04 EDL Differential linearity error
<±1
TBD LSb
LSb VREF = VDD 3.0V
VREF = VDD < 3.0V
A05 EFS Full scale error
<±1
TBD LSb
LSb VREF = VDD 3.0V
VREF = VDD < 3.0V
A06 EOFF Offset error
<±1
TBD LSb
LSb VREF = VDD 3.0V
VREF = VDD < 3.0V
A10 Monotonicity guaranteed(3)—VSS VAIN VREF
A20 VREF Reference voltage
(VREFH - VREFL)0V V
A20A 3V V For 10-bit resolution
A21 VREFH Reference voltage High AVSS —AVDD + 0.3V V
A22 VREFL Reference voltage Low AVSS - 0.3V AVDD V
A25 VAIN Analog input voltage AVSS - 0.3V VREF + 0.3V V
A30 ZAIN Recommended impedance of
analog voltage source 10.0 k
A40 IAD A/D conversion
current (VDD)PIC18CXXX 180 µA Average current
co nsumption when
A/D is on. (Note 1)
PIC18LCXXX 90 µA
A50 IREF VREF input current (Note 2) 10
1000
10
µA
µA
During VAIN acquisition .
Based on differential of
VHOLD to VAIN. To charge
CHOLD see Section 16.0.
During A/D conversion
cycle
Note1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is
selected as reference input.
2: VSS VAIN VREF
3: The A/D conversion result either increases or remains constant as the analog input increases.
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 271
FIGURE 21-22: A/D CONVERSION TIMING
TABLE 21-22: A/D CONVERSION REQUIREMENTS
Param
No. Symbol Characteristic Min Max Units Conditions
130 TAD A/D clock period PIC18CXXX 1.6 20 (5) µsTOSC based, VREF 3.0V
PIC18LCXXX 3.0 20 (5) µsT
OSC based, VREF full range
PIC18CXXX 2.0 6.0 µs A/D RC Mode
PIC18LCXXX 3.0 9.0 µs A/D RC Mode
131 TCNV Conversion time
(not including acquisition time) (Note 1) 11 12 TAD
132 TACQ Acqui s ition time (Note 3) 15
10
µs
µs-40°C Temp 125°C
0°C Temp 125°C
135 TSWC Switching Time from conver t sample N ote 4
136 TAMP Amplifier settling time (Note 2) 1 µs This may be used if the
“new” input voltage h as not
changed by more than 1LSb
(i.e. 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note1: ADRES register may be read on the following TCY cycle.
2: See the Section 16.0 for minimum conditions, when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedanc e (
R
S
) on the input channels is
50 .
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
Note 2
987 21 0
Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock star ts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 nS), which also disconnects the holding capacitor from the
analog input.
. . . . . .
TCY
PIC18CXX2
DS39026B-page 272 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 273
22.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables not available at this time.
PIC18CXX2
DS39026B-page 274 Preliminary 7/99 Microchip Technology Inc.
NOTES:
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 275
23.0 PACKA GING INFORMATION
23.1 Package Marking Information
Not available at time o f p rinting. Will be ma de a vailabl e
after def inition of Q S9000 compliant standard
23.2 Package Details
The following sections give the technical details of the
packages.
PIC18CXX2
DS39026B-page 276 Preliminary 7/99 Microchip Technology Inc.
Package Type: 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil
* Controlling Parameter.
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MO-095 AH
0.320
0.270
0.280
1.345
0.125
0.015
0.070
0.140
0.008
0.000
0.040
0.016
Mold Draft Angle Bottom
Mold Draft Angle Top
Overall Row Spacing
Radius to Radius Width
Molded Package Width
Tip to Seating Plane
Base to Seating Plane
Top of Lead to Seating Plane
Top to Seating Plane
Upper Lead Width
Lower Lead Width
PCB Row Spacing
Package Length
Lead Thickness
Shoulder Radius
Number of Pins
Dimension Limits
Pitch
Units
E
β
eB
E1
α
A1
A2
L
D
A
c
R
n
B1
B
p
MIN MIN
0.2950.288
5
510
0.350
0.283
10 0.380
0.295
15
15
0.090
1.365
0.130
0.020
0.150
0.010
0.005
NOM
INCHES*
28
0.053
0.019
0.100
0.300
1.385
0.135
0.025
0.110
0.160
0.012
0.010
0.065
0.022
MAX
7.497.307.11
8.89
7.18
5
8.13
6.86
510
10 15
15
9.65
7.49
34.67
3.30
0.51
2.29
3.81
0.25
0.13
1.33
0.48
2.54
7.62
MILLIMETERS
1.78
34.16
3.18
0.38
3.56
0.20
0.00
1.02
0.41
NOM
2.79
35.18
3.43
0.64
4.06
0.30
0.25
MAX
28
1.65
0.56
n 1
2
R
D
E
c
eB
β
E1
α
p
L
A1
B
B1
A
A2
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 277
Package Type: 28-Lead Ceramic Dual In-line with Window (JW) – 600 mil
* Controlling Parameter.
JEDEC equivalent: MO-103 AB
n1
2
R
MIN
Window Diameter
Overall Row Spacing
Radius to Radius Width
P ackage Width
P ackage Length
Tip to Seating Plane
Base to Seating Plane
Top of Lead to Seating Plane
Top to Seating Plane
Lead Thickness
Shoulder Radius
Upper Lead Width
Lower Lead Width
Number of Pins
PCB Row Spacing
Dimension Limits
Units
Pitch
W
eB
E1
A2
D
E
L
A
A1
c
R
B1
B
p
n
7.37
1.40
3.70
5.08
0.30
0.25
1.65
0.53
2.59
0.280
0.660
0.580
0.520
1.460
0.138
0.035
0.128
0.185
0.010
0.270
0.610
0.560
0.015
0.514
1.430
0.125
0.110
0.170
0.008
0.290
0.710
0.600
0.055
0.526
1.490
0.150
0.146
0.200
0.012
0.005
0.058
0.019
0.100
0.600
INCHES*
0.098
0.000
0.050
0.016
NOM MAX
28 0.102
0.010
0.065
0.021
37.08
6.86
15.49
14.22
13.06
36.32
3.18
0.38
2.78
4.32
0.20
7.11
16.76
14.73 18.03
15.24
0.89
3.49
13.21
3.24
4.70
0.25
13.36
37.85
3.81
NOM
MILLIMETERS
0.00
1.27
0.41
2.49
MIN
2.54
0.13
1.46
0.47
28
15.24 MAX
D
E
W
c
E1
eB p
A1
L
B1
B
A2
A
PIC18CXX2
DS39026B-page 278 Preliminary 7/99 Microchip Technology Inc.
Package Type: 28-Lead Plastic Small Outline (SO) Wide, 300 mil
MIN
pPitch
Mold Draft Angle Bottom
Mold Draft Angle Top
Lower Lead Width
Radius Centerline
Gull Wing Radius
Shoulder Radius
Chamfer Distance
Outside Dimension
Molded Package Width
Molded Package Length
Shoulder Height
Overall Pack. Height
Lead Thickness
Foot Angle
Foot Length
Standoff
Number of Pins
β
α
B
c
φ
X
A2
A1
A
n
E1
L
L1
R1
R2
E
D
Dimension Limits
Units
1.270.050
8
12
12
0.017
0
0.014
00.019
15
15
0.011
0.015
0.016
0.005
0.005
0.020
0.407
0.296
0.706
0.008
0.058
0.099
28
0.394
0.011
0.009
0.010
0
0.005
0.005
0.010
0.292
0.700
0.004
0.048
0.093
0.419
0.012
0.020
0.021
0.010
0.010
0.029
48
0.299
0.712
0.011
0.068
0.104
0.36
0
012
12
0.42
15
15
0.48
10.33
17.93
10.01
0.23
0.25
0.28
0.13
0.13
0.25
0
7.42
0.10
1.22
2.36
17.78
10.64
0.41
4
0.27
0.38
0.13
0.13
0.50
0.53
0.30
0.51
0.25
0.25
0.74
7.51
0.19
28
2.50
1.47
18.08
7.59
0.28
2.64
1.73
NOM
INCHES* MAX NOM
MILLIMETERS
MIN MAX
n1
2
R1
R2
D
p
B
E1
E
L1
L
c
β
45°
X
φ
A1
α
A
A2
* Controlling Parameter.
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC e
q
uivalent: MS-013 AE
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 279
Package Type: 40-Lead Plastic Dual In-line (P) – 600 mil
* Controlling Parameter.
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MS-011 AC
n2
1
R
Top to Seating Plane
Mold Draft Angle Bottom
Mold Draft Angle Top
Overall Row Spacing
Radius to Radius Width
Molded Package Width
Tip to Seating Plane
Base to Seating Plane
Top of Lead to Seating Plane
Package Length
E1
β
eB
α
L
E
D
A2
A1
0.670
0.585
0.540
2.023
0.135
0.040
0.113
0.545
5
5
0.630
0.125
0.530
2.013
0.020
0.073
0.565
10
0.610
10
0.130
0.535
2.018
0.020
0.093
16.00
13.84
13.46
51.13
3.18
0.51
1.85
15
15
14.35
5
510
15.49
10
3.30
13.59
51.26
0.51
2.36
14.86
17.02
15
15
13.72
51.38
3.43
1.02
2.87
PCB Row Spacing
Lead Thickness
Shoulder Radius
Upper Lead Width
Lower Lead Width
Pitch
Number of Pins
Dimension Limits
Units
p
c
A
R
B
B1
n
0.160
0.011
0.010
0.055
0.020
NOM
INCHES*
0.110
0.009
0.000
0.045
0.016
MIN
0.100
0.160
0.010
0.005
0.050
0.018
40
0.600 MAX
2.79
0.23
0.00
1.14
0.41
MIN
2.54
4.06
0.25
0.13
1.27
0.46
NOM
MILLIMETERS
15.24
40
4.06
0.28
0.25
1.40
0.51
MAX
A1
D
E
c
βeB
E1
α
p
L
B
B1
A
A2
PIC18CXX2
DS39026B-page 280 Preliminary 7/99 Microchip Technology Inc.
Package Type: 40-L ead Ceram ic Dual In-line with Window (JW) – 600 mil
* Controlling Parameter.
JEDEC equivalent: MO-103 AC
n1
2
R
Window Diameter
Overall Row Spacing
Radius to Radius Width
Package Width
Package Length
Tip to Seating Plane
Base to Seating Plane
Top of Lead to Seating Plane
Top to Seating Plane
Lead Thickness
Shoulder Radius
Upper Lead Width
Lower Lead Width
Number of Pins
PCB Row Spacing
Dimension Limits
Pitch
E1
W
eB
D
E
L
A2
A1
A
c
p
B1
R
B
n
9.14
18.03
15.24
13.36
52.32
3.68
3.89
5.59
0.36
0.25
0.58
2.59
MAX
0.0140.0110.008
0.350
0.660
0.580
0.520
2.050
0.140
0.035
0.135
0.205
0.560
0.340
0.610
0.514
2.040
0.135
0.015
0.117
0.190
0.600
0.360
0.710
0.526
2.060
0.145
0.055
0.153
0.220
0.005
0.053
0.020
0.100
0.600
NOM
0.000
0.050
0.016
0.098
MIN
40 0.102
0.010
0.055
0.023
MAX
0.280.20
14.22
15.49
8.64
13.06
51.82
3.43
0.38
2.97
4.83
14.73
16.76
8.89
13.21
52.07
3.56
0.89
3.43
5.21
MIN
2.49
1.27
0.00
0.41 2.54
1.33
0.13
0.50
15.24
NOM
40
1.40
1.40
D
W
E
c
eB
E1
p
L
A1
B1
B
A
A2
Units INCHES* MILLIMETERS
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 281
Pack age Type: 44-Lead Plastic Thin Quad Flatpack (PT)
10x10x1 mm Body, 1.0/0.1 mm Lead Form
0.025
0.390
0.390
0.463
0.463
0.012
0.004
0.003
0.005
0.003
0.003
0.002
0.015
0.039
p
Mold Draft Angle Bottom
Mold Draft Angle Top
Pin 1 Corner Chamfer
Molded Pack. Width
Molded Pack. Length
Outside Tip Width
Outside Tip Length
Lower Lead Width
Lead Thickness
Radius Centerline
Gull Wing Radius
Shoulder Radius
Shoulder Height
Ov erall Pack. Height
Pins along Width
Number of Pins
Foot Length
Foot Angle
Standoff
D
β
X
α
E
L
D1
E1
B
c
L1
φ
A1
R1
R2
A2
n1
A
n
Dimension Limits
Pitch
Units MIN
0.3980.394
5
512
0.035
0.394
10 0.045
0.398
15
15
0.010
0
0.472
0.472
0.015
0.006
0.008
3.5
0.025
0.006
0.003
0.004
0.043
11
44
0.015
0.482
0.482
0.018
0.008
0.013
7
0.008
0.010
0.006
0.035
0.047
10.1010.009.90
12
10
0.89
10.00
5
0.64
9.90
515
15
1.14
10.10
12.00
12.00
0.38
0.15
0.20
3.5
0.25
0.14
0.08
0.10
0.64
1.10
11
44
0.13
11.75
11.75
0.30
0.09
0.08
0
0.38
0.08
0.08
0.05
1.00
0.38
12.25
12.25
0.45
0.20
0.33
7
0.89
0.20
0.25
0.15
1.20
MINNOM
INCHES
0.031 MAX 0.80
MILLIMETERS*
NOM MAX
X x 45°
n
1
2
R2
R1 L1
L
β
c
φ
D1D
B
p
# leads = n1
E
E1
α
A1
A2
A
* Controlling Parameter.
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MS-026 ACB
PIC18CXX2
DS39026B-page 282 Preliminary 7/99 Microchip Technology Inc.
Package Type: 44-Lead Plastic Leaded Chip Carrier (L) – Square
* Controlling Parameter.
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimens ion “B1.”
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MO -047 AC
0.015
0.003
0.050
0.015
0.026
0.008
0.610
0.610
0.650
0.650
0.685
0.685
0.000
0.040
0.024
0.015
0.095
0.165
MIN
pPitch
Mold Draft Angle Bottom
Mold Draft Angle Top
J-Bend Inside Radius
Shoulder Inside Radius
Upper Lead Length
Lower Lead Width
Upper Lead Width
Lead Thickness
Pins along Width
Footprint Length
Footprint Width
Molded Pack. Length
Molded Pack. Width
Overall Pack. Length
Overall Pack. Width
Corner Chamf er (other)
Corner Chamf er (1)
Side 1 Chamfer Dim.
Shoulder Height
Overall Pack. Height
Standoff
R2
R1
α
β
L
B
B1
D2
E2
CH2
CH1
A3
A2
E1
c
n1
E
D
D1
A1
A
Number of Pins
Dimension Limits
Units
n1.270.050
0
0
0.005
0.025
5
5
0.058
0.018
0.029
0.035
0.010
0.065
0.021
0.032
10
10
0.690
0.620
0.010
0.620
11
0.653
0.653
0.690
0.005
0.045
0.029
0.023
0.103
0.173
0.695
0.012
0.630
0.630
0.656
0.656
0.695
0.010
0.050
0.034
0.030
0.110
0.180
0.64
0.13
1.46
0.46
0.74
0.08
0.38
0
0
1.27
0.38
0.66
5
5
0.25
0.89
10
10
1.65
0.53
0.81
0.25
15.75
15.75
16.59
16.59
17.53
17.53
0.13
1.14
0.74
0.57
2.60
4.38
17.40
15.49
0.20
15.49
16.51
16.51
17.40
0.00
1.02
0.61
0.38
2.41
4.19
17.65
11
16.00
0.30
16.00
16.66
16.66
17.65
0.25
1.27
0.86
0.76
2.79
4.57
INCHES*
NOM44 MAX MILLIMETERS
MIN NOM MAX
44
1
CH2 x 45°nCH1 x 45°
2
β
R2
A1
R1
c
E2
D1
D
# leads = n1
E1
E
α
p
L
A3
A2
A
35°
B1
B
D2
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 283
APPENDIX A: REVISION HISTORY
Revision A
This is a new data sheet.
APPENDIX B: DEVICE DIFF ERENCES
The differences between the devices listed in this data
sheet are shown in Table 23-1.
TABLE 23-1: Device Differences
Feature PIC18C242 PIC18C252 PIC18C442 PIC18C452
Program Memory (Bytes) 8K 16K 8K 16K
Data Memory (Bytes) 16K 32K 16K 32K
A/D Channels 5 5 8 8
Parallel Slave Port (PSP) No No Yes Yes
Package Types 28-pin DIP
28-pin SOIC
28-pin JW
28-pin DIP
28-pin SOIC
28-pin JW
40-pin DI P
40-pin PLCC
40-pin TQFP
40-pin JW
40-pin DIP
40-pin PLCC
40-pin TQFP
40-pin JW
PIC18CXX2
DS39026B-page 284 Preliminary 7/99 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
This appendix discusses the considerations for con-
verting from previous version of a device to the ones
listed in this data sheet. Typically these changes are
due t o t h e dif feren c es in th e p r oc ess te c hn ol o gy used .
An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18CXXX).
The following are the list of modifications over the
PIC16C5X mic roc on trol ler family:
Not Currently Available
PIC18CXX2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 285
APPENDIX E: MIGRATION FROM
MIDRANGE TO
ENHANCED DEVICES
This se ction discus ses ho w to mig rate from a Mi drange
device (i.e., PIC16CXXX) to an Enhanced device (i.e.,
PIC18CXXX).
The following are the list of modifications over the
PIC16CXXX microcontroller family:
Not Currently Available
APPENDIX F: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
This section discusses how to migrate from a High-end
device (i.e., PIC17CXXX) to an Enhance MCU device
(i.e., PIC18CXXX).
The following are the list of modifications over the
PIC17CXXX microcontroller family:
Not Currently Available
PIC18CXX2
DS39026B-page 286 Preliminary 7/99 Microchip Technology Inc.
NOTES:
7/99 Microchip Technology Inc. Preliminary DS39026B-page 287
PIC18CXX2
INDEX
A
A/D ................................................................................... 167
A/D Converter Flag (ADIF Bit) .................................169
A/D Converter Interrupt, Configuring .......................170
ADCON0 Register ....................................................167
ADCON1 Register . ...........................................167, 168
ADRES Register ..............................................167, 169
Analog Port Pins ..................................................89, 90
Analog Port Pins, Configuring ..................................171
Block Diag ram ............................. ...... ..................... ..169
Block Diagram, Analog Input Model .........................170
Configuring the Module ............................................170
Conversion Clock (TAD) ........................................... 171
Conversion Status (GO/DONE Bit) ................ ..........169
Conversions .............................................................172
Converter Characteristics ........................................270
converter charac te ristics ............. .......... ...... .............249
Effects of a Reset .....................................................179
Operation During Sleep ...........................................179
Sampling Requirements ........................ .. .. ....... .. .... ..170
Special Event Trigger (CCP) ............................112, 172
Timing Dia g r a m .......... ...... ........... ...... ..................... ..271
Absolute Maximum Ratings .............................................241
ADCON0 Register ............................................................167
GO/DONE Bit ...........................................................169
ADCON1 Register ....................................................167, 168
ADDLW ............................................................................197
ADDWF ............................................................................ 197
ADDWFC .........................................................................198
ADRES Register ......................................................167, 169
AKS ..................................................................................139
Analog-to-Digital Converter.
See
A/D
ANDLW ............................................................................198
ANDWF ............................................................................ 199
Assembler
MPASM Assembler ..................................................235
B
Baud Rate Generator .. .....................................................136
BCF ..................................................................................200
BF ....................................................................................139
Block Diagrams
Baud Rate Generator ...............................................136
SSP (SPI Mode) ............................................ ...........121
Timer1 ......................................................................106
BRG .................................................................................136
Brown-out Reset (BOR) .............................................24, 181
Timing Dia g r a m .......... ...... ........... ...... ..................... ..256
BSF ..........................199 , 200, 201, 202, 203, 205, 206, 221
BTFSC .............................................................................204
BTFSS .............................................................................204
BTG ..................................................................................205
Bus Collision During a RESTART Condition ................ ....148
Bus Collision During a Start Condition .............................146
Bus Collision During a Stop Condition .............................149
C
C ........................................................................................54
CALL ................................................................................206
Capture (CCP Module) ................................... .. ......... .... ..111
Block Diag ram ............................. ...... ..................... ..111
CCP Pin Configuration .............................................111
CCPR1H:CCPR1L Registers ...................................111
Changing Between Capture Prescalers ...................111
Softwar e In terrupt ........ ........... ...... ........... ...... .......... 111
Timer1 Mode Selection . ........................................... 111
Capture/Compare /PWM (CCP) ............ ........... ...... .......... 109
CCP1 ....................................................................... 110
CCPR1H Register ........ ...... ................. ............ 110
CCPR1L Register ............................................ 110
CCP2 ....................................................................... 110
CCPR2H Register ........ ...... ................. ............ 110
CCPR2L Register ............................................ 110
Interaction of Two CCP Modules ............................. 110
Timer Resources ..................................................... 110
Timing Dia g ram ... ...... ....... .......... ...... ..................... .. 258
Clocking Scheme ............................................................... 37
CLRF ....................................................................... 207, 225
CLRWDT ......................................................................... 207
Code Examples
Loading the SSPBUF register ................................. 122
Code Protection . . ..................................................... 181, 189
COMF .............................................................................. 208
Compare (CCP Module) ............................................ .... .. 112
Block Diag ram ... ...... ................................ ...... .......... 112
CCP Pin Configuration ............................................ 112
CCPR1H:CCPR1L Registers .................................. 112
Softwar e In terrupt ........ ........... ...... ........... ...... .......... 112
Special Event Trigger ........................ 99, 107, 112, 172
Timer1 Mode Selection . ........................................... 112
Configuration Bits ............................................................ 181
Conversion Considerations .............................................. 286
CPFSEQ .......................................................................... 208
CPFSGT .......................................................................... 209
CPFSLT ........................................................................... 209
D
Data Memor y ........... ..................... ...... ........... ...... .......... .... 40
General Purpose Registers ....................................... 40
Special Function Registers ........................................ 40
DAW ................................................................................ 210
DC ..................................................................................... 54
DC Characteristics ................................... 243, 244, 247, 248
DECF ............................................................................... 210
DECFSNZ ........................................................................ 211
DECFSZ .......................................................................... 211
Development Support ...................................................... 235
Device Differences ........................................................... 285
Direct Add ressing ....................... ...... .......... ....... .......... ...... 49
E
Electrical Characteristics ................................................. 241
Errata ................................................................................... 4
F
Firmware Instructions ...................................................... 191
FS0 .................................................................................... 54
FS1 .................................................................................... 54
FS2 .................................................................................... 54
FS3 .................................................................................... 54
G
General Call Address Sequence ..................................... 133
General Call Address Support ......................................... 133
GOTO .............................................................................. 212
I
I/O Ports ........... ........... ...... ........... ..................... ................ 77
I2C (SSP Module) ............................................................ 128
ACK Pulse ............... .. .... ..... .... .. .... .. .. ....... .... .. .. 129, 130
Addressing ............................................................... 129
PIC18CXX2
DS39026B-page 288 Preliminary 7/99 Microchip Technology Inc.
Block Diag ram ........... ..................... ....... ...................128
Read/Write Bit Information (R/W Bit) ...............129, 130
Reception ................................................................. 130
Serial Clock (RC3/SCK/SCL) ...................................130
Slave Mode ..............................................................129
Timing Diagram, Data ..............................................265
Timing Diagram, Start/Stop Bits ...............................264
Transmission ............................................................130
I2C Master Mode Reception .............................................139
I2C Master Mode Restart Condition .................................138
I2C Module
Acknowledge Sequence timing ................................142
Baud Rate Generator .. .............................................136
BRG Block Diagram .................................................136
BRG Reset due to SDA Collision .............................147
BRG Timing .............................................................136
Bus Collision
Acknowledge ....................................................145
Restart Condition ................. ......... .. .... .... .. .......148
Restart Condition Timing (Case1) ....................148
Restart Condition Timing (Case2) ....................148
Start Condition .................................. .... .. .... .....146
Start Condition Timing .............................146, 147
Stop Condition ............... ........... ...... .................149
Stop Condition Timing (Case1) ........................149
Stop Condition Timing (Case2) ........................149
Transmit Timing ......... ..................... ...... ...........145
Bus Collision timing ...... ...... ...... ...... ....... ............ .......145
Clock Arbitration .......................................................144
Clock Arbitration Timing (Master Transmit) ..............144
General Call Address Support .................................133
Master Mode 7-bit Reception timing ........................141
Master Mode Operation ...........................................135
Master Mode Start Condition ...................................137
Master Mode Transmission ......................................139
Master Mode Transmit Sequence ............................135
Multi-master Mode . ..................................................145
Repeat Start Condition timing ...... .. ....... .. .. .. .... .. .. .....138
Stop Condition Receive or Transmit timing ..............143
Stop Condition timing ........... ............................... .....142
Waveforms for 7-bit Reception ................................130
Waveforms for 7-bit Transmission ...........................130
ID Locations .............................................................181, 189
INCF .................................................................................212
INCFSNZ ..........................................................................213
INCFSZ ............................................................................213
In-Circuit Serial Programming (ICSP) ......................181, 189
Indirect Addressing ............................................................49
FSR Register .............................................................48
Instruction Cycle .................................................................37
Instruction Flow/Pipelining .................................................38
Instruction Format ............................................................193
Instruction Set ..................................................................191
ADDLW ....................................................................197
ADDWF .................................................................... 197
ADDWFC .................................................................198
ANDLW ....................................................................198
ANDWF .................................................................... 199
BCF .......................................................................... 200
BSF ..................199, 200, 201, 202, 203, 205, 206, 221
BTFSC .....................................................................204
BTFSS .....................................................................204
BTG ..........................................................................205
CALL ........................................................................206
CLRF ................................................................207, 225
CLRWDT ..................................................................207
COMF ...................................................................... 208
CPFSEQ .................................................................. 208
CPFSGT .................................................................. 209
CPFSLT ................................................................... 209
DAW ........................................................................ 210
DECF ....................................................................... 210
DECFSNZ ................................................................ 211
DECFSZ .................................................................. 211
GOTO ...................................................................... 212
INCF ........................................................................ 212
INCFSNZ ................................................................. 213
INCFSZ .................................................................... 213
IORLW ..................................................................... 214
IORWF ..................................................................... 214
MOVFP .................................................................... 216
MOVLB .................................................................... 215
MOVLR ............................................................ 215, 216
MOVLW ................................................................... 217
MOVWF ................................................................... 217
MULLW ....................................................................218
MULWF .................................................................... 218
NEGW ..................................................................... 219
NOP ......................................................................... 219
RETFIE ............................................................ 221, 222
RETLW .................................................................... 222
RETURN .................................................................. 223
RLCF ....................................................................... 223
RLNCF ..................................................................... 224
RRCF ....................................................................... 224
RRNCF .................................................................... 225
SLEEP ..................................................................... 226
SUBLW .................................................................... 227
SUBWF .................................................... 226, 227, 228
SUBWFB ................................................................. 229
SWAPF .................................................................... 230
TABLRD ..................................................................231
TABLWT .................................................................. 232
TSTFSZ ................................................................... 233
XORLW ................................................................... 233
XORWF ................................................................... 234
Summary Ta b l e ............... ...... ........... ...... ........... ......194
INTCON Register
RBIF Bit .. ...... ........... ...... ........... ...... .......... ................. 80
Interrupt Sources ....................................................... 65, 181
A/D Conversion Complete ....................................... 170
Capture Complete (CCP) ......................................... 111
Compare Complete (CCP) ....................................... 112
Interrupt on Change (RB7:RB4 ) ............................... 80
RB0/INT Pin, External ................................................ 75
SSP Receive/Transmit Complete ............................ 117
TMR0 Overflow .......................................................... 95
TMR1 Overflow .................................... 97, 99 , 105, 107
TMR2 to PR2 Match ................................................ 103
TMR2 to PR2 Match (PWM) ............................ 102, 115
USART Receive/Transmit Complete ............. ...... .... 151
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) .................... .... ..... .. .. .. .. 111
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) ................................. 169
CCP1 Flag (CCP1IF Bit) .................................. 111, 112
Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ........ 80
IORLW ............................................................................. 214
IORWF ............................................................................. 214
K
KeeLoq Evaluation and Programmi ng Tools ................ 238
7/99 Microchip Technology Inc. Preliminary DS39026B-page 289
PIC18CXX2
M
Memory Organization
Data Memor y ............. ..................... ...... ........... ...... ....40
Program Memory .......................................................33
MOVFP ............................................................................216
MOVLB ............................................................................215
MOVLR ....................................................................215, 216
MOVLW ...........................................................................217
MOVWF ...........................................................................217
MPLAB Integrated Development Environment Software .235
MULLW ............................................................................ 218
Multi-Master Mode . ..........................................................145
Multiply Examples
16 x 16 Routine ..........................................................62
16 x 16 Signed Routine ............................. .. ....... .. .. ....63
8 x 8 Routine ..............................................................62
8 x 8 Signed Routine ........................... .. .... .. ..... .. .... .. ..62
MULWF ............................................................................218
N
NEGW ..............................................................................219
NOP .................................................................................219
O
OPCODE Field Descriptions ............................................192
OPTION_R EG Re g i ster ..... ..................... ...... ........... ...... ....51
PS2:PS0 Bits .............................................................95
PSA Bit .......................................................................95
T0CS Bit .....................................................................95
T0SE Bit .....................................................................95
OSCCON ...........................................................................18
OSCCON Register .............................................................18
Oscillator Configuration ..............................................15, 181
HS .............................................................................. 15
LP ...............................................................................15
RC ........................................................................15, 16
XT ..............................................................................15
Oscillator, Timer1 ......................... ............. ...97, 99, 105, 107
Oscillat o r, WDT ................ ................. ................ ...............185
OV ......................................................................................54
P
Packaging ........................................................................275
Parallel Slave Port (PSP) .............................................85, 90
Block Diag ram ............................. ...... ..................... ....90
RE0/RD/AN5 Pin ..................................................89, 90
RE1/WR/AN6 Pin .................................................89, 90
RE2/CS/AN7 Pin ..................................................89, 90
Read Waveforms .......................................................91
Select (PSPMODE Bit) ........................................85, 90
Timing Dia g r a m .......... ...... ........... ...... ..................... ..259
Write Waveforms .......................................................90
PICDEM-1 Low-Cost PICmicro Demo Board ...................237
PICDEM-2 Low-Cost PIC16CXX Demo Board ................237
PICDEM-3 Low-Cost PIC16CXX X Demo Boar d ..............237
PICSTART Plus Entry Level Development System ......237
Pin Functions
MCLR/Vpp .............................................................8, 11
OSC1/CLKIN ..........................................................8, 11
OSC2/CLKOUT ......................................................8, 11
RA0/AN0 ................................................................8, 11
RA1/AN1 ................................................................8, 11
RA2/AN2 ................................................................8, 11
RA3/AN3/Vref ........................................................8, 11
RA4/T0CKI .............................................................8, 11
RA5/AN4/SS ..........................................................8, 11
RB0/INT ................................................................. 9, 12
RB1 ........................................................................ 9, 12
RB2 ........................................................................ 9, 12
RB3 ........................................................................ 9, 12
RB4 ........................................................................ 9, 12
RB5 ........................................................................ 9, 12
RB6 ........................................................................ 9, 12
RB7 ........................................................................ 9, 12
RC0/T1OSO/T1CKI ............................................. 10, 13
RC1/T1OSI/CCP2 ............................................... 10, 13
RC2/CCP1 ........................................................... 10, 13
RC3/SCK/SCL ..................................................... 10, 13
RC4/SDI/SDA ...................................................... 10, 13
RC5/SDO ............................................................. 10, 13
RC6/TX/CK .......................................................... 10, 13
RC7/RX/DT .......................................................... 10, 13
RD0/PSP0 ................................................................. 14
RD1/PSP1 ................................................................. 14
RD2/PSP2 ................................................................. 14
RD3/PSP3 ................................................................. 14
RD4/PSP4 ................................................................. 14
RD5/PSP5 ................................................................. 14
RD6/PSP6 ................................................................. 14
RD7/PSP7 ................................................................. 14
RE0/RD/AN5 ............................................................. 14
RE1/WR/AN6 ............................................................. 14
RE2/CS/AN7 .............................................................. 14
Vdd ...................................................................... 10, 14
Vss ....................................................................... 10, 14
Pointer, FSR ...................................................................... 48
PORTA
Initialization ................................................................ 77
PORTA Register ........................................................ 77
RA3:RA0 and RA5 Port Pins ..................................... 78
RA4/T0CKI Pin ...... ...... .......................................... .... 78
TRISA Register .......................................................... 77
PORTB
Initialization ................................................................ 80
PORTB Register ........................................................ 80
RB0/INT Pin, External ............................................... 75
RB3:RB0 Port Pins .................................................... 80
RB7:RB4 Interrupt on Change Flag (RBIF Bit) .......... 80
RB7:RB4 Port Pins .................................................... 80
TRISB Register .......................................................... 80
PORTC
Block Diag ram ... ...... ................................ ...... ............ 83
Initialization .................................................... 83, 85, 87
PORTC Register ........................................................ 83
RC3/SCK/SCL Pin ................................................... 130
RC7/RX/DT Pi n ............................ ...... ..................... 153
TRISC Register ................................................. 83, 151
PORTD .............................................................................. 90
Block Diag ram ... ...... ................................ ...... ............ 85
Parallel Slave Port (PSP) Function ............................ 85
PORTD Register ........................................................ 85
TRISD Regist e r ......................................................... 85
PORTE
Analog Port Pins .................................................. 89, 90
Block Diag ram ... ...... ................................ ...... ............ 87
PORTE Register ........................................................ 87
PSP Mode Select (PSPM OD E Bit) ...................... 85, 90
RE0/RD/AN5 Pin ................................................. 89, 90
RE1/WR/AN6 Pin ................................................ 89, 90
RE2/CS/AN7 Pin ................................................. 89, 90
TRISE Register .......................................................... 87
Postscaler, WDT
PIC18CXX2
DS39026B-page 290 Preliminary 7/99 Microchip Technology Inc.
Assignment (PSA Bit) ...... ...... ........... ...... .......... ....... ..95
Rate Select (PS2:PS0 Bits) .......................................95
Switching Between Timer0 and WDT ................. .......95
Power-on Reset (POR) ..............................................24, 181
Oscillator Start-up Timer (OST) ........ .................24, 181
Power-up Timer (PWRT) ...................................24, 181
Time-out Sequence ................ .... .. ....... .... .... .. .... .. .......25
Time-out Sequence on Power-up ............... .. .... ...30, 31
Timing Dia g r a m ............................ ....... .....................256
Presca le r, Capture ...... ...... ........... ...... ..................... ....... ..111
Presca le r, Timer0 ............ ................................ ...... ........... ..95
Assignment (PSA Bit) ...... ...... ........... ...... .......... ....... ..95
Rate Select (PS2:PS0 Bits) .......................................95
Switching Between Timer0 and WDT ................. .......95
Presca le r, Timer1 ............ ................................ ...... ........... ..98
Presca le r, Timer2 ............ ................................ ...... ...........115
PRO MA TE II Universal Programmer ............................237
Product Identification System ...........................................297
Program Counter
PCL Register ..............................................................37
PCLATH Register ..... ........... ...... ..................... ....... ....37
Program Memory ...............................................................33
Inter rupt Vecto r ......... ....... .......... ........... ...... ........... ....33
Reset Vec to r ..... ........... ...... .......... ..................... ....... ..33
Program Verification .........................................................189
Programming, Device Instructions ...................................191
PWM (CCP Module) .................................................... .....114
Block Diag ram ........... ..................... ....... ...................114
CCPR1H:CCPR1L Registers ...................................115
Duty Cycle ............. .......................................... ....... ..115
Example Frequencies/Resolutions ..........................116
Output Dia g ram ............ .......... ...... ..................... .......114
Period .......................................................................115
Set-Up for PWM Operation ......................................116
TMR2 to PR2 Match ........................................102, 115
Q
Q-Clock ............................................................................115
R
RCSTA Register
SPEN Bit ..................................................................151
Register File ...... .......... ...... ..................... ....... .....................40
Registers
SSPSTAT .................................................................118
T1CON
Diagram ...........................................................105
Section ............................................................. 105
Reset ..........................................................................23, 181
Timing Dia g r a m ............................ ....... .....................256
RETFIE ....................................................................221, 222
RETLW .............................................................................222
RETURN ..........................................................................223
Revision History ...............................................................285
RLCF ................................................................................223
RLNCF .............................................................................224
RRCF ...............................................................................224
RRNCF .............................................................................225
S
SCK ..................................................................................121
SDI ...................................................................................121
SDO .................................................................................121
SEEVAL Evaluation and Programming System ............238
Serial Clock, SCK .............................................................121
Serial Data In, SDI ...........................................................121
Serial Data Out, SDO .......................................................121
Simplified Block Diagram of On-Chip Reset Circuit ........... 23
Slave Select Synchronization .......................................... 125
Slave Select, SS .............................................................. 121
SLEEP ............................................................. 181, 187, 226
Softwar e Simulator (MPLAB-SIM) ........ ...... ........... .......... 236
Special Features of the CPU ................................... 175, 181
Special Function Registers ................................................ 40
SPI Master Mode ............................................................ 124
Serial Clock .............................................................. 121
Serial Data In ...........................................................121
Serial Data Out ........................................................ 121
Slave Select ............................................................. 121
SPI clock .................................................................. 124
SPI Mode ................................................................. 121
SPI Master/Slave Connection .......................................... 123
SPI Module
Master/Slave Connection ....... ....... .... .. .... .. .. ....... .... .. 123
Slave Mode ...................... .... ......... .. .... .... .... ......... .. .. 125
Slave Select Synchronization ..................................125
Slave Synch Timnig ................................................. 125
Slave Timing with CKE = 0 ......................................126
Slave Timing with CKE = 1 ......................................126
SS .................................................................................... 121
SSP .................................................................................. 117
Block Diagram (SPI Mode) ...................................... 121
SPI Mode ................................................................. 121
SSPBUF .................................................................. 124
SSPCON1 ............................................................... 119
SSPCON2 ............................................................... 120
SSPSR .................................................................... 124
SSPSTAT ................................................................ 118
TMR2 Output for Clock Shift ............................ 102, 103
SSP Module
SPI Master Mode ..................................................... 124
SPI Master./Slave Connection . ................................ 123
SPI Slave Mode .......................................................125
SSPCON1 ........................................................................ 119
SSPCON2 ........................................................................ 120
SSPOV ............................................................................ 139
SSPSTAT ........................................................................ 118
SSPSTAT Register
R/W Bit ............................................................ 129, 130
SUBLW ............................................................................ 227
SUBWF ............................................................ 226, 227, 228
SUBWFB ......................................................................... 229
SWAPF ............................................................................ 230
T
TABLRD ........................................................................... 231
TABLWT .......................................................................... 232
Timer Modules
Timer1
Block Diag ram .................................. ....... ...... ..106
Timer0 ................................................................................ 93
Clock Source Edge Select (T0SE Bit) . ...................... 95
Clock Source Select (T0CS Bit) ................................. 95
Overflow In terrupt ....................... ...... .......... ....... ........ 95
Timing Diagram ....................................................... 257
Timer1 ........................................................................ 97, 105
Block Diagram ........................................................... 98
Oscillator .............................................. 97, 99 , 105, 107
Overflow Interrupt ........ .... .. .. ....... .. .. .... . 97, 99, 105, 107
Special Event Trigger (CCP) ..................... 99, 107, 112
Timing Diagram ....................................................... 257
TMR1H Register ................................................ 97, 105
7/99 Microchip Technology Inc. Preliminary DS39026B-page 291
PIC18CXX2
TMR1L Register .................................................97, 105
Timer2
Block Diag ram ............................. ...... ..................... ..103
Postscaler.
See
Postscaler, Timer2
PR2 Register ....................................................102, 115
Prescaler.
See
Prescaler, T imer2
SSP Clock Shift ... .............................................102, 103
TMR2 Register .........................................................102
TMR2 to PR2 Match Interrupt ..................102, 103, 115
Timing Diagrams
Acknowledge Sequence Timing . ..............................142
Baud Rate Generator with Clock Arbitration ............136
BRG Reset Due to SDA Collision ............................147
Bus Collision
Start Condition Timing ................ .... .... ......... .. ..146
Bus Collision During a Restart Condition (Case 1) ..148
Bus Collision During a Restart Condition (Case2) ...148
Bus Collision During a Start Condition (SCL = 0) ....147
Bus Collision During a Stop Condition ................... ..149
Bus Collision for Transmit and Acknowledge ...........145
I2C Bus Data ............................................................267
I2C Master Mode First Start bit timing ......................137
I2C Master Mode Reception timing ..........................141
I2C Master Mode Transmission timing .....................140
Master Mode Transmit Clock Arbitration ..................144
Repeat Start Condition .................. .. .. .... .. .. .. ....... .. .. ..138
Slave Synchronization .............................................125
SPI Mode Timing (Master Mode)SPI Mode
Master Mode Timing Diagram .........................124
SPI Mode Timing (Slave Mode with CKE = 0) .........126
SPI Mode Timing (Slave Mode with CKE = 1) .........126
Stop Condition Receive or Transmit ........................143
Time-out Sequence on Power-up ...................... ..30, 31
USART Asynch ronous Mas ter Transm ission ...........158
USART Asynchronous Reception ............................160
USART Synchronous Reception ..............................164
USART Synchronous Transmission ........................162
Wake - u p from SLEEP via In t e r ru p t ...... .. ..................188
Timing Diagrams and Specifications .............................. ..253
A/D Conversion ........ ............................... ....... ..........271
Brown-out Reset (BOR) ...........................................256
Capture/Compare/PWM (CCP) ................................258
CLKOUT and I/O ......................................................255
External Clock ..........................................................253
I2C Bus Data ............................................................265
I2C Bus Start/Stop Bits .............................................264
Oscillator Start-up Timer (OST) ...............................256
Parallel Slave Port (PSP) .........................................259
Power-up Tim e r ( PWRT) ............ ...... .......... ....... ......256
Reset ........................................................................256
Timer0 and Timer1 ...................................................257
USART Synchro nous Receive ( Master/ Slave) .......269
USART SynchronousTransmission ( Master/Slave) 268
Watchdog Timer (WDT) .............................. ........... ..256
TRISE Register ..................................................................87
PSPMODE Bit ......................................................85, 90
TSTFSZ ...........................................................................233
TXSTA Register
BRGH Bit .................................................................153
U
Universal Synchronous Asynchronous Receiver Transmitter.
See
USART
USART .............................................................................151
Asynchronous Mode ................................... .............157
Master Transmission .......................................158
Receive Block Diagram ................................... 159
Reception ........................................................ 160
Transmit Block Diagram .................................. 157
Baud Rate Generator (BRG) ................................... 153
Baud Rate Error, Calculating ........................... 153
Baud Rate Formula ......................................... 153
Baud Rates, Asynchronous Mode (B RG H=0) . 155
Baud Rates, Asynchronous Mode (B RG H=1) . 156
Baud Rates, Synchronous Mode ..................... 154
High Baud Rate Select (BRGH Bit) ................. 153
Sampling ......................................................... 153
Serial Port Enable (SPEN Bit) ................................. 151
Synchronous Master Mode ...................................... 161
Reception ........................................................ 164
Timing Diagram, Synchronous Receive .......... 269
Timing Diagram, Synchronous Transmission .. 268
Transmission ................................................... 162
Synchronous Slave Mode ............................ .. .... .... .. 165
W
Wake-up from SLEEP .............................................. 181, 187
Timing Dia g ram ... ...... ....... .......... ...... ..................... .. 188
Watchdog Timer (WDT) .................. .... .... .... ......... .... 181, 185
Block Diag ram ... ...... ................................ ...... .......... 186
Programming Considerations .................................. 185
RC Oscillator ........................................................... 185
Time-o u t Pe riod ..... ........... .......... ...... ........... .......... .. 185
Timing Dia g ram ... ...... ....... .......... ...... ..................... .. 256
Waveform for General Call Address Seq uence ............... 133
WCOL .............................................................. 137, 139, 142
WCOL Status Flag ........................................................... 137
WWW, On-Line Support ...................................................... 4
X
XORLW ........................................................................... 233
XORWF ........................................................................... 234
Z
Z ........................................................................................ 54
PIC18CXX2
DS39026B-page 292 Preliminary 7/99 Microchip Technology Inc.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 293
PIC18CXX2
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Connecting to the Microchip Internet Web Site
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vice to connect to:
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981103
PIC18CXX2
DS39026B-page 294 Preliminary 7/99 Microchip Technology Inc.
READER RESPONSE
It is our i ntention to provide you w ith the bes t d ocu me nta t io n po ss ible to ensure suc ce ss ful us e of your Microchi p pro d-
uct. If you wish to provide your comments on organization, clarity, subject matter , and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to fo llow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
To: Technical Publications Manager
RE: Reader Response Total Pages Sent
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DS39026B
PIC18CXX2 Literature Number:
1999 Microchip Technology Inc. Preliminary DS39026B-page 295
PIC18CXX2
PIC18CXX2 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC18CXX2(1), PIC18CXX2T(2);
VDD range 4.2V to 5.5V
PIC18LCXX2(1), PIC18LCXX2T(2);
VDD range 2.5V to 5.5V
Temperature
Range I= -40°C to+85×C(Industrial)
E= -40°C to+125×C(Extended)
Package JW = Windowed CERDIP(3)
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny plastic dip
P=PDIP
L=PLCC
Pattern QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC18LC452 - I/P 301 = Industrial
temp., PDIP package, 4 MHz,
Extended VDD limits, QTP pattern
#301.
b) PIC18LC242 - I/SO = Industrial
temp., SOIC package, Extended
VDD limits.
c) PIC18C442 - E/P = Extended temp.,
PDIP package, 40MHz, normal VDD
limits.
Note1: C = Standard Voltage range
LC = Wide Voltage Range
2: T = in tape and reel - SOIC,
PLCC, and TQFP
packages only.
3: JW Devices are UV erasable and
can be p r og r am m ed to any dev ic e
configuration. JW Devices meet
the elect ric al requirement of each
oscillator type (including LC
devices).
Data Sheets
Products supported b y a preliminary Data Sheet may hav e an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a par ticular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Information cont ai ned in this publication reg ardi ng device appl ications and the l ike is intended for suggestion onl y and m ay be supers eded by updates . No repr esentation or warranty is given and no liability is assumed
by Microchip Technology Incorpora ted with respect to the accuracy or us e of such informa tion, or infringe ment of patents or ot her intell ectual proper ty rights arising fr om such use or otherwi se. Use of Microc hip’s pro ducts
as critical c om ponents in life s upport system s i s no t authorized exc ept with express written approval by Mi cro chip. No licens es are conveyed, implicitly or otherw ise, under any in tellectual pro perty rights. The M i crochip
logo and name are registered trade ma rks of Mi cr ochip Technology Inc. in the U.S.A. and other countries. All rig hts reserved. All other trademarks mentione d herein are the property of t hei r res pective comp ani es .
1999 Microchip Technology Inc.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper.
AMERICAS
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AMERICAS (continued)
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ASIA/PACIFIC (continued)
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11/15/99
WORLDWIDE SALES AND SERVICE
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchips quality
system for the design and manufacture of
development systems is ISO 9001 certified.