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DESCRIPTION…
The SP7512 and HS3120 are precision 12-bit multiplying DACs, double–buffered for easy
interfacing with microprocessor busses. Both unipolar and bipolar operation can be accommo-
dated with a minimum of external components. The SP7512 is available for use in commercial
and industrial temperature ranges, packaged in a 28-pin SOIC. The HS3120 is available in
commercial and military temperature ranges, packaged in a 28–pin side–brazed DIP.
■Monolithic Construction
■12–Bit Resolution
■0.01% Non-Linearity
■Four–Quadrant Multiplication
■Latch-up Protected
■Low Power – 30mW
■ Single +15V Power Supply
910 1112
(MSB)
Bit 1 234
13 14 15 16
5678
17 18 19 20
91011
(LSB)
BIT 12
2
LDTR
28
V
26
DD1 VDD2
27
GND
8
GND
SP7512, HS3120
4
VREF
22
CE
25
HBE
24
MBE
23
LBE
21
LDAC
5
6
7
1
3
FB1
I01
I02
FB4
FB3
R/2R/2
R
DAC REGISTER 12 BIT MDAC
INPUT REGISTERINPUT REGISTERINPUT REGISTER
CONTROL
LOGIC
SP7512 and HS3120
Double–Buffered 12-Bit Multiplying DAC
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SPECIFICATIONS
(Typical @ 25 °C, nominal power supply, V REF = +10V, unipolar, unless otherwise noted)
PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
DIGITAL INPUT
Resolution 12 Bits
2–Quad, Unipolar Coding Binary & Comp. Binary The input coding is comple-
mentary binary if I02 is used.
4–Quad, Bipolar Coding Offset Binary
Logic Compatibility CMOS, TTL Digital input voltage must not
exceed supply voltage or go
below –0.5V ; “0” <0.8V;
2.4V < “1” ≤VDD
Input Current ±1µA
Data Set-up Time 250 ns All strobes are level triggered.
See Timing Diagram; GBD*
Strobe Width 250 ns All strobes are level triggered.
See Timing Diagram; GBD*
Data Hold Time 0 ns All strobes are level triggered.
See Timing Diagram; GBD*
REFERENCE INPUT
Voltage Range ±25 V
Input Impedance 4 12 KOhms
ANALOG OUTPUT
Scale Factor 62.5 187.5 µA/VREF
Scale Factor Accuracy ±0.4 % Using the internal feedback
resistor and an external op
amp.
Output Leakage 10 nA At 25°C; the output leakage
current will create an offset
voltage at the external op amps
output. It doubles every 10°C
temperature increase.
Output Capacitance
COUT 1, all inputs high 80 pF
COUT 1, all inputs low 40 pF
COUT 2, all inputs high 40 pF
COUT 2, all inputs low 80 pF
STATIC PERFORMANCE
Integral Linearity
SP7512BN/KN, HS3120–2 ±0.015 % FSR
Differential Linearity
SP7512BN/KN, HS3120–2 ±0.024 %FSR
Monotonicity
SP7512BN/KN, HS3120–2 Guaranteed to 12 bits
STABILITY (TMIN to TMAX)
Scale Factor 2 ppm FSR/°C Note 1
Integral Linearity 0.2 ppm FSR/°C
Differential Linearity 0.2 ppm FSR/°C
STABILITY (TMIN to TMAX)
Monotonicity Temp. Range
SP7512KN, HS3120C–_ 0 +70 °C
SP7512BN –40 +85 °C
HS3120B–_ –55 +125 °C
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SPECIFICATIONS (continued)
(Typical @ 25°C, nominal power supply, VREF = +10V, unipolar unless otherwise noted)
PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
DYNAMIC PERFORMANCE
Digital Small Signal Settling 1.0 µS
Full Scale Transition Settling 2.0 µS to 0.01% (strobed)
Reference Feedthrough Error (VREF = 20Vpp)
@ 1kHz <1 mV
@ 10kHz 2 mV
Delay to output
from Bits input 100 ns Delay times are twice the
from LDAC 200 ns amount shown at TA = +125° C
from CE 120 ns
POWER SUPPLY (VDD)
Operating Voltage +15 ±5% V specifications guaranteed
Voltage Range +5 +16 V
Current 2.5 mA
Rejection Ratio 0.002 %/%
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
SP7512K 0 +70 °C
SP7512B –40 +85 °C
HS3120–C 0 +70 °C
HS3120–B –55 +125 °C
HS3120–B/883 –55 +125 °C
Storage Temperature –65 +150 °C
Package
SP7512_N 28-pin SOIC
HS3120–C 28–pin Plastic DIP
HS3120–B 28–pin Side–Brazed DIP
Notes:
1. Using the internal feedback resistor, output leakage current creates an offset, which doubles every
10°C rise in temperature.
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Figure 1. Unipolar Operation
PIN ASSIGNMENTS
Pin 1 – FB4 – Feedback Bipolar Operation
Pin 2 – LDTR – Ladder Termination
Pin 3 – FB3 – Feedback Bipolar Operation
Pin 4 – VREF – Reference Voltage Input
Pin 5 – FB1 – Feedback, Unipolar/Bipolar
Pin 6 – IO1 – Current out into virtual ground
Pin 7 – IO2 – Current out-complement of I01
Pin 8 – VSS – Ground, Analog and DAC Register
Pin 9 – DB11 – MSB, Data Bit 1
Pin 10 – DB10 – Data Bit 2
Pin 11 – DB9 – Data Bit 3
Pin 12 – DB8 – Data Bit 4
Pin 13 – DB7 – Data Bit 5
Pin 14 – DB6 – Data Bit 6
Pin 15 – DB5 – Data Bit 7
Pin 16 – DB4 – Data Bit 8
Pin 17 – DB3 – Data Bit 9
Pin 18 – DB2 – Data Bit 10
Pin 19 – DB1 – Data Bit 11
Pin 20 – DB0 – LSB, Data Bit 12
Pin 21 – LDAC – Transfers data from input to
DAC register; a logic “0” latches data into
registers; a logic “1” allows data to change
(transfer to) register.
Pin 22 – CE – Chip Enable, active low
Pin 23 – LBE – Bit 12 to Bit 9 Enable
Pin 24 – MBE – Bit 8 to Bit 5 Enable
Pin 25 – HBE – Bit 4 to Bit 1 Enable
Pin 26 – VDD2 – Supply Analog and DAC
Register
Pin 27 – V SS1 – Ground input latches
Pin 28 – V DD1 – Supply input latches
NOTE: Pins 8 and 27, and pins 26 and 28 must
be connected externally.
FEATURES…
The SP7512 and HS3120 are precision 12-bit
multiplying DACs with internal two-stage input
storage registers for easy interfacing with mi-
croprocessor busses. The DACs are implemented
as a one-chip CMOS circuit with a resistor
ladder network designed for 0.01% linearity
without laser trimming.
The input registers are sectioned into 3 seg-
ments of 4 bits each, all individually address-
able. The DAC-register, following the input
registers, is a parallel 12-bit register for holding
the DAC data while the input registers are up-
dated. Only the data held in the DAC register
determines the analog output value of the con-
verter.
The SP7512 and HS3120 have been designed
for great flexibility in connecting to bus-ori-
ented systems. The 12 data inputs are organized
into 3 independent addressable 4-bit input reg-
isters such that the DACs can be connected to
either a 4, 8 or 16-bit data bus. The control logic
of the DACs includes chip enable and latch
enable inputs for flexible memory mapping. All
controls are level-triggered to allow static or
dynamic operation.
A total of 5 output lines are provided on the
DACs to allow unipolar and bipolar output
connection with a minimum of external compo-
nents. The feedback resistor is internal. The
resistor ladder network termination is exter-
nally available, thus eliminating an external
resistor for the 1 LSB offset in bipolar mode.
The SP7512 is available for use in commercial
and industrial temperature ranges, packaged in
VREF VDD2
400
VDD1
+15V
DIGITAL
INPUTS
FB1
IO1
LDTR +
-
IO2
FB4
FB3
VSS1
VSS
ROS
AVOUT
CE
HBE
MBE
LBE
LDAC
SP7512
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Figure 2. Bipolar Operation
TRANSFER FUNCTION (N=12)
BINARY INPUT UNIPOLAR OUTPUT BIPOLAR OUTPUT
111...111 –VREF (1 – 2–N)–V
REF (1 – 2 –(N – 1))
100...001 –VREF (1/2 + 2–N)–V
REF (2 –(N – 1))
100...000 –VREF /2 0
011...111 –VREF (1/2 – 2–N)V
REF (2 –(N – 1))
000...000 0 VREF
VREF VDD2
400Ω
VDD1
+15V
DIGITAL
INPUTS
FB1
IO1 +
-
IO2
FB4
FB3
VSS1
VSS
ROS1
AVOUT
CE
HBE
MBE
LBE
LDAC
SP7512 1
+
-A2
ROS2
VOUT1
A1, A2, LF411ACN
4KΩ
LDTR
3KΩ1KΩ
N.C.
N.C.
-15V +15V
20KΩ
4MΩ
ADJUSTMENT
RANGE 0.2%
a 28–pin SOIC. The HS3120 is available in
commercial and military temperature ranges,
packaged in a 28–pin side–brazed DIP. For
product processed and screened to the require-
ments of MIL–M–38510 and MIL–STD–883C,
please consult the factory (HS3120B only).
Table 1. Transfer Function
APPLICATIONS INFORMATION
Unipolar Operation
Figure 1 shows the interconnections for unipo-
lar operation. Connect IO1 and FB1 as shown in
diagram. Tie IO2 (Pin 7), FB3 (Pin 3), and FB4
(Pin 1) to Ground (Pin 8). To maintain specified
linearity, external amplifiers must be zeroed.
This is best done with VREF set to zero and, with
the DAC register loaded with all bits at zero,
adjust ROS for VOUT = 0V
Bipolar Operation
Figure 2 shows the interconnections for bipolar
operation. Connect IO1, IO2, FB1, FB3, FB4 as
shown in diagram. Tie LDTR to I O2. To main-
tain specified linearity, external amplifiers must
be zeroed. This is best done with VREF set to zero
and, the DAC register loaded with 10...0 (MSB
= 1), set ROS2 for VOUT1 = 0V. Then set ROS1 for
VOUT = 0V.
Grounding
Connect all GND pins to system analog ground
and tie this to digital ground. All unused input
pins must be grounded.
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TIMING
INPUT
DATA
t2
t3
t1
t1
t2
t3
CE
LBE
MBE
HBE
LDAC
OUTPUT
t2
t4
TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED.
t
1
: Data Setup Time, Time data must be stable before strobe (byte enable/
LDAC) goes to “0”, t
1
(min) = 250ns.
t
2
: Strobe Width. t
2
(min) = 250ns. (CE, LBE, MBE, HBE, LDAC).
t
3
: Hold Time. Time data must be stable after strobe goes to “0”, t
3
= 0ns.
t
4
: Delay from LDAC to Output, t
4
= 200ns.
NOTE: Minimum common active time for CE and any byte enable is 250ns.
ORDERING INFORMATION
Model .................................................................. Monotonicity ................................. Temperature Range........................................ Package
Double–Buffered 12–Bit Multiplying DAC
SP7512BN ............................................................... 12–Bit ......................................... –40°C to +85°C ......................................28-pin, 0.3" SOIC
SP7512KN ............................................................... 12–Bit .............................................. 0°C to +70°C ......................................28-pin, 0.3" SOIC
HS3120C–2N ........................................................... 12–Bit .............................................. 0°C to +70°C ............................ 28-pin, 0.6" Plastic DIP
HS3120C–2Q ........................................................... 12–Bit .............................................. 0°C to +70°C .................. 28-pin, 0.6" Side–Brazed DIP
HS3120B–2Q ........................................................... 12–Bit ....................................... –55°C to +125°C .................. 28-pin, 0.6" Side–Brazed DIP
HS3120B–2/883 ...................................................... 12–Bit ....................................... –55°C to +125°C .................. 28-pin, 0.6" Side–Brazed DIP
