SCLS199B - MARCH 1993 - REVISED APRIL 1996 D EPIC (Enhanced-Performance Implanted D D D OE 1D 2D 3D 4D 5D 6D 7D 8D GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK SN54LV574 . . . FK PACKAGE (TOP VIEW) description 3D 4D 5D 6D 7D These octal edge-triggered D-type flip-flops are designed for 2.7-V to 5.5-V VCC operation. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND CLK 8Q 7Q The 'LV574 feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. OE VCC 1Q D CMOS) 2- Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs 2D 1D D SN54LV574 . . . J OR W PACKAGE SN74LV574 . . . DB, DW, OR PW PACKAGE (TOP VIEW) On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74LV574 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LV574 is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV574 is characterized for operation from -40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated !"#$% !%&% %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# )$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/, ("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++ )&(&#$$(, * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 1 SCLS199B - MARCH 1993 - REVISED APRIL 1996 FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L H H L L L L H or L X Q0 H X X Z logic symbol OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 logic diagram (positive logic) EN OE C1 1D 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 CLK 1 11 1Q C1 2Q 1D 3Q 2 19 1Q 1D 4Q 5Q 6Q To Seven Other Channels 7Q 8Q This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for DB, DW, J, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. 2 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * SCLS199B - MARCH 1993 - REVISED APRIL 1996 recommended operating conditions (see Note 4) SN54LV574 VCC Supply voltage MIN MAX MIN MAX 2.7 5.5 2.7 5.5 VIH High-level input voltage VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VI VO Input voltage 0 Output voltage 0 IOH High-level output current VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V IOL Low-level output current VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V t /v Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. SN74LV574 2 2 3.15 3.15 0.8 0.8 1.65 0 0 V V 1.65 VCC VCC UNIT VCC VCC -8 -8 -16 -16 8 8 16 16 V V V mA mA 0 100 0 100 ns / V -55 125 -40 85 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH IOH = - 100 A IOH = - 8 mA MIN to MAX IOH = - 16 mA IOL = 100 A VOL VCC TEST CONDITIONS SN54LV574 MIN TYP II VI = VCC or GND IOZ VO = VCC or GND ICC VI = VCC or GND, nICC One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND Co VO = VCC or GND MIN TYP 3V VCC - 0.2 2.4 VCC - 0.2 2.4 4.5 3.6 3.6 MIN to MAX IOL = 8 mA IOL = 16 mA SN74LV574 MAX MAX V 0.2 0.2 3V 0.4 0.4 4.5 V 0.55 0.55 3.6 V 1 1 5.5 V 1 1 3.6 V 5 5 5.5 V 5 5 3.6 V 20 20 5.5 V 20 20 3 V to 3.6 V 500 500 IO = 0 UNIT 3.3 V 2.5 2.5 5V 3 3 3.3 V 7 7 5V 10 10 V A A A A A A A pF pF For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. %'(#&% !%!$(% )("! % $ '(#&1$ ( $0% )&$ ' $1$+)#$%, &(&!$(! && &% $( )$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$, * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 3 SCLS199B - MARCH 1993 - REVISED APRIL 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN54LV574 VCC = 5 V 0.5 V MIN fclock tw Clock frequency tsu Setup time before CLK th Hold time, data after CLK MAX VCC = 3.3 V 0.3 V MIN 50 Pulse duration, CLK high or low High or low MAX VCC = 2.7 V MIN 40 UNIT MAX 30 MHz 8 12 14 ns 5 8 9 ns 4 3 3 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN74LV574 VCC = 5 V 0.5 V MIN fclock tw Clock frequency tsu Setup time before CLK th Hold time, data after CLK MAX VCC = 3.3 V 0.3 V MIN 50 Pulse duration, CLK high or low High or low MAX VCC = 2.7 V MIN 40 UNIT MAX 30 MHz 8 12 14 ns 5 8 9 ns 4 3 3 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LV574 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V 0.5 V MIN TYP MAX fmax 50 tpd CLK Q ten OE tdis OE VCC = 3.3 V 0.3 V MIN TYP MAX 70 40 50 VCC = 2.7 V MIN MAX 30 UNIT MHz 12 17 17 24 26 ns Q 11 17 16 22 25 ns Q 14 19 18 27 28 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74LV574 FROM (INPUT) TO (OUTPUT) tpd CLK Q 12 17 17 24 26 ns ten OE Q 11 17 16 22 25 ns tdis OE Q 14 19 18 27 28 ns PARAMETER VCC = 5 V 0.5 V MIN TYP MAX fmax 50 VCC = 3.3 V 0.3 V MIN TYP MAX 70 40 %'(#&% !%!$(% )("! % $ '(#&1$ ( $0% )&$ ' $1$+)#$%, &(&!$(! && &% $( )$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$, 4 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 50 VCC = 2.7 V MIN MAX 30 UNIT MHz SCLS199B - MARCH 1993 - REVISED APRIL 1996 operating characteristics, TA = 25C PARAMETER TEST CONDITIONS VCC Outputs enabled Cpd Outputs enabled CL = 50 pF, Outputs disabled * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * UNIT 40 3.3 V Outputs disabled Power dissipation capacitance per flip-flop TYP 22 f = 10 MHz pF 44 5V 24 5 SCLS199B - MARCH 1993 - REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION S1 1 k From Output Under Test Vz Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Vz GND 1 k WAVEFORM CONDITION Vm Vi Vz LOAD CIRCUIT VCC = 4.5 V to 5.5 V 0.5 x VCC VCC 2 x VCC VCC = 2.7 V to 3.6 V 1.5 V 2.7 V 6V Vi Vm Timing Input 0V tw tsu Vi Input Vm th Vi Vm Vm Data Input Vm 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Vi Vm Input 0V Vm Vm VOL Output tPLH tPHL Output Waveform 2 S1 at GND (see Note B) VOH Vm 0V tPLZ Output Waveform 1 S1 at Vz (see Note B) VOH Output Vm Vm tPZL tPHL tPLH Vi Output Control Vm Vm VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Vm tPZH 0.5 x Vz VOL + 0.3 V VOL tPHZ Vm VOH - 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV574DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI SN74LV574DBR OBSOLETE SSOP DB 20 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) SN74LV574DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74LV574DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74LV574PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI SN74LV574PWR OBSOLETE TSSOP PW 20 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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