 
   
  
SCLS199B − MARCH 1993 − REVISED APRIL 1996
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
DEPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
DTypical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
DESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
DLatch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
DPackage Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These octal edge-triggered D-type flip-flops are
designed for 2.7-V to 5.5-V VCC operation.
The ’LV574 feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data
(D) inputs.
A buffered output-enable ( O E) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not af fect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN74LV574 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV574 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV574 is characterized for operation from −40°C to 85°C.
Copyright 1996, Texas Instruments Incorporated
    !"#$% !%&% 
 %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# 
)$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/,
("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++
)&(&#$$(,
EPIC is a trademark of Texas Instruments Incorporated.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q V
1Q
8D
GND
CLK
SN54LV574 . . . FK PACKAGE
(TOP VIEW)
CC
SN54LV574 ...J OR W PACKAGE
SN74LV574 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
 
   
  
SCLS199B − MARCH 1993 − REVISED APRIL 1996
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLK D
OUTPUT
Q
LH H
LLL
LH or L X Q0
H X X Z
logic symbollogic diagram (positive logic)
OE
1D
2
1D 3
2D 4
3D 5
4D 6
5D
11
CLK
1Q
19
2Q
18
3Q
17
4Q
16
5Q
15
6Q
14
7Q
13
8Q
12
7
6D 8
7D 9
8D
EN
1OE
CLK
1D 1Q
1
11
219
To Seven Other Channels
1D
C1
C1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for DB, DW, J, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) 0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) 0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3):DB package 0.6 W. . . . . . . . . . . . . . . . . . .
DW package 1.6 W. . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
 
   
  
SCLS199B − MARCH 1993 − REVISED APRIL 1996
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
recommended operating conditions (see Note 4)
SN54LV574 SN74LV574
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2.7 5.5 2.7 5.5 V
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V 2 2
V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 3.15 3.15 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V 0.8 0.8
V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 1.65 1.65 V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
IOH
High-level output current
VCC = 2.7 V to 3.6 V −8 −8
mA
IOH High-level output current VCC = 4.5 V to 5.5 V −16 −16 mA
IOL
Low-level output current
VCC = 2.7 V to 3.6 V 8 8
mA
IOL Low-level output current VCC = 4.5 V to 5.5 V 16 16 mA
t/vInput transition rise or fall rate 0 100 0 100 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
SN54LV574 SN74LV574
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX MIN TYP MAX
UNIT
IOH = −100 µAMIN to MAX VCC − 0.2 VCC − 0.2
V
OH
IOH = − 8 mA 3 V 2.4 2.4 V
VOH
IOH = − 16 mA 4.5 3.6 3.6
V
IOL = 100 µAMIN to MAX 0.2 0.2
V
OL
IOL = 8 mA 3 V 0.4 0.4 V
VOL
IOL = 16 mA 4.5 V 0.55 0.55
V
II
VI = VCC or GND
3.6 V ±1±1
A
IIVI = VCC or GND 5.5 V ±1±1µA
IOZ
VO = VCC or GND
3.6 V ±5±5
A
IOZ VO = VCC or GND 5.5 V ±5±5µA
ICC
VI = VCC or GND,
IO = 0
3.6 V 20 20
A
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 µA
nICC One input at VCC − 0.6 V,
Other inputs at VCC or GND 3 V to 3.6 V 500 500 µA
Ci
VI = VCC or GND
3.3 V 2.5 2.5
pF
CiVI = VCC or GND 5 V 3 3 pF
Co
VO = VCC or GND
3.3 V 7 7
pF
C
o
V
O
= V
CC
or GND
5 V 10 10
pF
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
  %'(#&% !%!$(% )("! % $ '(#&1$ (
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)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 
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 
   
  
SCLS199B − MARCH 1993 − REVISED APRIL 1996
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV574
VCC = 5 V
± 0.5 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 50 40 30 MHz
twPulse duration, CLK high or low 8 12 14 ns
tsu Setup time before CLKHigh or low 5 8 9 ns
thHold time, data after CLK4 3 3 ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN74LV574
VCC = 5 V
± 0.5 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 50 40 30 MHz
twPulse duration, CLK high or low 8 12 14 ns
tsu Setup time before CLKHigh or low 5 8 9 ns
thHold time, data after CLK4 3 3 ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LV574
PARAMETER FROM
TO
VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT
PARAMETER
MIN TYP MAX MIN TYP MAX MIN MAX
UNIT
fmax 50 70 40 50 30 MHz
tpd CLK Q12 17 17 24 26 ns
ten OE Q 11 17 16 22 25 ns
tdis OE Q 14 19 18 27 28 ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN74LV574
PARAMETER FROM
TO
VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT
PARAMETER
MIN TYP MAX MIN TYP MAX MIN MAX
UNIT
fmax 50 70 40 50 30 MHz
tpd CLK Q12 17 17 24 26 ns
ten OE Q 11 17 16 22 25 ns
tdis OE Q 14 19 18 27 28 ns
  %'(#&% !%!$(% )("! % $ '(#&1$ (
$0% )&$ ' $1$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 
!&%0$ ( !%%"$ $$ )("! ." %!$,
 
   
  
SCLS199B − MARCH 1993 − REVISED APRIL 1996
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Outputs enabled
3.3 V
40
Cpd
Power dissipation capacitance per flip-flop
Outputs disabled
CL = 50 pF,
f = 10 MHz
3.3 V
22
pF
Cpd
Power dissipation capacitance per flip-flop
Outputs enabled
C
L
= 50 pF,
f = 10 MHz
5 V
44
pF
Outputs disabled
5 V
24
 
   
  
SCLS199B − MARCH 1993 − REVISED APRIL 1996
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
Vm
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
V
zOpen
GND
1 k
1 k
Data Input
Timing Input Vm
Vi
0 V
VmVm
Vi
0 V
Vi
0 V
VmVm
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VmVm
Vi
0 V
Vm
Vm
Input
Vm
Output
Control
Output
Waveform 1
S1 at Vz
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
Vm
Vm
0.5 × Vz
0 V
VmVOL + 0.3 V
VmVOH − 0.3 V
[ 0 V
Vi
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
Vz
GND
TEST S1
0.5 ×VCC
VCC
2 ×VCC
1.5 V
2.7 V
6 V
WAVEFORM
CONDITION VCC = 4.5 V
to 5.5 V VCC = 2.7 V
to 3.6 V
Vm
Vi
Vz
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV574DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI
SN74LV574DBR OBSOLETE SSOP DB 20 TBD Call TI Call TI
SN74LV574DW OBSOLETE SOIC DW 20 TBD Call TI Call TI
SN74LV574DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI
SN74LV574PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI
SN74LV574PWR OBSOLETE TSSOP PW 20 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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