SCLS199B − MARCH 1993 − REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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DEPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
DTypical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
DESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
DLatch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
DPackage Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These octal edge-triggered D-type flip-flops are
designed for 2.7-V to 5.5-V VCC operation.
The ’LV574 feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data
(D) inputs.
A buffered output-enable ( O E) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not af fect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN74LV574 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV574 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV574 is characterized for operation from −40°C to 85°C.
Copyright 1996, Texas Instruments Incorporated
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EPIC is a trademark of Texas Instruments Incorporated.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q V
1Q
8D
GND
CLK
SN54LV574 . . . FK PACKAGE
(TOP VIEW)
CC
SN54LV574 ...J OR W PACKAGE
SN74LV574 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.