1. General description
The PCA9538 is a 16-pin CMOS device that provides 8 bits of General Purpose parallel
Input/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applications
and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders.
I/O expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push-buttons, LEDs, fans, etc.
The PCA9538 consists of an 8-bit Configuration register (input or output selection),
8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register
(active HIGH or active LOW operation). The system master can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output
is kept in the corresponding Input Port or Output Port register. The polarity of the Input
Port register can be inverted with the Polarity Inversion register. All registers can be read
by the system master.
The PCA9538 is identical to the PCA9554 except for the removal of the internal I/O pull-up
resistor which greatly reduces power consumption when the I/Os are held LOW,
replacement of A2 with RESET and different address range.
The PCA9538 open-drain interrupt output (INT) is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed. The power-on reset sets the registers to their
default values and initializes the device state machine. The RESET pin causes the same
reset/initialization to occur without de-powering the device.
Two hardware pins (A0 and A1) vary the fixed I2C-bus address and allow up to four
devices to share the same I2C-bus/SMBus.
2. Features
n8-bit I2C-bus GPIO with interrupt and reset
nOperating power supply voltage range of 2.3 V to 5.5 V
n5 V tolerant I/Os
nPolarity Inversion register
nActive LOW interrupt output
nActive LOW reset input
nLow standby current
nNoise filter on SCL/SDA inputs
nNo glitch on power-up
nInternal power-on reset
PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and
reset
Rev. 05 — 28 May 2009 Product data sheet
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 2 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
n8 I/O pins which default to 8 inputs
n0 Hz to 400 kHz clock frequency
nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
nOffered in three different packages: SO16, TSSOP16 and HVQFN16
3. Ordering information
4. Block diagram
Table 1. Ordering information
T
amb
=
40
°
C to +85
°
C
Type number Topside
mark Package
Name Description Version
PCA9538D PCA9538D SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
PCA9538PW PCA9538 TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
PCA9538BS 9538 HVQFN16 plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4 ×4×0.85 mm SOT629-1
Remark: All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9538
PCA9538
POWER-ON
RESET
002aae667
INPUT
FILTER
SCL
SDA
VDD
IO0
VSS
8-bit
write pulse
read pulse
IO2
IO1
IO3
LP
FILTER
VDD
INT
RESET
A0
A1
IO4
IO6
IO5
IO7
I2C-BUS/SMBus
CONTROL
INPUT/
OUTPUT
PORTS
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 3 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
5. Pinning information
5.1 Pinning
Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16
Fig 4. Pin configuration for HVQFN16
PCA9538D
A0 VDD
A1 SDA
RESET SCL
IO0 INT
IO1 IO7
IO2 IO6
IO3 IO5
VSS IO4
002aae668
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15 VDD
SDA
SCL
INT
IO7
IO6
IO5
IO4
A0
A1
RESET
IO0
IO1
IO2
IO3
VSS
PCA9538PW
002aae669
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
002aae670
PCA9538BS
Transparent top view
IO2 IO6
IO1 IO7
IO0 INT
SCL
IO3
VSS
IO4
IO5
A1
A0
VDD
SDA
4 9
3 10
2 11
1 12
5
6
7
8
16
15
14
13
terminal 1
index area
RESET
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 4 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
5.2 Pin description
[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
Table 2. Pin description
Symbol Pin Description
SO16, TSSOP16 HVQFN16
A0 1 15 address input 0
A1 2 16 address input 1
RESET 3 1 active LOW reset input
IO0 4 2 input/output 0
IO1 5 3 input/output 1
IO2 6 4 input/output 2
IO3 7 5 input/output 3
VSS 86
[1] supply ground
IO4 9 7 input/output 4
IO5 10 8 input/output 5
IO6 11 9 input/output 6
IO7 12 10 input/output 7
INT 13 11 interrupt output (open-drain)
SCL 14 12 serial clock line
SDA 15 13 serial data line
VDD 16 14 supply voltage
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 5 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9538”.
6.1 Device address
6.2 Registers
6.2.1 Command byte
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the registers will be written or read.
6.2.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Fig 5. PCA9538 address
R/W
002aae707
1 1 1 0 0 A1 A0
slave address
fixed hardware
selectable
Table 3. Command byte
Command Protocol Function
0 read byte Input Port register
1 read/write byte Output Port register
2 read/write byte Polarity Inversion register
3 read/write byte Configuration register
Table 4. Register 0 - Input Port register bit description
Legend: * default value.
Bit Symbol Access Value Description
7 I7 read only X* value ‘X’ is determined by externally applied
logic level
6 I6 read only X*
5 I5 read only X*
4 I4 read only X*
3 I3 read only X*
2 I2 read only X*
1 I1 read only X*
0 I0 read only X*
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 6 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
6.2.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a 0), the Input Port data polarity is retained.
Table 5. Register 1 - Output Port register bit description
Legend: * default value.
Bit Symbol Access Value Description
7 O7 R 1* reflects outgoing logic levels of pins defined as outputs
by Register 3
6O6 R 1*
5O5 R 1*
4O4 R 1*
3O3 R 1*
2O2 R 1*
1O1 R 1*
0O0 R 1*
Table 6. Register 2 - Polarity Inversion register bit description
Legend: * default value.
Bit Symbol Access Value Description
7 N7 R/W 0* inverts polarity of Input Port register data
0 = Input Port register data retained (default value)
1 = Input Port register data inverted
6 N6 R/W 0*
5 N5 R/W 0*
4 N4 R/W 0*
3 N3 R/W 0*
2 N2 R/W 0*
1 N1 R/W 0*
0 N0 R/W 0*
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 7 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs.
6.3 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9538 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9538 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst).
The PCA9538 registers and SMBus/I2C-bus state machine will be held in their default
state until the RESET input is once again HIGH. This input requires a pull-up resistor to
VDD if no active connection is used.
6.5 Interrupt output
The open-drain interrupt output (INT) is activated when one of the port pins changes state
and the pin is configured as an input. The interrupt is de-activated when the input returns
to its previous state or the Input Port register is read.
Note that changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
Table 7. Register 3 - Configuration register bit description
Legend: * default value.
Bit Symbol Access Value Description
7 C7 R/W 1* configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as an input
(default value)
6 C6 R/W 1*
5 C5 R/W 1*
4 C4 R/W 1*
3 C3 R/W 1*
2 C2 R/W 1*
1 C1 R/W 1*
0 C0 R/W 1*
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 8 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.6 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS.
Remark: At power-on reset, all registers return to default values.
Fig 6. Simplified schematic of IO0 to IO7
VDD
I/O pin
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aad723
FF
data from
shift register
FF
FF
FF
Q1
Q2
VSS
to INT
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 9 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.7 Bus transactions
Data is transmitted to the PCA9538 registers using the write mode as shown in Figure 7
and Figure 8. Data is read from the PCA9538 registers using the read mode as shown in
Figure 9 and Figure 10. These devices do not implement an auto-increment function so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
Expanded diagram is shown in Figure 18.
Fig 7. Write to output port register
0 AS
slave address
START condition R/W acknowledge
from slave
002aae708
00000010
command byte
A
acknowledge
from slave
12345678SCL 9
SDA DATA 1 A
write to port
data out from port
tv(Q)
acknowledge
from slave
DATA 1 VALID
data to port
1100A1A01P
STOP
condition
Fig 8. Write to configuration or polarity inversion registers
0 AS
slave address
START condition R/W acknowledge
from slave
002aae709
0000011/00
command byte
A
acknowledge
from slave
12345678SCL 9
SDA DATA 1 A
data to register
acknowledge
from slave
data to register
1100A1A01P
STOP
condition
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 10 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Fig 9. Read from register
AS
START condition R/W
acknowledge
from slave
002aae710
A
acknowledge
from slave
SDA
A P
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.) 1100A1A01A1
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
COMMAND BYTE
1100A1A01 0
data from register
DATA (last byte)
data from register
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
Expanded diagram is shown in Figure 17.
Fig 10. Read input port register
1100A1A01AS1
slave address
START condition R/W acknowledge
from slave
002aae711
data from port
A
acknowledge
from master
SDA NA
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2 DATA 3
P
STOP
condition
tv(INT) trst(INT)
th(D) tsu(D)
12345678SCL 9
DATA 1
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 11 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
7. Application design-in information
Device address is 1110 000x for this example.
IO0, IO2, IO3 configured as outputs.
IO1, IO4, IO5 configured as inputs.
IO6, IO7 are not used and need 100 k pull-up resistors to protect them from floating.
Fig 11. Typical application
PCA9538
IO0
IO1
SCL
SDA
VDD
(5 V)
MASTER
CONTROLLER
SCL
SDA
INT IO2
VDD
VDD
VSS
INT
10 kSUB-SYSTEM 1
(e.g., temp sensor)
IO3
INT
SUB-SYSTEM 2
(e.g., counter)
RESET
controlled
switch
(e.g., CBT device)
A
B
enable
VSS
002aae712
10 k10 k2 k100 k
(× 3)
RESET RESET
10 k
IO4
IO5
IO6
IO7
A1
A0 SUB-SYSTEM 3
(e.g., alarm system)
ALARM
VDD
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 12 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
7.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 11. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI
at or above VDD and prevents additional supply current consumption when the LED is off.
Fig 12. High value resistor in parallel with
the LED Fig 13. Device supplied by a lower voltage
002aac660
LED
VDD
IOn
100 k
VDD
002aac661
LED
VDD
IOn
3.3 V 5 V
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 13 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
8. Limiting values
9. Static characteristics
Table 8. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +6.0 V
IIinput current - ±20 mA
VI/O voltage on an input/output pin VSS 0.5 5.5 V
IO(IOn) output current on pin IOn - ±50 mA
IDD supply current - 85 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature 65 +150 °C
Tamb ambient temperature operating 40 +85 °C
Tj(max) maximum junction temperature - +125 °C
Table 9. Static characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD = 5.5 V;
no load; fSCL = 100 kHz - 104 175 µA
IstbL LOW-level standby current Standby mode; VDD = 5.5 V;
no load; VI=V
SS;
fSCL = 0 kHz; I/O = inputs
- 0.25 1 µA
IstbH HIGH-level standby current Standby mode; VDD = 5.5 V;
no load; VI=V
DD;
fSCL = 0 kHz; I/O = inputs
- 0.25 1 µA
VPOR power-on reset voltage no load; VI=V
DD or VSS [1] - 1.5 1.65 V
Input SCL; input/output SDA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VOL = 0.4 V 3 7 - mA
ILleakage current VI=V
DD =V
SS 1-+1µA
Ciinput capacitance VI=V
SS - 5 10 pF
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 14 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
I/Os
VIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL = 0.5 V
VDD = 2.3 V [2] 810- mA
VDD = 3.0 V [2] 814- mA
VDD = 4.5 V [2] 817- mA
VOL = 0.7 V
VDD = 2.3 V [2] 10 13 - mA
VDD = 3.0 V [2] 10 19 - mA
VDD = 4.5 V [2] 10 24 - mA
VOH HIGH-level output voltage IOH =8mA
VDD = 2.3 V [3] 1.8 - - V
VDD = 3.0 V [3] 2.6 - - V
VDD = 4.5 V [3] 4.1 - - V
IOH =10 mA
VDD = 2.3 V [3] 1.7 - - V
VDD = 3.0 V [3] 2.5 - - V
VDD = 4.5 V [3] 4.0 - - V
ILI input leakage current VI=V
DD =V
SS 1-+1µA
Ciinput capacitance - 5 10 pF
Interrupt INT
IOL LOW-level output current VOL = 0.4 V 3 13 - mA
Select inputs A0, A1, RESET
VIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current 1-+1µA
Table 9. Static characteristics
…continued
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 15 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
10. Dynamic characteristics
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for the SDA data out to be valid following SCL LOW.
[3] Cb = total capacitance of one bus line in pF.
Table 10. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode I2C-bus Unit
Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition 4.7 - 1.3 - µs
tHD;STA hold time (repeated) START condition 4.0 - 0.6 - µs
tSU;STA set-up time for a repeated START
condition 4.7 - 0.6 - µs
tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs
tHD;DAT data hold time 0 - 0 - ns
tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 µs
tVD;DAT data valid time [2] 300 - 50 - ns
tSU;DAT data set-up time 250 - 100 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - µs
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs
trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns
tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns
tSP pulse width of spikes that must be
suppressed by the input filter - 50 - 50 ns
Port timing
tv(Q) data output valid time - 200 - 200 ns
tsu(D) data input set-up time 100 - 100 - ns
th(D) data input hold time 1 - 1 - µs
Interrupt timing
tv(INT) valid time on pin INT - 4 - 4 µs
trst(INT) reset time on pin INT - 4 - 4 µs
RESET
tw(rst) reset pulse width 4 - 4 - ns
trec(rst) reset recovery time 0 - 0 - ns
trst reset time 400 - 400 - ns
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 16 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Fig 14. Definition of timing
tSP
tBUF
tHD;STA PP S
tLOW
tr
tHD;DAT
tf
tHIGH tSU;DAT tSU;STA
Sr
tHD;STA
tSU;STO
SDA
SCL
002aaa986
Rise and fall times refer to VIL and VIH.
Fig 15. I2C-bus timing diagram
SCL
SDA
tHD;STA tSU;DAT tHD;DAT
tf
tBUF
tSU;STA tLOW tHIGH
tVD;ACK
002aab285
tSU;STO
protocol START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6) bit 1
(D1) bit 0
(D0)
1 / fSCL
tr
tVD;DAT
acknowledge
(A)
STOP
condition
(P)
Fig 16. Definition of RESET timing
SDA
SCL
002aad732
trst
50 %
30 %
50 % 50 %
50 %
trec(rst) tw(rst)
RESET
IOn after reset,
I/Os reconfigured
as inputs
START
trst
ACK or read cycle
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 17 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Fig 17. Expanded view of read input port register
Fig 18. Expanded view of write to output port register
SCL
002aae641
210AP
70 %
30 %
SDA
input 50 %
INT
tv(INT) trst(INT)
th(D)
tsu(D)
SCL
002aad735
210AP
70 %
SDA
output 50 %
tv(Q)
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 18 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
11. Test information
RL = load resistor.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 19. Test circuitry for switching times
Fig 20. Test circuit
Table 11. Test data
Test Load Switch
RLCL
tv(Q) 500 50 pF 2 ×VDD
PULSE
GENERATOR
VO
CL
50 pF
RL
500
002aab880
RT
VI
VDD
DUT
VDD
open
VSS
CL
50 pF
002aac226
RL
500
from output under test 2VDD
open
GND
S1
RL
500
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 19 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
12. Package outline
Fig 21. Package outline SOT162-1 (SO16)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 10.5
10.1 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT162-1
8
16
wM
bp
D
detail X
Z
e
9
1
y
0.25
075E03 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.41
0.40 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
0 5 10 mm
scale
SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
99-12-27
03-02-19
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 20 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Fig 22. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 21 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Fig 23. Package outline SOT629-1 (HVQFN16)
terminal 1
index area
0.651
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.1
3.9
Dh
2.25
1.95
y1
4.1
3.9 2.25
1.95
e1
1.95
e2
1.95
0.38
0.23
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT629-1 MO-220 - - -- - -
0.75
0.50
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT629-1
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 4 x 4 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
58
16 13
12
9
4
1
X
D
E
C
BA
e2
01-08-08
02-10-22
terminal 1
index area
1/2 e
1/2 e
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
PCA9538_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 28 May 2009 22 of 28
NXP Semiconductors PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
13. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in
JESD625-A
or equivalent standards.
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note
AN10365 “Surface mount reflow
soldering description”
.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are: