Philips Semiconductors Product specification eee eee eee ee ee ee ee 8-bit A/D and D/A converter PCF8591 I CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.4 Addressing 7.2 Control byte 7.3 D/A conversion 74 A/D conversion 75 Reference voltage 7.6 Oscillator 8 CHARACTERISTICS OF THE I2C-BUS 8.1 Bit transfer 8.2 Start and stop conditions 8.3 System configuration 8.4 Acknowledge 8.5 l?C-bus protocol 9 LIMITING VALUES 10 HANDLING 11 DC CHARACTERISTICS 12 D/A CHARACTERISTICS 13 A/D CHARACTERISTICS 14 AC CHARACTERISTICS 15 APPLICATION INFORMATION 16 PACKAGE OUTLINES 17 SOLDERING 17.1 Introduction 17.2 DIP 17.2.1 Soldering by dipping or by wave 17.2.2 Repairing soldered joints 17.3 SO 17.3.1 Reflow soldering 17.3.2 Wave soldering 17.3.3 Repairing soldered joints 18 DEFINITIONS 19 LIFE SUPPORT APPLICATIONS 20 PURGHASE OF PHILIPS |2?@ COMPONENTS 1998 Jul 02 2Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 1 FEATURES e Single power supply e Operating supply voltage 2.5 V to 6 V e Low standby current Serial input/output via |@C-bus e Address by 3 hardware address pins Sampling rate given by I?C-bus speed e 4 analog inputs programmable as single-ended or differential inputs e Auto-incremented channel selection e Analog voltage range from Vgs to Vpp e On-chip track and hold circuit 8-bit successive approximation A/D conversion Multiplying DAC with one analog output. 2 APPLICATIONS Closed loop control systems e Low power converter for remote data acquisition e Battery operated equipment Acquisition of analog values in automotive, audio and TV applications. 4 ORDERING INFORMATION 3 GENERAL DESCRIPTION The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device with four analog inputs, one analog output and a serial I@C-bus interface. Three address pins AO, A1 and A2 are used for programming the hardware address, allowing the use of up to eight devices connected to the I2C-bus without additional hardware. Address, control and data to and from the device are transferred serially via the two-line bidirectional I@C-bus. The functions of the device include analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The maximum conversion rate is given by the maximum speed of the |2C-bus. TYPE PACKAGE NUMBER NAME DESCRIPTION VERSION PCA8591P DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 PCA8591T S016 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 1998 Jul 02 3Product specification Philips Semiconductors PCF8591 8-bit A/D and D/A converter 5 BLOCK DIAGRAM (260824 weiBelp yooig 1614 ONOV >| dad, >| ova 91IDO1/4LSID3Y NO!ILVWIXOUdd YY JAISSIOONS \Z Zn H/S H/S Lnov YaXS 1d -ILINW a oIbo7 TOHLNOO YOLYTTHOSO SNBOWNY 4# ENIV cNivV it iNIV 4 ONIV ____- 980 13sauy NO aMOd Y3LSI93Y Viva 90V yaLSIO3Y ivd Ova YALSID3Y SALVLS t SS, me ada 1x3 SOVIYALNI sng 9,! i+ ZV t lv 4 OV + VOS H4 10S 1998 Jul 02Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 6 PINNING SYMBOL | PIN DESCRIPTION AINO 1 AIN1 2 analog inputs AIN2 3 (A/D converter) AINO i U he] Vp AIN3 4 fe rs] aout 15 AO 5 AIN1 | 2 Al 6 hardware address ain2 [3 | [14] Vrer A2 7 Aina [4 113] AGND Vss 8 negative supply voltage ao fs PorBSS1 n2] EXT SDA 9 l2C-bus data input/output i] osc 1 SCL 10 = | |?C-bus clock input are OSC 14 oscillator input/output A247 fio] sci EXT 12 | external/internal switch for oscillator Vgg [a | Ell SDA input 7Z80959.1 AGND 13 analog ground , VREF 14 voltage reference input AOUT 15 | analog output (D/A converter) Fig.2 Pinning diagram. Vop 16 positive supply voltage 1998 Jul 02Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 7 FUNCTIONAL DESCRIPTION 7.1 Addressing Each PCF8591 device in an I?C-bus system is activated by sending a valid address to the device. The address consists of a fixed part and a programmable part. The programmable part must be set according to the address pins AO, Ai and A2. The address always has to be sent as the first byte after the start condition in the |2C-bus protocol. The last bit of the address byte is the read/write-bit which sets the direction of the following data transfer (see Figs 3, 15 and 16). MSB LSB 1} 0] 0] 1 1|A2] a1| ao IR/W \ A ~y- fixed part programmable part Fig.3 Address byte. 7Z80960 1998 Jul 02 7.2 Control byte The second byte sent to a PCF8591 device will be stored in its control register and is required to control the device function. The upper nibble of the control register is used for enabling the analog output, and for programming the analog inputs as single-ended or differential inputs. The lower nibble selects one of the analog input channels defined by the upper nibble (see Fig.4). If the auto-increment flag is set the channel number is incremented automatically after each A/D conversion. If the auto-increment mode is desired in applications where the internal oscillator is used, the analog output enable flag in the control byte (bit 6) should be set. This allows the internal oscillator to run continuously, thereby preventing conversion errors resulting from oscillator start-up delay. The analog output enable flag may be reset at other times to reduce quiescent power consumption. The selection of a non-existing input channel results in the highest available channel number being allocated. Therefore, if the auto-increment flag is set, the next selected channel will be always channel 0. The most significant bits of both nibbles are reserved for future functions and have to be set to 0. After a Power-on reset condition all bits of the control register are reset to 0. The D/A converter and the oscillator are disabled for power saving. The analog output is switched to a high-impedance state.Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 MSB LSB 0 xX x x 0 x x x CONTROL BYTE {J TT A/D CHANNEL NUMBER: 00 channel 0 01 channel 1 10 channei 2 11 channel 3 - AUTOINCREMENT FLAG: (switched on if 1) -- ANALOGUE INPUT PROGRAMMING: 00 Four single ended inputs AINO channel 0 AIN1. __-- channel 1 AIN2 - channel 2 AIN3. channel 3 a1 Three differential inputs AINO channel 0 AIN1 -~ channel 1 $ AIN2 AIN3 channel 2 10 Singie ended and differential mixed AINO ~ channel 0 AINt -_ channel 1 AIN2 y channel 2 AIN3 it Two differential inputs AINO > channel 0 AINt_ + AIN2 -" > channel 1 AIN3 1> ANALOGUE OUTPUT ENABLE FLAG: (analogue output active if 1) 7280961 Fig.4 Control byte. 1998 Jul 02 7Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 7.3 D/A conversion The third byte sent to a PCF8591 device is stored in the DAC data register and is converted to the corresponding analog voltage using the on-chip D/A converter. This D/A converter consists of a resistor divider chain connected to the external reference voltage with 256 taps and selection switches. The tap-decoder switches one of these taps to the DAC output line (see Fig.5). The analog output voltage is buffered by an auto-zeroed unity gain amplifier. This buffer amplifier may be switched on or off by setting the analog output enable flag of the control register. In the active state the output voltage is held until a further data byte is sent. The on-chip D/A converter is also used for successive approximation A/D conversion. In order to release the DAC for an A/D conversion cycle the unity gain amplifier is equipped with a track and hold circuit. This circuit holds the output voltage while executing the A/D conversion. The output voltage supplied to the analog output AOUT is given by the formula shown in Fig.6. The waveforms of a D/A conversion sequence are shown in Fig.7. VREE -> DAC OUT R256 R255 FF I 1 I { \ 1 I \ 4+# D7 R3 i+_ D6 TAP l OECODER | R2 02 i+ D0 1 R1 g AGND 00 7280962 Fig.5 DAC resistor divider chain. 1998 Jul 02Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 MSB LSB 7280963 D7 | 06 | Ds | D4} 03 | D2 | D1 | Do reuisten VAQUT & Vv Vv 7 REF ~ VaGNO oj Va = VaGnp + see DO x2 Voo+ Our GND 256 io VREF T - T ens 4 ~ a a a 4 - 4 eo 4 en - VAGND T \ Vv ++_+_++-+ +++ > SS00 01 02 03 04 FE FF HEX CODE Fig.6 DAC data and DC conversion characteristics. PROTOCOL | S ADDRESS 0 A CONTROL BYTE A DATA BYTE 1 A DATA BYTE 2 A | | oo \(YY\ Sy Y\ sy Vs yy VaouT ee PREVIOUS VALUE VALUE OF HELD IN DAC DATA BYTE 1 HIGH IMPEDANCE STATE OR REGISTER PREVIOUS VALUE HELD IN DAC REGISTER 7280964 time Fig.7 D/A conversion sequence. 1998 Jul 02 9Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 7.4 A/D conversion The A/D converter makes use of the successive approximation conversion technique. The on-chip D/A converter and a high-gain comparator are used temporarily during an A/D conversion cycle. An A/D conversion cycle is always started after sending a valid read mode address to a PCF8591 device. The A/D conversion cycle is triggered at the trailing edge of the acknowledge clock pulse and is executed while transmitting the result of the previous conversion (see Fig.8). Once a conversion cycle is triggered an input voltage sample of the selected channel is stored on the chip and is converted to the corresponding 8-bit binary code. Samples picked up from differential inputs are converted to an 8-bit twos complement code (see Figs 9 and 10). The conversion result is stored in the ADC data register and awaits transmission. If the auto-increment flag is set the next channel is selected. The first byte transmitted in a read cycle contains the conversion result code of the previous read cycle. After a Power-on reset condition the first byte read is a hexadecimal 80. The protocol of an I?C-bus read cycle is shown in Chapter 8, Figs 15 and 16. The maximum A/D conversion rate is given by the actual speed of the |2C-bus. PROTOCOL | S DATA BYTE 0 ADDRESS | 1 A A DATA SYTE 1 A DATA BYTE 2 A [ SAMPLING oo lf YY) \LE yisyy ist Vis 7280965 SAMPLING SAMPLING BYTE 1 BYTE 2 BYTE 3 CONVERSION CONVERSION CONVERSION OF BYTE 1 OF BYTE 2 OF BYTE 3 \ \ F I J qt qT v 7 TRANSMISSION TRANSMISSION TRANSMISSION OF PREVIOUSLY OF BYTE 1 OF BYTE 2 CONVERTED BYTE Fig.8 A/D conversion sequence. 1998 Jul 02 10Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 CODE 7280966 FF + FE+ =. YREF VAGND 4 LSB 256 x 04 + 7 03 + A 02 + L ot po Y~ 00 + + t + t + ++ + 0 4 2 38 4 wlan 254 285 = Vain VaGND VisB Fig.9 A/D conversion characteristics of single-ended inputs. HEX CODE 4 7280967 o+ 4 \ , , , 00 \ , \ \ -128 -127 --- -2 yy 0 1 2 --- 126 127 Wing ~ Vain +FF Ves 7 LSB 7 + FE 1 a | Vrer VAGND Viss = 256 781 _ 4d Fig.10 A/D conversion characteristics of differential inputs. 1998 Jul 02 11Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 7.5 Reference voltage For the D/A and A/D conversion either a stable external voltage reference or the supply voltage has to be applied to the resistor divider chain (pins Vage and AGND). The AGND pin has to be connected to the system analog ground and may have a DC off-set with reference to Vss. A low frequency may be applied to the Vaer and AGND pins. This allows the use of the D/A converter as a one-quadrant multiplier; see Chapter 15 and Fig.6. The A/D converter may also be used as a one or two quadrant analog divider. The analog input voltage is divided by the reference voltage. The result is converted to a binary code. In this application the user has to keep the reference voltage stable during the conversion cycle. 1998 Jul 02 12 7.6 Oscillator An on-chip oscillator generates the clock signal required for the A/D conversion cycle and for refreshing the auto-zeroed buffer amplifier. When using this oscillator the EXT pin has to be connected to Vsg. At the OSC pin the oscillator frequency is available. lf the EXT pin is connected to Vpp the oscillator output OSC is switched to a high-impedance state allowing the user to feed an external clock signal to OSC.Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 8 CHARACTERISTICS OF THE I?C-BUS The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. SDA / I I data line | change | | stable; | ofdata | | data valid | allowed | MBCE1 Fig.11 Bit transfer. 8.2 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the stop condition (P). SCL \ / \ / SCL s 1, P | a a START condition STOP condition acsee Fig.12 Definition of START and STOP condition. 1998 Jul 02 13Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 8.3. System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. SDA TT | | | | MASTER SLAVE MASTER TRANSMITTER / RECEIVER TRANSMITTER / TRANSM er TRANSMITTER / RECEIVER RECEIVER RECEIVER MBAG05 Fig.13 System configuration. 8.4 Acknowledge The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited. Each data byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master also generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. {XXX / not acknowledge en DATA OUTPUT | \ BY TRANSMITTER ! | | | | DATA OUTPUT BY RECEIVER acknowledge SCL FROM ero ; VY Sfe\ f\. LS f START condition clock pulse for acknowledgement MBC602 Fig.14 Acknowledgement on the |2C-bus. 1998 Jul 02 14Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 8.5 After a start condition a valid hardware address has to be sent to a PCF8591 device. The read/write bit defines the direction of the following single or multiple byte data transfer. For the format and the timing of the start condition (S), the stop condition (P) and the acknowledge bit (A) refer to the I?C-bus characteristics. In the write mode a data transfer is terminated by sending either a stop condition or the start condition of the next data transfer. I2C-bus protocol Acknowledge from PCF8591 from PCF8591 from PCFB591 ! s ADDRESS 0 A CONTROL BYTE A DATA BYTE A PS 1 -_ N=0toM DATA BYTES 7280968 Acknowledge Acknowledge | | Fig.15 Bus protocol for write mode, D/A conversion. Acknowledge from PCF&591 Acknowledge from master No acknowledge ! ADORESS 1 A DATA BYTE A LAST DATA BYTE 1 P A 7280969 N=0toM DATA BYTES Fig.16 Bus protocol for read mode, A/D conversion. 15Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT Vop supply voltage (pin 16) -0.5 +8.0 Vv Vi input voltage (any input) -0.5 Vpp + 0.5 Vv I DC input current - +10 mA lo DC output current - +20 mA Ipp; Iss Vpp or Vgs current = +50 mA Prot total power dissipation per package - 300 mW Po power dissipation per output - 100 mW Tamb operating ambient temperature 40 +85 C T stg storage temperature 65 +150 C 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC 12 under Handling MOS Devices. 1998 Jul 02 16Philips Sem iconductors Product specification 8-bit A/D and D/A converter PCF8591 11 DC CHARACTERISTICS Vpp = 2.5 V to 6 V; Vgg = 0 V; Tamp = 40 C to +85 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS | min. | typ | MAX. | UNIT Supply Vop supply voltage (operating) 2.5 - 6.0 Vv Ipp supply current standby V, = Vgg or Vpp; no load - 1 15 HA operating, AOUT off fgc_ = 100 kHz - 125 250 HA operating, AOUT active fgce_ = 100 kHz - 0.45 1.0 mA Vpor Power-on reset level note 1 0.8 - 2.0 Vv Digital inputs/output: SCL, SDA, AO, A1, A2 Vit LOW level input voltage 0 - 0.3 x Vpp | V Vin HIGH level input voltage 0.7 Vpp |- Vpp Vv IL leakage current AO, A1, A2 Vi=Vss to Vpp 250 = +250 nA SCL, SDA V, = Vgg to Vpp -1 - +1 HA Ci input capacitance - - 5 pF lot LOW level SDA output current | Vo. = 0.4 V 3.0 - - mA Reference voltage inputs VREF reference voltage Vrer > Vacanp; note 2 Vgg + 1.6 |- Vpp Vv VacGnpb analog ground voltage Vrer > Vacanp; note 2 Vgs - Vpp 0.8] V lu input leakage current 250 - +250 nA Rrer input resistance pins Vaer and AGND - 100 - kQ Oscillator: OSC, EXT lu input leakage current - - 250 nA fosc oscillator frequency 0.75 - 1.25 MHz Notes 1. The power on reset circuit resets the I2C-bus logic when Vpp is less than Vpor. 2. A further extension of the range is possible, if the following conditions are fulfilled: Vv +V REF * YAGND 3 2 0.8V, Vopn- 1998 Jul 02 Veer + V 2 AGND >0.4V 17Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 12 D/A CHARACTERISTICS Vpp = 5.0 V; Veg = 0 V; Vrer = 5.0 V; Vaenp = 0 V; Rr = 10 kQ; C, = 100 pF; Tamp = 40 C to +85 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS | min. | Typ | max. | UNIT Analog output Voa output voltage no resistive load Vss - Vpp Vv R_ = 10 kQ Vss - 0.9xVpp | V ILo output leakage current AOUT disabled - - 250 nA Accuracy OS, offset error Tamb = 25 C - - 50 mV Le linearity error - - +1.5 LSB Ge gain error no resistive load - - 1 % tpac settling time to LSB full scale step - - 90 ys foac conversion rate - - 11.1 kHz SNRR supply noise rejection ratio | f = 100 Hz; - 40 - dB Vppn = 0.1 X Vpp 13 A/D CHARACTERISTICS Vpp = 5.0 V; Vssg = 0 V; Vrer = 5.0 V; Vaanp = 0 V; Rg = 10 kQ; Tamp = 40 C to +85 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS | min. | typ | max. | UNIT Analog inputs Via analog input voltage Vss - Vop Vv ILia analog input leakage current - - 100 nA Cia analog input capacitance - 10 - pF Cip differential input capacitance - 10 - pF Vis single-ended voltage measuring range VaGND - VREF Vv Vip differential voltage measuring range; Veg - +Veg Vv Ves = Vrer Vacnp a 2 Accuracy OS, offset error Tamb = 25 C - - 20 mV Le linearity error - - +1.5 LSB Ge gain error - - 1 % GS. small-signal gain error AV, = 16 LSB - - 5 % CMRR common-mode rejection - 60 - dB ratio SNRR supply noise rejection ratio | f = 100 Hz; - 40 - dB Vppn = 9.1 x Vpp tapc conversion time - - 90 ys fapc sampling/conversion rate - - 11.1 kHz 1998 Jul 02 18Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 200 7294726 160 7294727 Ipp 'pp (uA) (uA) 150 A 120 a > BZ - 40 9 100 a a0 | at yA Are rs on +27%% 50 40 Le 0 0 2 3 4 5 6 2 3 4 5 6 Yop (V} Vop (V) (a) Internal oscillator; Tamb = +27 C. (ob) External oscillator. Fig.17 Operating supply current as a function of supply voltage (analog output disabled). 7294728 7294729 00 _ 500 S a 2 = 2 9 400 5 3 3 400 a = 3 3 5 300 & 300 8 8 5 < a 200 200 100 100 o 0 oo 82 0498 vitae od OA BO co DO 0 FO. FF ex input code hex input code (a) Output impedance near negative power rail; Tambp = +27 C. (6) Output impedance near positive power rail; Tamp = +27 C. The x-axis represents the hex input-code equivalent of the output voltage. Fig.18 Output impedance of analog output buffer (near power rails). 1998 Jul 02 19Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 14 AC CHARACTERISTICS All timing values are valid within the operating supply voltage and ambient temperature range and reference to Vj_ and Vin with an input voltage swing of Vgg to Vpp. SYMBOL PARAMETER | min. | Typ. | MAX. | UNIT I2C-bus timing (see Fig.19; note 1) fsc SCL clock frequency - - 100 kHz tsp tolerable spike width on bus - - 100 ns tBuF bus free time 4.7 - - ys tsu:STA START condition set-up time 47 - - ys tHD:STA START condition hold time 4.0 - - ys tlow SCL LOW time 4.7 - - ys tHiGH SCL HIGH time 4.0 - - ys tr SCL and SDA rise time - - 1.0 us tt SCL and SDA fall time - - 0.3 us tsu:DAT data set-up time 250 - - ns tHD:DAT data hold time 0 - - ns typ:DaAT SCL LOW-to-data out valid - - 3.4 ys tsu:sto STOP condition set-up time 4.0 - - ys Note 1. Adetailed description of the I@C-bus specification, with applications, is given in brochure The PC-bus and how to use it. This brochure may be ordered using the code 9398 393 40011. SCL START BIT7 BIT 6 BITO | ACKNOWLEDGE STOP PROTOCOL CONDITION MSB (A6) LSB (A) CONDITION (S) (A?) (RM) (P) 'su:sTA tlow THIGH T/T gclm [ \ SDA X " SU;DAT Ll 'up-paT MBD820 Fig.19 |?C-bus timing diagram; rise and fall times refer to Vi_ and Vi. 1998 Jul 02 20Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 15 APPLICATION INFORMATION Inputs must be connected to Vgg or Vpp when not in use. Analog inputs may also be connected to AGND or Vref. In order to prevent excessive ground and supply noise and to minimize cross-talk of the digital to analog signal paths the user has to design the printed-circuit board layout very carefully. Supply lines common to a PCF8591 device and noisy digital circuits and ground loops should be avoided. Decoupling capacitors (>10 uF) are recommended for power supply and reference voltage inputs. Yoo tH Vbp AINO AOUT AIN1 VaEF AIN2 AGND AIN3 EXT Ao PCFB591 Ge, Al SCL A2 SDA Vss +6 | f al _ Vop AINO AOUT F Vout AIN1 VREF AIN2 AGND -}*8 AIN3 ExT Vo AO PCF8591 OSC /- 7 Al SCL A2 SDA Vs 7 as ANALOGUE GROUND MASTER TRANSMITTER J pierrat GROUND s ,v 2 Li 7280970. 1c BUS Fig.20 Application diagram. 1998 Jul 02 21Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 16 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 oD Cc @ a D 3 D n L pin 1 index ac fet | LAL EI EG CL | 3 0 5 10 mm bee a scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay A2 (1) (1) z@ UNIT | max. | min. | max. b by ce D E e ha L Me Mu w max. 1.40 0.53 0.32 21.8 6.48 3.9 8.25 9.5 mmo) 47 | 051 | 37 |) 444 | o38 | 023 | 214 | 620 | 254 | 792 | 34 | 780 | a3 | 9754) 22 ; 0.055 | 0.021 0.013 0.86 0.26 0.15 0.32 0.37 inches | 0.19 | 0.020 | 0.15 | go4s | 0.015 | 0.009 | 0.84 | o24 | 19 | 99 | g43 | o31 | o33 | %O1 | 0087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ 92-+0-62- SOT38-1 050G09 MO-001AE f--} S01 te 1998 Jul 02 22Philips Semiconductors 8-bit A/D and D/A converter $016: plastic small outline package; 16 leads; body width 7.5 mm Product specification PCF8591 SOT162-1 tm 20ti | == 7 ere T LALA AA , ao 7 | - - - Ta | Ve | pin 1 index f ali, a. iH Hl Wb Uo. = oe scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | max. | A1 | A2 | As | bp c Dp | ED | HE L Lp Q v w y z | 9 0.30 | 2.45 0.49 | 032 | 105 | 7.6 10.65 wt] 4a 0.9 mm | 265 | oo | 225 | 975 | o36 | 023 | 101] 74 | 127 | 1000] '* | o4 | 10 | 97] 925 | O14 | og | go oO 0.012 | 0.096 0.019 | 0.013] 0.41 | 0.30 0.419 0.043 | 0.043 0.035| inches | 0.10 | 4'o04 | 0.089 | 91 | 0.014 | 0.009} 0.40 | 0.29 | 9-952 | o.394 | 9-955 | o.016| 0.039 | 9-91 | 901 | 9-004 | 9 1g Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ 95-04-24 SOT162-1 075E03 MS-013AA f+ 97 08D? 1998 Jul 02 23Philips Semiconductors Product specification 8-bit A/D and D/A converter PCF8591 17 SOLDERING 17.1. Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook 1C26; Integrated Circuit Packages (order code 9398 652 90011). 17.2. DIP 17.2.1. SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tgig max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 17.2.2 REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 17.3. SO 17.3.1. REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 Jul 02 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 17.3.2 WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: e A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. e The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.3.3. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.