1
June 1998
HA-5147/883
100MHz, Ultra Low Noise, Precision,
High Slew Rate Operational Amplifier
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• High Slew Rate. . . . . . . . . . . . . . . . . . . . . . 28V/µs (Min)
• Wide Gain Bandwidth (AV≥ 10) . . . . . . . 100MHz (Min)
• Low Noise (at 1kHz). . . . . . . . . . . . . . . 4.5nV/√Hz (Max)
• Low Offset Voltage. . . . . . . . . . . . . . . . . . . .100µV (Max)
• Low Offset Drift With Temperature. . . . 1.8µV/oC (Max)
• High CMRR. . . . . . . . . . . . . . . . . . . . . . . . . .100dB (Min)
• High Voltage Gain . . . . . . . . . . . . . . . . . . 700kV/V (Min)
Applications
• High Speed Signal Conditioners
• Wide Bandwidth Instrumentation Amplifiers
• Low Level Transducer Amplifiers
• Fast, Low Level Voltage Comparators
• Highest Quality Audio Preamplifiers
• Pulse/RF Amplifiers
Description
The HA-5147/883 monolithic operational amplifier features
an unparalleled combination of precision DC and wideband
high speed characteristics. Utilizing the Intersil DI technol-
ogy and advanced processing techniques, this unique
design unites low noise precision instrumentation perfor-
mance with high speed wideband capability.
This amplifier’s impressive list of features include low VOS,
wide gain-bandwidth, high open loop gain, and high CMRR.
Additionally, this flexible device operates over a wide supply
range while consuming only 120mW of power.
Using the HA-5147/883 allows designers to minimize errors
while maximizing speed and bandwidth in applications
requiring gains greater than ten.
This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize the
HA-5147/883’s qualities include instrumentation amplifiers,
pulse or RF amplifiers, audio preamplifiers, and signal condi-
tioning circuits.
Pinouts
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HA4-5147/883 -55 to 125 20 Ld CLCC J20.A
HA7-5147/883 -55 to 125 8 Ld CERDIP F8.3A
HA-5147/883
(CERDIP)
TOP VIEW
HA-5147/883
(CLCC)
TOP VIEW
1
2
3
4
8
7
6
5
V+
OUT
BAL
V-
-
BAL
NC
-IN
+IN +4
5
6
7
8
9101112
13
3212019
15
14
18
17
16
BAL
NC
V-
NC
NC
NC
NC
NC
V+
OUT
NC
NC
NC
NC
BAL
NC
NC
+
NC
-IN
+IN
-
Spec Number 511009-883
File Number 3715.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Copyright © Intersil Corporation 1999
2Spec Number 511009-883
Absolute Maximum Ratings Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 44V
Differential Input Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . .0.7V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA
Output Current . . . . . . . . . . . . . . . . . . . Full Short Circuit Protection
ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
VINCM ≤ 1/2 (V+ - V-)
RL≥ 600Ω
Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . 115 28
CLCC Package . . . . . . . . . . . . . . . . . . 65 15
Package Power Dissipation Limit at 75oC for TJ≤ 175oC
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870mW
CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.54W
Package Power Dissipation Derating Factor Above 75oC
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.7mW/oC
CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15.4mW/oC
Maximum Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: VSUPPLY = ±15V, RSOURCE = 50Ω, RLOAD = 100kΩ, VOUT = 0V, Unless Otherwise Specified.
PARAMETER SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMP. (oC) MIN MAX UNITS
Input Offset Voltage VIO VCM = 0V 1 25 -100 100 µV
2, 3 125, -55 -300 300 µV
Input Bias Current IBVCM = 0V,
RS = 10kΩ, 50Ω 1 25 - 80 nA
2, 3 125, -55 - 150 nA
Input Offset Current IIO VCM = 0V,
+RS = 10kΩ,
-RS = 10kΩ
1 25 -75 75 nA
2, 3 125, -55 -135 135 nA
Common Mode
Range +CMR V+ = +4.7V,
V- = -25.3V 1 25 10.3 - V
2, 3 125, -55 10.3 - V
-CMR V+ = +25.3V,
V- = -4.7V 1 25 - -10.3 V
2, 3 125, -55 - -10.3 V
Large Signal Voltage
Gain +AVOL VOUT = 0V and +10V,
RL = 2kΩ4 25 700 - kV/V
5, 6 125, -55 300 - kV/V
-AVOL VOUT = 0V and -10V,
RL = 2kΩ4 25 700 - kV/V
5, 6 125, -55 300 - kV/V
Common Mode
Rejection Ratio +CMRR ∆VCM = +11V 1 25 100 - dB
∆VCM = +10V 2, 3 125, -55 100 - dB
-CMRR ∆VCM = -11V 1 25 100 - dB
∆VCM = -10V 2, 3 125, -55 100 - dB
+IBI–B
+
2
------------------------------
HA-5147/883
3
Output Voltage Swing +VOUT1 RL = 2kΩ4 25 11.5 - V
5, 6 125, -55 11.5 - V
-VOUT1 RL = 2kΩ4 25 - -11.5 V
5, 6 125, -55 - -11.5 V
+VOUT2 RL = 600Ω42510-V
-VOUT2 RL = 600Ω4 25 - -10 V
Output Current +IOUT VOUT = -10V 4 25 16.5 - mA
-IOUT VOUT = +10V 4 25 - -16.5 mA
Quiescent Power
Supply Current +ICC VOUT =0V,I
OUT = 0mA 1 25 - 4 mA
2, 3 125, -55 - 4 mA
-ICC VOUT =0V,I
OUT = 0mA 1 25 -4 - mA
2, 3 125, -55 -4 - mA
Power Supply
Rejection Ratio +PSRR ∆VSUP = +14V 1 25 86 - dB
∆VSUP = +13.5V 2, 3 125, -55 86 - dB
-PSRR ∆VSUP = +14V 1 25 86 - dB
∆VSUP = +13.5V 2, 3 125, -55 86 - dB
Offset Voltage
Adjustment +VIOAdj Note 3 1 25 VIO-1 - mV
2, 3 125, -55 VIO-1 - mV
-VIOAdj Note 3 1 25 VIO+1 - mV
2, 3 125, -55 VIO+1 - mV
NOTE:
3. Offset adjustment range is [VIO (Measured) ±1mV] minimum referred to output. This test is for functionality only to assure adjustment
through 0V.
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: VSUPPLY = ±15V, RSOURCE = 50Ω, RLOAD = 100kΩ, VOUT = 0V, Unless Otherwise Specified.
PARAMETER SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMP. (oC) MIN MAX UNITS
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: VSUPPLY =±15V, RSOURCE = 50Ω, RLOAD = 2kΩ, CLOAD = 50pF, AVCL = +10V/V, Unless Otherwise Specified.
PARAMETER SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMP. (oC) MIN MAX UNITS
Slew Rate +SR VOUT = -3V to +3V 7 25 28 - V/µs
-SR VOUT = +3V to -3V 7 25 28 - V/µs
Rise and Fall Time trVOUT = 0 to +200mV
10% ≤tr≤ 90% 7 25 - 50 ns
tfVOUT = 0 to -200mV
10% ≤tf≤ 90% 7 25 - 50 ns
Overshoot +OS VOUT = 0 to +200mV 7 25 - 40 %
-OS VOUT = 0 to -200mV 7 25 - 40 %
HA-5147/883
Spec Number 511009-883
4Spec Number 511009-883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Characterized at: VSUPPLY =±15V, RLOAD = 2kΩ, CLOAD = 50pF, AV = +10V/V, Unless Otherwise Specified.
PARAMETER SYMBOL CONDITIONS NOTES TEMP. (oC) MIN MAX UNITS
Average Offset Voltage
Drift VIOTC VCM = 0V 4 -55 to 125 - 1.8 µV/oC
Differential Input
Resistance RIN VCM = 0V 4 25 0.8 - MΩ
Low Frequency
Peak-to-Peak Noise ENP-P 0.1Hz to 10Hz 4 25 - 0.25 µVP-P
Input Noise Voltage
Density ENRS = 20Ω, fO = 10Hz 4 25 - 10 nV/√Hz
RS = 20Ω, fO = 100Hz 4 25 - 5.6 nV/√Hz
RS = 20Ω, fO = 1kHz 4 25 - 4.5 nV/√Hz
Input Noise Current
Density INRS = 2MΩ, fO = 10Hz 4 25 - 4.0 pA/√Hz
RS = 2MΩ, fO = 100Hz 4 25 - 2.3 pA/√Hz
RS = 2MΩ, fO = 1kHz 4 25 - 0.6 pA/√Hz
Gain Bandwidth Product GBWP VO= 100mV, fO=10kHz 4 25 120 - MHz
VO= 100mV, fO=1MHz 4 25 100 - MHz
Full Power Bandwidth FPBW VPEAK = 10V 4, 5 25 445 - kHz
Minimum Closed Loop
Stable Gain CLSG RL = 2kΩ, CL = 50pF 4 -55 to 125 ±10 - V/V
Settling Time tSTo 0.1% for a 10V Step 4 25 - 600 µs
Output Resistance ROUT Open Loop 4 25 - 100 Ω
Quiescent Power
Consumption PC VOUT =0V,I
OUT = 0mA 4, 6 -55 to 125 - 120 mW
NOTES:
4. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These pa-
rameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characteriza-
tion based upon data from multiple production runs which reflect lot to lot and within lot variation.
5. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πVPEAK).
6. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on output.)
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 AND 2)
Interim Electrical Parameters (Pre Burn-In) 1
Final Electrical Test Parameters 1 (Note 7), 2, 3, 4, 5, 6, 7
Group A Test Requirements 1, 2, 3, 4, 5, 6, 7
Groups C and D Endpoints 1
NOTE:
7. PDA applies to Subgroup 1 only.
HA-5147/883
5
Die Characteristics
DIE DIMENSIONS:
104.3 x 65 x 19 mils
2650 x 1650 x 483µm
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kű2kÅ
GLASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.)
Silox Thickness: 12kÅ ± 2kÅ
Nitride Thickness: 3.5kÅ ± 1.5kÅ
WORST CASE CURRENT DENSITY:
3.6 x 105A/cm2at 15mA
This device meets Glassivation Integrity Test Requirement
per MIL-STD-883 Method 2021 and MIL-I-38535 Paragraph
30.5.5.4.
SUBSTRATE POTENTIAL (Powered Up):
V-
TRANSISTOR COUNT:
63
PROCESS:
Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5147/883
BAL BAL
V+
OUT
NC
V-
+IN
-IN
HA-5147/883
Spec Number 511009-883
6Spec Number 511009-883
Burn-In Circuits
HA-5147/883 CERDIP
HA-5147/883 CLCC
NOTE:
R1 = R3 = 1kΩ,±5%, 1/4W (Min.)
R2 = 10kΩ,±5%, 1/4W (Min.)
C1 = C2 = 0.01µF/Socket or 0.1µF/Row (Min.)
D1 = D2 = 1N4002 or Equivalent/Board
|(V+) - (V-)| = 30V
V+
D1
R1
D2C2
V-
+
-
1
3
4
8
7
6
5
C1
R2
2
R3
9 10111213
32120 19
15
14
18
16
R2
V-
+
-
R3
C2D2
17
D1
C1
V+
4
5
6
7
8
R1
HA-5147/883
7
Typical Performance Information TA = 25oC, VSUPPLY = ±15V, Unless Otherwise Specified
NOTE: Tested offset adjustment range is |VOS ±1mV| minimum referred to output. Typical range is ±4mV with RT = 10kΩ.
SUGGESTED OFFSET VOLTAGE ADJUSTMENT
LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT
Vertical Scale: Input = 0.5V/Div.
Output = 5V/Div.
Horizontal Scale: 500ns/Div.
LARGE SIGNAL RESPONSE
Vertical Scale: Input = 10mV/Div.
Output = 100mV/Div.
Horizontal Scale: 100ns/Div.
SMALL SIGNAL RESPONSE
V+
+
-
1
3
4
8
7
6
5
RT
2
10kΩ
+
VAC
50pF
1.8kΩ
200Ω
-
50Ω
VACOUT
AV = +10V/V
OUT
IN
OUT
IN
HA-5147/883
Spec Number 511009-883
8Spec Number 511009-883
HA-5147/883
Ceramic Leadless Chip Carrier Packages (CLCC)
D
j x 45oD3
B
h x 45o
AA1
E
LL3
e
B3
L1
D2
D1
e1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010 E HS S
0.010 E F
SS
-E-
0.007 E FM S HS
B1
-H-
-F-
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.060 0.100 1.52 2.54 6, 7
A1 0.050 0.088 1.27 2.23 -
B-----
B1 0.022 0.028 0.56 0.71 2, 4
B2 0.072 REF 1.83 REF -
B3 0.006 0.022 0.15 0.56 -
D 0.342 0.358 8.69 9.09 -
D1 0.200 BSC 5.08 BSC -
D2 0.100 BSC 2.54 BSC -
D3 - 0.358 - 9.09 2
E 0.342 0.358 8.69 9.09 -
E1 0.200 BSC 5.08 BSC -
E2 0.100 BSC 2.54 BSC -
E3 - 0.358 - 9.09 2
e 0.050 BSC 1.27 BSC -
e1 0.015 - 0.38 - 2
h 0.040 REF 1.02 REF 5
j 0.020 REF 0.51 REF 5
L 0.045 0.055 1.14 1.40 -
L1 0.045 0.055 1.14 1.40 -
L2 0.075 0.095 1.91 2.41 -
L3 0.003 0.015 0.08 0.38 -
ND 5 5 3
NE 5 5 3
N20 203
Rev. 0 5/18/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the o verall pac kage thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
9
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products , see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Spec Number 511009-883
HA-5147/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Indexarea:Anotch or a pin one identification markshallbelocat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa C A - B
MD
SS
eA
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.405 - 10.29 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2 , 3
N8 88
Rev. 0 4/94
