To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual 78K0S/KA1+ 8-bit Single-Chip Microcontrollers PD78F9221 PD78F9221(A) PD78F9221(A2) PD78F9222 PD78F9222(A) PD78F9222(A2) Document No. U16898EJ6V0UD00 (6th edition) Date Published February 2009 NS (c) Printed in Japan 2003 PD78F9224 [MEMO] 2 User's Manual U16898EJ6V0UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U16898EJ6V0UD 3 EEPROM is a trademark of NEC Electronics Corporation. Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. * The information in this document is current as of February, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U16898EJ6V0UD INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the 78K0S/KA1+ in order to design and develop its application systems and programs. The target devices are the following subseries products. * 78K0S/KA1+: PD78F9221, 78F9222, 78F9224, 78F9221(A), 78F9222(A), <R> 78F9221(A2), 78F9222(A2) Purpose This manual is intended to give users on understanding of the functions described in the Organization below. Organization Two manuals are available for the 78K0S/KA1+: this manual and the Instruction Manual (common to the 78K/0S Series). 78K/0S Series 78K0S/KA1+ Instructions User's Manual User's Manual * Pin functions * CPU function * Internal block functions * Instruction set * Interrupts * Instruction description * Other internal peripheral functions * Electrical specifications How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of 78K0S/KA1+ Read this manual in the order of the CONTENTS. The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. How to read register formats For a bit number enclosed in a square, the bit name is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. To learn the detailed functions of a register whose register name is known See APPENDIX C REGISTER INDEX. To learn the details of the instruction functions of the 78K/0S Series Refer to 78K/0S Series Instructions User's Manual (U11047E) separately available. To learn the electrical specifications of the 78K0S/KA1+ See CHAPTER 21 and 22 ELECTRICAL SPECIFICATIONS. User's Manual U16898EJ6V0UD 5 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0S/KA1+ User's Manual This manual 78K/0S Series Instructions User's Manual U11047E <R> Documents Related to Development Software Tools (User's Manuals) Document Name RA78K0S Ver.2.00 Assembler Package CC78K0S Ver.2.00 C Compiler SM+ System Simulator ID78K0S-QB Ver.3.00 Integrated Debugger Document No. Operation U17391E Language U17390E Structured Assembly Language U17389E Operation U17416E Language U17415E Operation U18601E User Open Interface U18212E Operation U18493E PM+ Ver.6.30 U18416E Documents Related to Development Hardware Tools (User's Manuals) Document Name QB-78K0SKX1 In-Circuit Emulator U18219E QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 6 Document No. User's Manual U16898EJ6V0UD Documents Related to Flash Memory Writing (User's Manuals) Document Name Document No. PG-FP5 Flash Memory Programmer U18865E QB-Programmer Programming GUI Operation U18527E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User's Manual U16898EJ6V0UD 7 CONTENTS CHAPTER 1 OVERVIEW.........................................................................................................................14 1.1 1.2 1.3 1.4 1.5 1.6 Features ......................................................................................................................................14 Ordering Information .................................................................................................................16 Pin Configuration (Top View)....................................................................................................17 78K0S/Kx1+ Product Lineup .....................................................................................................18 Block Diagram ............................................................................................................................19 Functional Outline......................................................................................................................20 CHAPTER 2 PIN FUNCTIONS ...............................................................................................................21 2.1 2.2 Pin Function List ........................................................................................................................21 Pin Functions..............................................................................................................................23 2.2.1 2.3 P20 to P23 (Port 2)......................................................................................................................23 2.2.2 P30, P31, and P34 (Port 3)..........................................................................................................23 2.2.3 P40 to P45 (Port 4)......................................................................................................................24 2.2.4 P121 to P123 (Port 12)................................................................................................................24 2.2.5 P130 (Port 13) .............................................................................................................................24 2.2.6 RESET ........................................................................................................................................24 2.2.7 X1 and X2....................................................................................................................................25 2.2.8 AVREF ...........................................................................................................................................25 2.2.9 VDD...............................................................................................................................................25 2.2.10 VSS ...............................................................................................................................................25 Pin I/O Circuits and Connection of Unused Pins....................................................................25 CHAPTER 3 CPU ARCHITECTURE ......................................................................................................27 3.1 3.2 3.3 Memory Space ............................................................................................................................27 3.1.1 Internal program memory space..................................................................................................30 3.1.2 Internal data memory space ........................................................................................................31 3.1.3 Special function register (SFR) area............................................................................................31 3.1.4 Data memory addressing.............................................................................................................31 Processor Registers ..................................................................................................................34 3.2.1 Control registers ..........................................................................................................................34 3.2.2 General-purpose registers ...........................................................................................................36 3.2.3 Special function registers (SFRs) ................................................................................................37 Instruction Address Addressing ..............................................................................................43 3.3.1 3.4 8 Relative addressing .....................................................................................................................43 3.3.2 Immediate addressing .................................................................................................................44 3.3.3 Table indirect addressing.............................................................................................................44 3.3.4 Register addressing.....................................................................................................................45 Operand Address Addressing ..................................................................................................46 3.4.1 Direct addressing.........................................................................................................................46 3.4.2 Short direct addressing................................................................................................................47 3.4.3 Special function register (SFR) addressing .................................................................................48 3.4.4 Register addressing.....................................................................................................................49 3.4.5 Register indirect addressing ........................................................................................................50 3.4.6 Based addressing........................................................................................................................51 User's Manual U16898EJ6V0UD 3.4.7 Stack addressing......................................................................................................................... 52 CHAPTER 4 PORT FUNCTIONS........................................................................................................... 53 4.1 4.2 4.3 4.4 Functions of Ports ..................................................................................................................... 53 Port Configuration ..................................................................................................................... 54 4.2.1 Port 2........................................................................................................................................... 55 4.2.2 Port 3........................................................................................................................................... 56 4.2.3 Port 4........................................................................................................................................... 58 4.2.4 Port 12......................................................................................................................................... 63 4.2.5 Port 13......................................................................................................................................... 65 Registers Controlling Port Functions...................................................................................... 65 Operation of Port Function ....................................................................................................... 70 4.4.1 Writing to I/O port ........................................................................................................................ 70 4.4.2 Reading from I/O port.................................................................................................................. 70 4.4.3 Operations on I/O port................................................................................................................. 70 CHAPTER 5 CLOCK GENERATORS.................................................................................................... 71 5.1 5.2 5.3 5.4 5.5 5.6 Functions of Clock Generators ................................................................................................ 71 5.1.1 System clock oscillators .............................................................................................................. 71 5.1.2 Clock oscillator for interval time generation ................................................................................. 71 Configuration of Clock Generators.......................................................................................... 72 Registers Controlling Clock Generators ................................................................................. 74 System Clock Oscillators.......................................................................................................... 77 5.4.1 High-speed internal oscillator ...................................................................................................... 77 5.4.2 Crystal/ceramic oscillator ............................................................................................................ 77 5.4.3 External clock input circuit ........................................................................................................... 79 5.4.4 Prescaler ..................................................................................................................................... 79 Operation of CPU Clock Generator.......................................................................................... 80 Operation of Clock Generator Supplying Clock to Peripheral Hardware ............................ 85 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00............................................................................. 87 6.1 6.2 6.3 6.4 6.5 Functions of 16-bit Timer/Event Counter 00 ........................................................................... 87 Configuration of 16-bit Timer/Event Counter 00..................................................................... 88 Registers to Control 16-bit Timer/Event Counter 00 .............................................................. 92 Operation of 16-bit Timer/Event Counter 00 ........................................................................... 98 6.4.1 Interval timer operation................................................................................................................ 98 6.4.2 External event counter operation............................................................................................... 100 6.4.3 Pulse width measurement operations ....................................................................................... 103 6.4.4 Square-wave output operation .................................................................................................. 111 6.4.5 PPG output operations .............................................................................................................. 113 6.4.6 One-shot pulse output operation ............................................................................................... 116 Cautions Related to 16-bit Timer/Event Counter 00.............................................................121 CHAPTER 7 8-BIT TIMER 80..............................................................................................................128 7.1 7.2 7.3 7.4 Function of 8-bit Timer 80 .......................................................................................................128 Configuration of 8-bit Timer 80 ..............................................................................................129 Register Controlling 8-bit Timer 80........................................................................................131 Operation of 8-bit Timer 80 .....................................................................................................132 User's Manual U16898EJ6V0UD 9 7.4.1 7.5 Operation as interval timer.........................................................................................................132 Notes on 8-bit Timer 80 ...........................................................................................................134 CHAPTER 8 8-BIT TIMER H1 .............................................................................................................135 8.1 8.2 8.3 8.4 Functions of 8-bit Timer H1.....................................................................................................135 Configuration of 8-bit Timer H1 ..............................................................................................135 Registers Controlling 8-bit Timer H1 .....................................................................................138 Operation of 8-bit Timer H1.....................................................................................................141 8.4.1 Operation as interval timer/square-wave output ........................................................................ 141 8.4.2 Operation as PWM output mode ...............................................................................................144 CHAPTER 9 WATCHDOG TIMER .......................................................................................................150 9.1 9.2 9.3 9.4 Functions of Watchdog Timer ................................................................................................150 Configuration of Watchdog Timer ..........................................................................................152 Registers Controlling Watchdog Timer .................................................................................153 Operation of Watchdog Timer.................................................................................................155 9.4.1 Watchdog timer operation when "low-speed internal oscillator cannot be stopped" is selected by option byte .................................................................................................................................155 9.4.2 Watchdog timer operation when "low-speed internal oscillator can be stopped by software" is selected by option byte ..............................................................................................................157 9.4.3 Watchdog timer operation in STOP mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte) .........................................................................................159 9.4.4 Watchdog timer operation in HALT mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte) .........................................................................................161 CHAPTER 10 A/D CONVERTER .........................................................................................................162 10.1 10.2 10.3 10.4 Functions of A/D Converter ....................................................................................................162 Configuration of A/D Converter ..............................................................................................164 Registers Used by A/D Converter ..........................................................................................166 A/D Converter Operations .......................................................................................................171 10.4.1 Basic operations of A/D converter .............................................................................................171 10.4.2 Input voltage and conversion results .........................................................................................173 10.4.3 A/D converter operation mode................................................................................................... 174 10.5 How to Read A/D Converter Characteristics Table ..............................................................176 10.6 Cautions for A/D Converter.....................................................................................................178 CHAPTER 11 SERIAL INTERFACE UART6 ......................................................................................182 11.1 11.2 11.3 11.4 Functions of Serial Interface UART6......................................................................................182 Configuration of Serial Interface UART6 ...............................................................................186 Registers Controlling Serial Interface UART6 ......................................................................189 Operation of Serial Interface UART6......................................................................................198 11.4.1 Operation stop mode .................................................................................................................198 11.4.2 Asynchronous serial interface (UART) mode.............................................................................199 11.4.3 Dedicated baud rate generator ..................................................................................................213 CHAPTER 12 INTERRUPT FUNCTIONS ............................................................................................220 12.1 Interrupt Function Types.........................................................................................................220 12.2 Interrupt Sources and Configuration .....................................................................................220 10 User's Manual U16898EJ6V0UD 12.3 Interrupt Function Control Registers.....................................................................................223 12.4 Interrupt Servicing Operation.................................................................................................228 12.4.1 Maskable interrupt request acknowledgment operation ............................................................ 228 12.4.2 Multiple interrupt servicing......................................................................................................... 230 12.4.3 Interrupt request pending .......................................................................................................... 232 CHAPTER 13 STANDBY FUNCTION..................................................................................................233 13.1 Standby Function and Configuration ....................................................................................233 13.1.1 Standby function........................................................................................................................ 233 13.1.2 Registers used during standby .................................................................................................. 235 13.2 Standby Function Operation ..................................................................................................236 13.2.1 HALT mode ............................................................................................................................... 236 13.2.2 STOP mode .............................................................................................................................. 239 CHAPTER 14 RESET FUNCTION .......................................................................................................243 14.1 Register for Confirming Reset Source ..................................................................................250 CHAPTER 15 POWER-ON-CLEAR CIRCUIT .....................................................................................251 15.1 15.2 15.3 15.4 Functions of Power-on-Clear Circuit .....................................................................................251 Configuration of Power-on-Clear Circuit...............................................................................252 Operation of Power-on-Clear Circuit .....................................................................................252 Cautions for Power-on-Clear Circuit......................................................................................253 CHAPTER 16 LOW-VOLTAGE DETECTOR.......................................................................................255 16.1 16.2 16.3 16.4 16.5 Functions of Low-Voltage Detector .......................................................................................255 Configuration of Low-Voltage Detector.................................................................................255 Registers Controlling Low-Voltage Detector ........................................................................256 Operation of Low-Voltage Detector .......................................................................................258 Cautions for Low-Voltage Detector........................................................................................262 CHAPTER 17 OPTION BYTE ...............................................................................................................265 17.1 Functions of Option Byte ........................................................................................................265 17.2 Format of Option Byte .............................................................................................................266 17.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34).............................267 CHAPTER 18 FLASH MEMORY..........................................................................................................268 18.1 18.2 18.3 18.4 18.5 18.6 Features ....................................................................................................................................268 Memory Configuration.............................................................................................................269 Functional Outline ...................................................................................................................270 Writing with Flash Memory Programmer...............................................................................271 Programming Environment.....................................................................................................272 Pin Connection on Board........................................................................................................274 18.6.1 X1 and X2 pins .......................................................................................................................... 274 18.6.2 RESET pin ................................................................................................................................ 275 18.6.3 Port pins .................................................................................................................................... 276 18.6.4 Power supply............................................................................................................................. 276 18.7 On-Board and Off-Board Flash Memory Programming .......................................................277 User's Manual U16898EJ6V0UD 11 18.7.1 Flash memory programming mode............................................................................................277 18.7.2 Communication commands .......................................................................................................277 18.7.3 Security settings ........................................................................................................................278 18.8 Flash Memory Programming by Self Programming .............................................................279 18.8.1 Outline of self programming.......................................................................................................279 18.8.2 Cautions on self programming function .....................................................................................282 18.8.3 Registers used for self programming function ...........................................................................282 18.8.4 Example of shifting normal mode to self programming mode .................................................... 291 18.8.5 Example of shifting self programming mode to normal mode ....................................................294 18.8.6 Example of block erase operation in self programming mode ...................................................297 18.8.7 Example of block blank check operation in self programming mode .........................................300 18.8.8 Example of byte write operation in self programming mode ......................................................303 18.8.9 Example of internal verify operation in self programming mode ................................................306 18.8.10 Examples of operation when command execution time should be minimized in self programming 18.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode .........................................................................................................................................310 mode .........................................................................................................................................317 CHAPTER 19 ON-CHIP DEBUG FUNCTION .......................................................................................328 19.1 Connecting QB-MINI2 to 78K0S/KA1+ ...................................................................................328 19.1.1 Connection of INTP3 pin............................................................................................................329 19.1.2 Connection of X1 and X2 pins ...................................................................................................330 19.2 Securing of user resources.....................................................................................................331 CHAPTER 20 INSTRUCTION SET OVERVIEW .................................................................................332 20.1 Operation ..................................................................................................................................332 20.1.1 Operand identifiers and description methods ............................................................................332 20.1.2 Description of "Operation" column .............................................................................................333 20.1.3 Description of "Flag" column......................................................................................................333 20.2 Operation List ...........................................................................................................................334 20.3 Instructions Listed by Addressing Type ...............................................................................339 CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) .................342 CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product)................................................354 CHAPTER 23 PACKAGE DRAWING ..................................................................................................368 CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS...........................................................371 APPENDIX A DEVELOPMENT TOOLS...............................................................................................373 A.1 A.2 A.3 A.4 12 Software Package ....................................................................................................................376 Language Processing Software .............................................................................................376 Flash Memory Writing Tools ...................................................................................................377 A.3.1 When using flash memory programmer PG-FP5 and FL-PR5................................................... 377 A.3.2 When using on-chip debug emulator with programming function QB-MINI2 .............................377 Debugging Tools (Hardware) ..................................................................................................377 User's Manual U16898EJ6V0UD A.5 A.4.1 When using in-circuit emulator QB-78K0SKX1 ......................................................................... 377 A.4.2 When using on-chip debug emulator with programming function QB-MINI2 ............................. 378 Debugging Tools (Software)...................................................................................................379 APPENDIX B NOTES ON DESIGNING TARGET SYSTEM ................................................................380 APPENDIX C REGISTER INDEX.........................................................................................................382 C.1 C.2 Register Index (Register Name) .............................................................................................382 Register Index (Symbol)..........................................................................................................384 APPENDIX D LIST OF CAUTIONS.....................................................................................................386 APPENDIX E REVISION HISTORY .....................................................................................................405 E.1 E.2 Major Revisions in This Edition .............................................................................................405 Revision History up to Previous Editions .............................................................................406 User's Manual U16898EJ6V0UD 13 CHAPTER 1 OVERVIEW 1.1 Features O 78K0S CPU core O ROM and RAM capacities Item Program Memory (Flash Memory) Memory (Internal High-Speed RAM) Part number <R> PD78F9221 2 KB 128 bytes PD78F9222 4 KB 256 bytes PD78F9224 8 KB O Minimum instruction execution time: 0.2 s (with 10 MHz@4.0 to 5.5 V operation) O Clock * High-speed system clock ... Selected from the following three sources - Ceramic/crystal resonator: 2 to 10 MHz (Standard product, (A) grade product) 2 to 8 MHz ((A2) grade product) - External clock: 2 to 10 MHz (Standard product, (A) grade product) 2 to 8 MHz ((A2) grade product) - High-speed internal oscillator: 8 MHz 3% (-10 to +80C), 8 MHz 5% (Standard product, (A) grade product: -40 to +85C, (A2) grade product: -40 to +125C) * Low-speed internal oscillator 240 kHz (TYP.) ... Watchdog timer, timer clock in intermittent operation O I/O ports: 17 (CMOS I/O: 15, CMOS input: 1, CMOS output: 1) O Timer: 4 channels * 16-bit timer/event counter: 1 channel ... Timer output x 1, capture input x 2 * 8-bit timer: 2 channels ... PWM output x 1 * Watchdog timer: 1 channel ... Operable with low-speed internal oscillation clock O Serial interface: UART (LIN (Local Interconnect Network) bus supported) 1 channel O 10-bit resolution A/D converter: 4 channels O On-chip power-on-clear (POC) circuit (A reset is automatically generated when the voltage drops to 2.1 V (TYP.) or below) O On-chip low voltage detector (LVI) circuit (An interrupt/reset (selectable) is generated when the detection voltage is reached) * Detection voltage: Selectable from ten levels between 2.35 and 4.3 V O Single-power-supply flash memory * Flash self programming enabled * Software protection function: Protected from outside party copying (no flash reading command) * Time required for writing by dedicated flash memory programmer: Approximately 3 seconds (4 KB) Flash programming on mass production lines supported O Safety function * Watchdog timer operated by clock independent from CPU ... A hang-up can be detected even if the system clock stops * Supply voltage drop detectable by LVI ... Appropriate processing can be executed before the supply voltage drops below the operation voltage * Equipped with option byte function ... Important system operation settings set in hardware 14 User's Manual U16898EJ6V0UD CHAPTER 1 OVERVIEW O Assembler and C language supported O Enhanced development environment * Support for full-function emulator (IECUBE), simplified emulator (MINICUBE2), and simulator O Supply voltage: VDD = 2.0 to 5.5 V Use these products in the following voltage range because the detection voltage (VPOC) of the POC circuit is the supply voltage range. Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V O Operating temperature range: * Standard product, (A) grade product: TA = -40 to +85C * (A2) grade product: TA = -40 to +125C User's Manual U16898EJ6V0UD 15 CHAPTER 1 OVERVIEW 1.2 Ordering Information Part Number PD78F9 xxx - xx (x) - xxx -x Semiconductor component Lead-free Product contains no lead in any area -A (Terminal finish is Sn/Bi plating) -AX Product contains no lead in any area (Terminal finish is Ni/Pd/Au plating) Quality Grades Blank Standard (A) Special (A2) Package type MC-5A4 Plastic SSOP MC-CAA CS-CAC Plastic SDIP Number of pins <R> High-speed RAM Flash memory 221 20 pins 128 bytes 2 K bytes 222 20 pins 256 bytes 4 K bytes 224 20 pins 256 bytes 8 K bytes Product type F Flash memory versions Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. [Part number list] <R> PD78F9221MC-5A4-A PD78F9222MC-5A4-A PD78F9221MC(A)-5A4-A PD78F9222MC(A)-5A4-A PD78F9221MC(A2)-5A4-A PD78F9222MC(A2)-5A4-A PD78F9221MC(A)-CAA-AX PD78F9222MC(A)-CAA-AX PD78F9221MC(A2)-CAA-AX PD78F9222MC(A2)-CAA-AX PD78F9221CS-CAC-A PD78F9222CS-CAC-A 16 User's Manual U16898EJ6V0UD PD78F9224MC-5A4-A CHAPTER 1 OVERVIEW 1.3 Pin Configuration (Top View) * 20-pin plastic SSOP VSSNote 1 20 AVREF P121/X1 2 19 P20/ANI0 P122/X2 3 18 P21/ANI1 P123 4 17 P22/ANI2 VDD 5 16 P23/ANI3 RESET/P34 6 15 P130 P31/TI010/TO00/INTP2 7 14 P45 P30/TI000/INTP0 8 13 P44/RxD6 P40 9 12 P43/TxD6/INTP1 10 11 P42/TOH1 P41/INTP3 * 20-pin plastic SDIP P23/ANI3 1 20 P130 P22/ANI2 2 19 P45 P21/ANI1 3 18 P44/RxD6 P20/ANI0 4 17 P43/TxD6/INTP1 AVREF 5 16 P42/TOH1 VSSNote 6 15 P41/INTP3 P121/X1 7 14 P40 P122/X2 8 13 P30/TI000/INTP0 P123 9 12 P31/TI010/TO00/INTP2 10 11 RESET/P34 VDD Pin Name ANI0 to ANI3: Analog input P130: Port 13 AVREF: Analog Power Supply, RESET: Reset Analog Reference Voltage, RxD6: Receive data Power Supply for P20 to P23 TI000, TI010: Timer input INTP0 to INTP3: External interrupt input TO00, TOH1: Timer output P20 to P23: Port 2 TxD6: Transmit data P30, P31, P34: Port 3 VDD: Power supply P40 to P45: Port 4 VSSNote: Ground P121 to P123: Port 12 X1, X2: Crystal oscillator (X1 input clock) Note In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). User's Manual U16898EJ6V0UD 17 CHAPTER 1 OVERVIEW 1.4 78K0S/Kx1+ Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number 78K0S/KU1+ 78K0S/KY1+ 78K0S/KA1+ 78K0S/KB1+ 10 pins 16 pins 20 pins 30/32 pins Item Number of pins <R> Internal Flash memory 1 KB, 2 KB, 4 KB 2 KB 4 KB, memory 4 KB, 8 KB 8 KB RAM 128 bytes 128 256 bytes bytes VDD = 2.0 to 5.5 V Supply voltage 256 bytes Note 1 Minimum instruction 0.20 s (10 MHz, VDD = 4.0 to 5.5 V) execution time 0.33 s (6 MHz, VDD = 3.0 to 5.5 V) 0.40 s (5 MHz, VDD = 2.7 to 5.5 V) 1.0 s (2 MHz, VDD = 2.0 to 5.5 V) High-speed internal oscillation (8 MHz (TYP.)) Note 2 Crystal/ceramic oscillation (2 to 10 MHz) System clock (oscillation frequency) External clock input oscillation (2 to 10 MHz) Clock for TMH1 and WDT Low-speed internal oscillation (240 kHz (TYP.)) (oscillation frequency) Port Timer CMOS I/O 7 13 15 24 CMOS input 1 1 1 1 CMOS output - - 1 1 1 ch 16-bit (TM0) 8-bit (TMH) 1 ch - 8-bit (TM8) 1 ch WDT 1 ch - Serial interface LIN-Bus-supporting UART: 1 ch Note 4 Note 4 A/D converter 10 bits: 4 ch (2.7 to 5.5V) Multiplier (8 bits x 8 bits) Interrupts - 5 Internal External Reset 9 2 4 Provided POC 2.1 V (TYP.) LVI Provided (selectable by software) WDT Notes 1 Provided Note 5 RESET pin Operating temperature range Note 3 Provided Standard products: Standard products, (A) grade products: -40 to +85C -40 to +85C (A2) grade products: -40 to +125C Use these products in the following voltage range because the detection voltage (VPOC) of the power-onclear (POC) circuit is the supply voltage range. Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V 18 2 PD78F95xx does not support the crystal/ceramic oscillation. 3 The product without A/D converter ( PD78F950x) in the 78K0S/KU1+ is not supported. User's Manual U16898EJ6V0UD CHAPTER 1 OVERVIEW Notes 4 The product without A/D converter ( PD78F95xx) is provided for the 78K0S/KU1+ and 78K0S/KY1+ respectively. This product has A/D converter. 5 There are 2 and 4 factors for the products without A/D converter in the 78K0S/KU1+ and 78K0S/KY1+, respectively. 1.5 Block Diagram TO00/TI010/P31 Port 2 16-bit timer/event counter 00 TI000/P30 Port 3 4 P20 to P23 2 P30, P31 P34 8-bit timer 80 TOH1/P42 8-bit timer H1 78K0S CPU core Low-speed internal oscillator Flash memory Port 4 6 P40 to P45 Port 12 3 P121 to P123 Port 13 P130 Power on clear/ low voltage indicator POC/LVI control Watchdog timer RxD6/P44 Serial interface UART6 TxD6/P43 ANI0/P20 to ANI3/P23 Internal high-speed RAM 4 Reset control A/D converter AVREF RESET/P34 INTP0/P30 INTP1/P43 System control Interrupt control X1/P121 X2/P122 INTP2/P31 High-speed internal oscillator INTP3/P41 VDD VSSNote Note In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). User's Manual U16898EJ6V0UD 19 CHAPTER 1 OVERVIEW 1.6 Functional Outline <R> PD78F9221 Item Internal memory PD78F9222 Flash memory 2 KB 4 KB High-speed RAM 128 bytes 256 bytes Memory space 64 KB X1 input clock (oscillation frequency) Crystal/ceramic/external clock input: PD78F9224 8 KB 10 MHz (VDD = 2.0 to 5.5 V) Internal High speed (oscillation oscillation frequency) clock Low speed (for TMH1 Internal oscillation: 8 MHz (TYP.) Internal oscillation: 240 kHz (TYP.) and WDT) General-purpose registers 8 bits x 8 registers Instruction execution time 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (X1 input clock: fX = 10 MHz) I/O port Total: Timer Timer output 17 pins CMOS I/O: 15 pins CMOS input: 1 pin CMOS output: 1 pin * 16-bit timer/event counter: 1 channel * 8-bit timer (timer H1): 1 channel * 8-bit timer (timer 80): 1 channel * Watchdog timer: 1 channel 2 pins (PWM: 1 pin) A/D converter 10-bit resolution x 4 channels Serial interface LIN-bus-supporting UART mode: 1 channel Vectored interrupt sources External 4 Internal 9 * Reset by RESET pin * Internal reset by watchdog timer * Internal reset by power-on-clear Reset * Internal reset by low-voltage detector Note Supply voltage VDD = 2.0 to 5.5 V Operating temperature range Standard products, (A) grade products: TA = -40 to +85C (A2) grade products: TA = -40 to +125C Package * 20-pin plastic SSOP * 20-pin plastic SDIP Note Use these products in the following voltage range because the detection voltage (VPOC) of the power-on-clear (POC) circuit is the supply voltage range. Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V 20 User's Manual U16898EJ6V0UD CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port functions Pin Name I/O Function After Reset AlternateFunction Pin P20 to P23 I/O Port 2. Input ANI0 to ANI3 Input TI000/INTP0 4-bit I/O port. Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting software. I/O P30 Can be set to input or output mode in 1- Port 3 bit units. P31 TI010/TO00/ An on-chip pull-up resistor can be INTP2 connected by setting software. P34 Note Input P40 I/O Input only Port 4. Input - Input 6-bit I/O port. P41 Note RESET INTP3 Can be set to input or output mode in 1-bit units. P42 TOH1 An on-chip pull-up resistor can be connected by setting software. P43 TxD6/INTP1 P44 RxD6 - P45 P121 Note P122 Note I/O Port 12. Input 3-bit I/O port. Can be set to input or output mode in 1-bit units. P123 X1 Note X2 Note - An on-chip pull-up resistor can be connected only to P123 by setting software. P130 Output Port 13. Output - 1-bit output-only port Note For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. Caution The P121/X1 and P122/X2 pins are pulled down during reset. User's Manual U16898EJ6V0UD 21 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions Pin Name I/O Function After Reset AlternateFunction Pin INTP0 Input External interrupt input for which the valid edge (rising edge, Input falling edge, or both rising and falling edges) can be specified INTP1 P30/TI000 P43/TxD6 INTP2 P31/TI010/TO00 INTP3 P41 RxD6 Input Serial data input for asynchronous serial interface Input P44 TxD6 Output Serial data output for asynchronous serial interface Input P43/INTP1 TI000 Input External count clock input to 16-bit timer/event counter 00. Input P30/INTP0 Capture trigger input to capture registers (CR000 and CR010) of 16-bit timer/event counter 00 TI010 Capture trigger input to capture register (CR000) of 16-bit P31/TO00/INTP2 timer/event counter 00 TO00 Output 16-bit timer/event counter 00 output Input P31/TI010/INTP2 TOH1 Output 8-bit timer H1 output Input P42 ANI0 to ANI3 Input Analog input of A/D converter Input P20 to P23 - AVREF A/D converter reference voltage input and positive power supply - - for P20 to P23 and A/D converter RESET Input System reset input - P34 Note Input Connection of crystal/ceramic resonator for system clock - P121 Note - P122 Note Note X1 Note oscillation. External clock input X2 Note - Connection of crystal/ceramic resonator for system clock oscillation. VDD - Positive power supply - - VSS - Ground potential - - Note For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. Caution The P121/X1 and P122/X2 pins are pulled down during reset. 22 User's Manual U16898EJ6V0UD CHAPTER 2 PIN FUNCTIONS 2.2 Pin Functions 2.2.1 P20 to P23 (Port 2) P20 to P23 constitute a 4-bit I/O port, port 2. In addition to I/O port pins, these pins also have a function to input analog signals to the A/D converter. These pins can be set to the following operation modes in 1-bit units. (1) Port mode P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 2 (PU2). (2) Control mode P20 to P23 function as the analog input pins (ANI0 to ANI3) of the A/D converter. When using these pins as analog input pins, refer to 10.6 Cautions for A/D converter (5) ANI0/P20 to ANI3/P23. 2.2.2 P30, P31, and P34 (Port 3) P30 and P31 constitute a 2-bit I/O port, port 3. In addition to I/O port pins, these pins also have functions to input/output a timer signal, and input an external interrupt request signal. P34 is a 1-bit input-only port. This pin is also used as a RESET pin, and when the power is turned on, this is the reset function. For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. When P34 is used as an input port pin, connect the pull-up resistor. P30, P31 and P34 can be set to the following operation modes in 1-bit units. (1) Port mode P30 and P31 function as a 2-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 3 (PM3). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 3 (PU3). P34 functions as a 1-bit input-only port. (2) Control mode P30 and P31 function to input/output signals to/from internal timers, and to input an external interrupt request signal. (a) INTP0 and INTP2 These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI000 This pin inputs an external count clock to 16-bit timer/event counter 00, or a capture trigger signal to the capture registers (CR000 and CR010) of 16-bit timer/event counter 00. (c) TI010 This pin inputs a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00. (d) TO00 This pin outputs a signal from 16-bit timer/event counter 00. User's Manual U16898EJ6V0UD 23 CHAPTER 2 PIN FUNCTIONS 2.2.3 P40 to P45 (Port 4) P40 to P45 constitute a 6-bit I/O port, port 4. In addition to I/O port pins, these pins also have functions to output a timer signal, input external interrupt request signals, and input/output the data of the serial interface. These pins can be set to the following operation modes in 1-bit units. (1) Port mode P40 to P45 function as a 6-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 4 (PU4). (2) Control mode P40 to 45 function to output a signal from an internal timer, input external interrupt request signals, and input/output data of the serial interface. (a) INTP1 and INTP3 These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TOH1 This is the output pin of 8-bit timer H1. (c) TxD6 This pin outputs serial data from the asynchronous serial interface. (d) RxD6 This pin inputs serial data to the asynchronous serial interface. 2.2.4 P121 to P123 (Port 12) P121 to P123 constitute a 3-bit I/O port, port 12. Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). An on-chip pullup resistor can be connected to P123 by using pull-up resistor option register 12 (PU12). P121 and P122 also function as the X1 and X2, respectively. For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. Caution The P121/X1 and P122/X2 pins are pulled down during reset. 2.2.5 P130 (Port 13) This is a 1-bit output-only port. 2.2.6 RESET This pin inputs an active-low system reset signal. When the power is turned on, this is the reset function, regardless of the option byte setting. 24 User's Manual U16898EJ6V0UD CHAPTER 2 PIN FUNCTIONS 2.2.7 X1 and X2 These pins connect an oscillator to oscillate the X1 input clock. X1 and X2 also function as the P121 and P122, respectively. For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. Supply an external clock to X1. Caution The P121/X1 and P122/X2 pins are pulled down during reset. 2.2.8 AVREF This is the A/D converter reference voltage input pin and the positive power supply pin of P20 to P23 and A/D converter. When the A/D converter is not used, connect this pin to VDD. 2.2.9 VDD This is the positive power supply pin. 2.2.10 VSS This is the ground pin. In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 2.3 Pin I/O Circuits and Connection of Unused Pins Table 2-1 shows I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins Pin Name P20/ANI0 to P23/ANI3 I/O Circuit Type 11 I/O I/O Recommended Connection of Unused Pin Input: Independently connect to AVREF or VSS via a resistor. Output: Leave open. P30/TI000/INTP0 8-A Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P31/TI010/TO00/INTP2 P34/RESET 2 Input P40 8-A I/O Connect to VDD via a resistor. Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P41/INTP3 P42/TOH1 P43/TxD6/INTP1 P44/RxD6 P45 P121/X1 16-B Input: P122/X2 P123 Independently connect to VSS via a resistor. Output: Leave open. 8-A Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P130 AVREF 3-C - Output Leave open. Input Directly connect to VDD. User's Manual U16898EJ6V0UD 25 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 2 VDD Type 11 Pull up enable P-ch AVREF Data P-ch IN IN/OUT Output disable N-ch VSS Schmitt-triggered input with hysteresis characteristics Comparator P-ch + N-ch VSS AVREF (Threshold voltage) Input enable Type 3-C Type 16-B Feedback cut-off P-ch VDD P-ch Data OUT X1, IN/OUT OSC enable X2, IN/OUT N-ch VSS VDD Data P-ch Type 8-A Output disable VDD N-ch VSS Pull up enable P-ch VDD Data Data P-ch P-ch IN/OUT Output disable N-ch Output Disable VSS VSS 26 N-ch User's Manual U16898EJ6V0UD CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The 78K0S/KA1+ can access up to 64 KB of memory space. Figures 3-1 to 3-3 show the memory maps. Figure 3-1. Memory Map (PD78F9221) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 128 x 8 bits FE80H FE7FH Use prohibited Data memory space 07FFH 0800H 07FFH Program area Program memory space Flash memory 2,048 x 8 bits 0 0 0 0 082 081 080 07F H H H H Protect byte area Option byte area CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 0000H 0000H Remark The option byte and protect byte are 1 byte each. User's Manual U16898EJ6V0UD 27 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD78F9222) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Use prohibited Data memory space 0FFFH 1000H 0FFFH Program area Program memory space Flash memory 4,096 x 8 bits 0082H 0081H 0080H 007FH Protect byte area Option byte area CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 0000H 0000H Remark 28 The option byte and protect byte are 1 byte each. User's Manual U16898EJ6V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD78F9224) <R> FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Use prohibited Data memory space 1FFFH 2000H 1FFFH Program area Program memory space Flash memory 8,192 x 8 bits 0082H 0081H 0080H 007FH Protect byte area Option byte area CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 0000H 0000H Remark The option byte and protect byte are 1 byte each. User's Manual U16898EJ6V0UD 29 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KA1+ provides the following internal ROMs (or flash memory) containing the following capacities. Table 3-1. Internal ROM Capacity Part Number Internal ROM Structure PD78F9221 <R> Capacity 2,048 x 8 bits Flash memory PD78F9222 4,096 x 8 bits PD78F9224 8,192 x 8 bits The following areas are allocated to the internal program memory space. (1) Vector table area The 34-byte area of addresses 0000H to 0021H is reserved as a vector table area. This area stores program start addresses to be used when branching by Reset or interrupt request generation. Of a 16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 3-2. Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H Reset 0012H INTAD 0006H INTLVI 0016H INTP2 0008H INTP0 0018H INTP3 000AH INP1 001AH INTTM80 000CH INTTMH1 001CH INTSRE6 000EH INTTM000 001EH INTSR6 0010H INTTM010 0020H INTST6 Caution (2) No interrupt sources correspond to the vector table address 0014H. CALLT instruction table area The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH. (3) Option byte area The option byte area is the 1-byte area of address 0080H. For details, refer to CHAPTER 17 OPTION BYTE. (4) Protect byte area The protect byte area is the 1-byte area of address 0081H. For details, refer to CHAPTER 18 FLASH MEMORY. 30 User's Manual U16898EJ6V0UD CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space <R> 128-byte internal high-speed RAM is provided in the PD78F9221, and 256-byte in the PD78F9222 and PD78F9224. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3). 3.1.4 Data memory addressing The 78K0S/KA1+ is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. The area (FE80H to FEFFH or FE00H to FEFFH) which contains a data memory and the special function register area (SFR) can be accessed using a unique addressing mode in accordance with each function. Figures 3-4 to 3-6 illustrate the data memory addressing. Figure 3-4. Data Memory Addressing (PD78F9221) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 128 x 8 bits FE80H FE7FH Direct addressing Register indirect addressing Based addressing Use prohibited 0800H 07FFH Flash memory 2,048 x 8 bits 0000H User's Manual U16898EJ6V0UD 31 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Data Memory Addressing (PD78F9222) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Use prohibited 1000H 0FFFH Flash memory 4,096 x 8 bits 0000H 32 User's Manual U16898EJ6V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Data Memory Addressing (PD78F9224) <R> FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Use prohibited 2000H 1FFFH Flash memory 8,192 x 8 bits 0000H User's Manual U16898EJ6V0UD 33 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0S/KA1+ provides the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-7. Program Counter Configuration 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are stored in stack area upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETI and POP PSW instructions. Reset signal generation sets PSW to 02H. Figure 3-8. Program Status Word Configuration 7 PSW IE 0 Z 0 AC 0 0 1 CY (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled. When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources. This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases. 34 User's Manual U16898EJ6V0UD CHAPTER 3 CPU ARCHITECTURE (d) Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack area). Figure 3-9. Stack Pointer Configuration 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented before writing (saving) to the stack memory and is incremented after reading (restoring) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-10 and 3-11. Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack memory. 2. Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits can be actually set. Thus, if the stack pointer is specified to 0FF00H, it is converted to 0FB00H in the highspeed RAM area, since 0FF00H is in the SFR area and not in the high-speed RAM area. When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to become 0FAFFH, but since that value is not in the high-speed RAM area, it is converted to 0FEFFH, which is the same value as when 0FF00H is set to the stack pointer. Figure 3-10. Data to Be Saved to Stack Memory PUSH rp instruction Interrupt CALL, CALLT instructions SP SP SP _ 2 SP SP _ 2 SP _ 3 SP _ 3 PC7 to PC0 SP _ 2 Lower half register pairs SP _ 2 PC7 to PC0 SP _ 2 PC15 to PC8 SP _ 1 Upper half register pairs SP _ 1 PC15 to PC8 SP _ 1 PSW SP SP User's Manual U16898EJ6V0UD SP 35 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data to Be Restored from Stack Memory POP rp instruction SP RET instruction RETI instruction SP Lower half register pairs SP PC7 to PC0 SP PC7 to PC0 SP + 1 Upper half register pairs SP + 1 PC15 to PC8 SP + 1 PC15 to PC8 SP + 2 PSW SP + 2 SP SP + 2 SP SP + 3 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 3-12. General-Purpose Register Configuration (1/2) (a) Function names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 36 0 7 User's Manual U16898EJ6V0UD 0 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. General-Purpose Register Configuration (2/2) (b) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 3.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with the address and bit. * 8-bit manipulation Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying an address, describe an even address. Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows: * Symbol Indicates the addresses of the implemented special function registers. It is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. User's Manual U16898EJ6V0UD 37 CHAPTER 3 CPU ARCHITECTURE * R/W Indicates whether the special function register can be read or written. R/W: Read/write R: Read only W: Write only * Number of bits manipulated simultaneously Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated. * After reset Indicates the status of the special function register when a reset is input. 38 User's Manual U16898EJ6V0UD CHAPTER 3 CPU ARCHITECTURE <R> Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously - FF00H, 7 6 5 4 3 2 1 0 - - - - - - - - 1 8 16 - - - - - - R/W - 00H 66 - 00H 66 - 00H 66 - - - - - page Address Reference Table 3-3. Special Function Registers (1/4) FF01H FF02H P2 0 0 0 0 P23 P22 P21 P20 FF03H P3 0 0 0 P34 0 0 P31 P30 FF04H P4 0 0 P45 P44 P43 P42 P41 P40 - - - - - - - - Note 1 - FF05H to - FF0BH FF0CH P12 0 0 0 0 P123 P122 P121 0 FF0DH P13 0 0 0 0 0 0 0 P130 FF0EH CMP01 - - - - - - - - FF0FH CMP11 - - - - - - - - - - - - - - - - - TM00 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 00H 66 - 00H 66 - - 00H 137 - - 00H 137 - - - - - - R - - 0000H 89 R/W - - 0000H 89 - - 0000H 91 - - Undefined 169 - - R/W Note 1 FF10H, R/W FF11H FF12H FF13H FF14H CR000 FF15H CR010 FF16H Note 2 - - - - - - - - - - - - - - - - 0 0 0 0 0 0 - - ADCRH - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 PM23 PM22 PM21 PM20 R/W - FFH FF19H FF1AH Note 2 ADCR FF17H FF18H Note 2 - FF1BH R Note 2 170 - to FF21H FF22H PM2 65, 170 FF23H PM3 1 1 1 1 1 1 PM31 PM30 - FFH 65, 97 FF24H PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40 - FFH 65, 140, 197 - FF25H to - - - - - - - - - - - - - - FF2BH FF2CH PM12 1 1 1 1 1 R/W - FFH 65 FF2DH - - - - - - - - - - - - - - - R/W - 00H 69 - 00H 69 - 00H 69 - - - - - PM123 PM122 PM121 to FF31H FF32H PU2 0 0 0 0 PU23 PU22 PU21 PU20 FF33H PU3 0 0 0 0 0 0 PU31 PU30 FF34H PU4 0 0 PU45 PU44 PU43 PU42 PU41 PU40 - - - - - - - - - FF35H to - FF3BH FF3CH PU12 0 0 0 0 PU123 0 0 0 R/W - 00H 69 FF3DH - - - - - - - - - - - - - - - to FF47H Notes 1. Only P34 is an input-only port. 2. A 16-bit access is possible only by the short direction addressing. User's Manual U16898EJ6V0UD 39 CHAPTER 3 CPU ARCHITECTURE <R> Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF48H WDTM 7 6 5 4 3 2 1 0 0 1 1 WDCS WDCS WDCS WDCS WDCS 4 3 2 1 0 R/W page Address Reference Table 3-3. Special Function Registers (2/4) 1 8 16 - - 67H 153 FF49H WDTE - - - - - - - - - - 9AH 154 FF50H LVIM <LVI 0 0 0 0 0 <LVI <LVI - 00H 256 MD> F> LVIS1 LVIS0 ON> FF51H LVIS 0 0 0 0 LVIS3 LVIS2 Note 1 - - 00H 257 Note 1 - FF52H, - - - - - - - - - - - - 0 0 0 WDT 0 0 0 LVIRF R - - - - FF53H FF54H RESF - - - - - - - - LSRCM 0 0 0 0 0 0 0 FF55H to 00H 250 Note 2 RF - - - - - - - <LSR R/W - 00H 75 FF57H FF58H STOP> - FF59H to - - - - - - - - - - - - - - 0 0 0 0 TMC TMC TMC <OVF R/W - 00H 92 003 002 001 00> 0 0 PRM PRM - 00H 96 001 000 CRC CRC CRC - 00H 94 002 001 000 - 00H 95 - - - - - - R/W - 00H FF5FH FF60H TMC00 FF61H PRM00 FF62H CRC00 FF63H TOC00 ES110 0 0 ES100 0 ES010 0 <OSPT <OSPE ES000 0 0 TOC <LVS <LVR TOC <TOE 00> 00> 004 00> 00> 001 00> - - - - - - - - - TMHMD <TMH CKS12 CKS11 CKS10 TMMD TMMD 11 10 V1> 1> - - - - - - - - R/W - 00H 167 - 00H 169 - - - - - R/W - 00H FF64H to FF6FH FF70H 1 E1> - FF71H to - - - - - <TOLE <TOEN 138 - FF7FH FF80H ADM <ADCS> 0 FR2 FR1 FR0 0 0 <ADCE> FF81H ADS 0 0 0 0 0 0 ADS1 ADS0 FF82H, - - - - - - - - - 0 0 0 0 - - - - - - - - - - - - - 0 0 0 0 0 0 ISC1 ISC0 R/W - 00H - FF83H FF84H PMC2 - FF85H to PMC23 PMC22 PMC21 PMC20 67, 170 - FF8BH FF8CH ISC 197 Notes 1. Retained only after a reset by LVI. 2. Varies depending on the reset cause. Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. 40 User's Manual U16898EJ6V0UD CHAPTER 3 CPU ARCHITECTURE <R> Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously - FF8DH 7 6 5 4 3 2 1 0 1 8 16 - - - - - - - - - - - - - PS61 PS60 CL6 SL6 ISRM6 R/W - 01H - - - - - - - - - - R page Address Reference Table 3-3. Special Function Registers (3/4) - to FF8FH FF90H ASIM6 <POW <TXE6> <RXE6> 189 ER6> - FF91H - - - - FF92H RXB6 - - - - - - - - FF93H ASIS6 0 0 0 0 0 PE6 FE6 OVE6 FF94H TXB6 - - - - - - - - R/W - - FFH 188 FF95H ASIF6 0 0 0 0 0 0 TXBF6 TXSF6 R - - 00H 192 0 0 0 0 TPS63 TPS62 TPS61 TPS60 R/W - - 00H 193 - - FFH 194 - 16H 195 - - - - - - FF96H CKSR6 FF97H BRGC6 MLD67 MLD66 MLD65 MLD64 MLD63 MLD62 FF98H ASICL6 <SBRF <SBRT SBTT6 SBL62 SBL61 6> 6> - - - - - - FFA0H PFCMD REG7 REG6 REG5 REG4 FFA1H PFS 0 0 0 0 FF99H to SBL60 MLD61 MLD60 DIR6 TXDLV - - FFH 188 - - 00H 191 6 - - - REG3 REG2 REG1 REG0 W - - Undefined 283 0 WEPR VCE FPR R/W - 00H 284 ERR RR ERR 0 FLSPM - - Undefined 282 FLCM - 00H 285 Undefined 286 FF9FH FFA2H FFA3H FLPMC FLCMD 0 0 PRSEL PRSEL PRSEL PRSEL PRSEL F4 F3 F2 F1 0 0 0 0 F0 FLCMD FLCMD 2 1 D0 FFA4H FLAPL FLAP7 FLAP6 FLAP5 FLAP4 FLAP3 FLAP2 FLAP1 FLAP0 - FFA5H FLAPH 0 0 0 0 FLA FLA FLA FLA - P11 P10 P9 P8 FLAP FLAP FLAP FLAP - C11 C10 C9 C8 - FFA6H FFA7H FFA8H FLAPHC FLAPLC 0 0 0 0 FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP C7 C6 C5 C4 C3 C2 C1 C0 286 00H 287 287 FLW7 FLW6 FLW5 FLW4 FLW3 FLW2 FLW1 FLW0 - - - - - - - - - - - - - - - - TMC80 <TCE 0 0 0 0 TCL TCL 0 R/W - 00H 131 801 800 - - - W - - Undefined 130 130 FLW FFA9H to 288 - FFCBH FFCCH 80> FFCDH CR80 - FFCEH TM80 - - - - - - - - R - - 00H - - - - - - - - - - - - - <ADIF> <TMIF <TMIF <TMIF <PIF1> <PIF0> <LVIIF> 0 R/W - 00H 224 010> 000> H1> <STIF <SRIF <SRE <TMIF 0 - 00H 224 6> 6> IF6> 80> - FFCFH to - - - - - FFDFH FFE0H FFE1H IF0 IF1 0 <PIF3> <PIF2> Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. User's Manual U16898EJ6V0UD 41 CHAPTER 3 CPU ARCHITECTURE <R> Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously - FFE2H, page Address Reference Table 3-3. Special Function Registers (4/4) 7 6 5 4 3 2 1 0 1 8 16 - - - - - - - - - - - - - 1 R/W - FFH 225 - FFH 225 - FFE3H FFE4H MK0 FFE5H MK1 FFE6H to - <ADM <TMM <TMM <TMM <PMK <PMK <LVI K> K010> K000> KH1> 1> 0> MK> 1 <STMK <SRM <SRE <TMM <PMK <PMK 6> K6> MK6> K80> 3> 2> - - - - - - - - - - - - - ES21 ES20 ES11 ES10 ES01 ES00 0 0 R/W - - 00H 226 - - 00H 227 - - - - - - R/W - 02H 74 - - Undefined 76, 235 1 - FFEBH FFECH INTM0 FFEDH INTM1 - FFEEH 0 0 0 0 0 0 ES31 ES30 - - - - - - - - to FFF2H FFF3H PPCC 0 0 0 0 0 0 PPCC1 PPCC0 FFF4H OSTS 0 0 0 0 0 0 OSTS1 OSTS0 Note FFF5H to - - - - - - - - - - - - - - - FFFAH FFFBH PCC 0 0 0 0 0 0 PCC1 0 R/W - 02H 74 FFFCH - - - - - - - - - - - - - - - to FFFFH Note The oscillation stabilization time that elapses after release of reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. 42 User's Manual U16898EJ6V0UD CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination address information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) to branch. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes the sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC is the start address of PC the next instruction of a BR instruction. + 8 15 7 6 0 S jdisp8 15 0 PC When S = 0, indicates that all bits are "0". When S = 1, indicates that all bits are "1". User's Manual U16898EJ6V0UD 43 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions 7 0 PC CALL or BR PC+1 Low addr. PC+2 High addr. 15 8 7 0 PC 3.3.3 Table indirect addressing [Function] The table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH. [Illustration] Instruction code 7 6 0 1 5 1 ta4-0 0 15 Effective address 0 7 0 0 0 0 0 0 Memory (Table) 0 8 7 6 0 0 1 5 1 0 0 0 Low addr. High addr. Effective address + 1 15 8 7 PC 44 User's Manual U16898EJ6V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 7 A 15 0 X 8 7 0 PC User's Manual U16898EJ6V0UD 45 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !0FE80H; When setting !addr16 to FE80H Instruction code 0 0 1 0 1 0 0 1 OP code 1 0 0 0 0 0 0 0 80H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (low) addr16 (high) Memory 46 User's Manual U16898EJ6V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH (FE80H to FEFFH (internal high-speed RAM) + FF00H to FF1FH (special function registers)) for the PD78F9221, or the 256-byte space FE20H to FF1FH (FE20H to FEFFH (internal high-speed RAM) + FF00H to FF1FH (special function <R> registers)) for the PD78F9222 and 78F9224. The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below. [Operand format] Identifier Description saddr PD78F9221: Label or FE80H to FF1FH immediate data PD78F9222, 78F9224: Label or FE20H to FF1FH immediate data saddrp PD78F9221: Label or FE80H to FF1FH immediate data (even address only) PD78F9222, 78F9224: Label or FE20H to FF1FH immediate data (even address only) <R> <R> [Description example] EQU DATA1 0FE90H ; DATA1 shows FE90H of a saddr area, MOV FE90H, #50H ; When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 0 90H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 0 OP code saddr-offset Short direct memory 15 Effective address 1 8 1 1 1 1 1 1 0 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. User's Manual U16898EJ6V0UD 47 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH are accessed with short direct addressing. [Operand format] Identifier Description sfr Special function register name [Description example] MOV PM0, A; When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 0 OP code sfr-offset SFR 15 Effective address 48 1 8 7 1 1 1 1 1 1 1 User's Manual U16898EJ6V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL `r' and `rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register specify code INCW DE; When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code User's Manual U16898EJ6V0UD 49 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [DE], [HL] [Description example] MOV A, [DE]; When selecting register pair [DE] Instruction code 0 0 1 0 1 0 1 1 [Illustration] 15 8 7 E D DE 0 7 The contents of addressed memory are transferred 7 0 A 50 User's Manual U16898EJ6V0UD 0 Memory address specified by register pair DE CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier Description - [HL+byte] [Description example] MOV A, [HL+10H]; When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 [Illustration] 16 8 7 0 L H HL 7 Memory 0 +10H The contents of addressed memory are transferred 7 0 A User's Manual U16898EJ6V0UD 51 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt request generation. Stack addressing can be used to access the internal high-speed RAM area only. [Description example] In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 [Illustration] 7 SP SP 52 FEE0H FEDEH Memory FEE0H FEDFH D FEDEH E User's Manual U16898EJ6V0UD 0 CHAPTER 4 PORT FUNCTIONS 4.1 Functions of Ports The 78K0S/KA1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Functions P40 P20 Port 2 Port 4 P23 P45 P121 P30 P31 P34 Port 3 Port 12 P123 Port 13 P130 User's Manual U16898EJ6V0UD 53 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name I/O Function After Reset AlternateFunction Pin P20 to P23 I/O Port 2. Input ANI0 to ANI3 Input TI000/INTP0 4-bit I/O port. Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected by setting software. I/O P30 Can be set to input or output mode in 1- Port 3 bit units. P31 TI010/TO00/ On-chip pull-up resistor can be connected by setting software. P34 Note Input I/O P40 Input only INTP2 Input Port 4. INTP3 Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected setting software. P42 - Input 6-bit I/O port. P41 Note RESET TOH1 P43 TxD6/INTP1 P44 RxD6 - P45 P121 Note P122 Note I/O Port 12. Input 3-bit I/O port. Note - On-chip pull-up resistor can be connected only to P123 by setting software. P130 Output X1 X2 Can be set to input or output mode in 1-bit units. P123 Note Port 13. Output - 1-bit output-only port. Note For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. Caution The P121/X1 and P122/X2 pins are pulled down during reset. Remarks 1. P121 and P122 can be allocated when the high-speed internal oscillation is selected as the system clock. 2. P122 can be allocated when an external clock is selected as the system clock. 4.2 Port Configuration Ports consist of the following hardware units. Table 4-2. Configuration of Ports Item Control registers Configuration Port mode registers (PM2, PM3, PM4, PM12) Port registers (P2, P3, P4, P12, P13) Port mode control register 2 (PMC2) Pull-up resistor option registers (PU2, PU3, PU4, PU12) Ports Total: 17 (CMOS I/O: 15, CMOS input: 1, CMOS output: 1) Pull-up resistor Total: 13 54 User's Manual U16898EJ6V0UD CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 2 Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2). This port is also used as the analog input pins of the internal A/D converter. Reset signal generation sets port 2 to the input mode. Figure 4-2 shows the block diagram of port 2. Figure 4-2. Block Diagram of P20 to P23 VDD WRPU PU2 PU20 to PU23 P-ch WRPMC PMC2 PMC20 to PMC23 Selector Internal bus RD WRPORT P2 Output latch (P20 to P23) P20/ANI0 to P23/ANI3 WRPM PM2 PM20 to PM23 A/D converter P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 RD: Read signal WRxx: Write signal User's Manual U16898EJ6V0UD 55 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 3 Pins P30 and P31 constitute a 2-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 3 (PM3). When the P30 to P31 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3). This port is also used for both timer I/O and external interrupt request input pin functions. Reset signal generation sets port 3 to the input mode. P34 is a 1-bit input-only port. This pin is also used as a RESET pin, and when the power is turned on, this is the reset function. For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. When P34 is used as an input port pin, connect the pull-up resistor. Figures 4-3 to 4-5 show the block diagrams of port 3. Figure 4-3. Block Diagram of P30 VDD WRPU PU3 PU30 P-ch Alternate function Internal bus Selector RD WRPORT P3 Output latch (P30) WRPM P30/TI000/INTP0 PM3 PM30 P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal 56 User's Manual U16898EJ6V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P31 VDD WRPU PU3 PU31 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P31) P31/TI010/TO00/INTP2 WRPM PM3 PM31 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal User's Manual U16898EJ6V0UD 57 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P34 Internal bus RD P34/RESET Reset Option byte RD: Read signal Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Also, since the option byte is referenced after the reset release, if low level is input to the RESET pin before the referencing, then the reset state is not released. When it is used as an input port pin, connect the pull-up resistor. 4.2.3 Port 4 Port 4 is a 6-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4). When the P40 to P45 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 4 (PU4). Alternate functions include external interrupt request input, serial interface data I/O, and timer output. Reset signal generation sets port 4 to the input mode. Figures 4-6 to 4-9 show the block diagrams of port 4. 58 User's Manual U16898EJ6V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P40 and P45 VDD WRPU PU4 PU40, PU45 P-ch Selector Internal bus RD WRPORT P4 Output latch (P40, P45) P40, P45 WRPM PM4 PM40, PM45 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal User's Manual U16898EJ6V0UD 59 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P41 and P44 VDD WRPU PU4 PU41, PU44 P-ch Alternate function Selector Internal bus RD WRPORT P4 Output latch (P41, P44) P41/INTP3, P44/RxD6 WRPM PM4 PM41, PM44 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal 60 User's Manual U16898EJ6V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P42 VDD WRPU PU4 PU42 P-ch Selector Internal bus RD WRPORT P4 Output latch (P42) P42/TOH1 WRPM PM4 PM42 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal User's Manual U16898EJ6V0UD 61 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P43 VDD WRPU PU4 PU43 P-ch Alternate function Selector Internal bus RD WRPORT P4 Output latch (P43) P43/TxD6/INTP1 WRPM PM4 PM43 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal 62 User's Manual U16898EJ6V0UD CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 12 Port 12 is a 3-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). When the P123 pin is used as an input port, an on-chip pull-up resistor can be connected by using pull-up resistor option register 12 (PU12). The P121 and P122 pins are also used as the X1 and X2 pins of the system clock oscillator. The functions of the P121 and P122 pins differ, therefore, depending on the selected system clock oscillator. The following three system clock oscillators can be used. (1) High-speed internal oscillator The P121 and P122 pins can be used as I/O port pins. (2) Crystal/ceramic oscillator The P121 and P122 pins cannot be used as I/O port pins because they are used as the X1 and X2 pins. (3) External clock input The P121 pin is used as the X1 pin to input an external clock, and therefore it cannot be used as an I/O port pin. The P122 pin can be used as an I/O port pin. The system clock oscillation is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Reset signal generation sets port 12 to the input mode. Figures 4-10 and 4-11 show the block diagrams of port 12. Figure 4-10. Block Diagram of P121 and P122 Selector Internal bus RD WRPORT P12 Output latch (P121, P122) P121/X1, P122/X2 WRPM PM12 PM121, PM122 P12: Port register 12 PM12: Port mode register 12 RD: Read signal WRxx: Write signal User's Manual U16898EJ6V0UD 63 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P123 VDD WRPU PU12 PU123 P-ch Selector Internal bus RD WRPORT P12 Output latch (P123) P123 WRPM PM12 PM123 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WRxx: Write signal 64 User's Manual U16898EJ6V0UD CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 13 This is a 1-bit output-only port. Figure 4-12 shows the block diagram of port 13. Figure 4-12. Block Diagram of P130 Internal bus RD WRPORT P13 Output latch (P130) P13: Port register 13 RD: Read signal P130 WRxx: Write signal Remark When a reset is input, P130 outputs a low level. If P130 outputs a high level immediately after reset is released, the output signal of P130 can be used as a dummy CPU reset signal. 4.3 Registers Controlling Port Functions The ports are controlled by the following four types of registers. * Port mode registers (PM2, PM3, PM4, PM12) * Port registers (P2, P3, P4, P12, P13) * Port mode control register 2 (PMC2) * Pull-up resistor option registers (PU2, PU3, PU4, PU12) (1) Port mode registers (PM2, PM3, PM4, PM12) These registers are used to set the corresponding port to the input or output mode in 1-bit units. Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When a port pin is used as an alternate-function pin, set its port mode register and output latch as shown in Table 4-3. Caution Because P30, P31, and P43 are also used as external interrupt pins, the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. To use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance. User's Manual U16898EJ6V0UD 65 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Format of Port Mode Register Address: FF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 Address: FF23H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 1 1 1 1 PM31 PM30 Address: FF24H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40 Address: FF2CH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM12 1 1 1 1 PM123 PM122 PM121 1 PMmn Selection of I/O mode of Pmn pin (m = 2, 3, 4, or 12; n = 0 to 5) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF) (2) Port registers (P2, P3, P4, P12, P13) These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin level is read in the input mode, and the value of the output latch of the port is read in the output mode. P20 to P23, P30, P31, P34, P40 to P45, P121 to P123, and P130 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H. 66 User's Manual U16898EJ6V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Port Register Address: FF02H After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P2 0 0 0 0 P23 P22 P21 P20 Address: FF03H After reset: 00H Note (Output latch) R/W Note Symbol 7 6 5 4 3 2 1 0 P3 0 0 0 P34 0 0 P31 P30 Address: FF04H After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P4 0 0 P45 P44 P43 P42 P41 P40 Address: FF0CH After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P12 0 0 0 0 P123 P122 P121 0 Address: FF0DH After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P13 0 0 0 0 0 0 0 P130 Pmn m = 2, 3, 4, 12, or 13; n = 0 to 5 Controls of output data (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level Note Because P34 is read-only, its reset value is undefined. (3) Port mode control register 2 (PMC2) This register specifies the port mode or A/D converter mode. Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units. PMC2 is set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PMC2 to 00H. User's Manual U16898EJ6V0UD 67 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Format of Port Mode Control Register 2 Address: FF84H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Specification of operation mode (n = 0 to 3) 0 Port mode 1 A/D converter mode Caution When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot be used as port pins. Be sure to set the pull-up resistor option registers (PU20 to PU23) to 0 for the pins set to A/D converter mode. Table 4-3. Setting of Port Mode Register, Port Register (Output Latch), and Port Mode Control Register When Alternate Function Is Used Port Name Alternate-Function Pin PMxx Name Pxx PMC2n (n = 0 to 3) I/O P20 to P23 ANI0 to ANI3 Input 1 x 1 P30 TI000 Input 1 x - INTP0 Input 1 x - TO00 Output 0 0 - TI010 Input 1 x - INTP2 Input 1 x - P41 INTP3 Input 1 x - P42 TOH1 Output 0 0 - P43 TxD6 Output 0 1 - INTP1 Input 1 x - RxD6 Input 1 x - P31 P44 Remark x: don't care PMxx: Port mode register, Pxx: Port register (output latch of port) PMC2x: Port mode control register 68 User's Manual U16898EJ6V0UD CHAPTER 4 PORT FUNCTIONS (4) Pull-up resistor option registers (PU2, PU3, PU4, PU12) These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P30, P31, P40 to P45, and P123. By setting PU2, PU3, PU4, or PU12, an on-chip pull-up resistor can be connected to the port pin corresponding to the bit of PU2, PU3, PU4, or PU12. PU2, PU3, PU4, and PU12 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation set these registers to 00H. Figure 4-16. Format of Pull-up Resistor Option Register Address: FF32H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU2 0 0 0 0 PU23 PU22 PU21 PU20 Address: FF33H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU3 0 0 0 0 0 0 PU31 PU30 Address: FF34H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU4 0 0 PU45 PU44 PU43 PU42 PU41 PU40 Address: FF3CH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU12 0 0 0 0 PU123 0 0 0 PUmn Selection of connection of on-chip pull-up resistor of Pmn (m = 2, 3, 4, or 12; n = 0 to 5) 0 Does not connect on-chip pull-up resistor 1 Connects on-chip pull-up resistor User's Manual U16898EJ6V0UD 69 CHAPTER 4 PORT FUNCTIONS 4.4 Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and outputs. 4.4.1 Writing to I/O port (1) In output mode The data can be written to the output latch by a transfer instruction. In addition, the data of the output latch are output from the pin. Once data is written to the output latch, it is retained until new data is written to the output latch. When a reset signal is generated, cleans the data in the output latch. (2) In input mode The data can be written to the output latch by a transfer instruction. Because the output buffer is off, however, the pin status remains unchanged. Once data is written to the output latch, it is retained until new data is written to the output latch. When a reset signal is generated, cleans the data in the output latch. 4.4.2 Reading from I/O port (1) In output mode The data of the output latch can be read by a transfer instruction. The data of the output latch remain unchanged. (2) In input mode The pin status can be read by a transfer instruction. The contents of the output latch remain unchanged. 4.4.3 Operations on I/O port (1) In output mode An operation is performed on the data of the output latch. The result is written to the output latch. The data of the output latch are output from the pin. Once data is written to the output latch, it is retained until new data is written to the output latch. When a reset signal is generated, cleans the data in the output latch. (2) In input mode The pin level is read and an operation is performed on its data. The operation result is written to the output latch. However, the pin status remains unchanged because the output buffer is off. When a reset signal is generated, cleans the data in the output latch. 70 User's Manual U16898EJ6V0UD CHAPTER 5 CLOCK GENERATORS 5.1 Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the watchdog timer and 8-bit timer H1 (TMH1). 5.1.1 System clock oscillators The following three types of system clock oscillators are used. * High-speed internal oscillator This circuit internally oscillates a clock of 8 MHz (TYP.). Its oscillation can be stopped by execution of the STOP instruction. If the high-speed internal oscillator is selected to supply the system clock, the X1 and X2 pins can be used as I/O port pins. * Crystal/ceramic oscillator This circuit oscillates a clock with a crystal/ceramic oscillator connected across the X1 and X2 pins. It can oscillate a clock of 2 to 10 MHz. Oscillation of this circuit can be stopped by execution of the STOP instruction. * External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. A clock of 2 to 10 MHz can be supplied. Internal clock supply can be stopped by execution of the STOP instruction. If the external clock input is selected as the system clock, the X2 pin can be used as an I/O port pin. The system clock source is selected by using the option byte. For details, refer to CHAPTER 17 OPTION BYTE. When using the X1 and X2 pins as I/O port pins, refer to CHAPTER 4 PORT FUNCTIONS for details. 5.1.2 Clock oscillator for interval time generation The following circuit is used as a clock oscillator for interval time generation. * Low-speed internal oscillator This circuit oscillates a clock of 240 kHz (TYP.). Its oscillation can be stopped by using the low-speed internal oscillation mode register (LSRCM) when it is specified by the option byte that its oscillation can be stopped by software. User's Manual U16898EJ6V0UD 71 CHAPTER 5 CLOCK GENERATORS 5.2 Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Control registers Configuration Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillation stabilization time select register (OSTS) Oscillators Crystal/ceramic oscillator High-speed internal oscillator External clock input circuit Low-speed internal oscillator 72 User's Manual U16898EJ6V0UD CHAPTER 5 CLOCK GENERATORS Figure 5-1. Block Diagram of Clock Generators Internal bus Oscillation stabilization time select register (OSTS) OSTS1 OSTS0 Processor clock control register (PCC) Preprocessor clock control register (PPCC) PPCC1 PPCC0 PCC1 System clock oscillation stabilization time counter Controller STOP Watchdog timer System clock oscillatorNote Crystal/ceramic oscillation X2/P122 External clock input CPU clock (fCPU) Prescaler fX fX 2 fX 22 Selector X1/P121 C P U High-speed internal oscillation Selector fXP 22 fXP Prescaler Clock to peripheral hardware (fXP) Low-speed internal oscillator fRL 8-bit timer H1, watchdog timer Option byte 1: Cannot be stopped. 0: Can be stopped. LSRSTOP Low-speed internal oscillation mode register (LSRCM) Internal bus Note Select the high-speed internal oscillator, crystal/ceramic oscillator, or external clock input circuit as the system clock source by using the option byte. User's Manual U16898EJ6V0UD 73 CHAPTER 5 CLOCK GENERATORS 5.3 Registers Controlling Clock Generators The clock generators are controlled by the following four registers. * Processor clock control register (PCC) * Preprocessor clock control register (PPCC) * Low-speed internal oscillation mode register (LSRCM) * Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) and preprocessor clock control register (PPCC) These registers are used to specify the division ratio of the system clock. PCC and PPCC are set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC and PPCC to 02H. Figure 5-2. Format of Processor Clock Control Register (PCC) Address: FFFBH After reset: 02H R/W Symbol 7 6 5 4 3 2 1 0 PCC 0 0 0 0 0 0 PCC1 0 Figure 5-3. Format of Preprocessor Clock Control Register (PPCC) Address: FFF3H After reset: 02H R/W Symbol 7 6 5 4 3 2 1 0 PPCC 0 0 0 0 0 0 PPCC1 PPCC0 PPCC1 PPCC0 PCC1 0 0 0 fX 0 1 0 fX/2 0 0 1 fX/2 2 1 0 0 fX/2 2 Note 2 0 1 1 fX/2 3 Note 1 1 0 1 fX/2 4 Note 2 Other than above Selection of CPU clock (fCPU) Note 1 Setting prohibited Notes 1. If PPCC = 01H, the clock (fXP) supplied to the peripheral hardware is fX/2. 2. If PPCC = 02H, the clock (fXP) supplied to the peripheral hardware is fX/22. 74 User's Manual U16898EJ6V0UD CHAPTER 5 CLOCK GENERATORS The fastest instruction of the 78K0S/KA1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Note Minimum Instruction Execution Time: 2/fCPU High-speed internal oscillation clock (at 8.0 MHz (TYP.)) fX Crystal/ceramic oscillation clock or external clock input (at 10.0 MHz) 0.25 s 0.2 s 0.5 s 0.4 s fX/2 2 1.0 s 0.8 s fX/2 3 2.0 s 1.6 s fX/2 4 4.0 s 3.2 s fX/2 Note The CPU clock (high-speed internal oscillation clock, crystal/ceramic oscillation clock, or external clock input) is selected by the option byte. (2) Low-speed internal oscillation mode register (LSRCM) This register is used to select the operation mode of the low-speed internal oscillator (240 kHz (TYP.)). This register is valid when it is specified by the option byte that the low-speed internal oscillator can be stopped by software. If it is specified by the option byte that the low-speed internal oscillator cannot be stopped by software, setting of this register is invalid, and the low-speed internal oscillator continues oscillating. In addition, the source clock of WDT is fixed to the low-speed internal oscillator. For details, refer to CHAPTER 9 WATCHDOG TIMER. LSRCM can be set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets LSRCM to 00H. Figure 5-4. Format of Low-Speed internal oscillation Mode Register (LSRCM) Address: FF58H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> LSRCM 0 0 0 0 0 0 0 LSRSTOP LSRSTOP Oscillation/stop of low-speed internal oscillator 0 Low-speed internal oscillates 1 Low-speed internal oscillator stops User's Manual U16898EJ6V0UD 75 CHAPTER 5 CLOCK GENERATORS (3) Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released. If the high-speed internal oscillator or external clock input is selected as the system clock source, no wait time elapses. The system clock oscillator and the oscillation stabilization time that elapses after power application or release of reset are selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. OSTS is set by using an 8-bit memory manipulation instruction. Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFF4H After reset: Undefined R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 0 0 2 /fX (102.4 s) 0 1 2 /fX (409.6 s) 1 0 2 /fX (3.27 ms) 1 1 2 /fX (13.1 ms) Selection of oscillation stabilization time 10 12 15 17 Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows. Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS 2. The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset signal generation or interrupt generation. STOP mode is released Voltage waveform of X1 pin a 3. The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Remarks 1. ( ): fX = 10 MHz 2. Determine the oscillation stabilization time of the resonator by checking the characteristics of the resonator to be used. 76 User's Manual U16898EJ6V0UD CHAPTER 5 CLOCK GENERATORS 5.4 System Clock Oscillators The following three types of system clock oscillators are available. * High-speed internal oscillator: Internally oscillates a clock of 8 MHz (TYP.). * Crystal/ceramic oscillator: Oscillates a clock of 2 to 10 MHz. * External clock input circuit: Supplies a clock of 2 to 10 MHz to the X1 pin. 5.4.1 High-speed internal oscillator The 78K0S/KA1+ includes a high-speed internal oscillator (8 MHz (TYP.)). If the high-speed internal oscillation is selected by the option byte as the clock source, the X1 and X2 pins can be used as I/O port pins. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. 5.4.2 Crystal/ceramic oscillator The crystal/ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2 pins. If the crystal/ceramic oscillator is selected by the option byte as the system clock source, the X1 and X2 pins are used as crystal or ceramic resonator connection pins. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. Figure 5-6 shows the external circuit of the crystal/ceramic oscillator. Figure 5-6. External Circuit of Crystal/Ceramic Oscillator VSS X1 X2 Crystal resonator or ceramic resonator Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken lines in Figure 5-6 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. User's Manual U16898EJ6V0UD 77 CHAPTER 5 CLOCK GENERATORS Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines PORT VSS X1 X2 VSS (c) Wiring near high fluctuating current X1 X2 (d) Current flowing through ground line of oscillator (Potential at points A, B, and C fluctuates.) VDD PORT X1 X2 VSS X1 A B X2 High current VSS High current 78 User's Manual U16898EJ6V0UD C CHAPTER 5 CLOCK GENERATORS Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched VSS 5.4.3 X1 X2 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O port pin. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. 5.4.4 Prescaler The prescaler divides the clock (fX) output by the system clock oscillator to generate a clock (fXP) to be supplied to the peripheral hardware. It also divides the clock to peripheral hardware (fXP) to generate a clock to be supplied to the CPU. Remark The clock output by the oscillator selected by the option byte (high-speed internal oscillator, crystal/ceramic oscillator, or external clock input circuit) is divided. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. User's Manual U16898EJ6V0UD 79 CHAPTER 5 CLOCK GENERATORS 5.5 Operation of CPU Clock Generator A clock (fCPU) is supplied to the CPU from the system clock (fX) oscillated by one of the following three types of oscillators. * High-speed internal oscillator: Internally oscillates a clock of 8 MHz (TYP.). * Crystal/ceramic oscillator: Oscillates a clock of 2 to 10 MHz. * External clock input circuit: Supplies a clock of 2 to 10 MHz to X1 pin. The system clock oscillator is selected by the option byte. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. (1) High-speed internal oscillator When the high-speed internal oscillation is selected by the option byte, the following is possible. * Shortening of start time If the high-speed internal oscillator is selected as the oscillator, the CPU can be started without having to wait for the oscillation stabilization time of the system clock. Therefore, the start time can be shortened. * Improvement of expandability If the high-speed internal oscillator is selected as the oscillator, the X1 and X2 pins can be used as I/O port pins. For details, refer to CHAPTER 4 PORT FUNCTIONS. Figures 5-8 and 5-9 show the timing chart and status transition diagram of the default start by the high-speed internal oscillation. Remark When the high-speed internal oscillation is used, the clock accuracy is 5%. Figure 5-8. Timing Chart of Default Start by High-Speed Internal Oscillation (a) VDD RESET H Internal reset (b) System clock CPU clock High-speed internal oscillation clock PCC = 02H, PPCC = 02H Option byte is read. System clock is selected. (Operation stopsNote) Note Operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). 80 User's Manual U16898EJ6V0UD CHAPTER 5 CLOCK GENERATORS (a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the high-speed internal oscillation clock operates as the system clock. Figure 5-9. Status Transition of Default Start by High-Speed internal oscillation Power application VDD > 2.1 V (TYP.) Reset by power-on-clear Reset signal High-speed internal oscillator selected by option byte Start with PCC = 02H, PPCC = 02H Clock division ratio variable during CPU operation Interrupt Interrupt HALT instruction STOP instruction HALT Remark PCC: STOP Processor clock control register PPCC: Preprocessor clock control register (2) Crystal/ceramic oscillator If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 to 10 MHz can be selected and the accuracy of processing is improved because the frequency deviation is small, as compared with high-speed internal oscillation (8 MHz (TYP.)). Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic oscillator. User's Manual U16898EJ6V0UD 81 CHAPTER 5 CLOCK GENERATORS Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator (a) VDD RESET H Internal reset (b) System clock (c) Crystal/ceramic oscillator clock PCC = 02H, PPCC = 02H CPU clock Option byte is read. System clock is selected. (Operation stopsNote 1) Notes 1. 2. Clock oscillation stabilization timeNote 2 Operation stop time is 276 s (MIN.), 544 s (TYP.), and 1.074 ms (MAX.). The clock oscillation stabilization time for default start is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode is released is selected by the oscillation stabilization time select register (OSTS). (a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) After high-speed internal oscillation clock is generated, the option byte is referenced and the system clock is selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock. (c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. 82 User's Manual U16898EJ6V0UD CHAPTER 5 CLOCK GENERATORS Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation Power application VDD > 2.1 V (TYP.) Reset by power-on-clear Reset signal Crystal/ceramic oscillation selected by option byte Wait for clock oscillation stabilization Start with PCC = 02H, PPCC = 02H Clock division ratio variable during CPU operation Interrupt HALT instruction Interrupt STOP instruction HALT Remark PCC: STOP Processor clock control register PPCC: Preprocessor clock control register (3) External clock input circuit If external clock input is selected by the option byte, the following is possible. * High-speed operation The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.)) because an oscillation frequency of 2 to 10 MHz can be selected and an external clock with a small frequency deviation can be supplied. * Improvement of expandability If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For details, refer to CHAPTER 4 PORT FUNCTIONS. Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input. User's Manual U16898EJ6V0UD 83 CHAPTER 5 CLOCK GENERATORS Figure 5-12. Timing of Default Start by External Clock Input (a) VDD RESET H Internal reset (b) System clock External clock input PCC = 02H, PPCC = 02H CPU clock Option byte is read. System clock is selected. (Operation stopsNote) Note Operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). (a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the external clock operates as the system clock. Figure 5-13. Status Transition of Default Start by External Clock Input Power application VDD > 2.1 V (TYP.) Reset by power-on-clear Reset signal External clock input selected by option byte Start with PCC = 02H, PPCC = 02H Clock division ratio variable during CPU operation Interrupt HALT instruction Interrupt STOP instruction HALT Remark PCC: STOP Processor clock control register PPCC: Preprocessor clock control register 84 User's Manual U16898EJ6V0UD CHAPTER 5 CLOCK GENERATORS 5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. * Clock to peripheral hardware (fXP) * Low-speed internal oscillation clock (fRL) (1) Clock to peripheral hardware The clock to the peripheral hardware is supplied by dividing the system clock (fX). The division ratio is selected by the pre-processor clock control register (PPCC). Three types of frequencies are selectable: "fX", "fX/2", and "fX/22". Table 5-3 lists the clocks supplied to the peripheral hardware. Table 5-3. Clocks to Peripheral Hardware PPCC1 PPCC0 Selection of clock to peripheral hardware (fXP) 0 0 fX 0 1 fX/2 1 0 fX/2 1 1 Setting prohibited 2 (2) Low-speed internal oscillation clock The low-speed internal oscillator of the clock oscillator for interval time generation is always started after release of reset, and oscillates at 240 kHz (TYP.). It can be specified by the option byte whether the low-speed internal oscillator can or cannot be stopped by software. If it is specified that the low-speed internal oscillator can be stopped by software, oscillation can be started or stopped by using the low-speed internal oscillation mode register (LSRCM). If it is specified that it cannot be stopped by software, the clock source of WDT is fixed to the low-speed internal oscillation clock (fRL). The low-speed internal oscillator is independent of the CPU clock. If it is used as the source clock of WDT, therefore, a hang-up can be detected even if the CPU clock is stopped. If the low-speed internal oscillator is used as a count clock source of 8-bit timer H1, 8-bit timer H1 can operate even in the standby status. Table 5-4 shows the operation status of the low-speed internal oscillator when it is selected as the source clock of WDT and the count clock of 8-bit timer H1. Figure 5-14 shows the status transition of the low-speed internal oscillator. Table 5-4. Operation Status of Low-Speed Internal Oscillator Option Byte Setting Can be stopped by software LSRSTOP = 1 CPU Status Operation mode LSRSTOP = 0 LSRSTOP = 1 Standby LSRSTOP = 0 Cannot be stopped Operation mode WDT Status TMH1 Status Stopped Stopped Operates Operates Stopped Stopped Stopped Operates Operates Standby User's Manual U16898EJ6V0UD 85 CHAPTER 5 CLOCK GENERATORS Figure 5-14. Status Transition of Low-Speed Internal Oscillation Power application VDD > 2.1 V (TYP.) Reset by power-on-clear Reset signal Select by option byte if low-speed internal oscillator can be stopped or not Can be stopped Cannot be stopped Clock source of WDT is selected by softwareNote Clock source of WDT is fixed to fRL Low-speed internal oscillator can be stopped Low-speed internal oscillator cannot be stopped LSRSTOP = 1 LSRSTOP = 0 Low-speed internal oscillator stops Note The clock source of the watchdog timer (WDT) is selected from fX or fRL, or it may be stopped. For details, refer to CHAPTER 9 WATCHDOG TIMER. 86 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. * Number of counts: 2 to 65536 (2) External event counter 16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of valid level pulse width or more of a signal input externally. * Valid level pulse width: 2/fXP or more (3) Pulse width measurement 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. * Valid level pulse width: 2/fXP or more (4) Square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. * Cycle: (2 to 65536) x 2 x count clock cycle (5) PPG output 16-bit timer/event counter 00 can output a square wave that have arbitrary cycle and pulse width. * 1 < Pulse width < Cycle 65536 (6) One-shot pulse output 16-bit timer/event counter 00 can output a one-shot pulse for which output pulse width can be set to any desired value. User's Manual U16898EJ6V0UD 87 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-bit Timer/Event Counter 00 Item Configuration Timer counter 16-bit timer counter 00 (TM00) Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010) Timer input TI000, TI010 Timer output TO00, output controller Control registers 16-bit timer mode control register 00 (TMC00) Capture/compare control register 00 (CRC00) 16-bit timer output control register 00 (TOC00) Prescaler mode register 00 (PRM00) Port mode register 3 (PM3) Port register 3 (P3) Figures 6-1 shows a block diagram of these counters. Figure 6-1. Block Diagram of 16-bit Timer/Event Counter 00 Internal bus Capture/compare control register 00 (CRC00) TI010/TO00/ INTP2/P31 Selector Noise eliminator Selector CRC002CRC001 CRC000 16-bit timer capture/compare register 000 (CR000) INTTM000 Match Noise eliminator 16-bit timer counter 00 (TM00) Output controller TO00/TI010/ INTP2/P31 Match 2 Output latch (P31) Noise eliminator TI000/INTP0/P30 Clear PM31 16-bit timer capture/compare register 010 (CR010) Selector fX Selector fXP fXP/22 fXP/28 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus 88 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. Figure 6-2. Format of 16-bit Timer Counter 00 (TM00) Address: FF12H, FF13H Symbol After reset: 0000H R FF13H 7 6 5 4 FF12H 3 2 1 0 7 6 5 4 3 2 1 0 TM00 The count value is reset to 0000H in the following cases. <1> A reset signal is generated. <2> If TMC003 and TMC002 are cleared <3> If the valid edge of TI000 is input in the clear & start mode entered by inputting the valid edge of TI000 <4> If TM00 and CR000 match in the clear & start mode entered on a match between TM00 and CR000 <5> If OSPT00 is set to 1 in the one-shot pulse output mode Cautions 1. Even if TM00 is read, the value is not captured by CR010. 2. When TM00 is read, count misses do not occur, since the input of the count clock is temporarily stopped and then resumed after the read. (2) 16-bit timer capture/compare register 000 (CR000) CR000 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control register 00 (CRC00). CR000 is set by 16-bit memory manipulation instruction. A reset signal generation clears CR000 to 0000H. Figure 6-3. Format of 16-bit Timer Capture/Compare Register 000 (CR000) Address: FF14H, FF15H Symbol After reset: 0000H R/W FF15H 7 6 5 4 3 FF14H 2 1 0 7 6 5 4 3 2 1 0 CR000 * When CR000 is used as a compare register The value set in CR000 is constantly compared with the 16-bit timer/counter 00 (TM00) count value, and an interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the interval time then TM00 is set to interval timer operation. * When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 62). User's Manual U16898EJ6V0UD 89 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Rising edge 0 1 Rising edge Falling edge 0 0 No capture operation Both rising and falling edges 1 1 (2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1) CR000 Capture Trigger TI010 Pin Valid Edge ES110 ES100 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited. 2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00) ES110, ES100: Bits 7 and 6 of prescaler mode register 00 (PRM00) CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00) Cautions 1. Set CR000 to other than 0000H in the clear & start mode entered on match between TM00 and CR000. This means a 1-pulse count operation cannot be performed when this register is used as an external event counter. However, in the free-running mode and in the clear & start mode using the valid edge of TI000 pin, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H following overflow (FFFFH). 2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR000 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR000 is changed. 3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed. 4. The capture operation may not be performed for CR000 set in compare mode even if a capture trigger is input. 5. When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge. 6. If the register read period and the input of the capture trigger conflict when CR000 is used as a capture register, the capture trigger input takes precedence and the read data is undefined. Also, if the count stop of the timer and the input of the capture trigger conflict, the capture trigger is undefined. 7. Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. 90 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit capture/compare register 010 (CR010) CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00). CR010 is set by 16-bit memory manipulation instruction. Reset signal generation clears CR010 to 0000H. Figure 6-4. Format of 16-bit Timer Capture/Compare Register 010 (CR010) Address: FF16H, FF17H Symbol After reset: 0000H R/W FF17H 7 6 5 4 FF16H 3 2 1 0 7 6 5 4 3 2 1 0 CR010 * When CR010 is used as a compare register The value set in CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an interrupt request (INTTM010) is generated if they match. * When CR010 is used as a capture register It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by means of prescaler mode register 00 (PRM00) (refer to Table 6-3). Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1) CR010 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1. Setting ES010, ES000 = 1, 0 is prohibited. 2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00) CRC002: Bit 2 of capture/compare control register 00 (CRC00) Cautions 1. In the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010 changes from 0000H to 0001H following overflow (FFFFH). 2. If the new value of CR010 is less than the value of 16-bit timer counter 0 (TM00), TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR010 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR010 is changed. 3. The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed. 4. The capture operation may not be performed for CR010 set in compare mode even if a capture trigger is input. 5. If the register read period and the input of the capture trigger conflict when CR010 is used as a capture register, the capture trigger input takes precedence and the read data is undefined. Also, if the timer count stop and the input of the capture trigger conflict, the capture data is undefined. 6. Changing the CR010 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. User's Manual U16898EJ6V0UD 91 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers to Control 16-bit Timer/Event Counter 00 The following six types of registers are used to control 16-bit timer/event counter 00. * 16-bit timer mode control register 00 (TMC00) * Capture/compare control register 00 (CRC00) * 16-bit timer output control register 00 (TOC00) * Prescaler mode register 00 (PRM00) * Port mode register 3 (PM3) * Port register 3 (P3) (1) 16-bit timer mode control register 00 (TMC00) This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output timing, and detects an overflow. TMC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of TMC00 to 00H. Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the operation. 92 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H Symbol 7 6 5 4 TMC00 0 0 0 0 TMC003 TMC002 TMC001 R/W 3 2 1 <0> TMC003 TMC002 TMC001 OVF00 Operating mode and clear mode selection TO00 inversion timing selection Interrupt request generation No change Not generated 1 Operation stop (TM00 cleared to 0) 1 0 Free-running mode Match between TM00 and CR000 or match between TM00 and CR010 0 1 1 1 0 0 <When operating as compare register> Generated on match between TM00 and CR000, or match between TM00 and CR010 <When operating as capture register> Generated on TI000 pin and TI010 pin valid edge 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 Match between TM00 and CR000, match between TM00 and CR010 or TI000 pin valid edge - Clear & start occurs on valid edge of TI000 pin Clear & start occurs on match between TM00 and CR000 OVF00 Match between TM00 and CR000 or match between TM00 and CR010 Match between TM00 and CR000, match between TM00 and CR010 or TI000 pin valid edge Overflow detection of 16-bit timer counter 00 (TM00) 0 Overflow not detected 1 Overflow detected Cautions 1. The timer operation must be stopped before writing to bits other than the OVF00 flag. 2. If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to the TI000/TI010 pins. 3. Except when the valid edge of the TI000 pin is selected as the count clock, stop the timer operation before setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts. 4. Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 (PRM00) after stopping the timer operation. 5. If the clear & start mode entered on a match between TM00 and CR000, clear & start mode at the valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. 6. Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is disabled. 7. The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n0), however, occurs at the rise of the next count clock. Remark TM00: 16-bit timer counter 00 CR000: 16-bit timer capture/compare register 000 CR010: 16-bit timer capture/compare register 010 User's Manual U16898EJ6V0UD 93 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of CRC00 to 00H. Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00) Address: FF62H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CRC00 0 0 0 0 0 CRC002 CRC001 CRC000 CRC002 CR010 operating mode selection 0 Operate as compare register 1 Operate as capture register CRC001 CR000 capture trigger selection 0 Capture on valid edge of TI010 pin 1 Capture on valid edge of TI000 pin by reverse phase CRC000 Note CR000 operating mode selection 0 Operate as compare register 1 Operate as capture register Note When the CRC001 bit value is 1, capture is not performed if both the rising and falling edges have been selected as the valid edges of the TI000 pin. Cautions 1. The timer operation must be stopped before setting CRC00. 2. When the clear & start mode entered on a match between TM00 and CR000 is selected by 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. 3. To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00) (refer to Figure 6-17). 94 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot pulse output operation enable/disable, and output trigger of one-shot pulse by software. TOC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of TOC00 to 00H. Figure 6-7. Format of 16-bit Timer Output Control Register 00 (TOC00) Address: FF63H After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger control via software 0 No one-shot pulse output trigger 1 One-shot pulse output trigger OSPE00 One-shot pulse output operation control 0 Successive pulse output mode 1 One-shot pulse output mode TOC004 Note Timer output F/F control using match of CR010 and TM00 0 Disables inversion operation 1 Enables inversion operation LVS00 LVR00 Timer output F/F status setting 0 0 No change 0 1 Timer output F/F reset (0) 1 0 Timer output F/F set (1) 1 1 Setting prohibited TOC001 Timer output F/F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation TOE00 Timer output control 0 Disables output (output fixed to level 0) 1 Enables output Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur. Cautions 1. 2. 3. 4. 5. The timer operation must be stopped before setting other than OSPT00. If LVS00 and LVR00 are read, 0 is read. OSPT00 is automatically cleared after data is set, so 0 is read. Do not set OSPT00 to 1 other than in one-shot pulse output mode. A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively. 6. When TOE00 is 0, set TOE00, LVS00, and LVR00 at the same time with the 8-bit memory manipulation instruction. When TOE00 is 1, LVS00 and LVR00 can be set with the 1-bit memory manipulation instruction. User's Manual U16898EJ6V0UD 95 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid edges. PRM00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of PRM00 to 00H. Figure 6-8. Format of Prescaler Mode Register 00 (PRM00) Address: FF61H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PRM00 ES110 ES100 ES010 ES000 0 0 PRM001 PRM000 ES110 ES100 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES010 ES000 0 0 Falling edge 0 1 Rising edge TI010 pin valid edge selection TI000 pin valid edge selection 1 0 Setting prohibited 1 1 Both falling and rising edges PRM001 PRM000 0 0 fXP (10 MHz) 0 1 fXP/2 (2.5 MHz) 1 0 fXP/2 (39.06 kHz) 1 1 TI000 pin valid edge Count clock selection 2 8 Note Remarks 1. fXP: Oscillation frequency of clock supplied to peripheral hardware 2. ( ): fXP = 10 MHz Note The external clock requires a pulse longer than two cycles of the internal count clock (fXP). 96 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. Always set data to PRM00 after stopping the timer operation. 2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin. 3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. <1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. <2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled after a low level is input to the TI0n0 pin If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is enabled. <3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then enabled after a high level is input to the TI0n0 pin If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. 4. The sampling clock used to eliminate noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fXP, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse width. 5. When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge. Remark n = 0, 1 (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO00/TI010/INTP2 pin for timer output, set PM31 and the output latch of P31 to 0. When using the P30/TI000/INTP0 and P31/TO00/TI010/INTP2 pins as a timer input, set PM30 and PM31 to 1. At this time, the output latches of P30 and P31 can be either 0 or 1. PM3 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of PM3 to FFH. Figure 6-9. Format of Port Mode Register 3 (PM3) Address: FF23H After reset: FFH R/W Symbol 7 6 5 4 3 2 PM3 1 1 1 1 1 1 PM3n 1 0 PM31 PM30 P3n pin I/O mode selection (n = 0 or 1) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U16898EJ6V0UD 97 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an interval timer. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-10 for the set value). <2> Set any value to the CR000 register. <3> Set the count clock by using the PRM00 register. <4> Set the TMC00 register to start the operation (see Figure 6-10 for the set value). Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Remark For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. Interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 000 (CR000) beforehand as the interval. When the count value of 16-bit timer counter 00 (TM00) matches the value set to CR000, counting continues with the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated. The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). 98 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Control Register Settings for Interval Timer Operation (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0/1 0 Clears and starts on match between TM00 and CR000. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the description of the respective control registers for details. Figure 6-11. Interval Timer Configuration Diagram 16-bit timer capture/compare register 000 (CR000) INTTM000 Selector fXP fXP/22 fXP/28 TI000/INTP0/P30 16-bit timer counter 00 (TM00) Note OVF00 Noise eliminator Clear circuit fXP Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 is set to FFFFH. User's Manual U16898EJ6V0UD 99 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-12. Timing of Interval Timer Operation t Count clock TM00 count value 0000H 0001H N Timer operation enabled CR000 0000H 0001H N Clear N 0000H 0001H N Clear N N N INTTM000 Interrupt request generated Remark Interrupt request generated Interval time = (N + 1) x t N = 0001H to FFFFH (settable range) When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N) before the change, it is necessary to restart the timer after changing CR000. Figure 6-13. Timing After Change of Compare Register During Timer Count Operation (N M: N > M) Count clock N CR000 TM00 count value Remark 6.4.2 X-1 M X FFFFH 0000H 0001H 0002H N>X>M External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-14 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set any value to the CR000 register (0000H cannot be set). <4> Set the TMC00 register to start the operation (see Figure 6-14 for the set value). Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. 100 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated. Input a value other than 0000H to CR000. (A count operation with a pulse cannot be carried out.) The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00). Because an operation is carried out only when the valid edge of the TI000 pin is detected twice after sampling with the internal clock (fXP), noise with a short pulse width can be removed. Figure 6-14. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 1 1 Selects external clock. Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0/1 0 Clears and starts on match between TM00 and CR000. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See the description of the respective control registers for details. User's Manual U16898EJ6V0UD 101 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-15. External Event Counter Configuration Diagram Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear fXP OVF00Note 16-bit timer counter 00 (TM00) Noise eliminator Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH. Figure 6-16. External Event Counter Operation Timing (with Rising Edge Specified) (1) INTTM000 generation timing immediately after operation starts Counting is started after a valid edge is detected twice. Timer operation starts Count starts TI000 pin input 1 TM00 count value 2 3 0000H 0001H 0002H 0003H N-2 N-1 N 0000H 0001H 0002H N CR000 INTTM000 (2) INTTM000 generation timing after INTTM000 has been generated twice TI000 pin input TM00 count value CR000 N 0000H 0001H 0002H 0003H 0004H N-1 N 0000H 0001H 0002H 0003H N INTTM000 Caution When reading the external event counter count value, TM00 should be read. 102 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin. When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate the necessary pulse width. Clear the overflow flag after checking it. The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-17. CR010 Capture Operation with Rising Edge Specified Count clock TM00 N-3 N-2 N-1 N N+1 TI000 Rising edge detection N CR010 INTTM010 Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figures 6-18, 6-21, 6-23, and 6-25 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set the TMC00 register to start the operation (see Figures 6-18, 6-21, 6-23, and 6-25 for the set value). Caution To use two capture registers, set the TI000 and TI010 pins. Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. User's Manual U16898EJ6V0UD 103 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Pulse width measurement with free-running counter and one capture register Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and ES010) of PRM00. When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the valid edge specified by PRM00 is input, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set. Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter. Figure 6-18. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI000 and CR010 Are Used) (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 0/1 0 CR000 used as compare register CR010 used as capture register (b) Prescaler mode register 00 (PRM00) ES101 ES100 ES010 ES000 PRM00 0/1 0/1 1 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. 104 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-19. Configuration Diagram for Pulse Width Measurement by Free-Running Counter fXP/22 fXP/26 Selector fXP 16-bit timer/counter 00 (TM00) 16-bit timer capture/compare register 010 (CR010) TI000/INTP0/P30 INTTM010 Internal bus Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock TM00 count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 TI000 pin input CR010 capture value D0 D1 D2 D3 INTTM010 (D1 - D0) x t (D2 - D1) x t Note (D3 - D2) x t Note The carry flag is set to 1. Ignore this setting. (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. Specify both the rising and falling edges as the valid edges of the TI000 and TI010 pins, by using bits 4 and 5 (ES000 and ES010) and bits 6 and 7 (ES100 and ES110) of PRM00. When the valid edge specified by bits 4 and 5 (ES000 and ES010) of PRM00 is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the valid edge specified by bits 6 and 7 (ES100 and ES110) of PRM00 is input to the TI010 pin, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal (INTTM000) is set. Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width. User's Manual U16898EJ6V0UD 105 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter. Figure 6-21. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 0 1 CR000 used as capture register Captures valid edge of TI010 pin to CR000. CR010 used as capture register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 1 1 1 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Specifies both edges for pulse width detection. (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. 106 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-22. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM00 count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3 TI000 pin input CR010 capture value D0 D1 D2 INTTM010 TI010 pin input CR000 capture value D1 D2 + 1 INTTM000 (D1 - D0) x t (D2 - D1) x t Note (D3 - D2) x t ((D2 + 1) - D1) x t Note Note The carry flag is set to 1. Ignore this setting. (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI000 pin. Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and ES010) of PRM00. When the valid edge specified by bits 4 and 5 (ES000 and ES010) of PRM00 is input to the TI010 pin, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000). Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter. User's Manual U16898EJ6V0UD 107 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000Note. CR010 used as capture register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode Note If the valid edge of TI000 pin is specified to be both the rising and falling edges, 16-bit timer capture/compare register 000 (CR000) cannot perform the capture operation. When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at that timing. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. 108 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H D0 D1 D0 + 1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 TI000 pin input CR010 capture value D0 D2 CR000 capture value D1 D3 INTTM010 (D1 - D0) x t (D2 - D1) x t Note (D3 - D2) x t Note The carry flag is set to 1. Ignore this setting. (4) Pulse width measurement by means of restart Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and ES010) of PRM00. When a valid edge of the TI000 pin is detected, the count value of 16-bit timer/counter 00 (TM00) is taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count. Sampling is performed at the interval selected by prescaler mode register 00 (PRM00) and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter. Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (1/2) (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000Note. CR010 used as capture register Note If the valid edge of TI000 pin is specified to be both the rising and falling edges, 16-bit timer capture/ compare register 000 (CR000) cannot perform the capture operation. User's Manual U16898EJ6V0UD 109 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (2/2) (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 0 0/1 0 Clears and starts at valid edge of TI000 pin. Figure 6-26. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H TI000 pin input CR010 capture value D0 D2 D1 CR000 capture value INTTM010 (D1 + 1) x t (D2 + 1) x t 110 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-27 for the set value). <3> Set the TOC00 register (see Figure 6-27 for the set value). <4> Set any value to the CR000 register (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figure 6-27 for the set value). Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 000 (CR000). The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 + 1 by setting bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave with any selected frequency to be output. Figure 6-27. Control Register Settings in Square-Wave Output Mode (1/2) (a) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register User's Manual U16898EJ6V0UD 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 0 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited). Does not invert output on match between TM00 and CR010. Disables one-shot pulse output. (d) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0 0 Clears and starts on match between TM00 and CR000. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the description of the respective control registers for details. Figure 6-28. Square-Wave Output Operation Timing Count clock TM00 count value CR000 0000H 0001H 0002H N-1 N 0000H 0001H 0002H N INTTM000 TO00 pin output 112 User's Manual U16898EJ6V0UD N-1 N 0000H CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-29 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-29 for the set value). <2> Set any value to the CR000 register as the cycle. <3> Set any value to the CR010 register as the duty factor. <4> Set the TOC00 register (see Figure 6-29 for the set value). <5> Set the count clock by using the PRM00 register. <6> Set the TMC00 register to start the operation (see Figure 6-29 for the set value). Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. 3. n = 0 or 1 In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer capture/compare register 000 (CR000), respectively. User's Manual U16898EJ6V0UD 113 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Control Register Settings for PPG Output Operation (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 x 0 0 CR000 used as compare register CR010 used as compare register (b) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 1 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited). Inverts output on match between TM00 and CR010. Disables one-shot pulse output. (c) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) (d) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0 0 Clears and starts on match between TM00 and CR000. Cautions 1. Values in the following range should be set in CR000 and CR010. 0000H < CR010 < CR000 FFFFH 2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). Remark 114 x: Don't care User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Configuration Diagram of PPG Output 16-bit timer capture/compare register 000 (CR000) Selector fXP fXP/22 fXP/28 Noise eliminator Output controller TI000/INTP0/P30 Clear circuit 16-bit timer counter 00 (TM00) fXP TO00/TI010/ INTP2/P31 16-bit timer capture/compare register 010 (CR010) Figure 6-31. PPG Output Operation Timing t Count clock TM00 count value N 0000H 0001H M-1 M Clear N-1 N 0000H 0001H Clear CR000 capture value N CR010 capture value M TO00 Pulse width: (M + 1) x t 1 cycle: (N + 1) x t Remark 0000H < M < N FFFFH User's Manual U16898EJ6V0UD 115 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figures 6-32 and 6-34 for the set value). <3> Set the TOC00 register (see Figures 6-32 and 6-34 for the set value). <4> Set any value to the CR000 and CR010 registers (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figures 6-32 and 6-34 for the set value). Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-32, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software. By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000 (CR000)Note. Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00 register, the TMC003 and TMC002 bits of the TMC00 register must be cleared to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR000 register and inactive with the CR010 register. Do not set N to M. Cautions 1. Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. 2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. 116 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) Prescaler mode register 00 (PRM00) PRM00 ES110 ES100 ES010 ES000 3 2 0/1 0/1 0/1 0/1 0 0 PRM001 PRM010 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0 0/1 0 CR000 as compare register CR010 as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 0 1 1 LVS00 LVR00 TOC001 TOE00 0/1 0/1 1 1 Enables TO00 output. Inverts output upon match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output upon match between TM00 and CR010. Sets one-shot pulse output mode. Set to 1 for output. (d) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 0 1 0 OVF00 0 Free-running mode Caution Do not set the CR000 and CR010 registers to 0000H. User's Manual U16898EJ6V0UD 117 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock TM00 count 0000H 0001H N N+1 0000H N-1 N M-1 M M+1 M+2 CR010 set value N N N N CR000 set value M M M M OSPT00 INTTM010 INTTM000 TO00 pin output Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC003 and TMC002 bits. Remark N<M (2) One-shot pulse output with external trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-34, and by using the valid edge of the TI000 pin as an external trigger. The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES010) of prescaler mode register 00 (PRM00). The rising, falling, or both the rising and falling edges can be specified. When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 000 (CR000)Note. Note The case where N < M is described here. When N > M, the output becomes active with the CR000 register and inactive with the CR010 register. Do not set N to M. Caution Do not input the external trigger again while the one-shot pulse is output. To output the oneshot pulse again, wait until the current one-shot pulse output is completed. 118 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) Prescaler mode register 00 (PRM00) PRM00 ES110 ES100 ES010 ES000 3 2 0/1 0/1 0 1 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies the rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 0 CRC000 0/1 0 CR000 used as compare register CR010 used as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 0 1 1 LVS00 LVR00 TOC001 TOE00 0/1 0/1 1 1 Enables TO00 output. Inverts output upon match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output upon match between TM00 and CR010. Sets one-shot pulse output mode. (d) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 0 1 0 Clears and starts at valid edge of TI000 pin. Caution Do not set the CR000 and CR010 registers to 0000H. User's Manual U16898EJ6V0UD 119 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-35. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) t Count clock TM00 count value 0000H 0001H 0000H N N+1 N+2 M-2 M-1 M M+1 M+2 CR010 set value N N N N CR000 set value M M M M TI000 pin input INTTM010 INTTM000 TO00 pin output Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC002 and TMC003 bits. Remark 120 N<M User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock. Figure 6-36. Start Timing of 16-bit Timer Counter 00 (TM00) Count clock TM00 count value 0000H 0001H 0002H 0003H 0004H Timer start (2) 16-bit timer counter 00 (TM00) operation <1> 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the operation. <2> Even if TM00 is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <3> When TM00 is read, count misses do not occur, since the input of the count clock is temporarily stopped and then resumed after the read. <4> If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to the TI000/TI010 pins. (3) Setting of 16-bit timer capture/compare registers 000, 010 (CR000, CR010) <1> Set 16-bit timer capture/compare register 000 (CR000) to other than 0000H in the clear & start mode entered on match between TM00 and CR000. This means a 1-pulse count operation cannot be performed when this register is used as an external event counter. <2> When the clear & start mode entered on a match between TM00 and CR000 is selected, CR000 should not be specified as a capture register. <3> In the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR0n0 is set to 0000H, an interrupt request (INTTM0n0) is generated when CR0n0 changes from 0000H to 0001H following overflow (FFFFH). <4> If the new value of CR0n0 is less than the value of TM00, TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR0n0 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR0n0 is changed. User's Manual U16898EJ6V0UD 121 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Capture register data retention The value of 16-bit timer capture/compare register 0n0 (CR0n0) after 16-bit timer/event counter 00 has stopped is not guaranteed. Remark n = 0, 1 (5) Setting of 16-bit timer mode control register 00 (TMC00) The timer operation must be stopped before writing to bits other than the OVF00 flag. (6) Setting of capture/compare control register 00 (CRC00) The timer operation must be stopped before setting CRC00. (7) Setting of 16-bit timer output control register 00 (TOC00) <1> Timer operation must be stopped before setting other than OSPT00. <2> If LVS00 and LVR00 are read, 0 is read. <3> OSPT00 is automatically cleared after data is set, so 0 is read. <4> Do not set OSPT00 to 1 other than in one-shot pulse output mode. <5> A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively. (8) Setting of prescaler mode register 00 (PRM00) Always set data to PRM00 after stopping the timer operation. (9) Valid edge setting Set the valid edge of the TI000 pin with bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) after stopping the timer operation. (10) One-shot pulse output One-shot pulse output normally operates only in the free-running mode or in the clear & start mode at the valid edge of the TI000 pin. Because an overflow does not occur in the clear & start mode on a match between TM00 and CR000, one-shot pulse output is not possible. (11) One-shot pulse output by software <1> Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. <2> When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. <3> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H. 122 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (12) One-shot pulse output with external trigger <1> Do not input the external trigger again while the one-shot pulse is output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. <2> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H. (13) Operation of OVF00 flag <1> The OVF00 flag is also set to 1 in the following case. Either of the clear & start mode entered on a match between TM00 and CR000, clear & start at the valid edge of the TI000 pin, or free-running mode is selected. CR000 is set to FFFFH. When TM00 is counted up from FFFFH to 0000H. Figure 6-37. Operation Timing of OVF00 Flag Count clock CR000 TM00 FFFFH FFFEH FFFFH 0000H 0001H OVF00 INTTM000 <2> Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is disabled. User's Manual U16898EJ6V0UD 123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (14) Conflicting operations If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture register, the capture trigger input takes precedence and the read data is undefined. Also, if the count stop of the timer and the input of the capture trigger conflict, the captured data is undefined. Figure 6-38. Capture Register Data Retention Timing Count clock TM00 count value N N+1 N+2 M M+1 M+2 Edge input INTTM010 Capture read signal CR010 capture value X N+2 Capture M+1 Capture, but read value is not guaranteed (15) Capture operation <1> If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin. <2> When the CRC001 bit value is 1, capture is not performed in the CR000 register if both the rising and falling edges have been selected as the valid edges of the TI000 pin. <3> When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at that timing. <4> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00). <5> The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n0), however, occurs at the rise of the next count clock. <6> To use two capture registers, set the TI000 and TI010 pins. (16) Compare operation The capture operation may not be performed for CR0n0 set in compare mode even if a capture trigger is input. Remark 124 n = 0, 1 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (17) Changing compare register during timer operation <1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare register, when changing CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the timing of the match, so the operation is not guaranteed in such cases. To change CR0n0 during timer counting, INTTM000 interrupt servicing performs the following operation. <Changing cycle (CR000)> 1. Disable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 0). 2. Disable the INTTM000 interrupt (TMMK000 = 1). 3. Rewrite CR000. 4. Wait for 1 cycle of the TM00 count clock. 5. Enable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 1). 6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0). 7. Enable the INTTM000 interrupt (TMMK000 = 0). <Changing duty (CR010)> 1. Disable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 0). 2. Disable the INTTM000 interrupt (TMMK000 = 1). 3. Rewrite CR010. 4. Wait for 1 cycle of the TM00 count clock. 5. Enable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 1). 6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0). 7. Enable the INTTM000 interrupt (TMMK000 = 0). While interrupts and timer output inversion are disabled (1 to 4 above), timer counting is continued. If the value to be set in CR0n0 is small, the value of TM00 may exceed CR0n0. Therefore, set the value, considering the time lapse of the timer clock and CPU clock after an INTTM000 interrupt has been generated. Remark n = 0, 1 <2> If CR010 is changed during timer counting without performing processing <1> above, the value in CR010 may be rewritten twice or more, causing an inversion of the output level of the TO00 pin at each rewrite. User's Manual U16898EJ6V0UD 125 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (18) Edge detection <1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. (a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. (b) If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled after a low level is input to the TI0n0 pin If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is enabled. (c) When the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then enabled after a high level is input to the TI0n0 pin If the rising edge or both rising and falling edges are specified as the valid edge, of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. Remark n = 0, 1 <2> The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fXP, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise with a short pulse width. (19) External event counter <1> The timing of the count start is after two valid edge detections. <2> When reading the external event counter count value, TM00 should be read. (20) PPG output <1> Values in the following range should be set in CR000 and CR010: 0000H < CR010 < CR000 FFFFH <2> The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). (21) STOP mode or system clock stop mode setting Except when the valid edge of the TI000 pin is selected as the count clock, stop the timer operation before setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts. (22) P31/TI010/TO00 pin When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge. 126 User's Manual U16898EJ6V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (23) External clock limitation <1> When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the AC characteristics. For the AC characteristics, refer to CHAPTER 21 and CHAPTER 22 ELECTRICAL SPECIFICATIONS. <2> When an external waveform is input to 16-bit timer/event counter 00, it is sampled by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device. Count clock (fsam) TI000 Sampling time on filter Input pulse through noise limiter circuit Remark The count clock (fsam) can be selected using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). User's Manual U16898EJ6V0UD 127 CHAPTER 7 8-BIT TIMER 80 7.1 Function of 8-bit Timer 80 8-bit timer 80 has an 8-bit interval timer function and generates an interrupt at intervals specified in advance. Table 7-1. Interval Time of 8-bit Timer 80 Minimum Interval Time fXP = 8.0 MHz 2 /fXP (8 s) 6 18 2 /fXP (128 s) 24 2 /fXP (8.19 ms) 14 2 /fXP (6.4 s) 16 2 /fXP (25.6 s) 18 2 /fXP (102 s) 24 2 /fXP (6.55 ms) 10 2 /fXP (32.7 ms) 2 /fXP (8.19 ms) 16 2 /fXP (2.01 s) 2 /fXP (6.4 s) 2 /fXP (1.64 ms) 2 /fXP (25.6 s) 2 /fXP (6.55 ms) 2 /fXP (102 s) 10 2 /fXP (26.2 ms) 16 2 /fXP (1.68 s) 2 /fXP (6.55 ms) 128 2 /fXP (32 s) 2 /fXP (128 s) 8 Remark 2 /fXP (8 s) 2 /fXP (8.19 ms) 6 Resolution 16 2 /fXP (2.05 ms) 2 /fXP (32 s) 8 fXP = 10.0 MHz Maximum Interval Time 14 fXP: Oscillation frequency of clock to peripheral hardware User's Manual U16898EJ6V0UD 6 8 10 16 6 8 10 16 CHAPTER 7 8-BIT TIMER 80 7.2 Configuration of 8-bit Timer 80 8-bit timer 80 consists of the following hardware. Table 7-2. Configuration of 8-bit Timer 80 Item Configuration Timer counter 8-bit timer counter 80 (TM80) Register 8-bit compare register 80 (CR80) Control register 8-bit timer mode control register 80 (TMC80) Figure 7-1. Block Diagram of 8-bit Timer 80 Internal bus 8-bit compare register 80 (CR80) Match INTTM80 fXP/28 fXP/210 Selector fXP/26 8-bit timer/counter 80 (TM80) Clear fXP/216 TCE80 TCL801 TCL800 8-bit timer mode control register 80 (TMC80) Internal bus Remark fXP: Oscillation frequency of clock to peripheral hardware User's Manual U16898EJ6V0UD 129 CHAPTER 7 8-BIT TIMER 80 (1) 8-bit compare register 80 (CR80) This 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (TM80). It generates an interrupt request signal (INTTM80) if the two values match. CR80 is set by using an 8-bit memory manipulation instruction. A value of 00H to FFH can be set to this register. Reset signal generation makes the contents of this register undefined. Figure 7-2. Format of 8-bit Compare Register 80 (CR80) Address: FFCDH Symbol After reset: Undefined 7 6 5 W 4 3 2 1 0 CR80 Caution When changing the value of CR80, be sure to stop the timer operation. If the value of CR80 is changed with the timer operation enabled, a match interrupt request signal is generated immediately and the timer may be cleared. (2) 8-bit timer counter 80 (TM80) This 8-bit register counts the count pulses. The value of TM80 can be read by using an 8-bit memory manipulation instruction. Reset signal generation clears TM80 to 00H. Figure 7-3. Format of 8-bit Timer Counter 80 (TM80) Address: FFCEH Symbol 7 After reset: 00H 6 5 R 4 3 TM80 130 User's Manual U16898EJ6V0UD 2 1 0 CHAPTER 7 8-BIT TIMER 80 7.3 Register Controlling 8-bit Timer 80 8-bit timer 80 is controlled by 8-bit timer mode control register 80 (TMC80). (1) 8-bit timer mode control register 80 (TMC80) This register is used to enable or stop the operation of 8-bit timer counter 80 (TM80), and to set the count clock of TM80. This register is set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TMC80 to 00H. Figure 7-4. Format of 8-bit Timer Mode Control Register 80 (TMC80) Address: FFCCH After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 TMC80 TCE80 0 0 0 0 TCL801 TCL800 0 TCE80 Control of operation of TM80 0 Stop operation (clear TM80 to 00H). 1 Enable operation. TCL801 TCL800 Selection of count clock of 8-bit timer 80 fXP = 8.0 MHz 0 0 1 1 0 1 0 1 fXP = 10.0 MHz fXP/2 6 125 kHz 156.3 kHz fXP/2 8 31.25 kHz 39.06 kHz fXP/2 10 7.81 kHz 9.77 kHz fXP/2 16 0.12 kHz 0.15 kHz Cautions 1. Be sure to set TMC80 after stopping the timer operation. 2. Be sure to clear bits 0 and 6 to 0. Remark fXP: Oscillation frequency of clock to peripheral hardware User's Manual U16898EJ6V0UD 131 CHAPTER 7 8-BIT TIMER 80 7.4 7.4.1 Operation of 8-bit Timer 80 Operation as interval timer When 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by the count value set in advance to 8-bit compare register 80 (CR80). To use 8-bit timer 80 as an interval timer, make the following setting. <1> Disable the operation of 8-bit timer counter 80 (clear TCE80 (bit 7 of 8-bit timer mode control register 80 (TMC80)) to 0). <2> Set the count clock of 8-bit timer 80 (refer to Tables 7-3 and 7-4). <3> Set the count value to CR80. <4> Enable the operation of TM80 (set TCE80 to 1). When the count value of 8-bit timer counter 80 (TM80) matches the set value of CR80, the value of TM80 is cleared to 00H and counting is continued. At the same time, an interrupt request signal (INTTM80) is generated. Tables 7-3 and 7-4 show the interval time, and Figure 7-5 shows the timing of the interval timer operation. Cautions 1. When changing the value of CR80, be sure to stop the timer operation. If the value of CR80 is changed with the timer operation enabled, a match interrupt request signal may be generated immediately. 2. If the count clock of TMC80 is set and the operation of TM80 is enabled at the same time by using an 8-bit memory manipulation instruction, the error of one cycle after the timer is started may be 1 clock or more (refer to 7.5 (1) Error when timer starts). Therefore, be sure to follow the above sequence when using TM80 as an interval timer. Table 7-3. Interval Time of 8-bit Timer 80 (fXP = 8.0 MHz) TCL801 TCL800 Minimum Interval Time Maximum Interval Time 0 2 /fXP (8 s) 0 1 2 /fXP (32 s) 2 /fXP (8.19 ms) 1 0 2 /fXP (128 s) 10 2 /fXP (32.7 ms) 1 1 2 /fXP (8.19 ms) 16 2 /fXP (2.01 s) 0 Remark 6 2 /fXP (8 s) 16 2 /fXP (32 s) 18 2 /fXP (128 s) 24 2 /fXP (8.19 ms) 2 /fXP (2.05 ms) 8 Resolution 14 6 8 10 16 fXP: Oscillation frequency of clock to peripheral hardware Table 7-4. Interval Time of 8-bit Timer 80 (fXP = 10.0 MHz) TCL801 Minimum Interval Time Maximum Interval Time 0 2 /fXP (6.4 s) 0 1 2 /fXP (25.6 s) 2 /fXP (6.55 ms) 1 0 2 /fXP (102 s) 10 2 /fXP (26.2 ms) 1 1 2 /fXP (6.55 ms) 16 2 /fXP (1.68 s) 0 Remark 132 TCL800 6 8 Resolution 14 2 /fXP (6.4 s) 16 2 /fXP (25.6 s) 18 2 /fXP (102 s) 24 2 /fXP (6.55 ms) 2 /fXP (1.64 ms) fXP: Oscillation frequency of clock to peripheral hardware User's Manual U16898EJ6V0UD 6 8 10 16 CHAPTER 7 8-BIT TIMER 80 Figure 7-5. Timing of Interval Timer Operation t Count clock TM80 count value 00H 01H N 00H 01H N Clear N CR80 00H 01H N Clear N N N TCE80 Count start INTTM80 Interrupt request generated Interval time Remark Interrupt request generated Interval time Interval time = (N + 1) x t N = 00H to FFH User's Manual U16898EJ6V0UD 133 CHAPTER 7 8-BIT TIMER 80 7.5 Notes on 8-bit Timer 80 (1) Error when timer starts The time from starting the timer to generation of the match signal includes an error of up to 1.5 clocks. This is because, if the timer is started while the count clock is high, the rising edge may be immediately detected and the counter may be incremented (refer to Figure 7-6). Figure 7-6. Case Where Error of 1.5 Clocks (Max.) Occurs Delay A Count pulse Selected clock 8-bit timer counter 80 (TM80) Clear signal TCE80 Delay B Selected clock TCE80 Clear signal Count pulse TM80 count value 00H 01H 02H 03H ... Delay A Delay B If the timer is started when the selected clock is high and if delay A > delay B, an error of up to 1.5 clocks occurs. (2) Setting of 8-bit compare register 80 8-bit compare register 80 (CR80) can be set to 00H. (3) Note on setting STOP mode Before executing the STOP instruction, be sure to stop the timer operation (TCE80 = 0). 134 User's Manual U16898EJ6V0UD CHAPTER 8 8-BIT TIMER H1 8.1 Functions of 8-bit Timer H1 8-bit timer H1 has the following functions. * Interval timer * PWM output mode * Square-wave output 8.2 Configuration of 8-bit Timer H1 8-bit timer H1 consists of the following hardware. Table 8-1. Configuration of 8-bit Timer H1 Item Configuration Timer register 8-bit timer counter H1 Registers 8-bit timer H compare register 01 (CMP01) 8-bit timer H compare register 11 (CMP11) Timer output TOH1 Control registers 8-bit timer H mode register 1 (TMHMD1) Port mode register 4 (PM4) Port register 4 (P4) Figure 8-1 shows a block diagram. User's Manual U16898EJ6V0UD 135 136 Figure 8-1. Block Diagram of 8-bit Timer H1 Internal bus 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 8-bit timer H compare register 11 (CMP11) 8-bit timer H compare register 01 (CMP01) 2 Decoder TOH1/P42 Selector Selector fXP fXP/22 fXP/24 fXP/26 fXP/212 fRL/27 Interrupt generator F/F R Output controller Level inversion Output latch (P42) 8-bit timer counter H1 Clear PWM mode signal Timer H enable signal 1 0 INTTMH1 PM42 CHAPTER 8 8-BIT TIMER H1 User's Manual U16898EJ6V0UD Match CHAPTER 8 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-2. Format of 8-bit Timer H Compare Register 01 (CMP01) Address: FF0EH Symbol 7 After reset: 00H 6 R/W 5 4 3 2 1 0 CMP01 Caution CMP01 cannot be rewritten during timer count operation. (2) 8-bit timer H compare register 11 (CMP11) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-3. Format of 8-bit Timer H Compare Register 11 (CMP11) Address: FF0FH Symbol 7 After reset: 00H 6 R/W 5 4 3 2 1 0 CMP11 CMP11 can be rewritten during timer count operation. If the CMP11 value is rewritten during timer operation, the compare value after the rewrite takes effect at the timing at which the count value and the compare value before the rewrite match. If the timing at which the count value and compare value match conflicts with the timing of the writing from the CPU to CMP11, the compare value after the rewrite takes effect at the timing at which the next count value and the compare value before the rewrite match. Caution In the PWM output mode, be sure to set CMP11 when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). User's Manual U16898EJ6V0UD 137 CHAPTER 8 8-BIT TIMER H1 8.3 Registers Controlling 8-bit Timer H1 The following three registers are used to control 8-bit timer H1. * 8-bit timer H mode register 1 (TMHMD1) * Port mode register 4 (PM4) * Port register 4 (P4) (1) 8-bit timer H mode register 1 (TMHMD1) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. 138 User's Manual U16898EJ6V0UD CHAPTER 8 8-BIT TIMER H1 Figure 8-4. Format of 8-bit Timer H Mode Register 1 (TMHMD1) Address: FF70H Symbol TMHMD1 After reset: 00H R/W <7> 6 5 4 TMHE1 CKS12 CKS11 CKS10 TMHE1 3 2 <0> <1> TMMD11 TMMD10 TOLEV1 TOEN1 Timer operation enable 0 Stop timer count operation (counter is cleared to 0) 1 Enable timer count operation (count operation started by inputting clock) CKS12 CKS11 CKS10 0 0 0 0 0 1 0 1 0 0 1 1 fXP/26 1 0 0 1 0 1 Other than above Count clock (fCNT) selection (10 MHz) fXP fXP/2 2 (2.5 MHz) fXP/2 4 (625 kHz) (2.44 kHz) 7 (1.88 kHz (TYP.)) fXP/2 fRL/2 Setting prohibited TMMD11 TMMD10 Timer operation mode 0 0 Interval timer mode 1 0 PWM output mode Other than above TOLEV1 (156.25 kHz) 12 Setting prohibited Timer output level control (in default mode) 0 Low level 1 High level TOEN1 Timer output control 0 Disable output 1 Enable output Cautions 1. When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. 2. In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware 2. fRL: Low-speed internal oscillation clock oscillation frequency 3. Figures in parentheses apply to operation at fXP = 10 MHz, fRL = 240 kHz (TYP.). User's Manual U16898EJ6V0UD 139 CHAPTER 8 8-BIT TIMER H1 (2) Port mode register 4 (PM4) This register sets port 4 input/output in 1-bit units. When using the P42/TOH1 pin for timer output, clear PM42 and the output latch of P42 to 0. PM4 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 8-5. Format of Port Mode Register 4 (PM4) Address: FF24H R/W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40 PM4n 140 After reset: FFH P4n pin I/O mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U16898EJ6V0UD CHAPTER 8 8-BIT TIMER H1 8.4 Operation of 8-bit Timer H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and 8-bit timer counter H1 is cleared to 00H. Compare register 11 (CMP11) is not used in interval timer mode. Since a match of 8-bit timer counter H1 and the CMP11 register is not detected even if the CMP11 register is set, timer output is not affected. By setting bit 0 (TOEN1) of timer H mode register 1 (TMHMD1) to 1, a square wave of any frequency (duty = 50%) is output from TOH1. (1) Usage Generates the INTTMH1 signal repeatedly at the same interval. <1> Set each register. Figure 8-6. Register Setting During Interval Timer/Square-Wave Output Operation (i) TMHMD1 Setting timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 0 0/1 0/1 0/1 TMMD11 TMMD10 TOLEV1 0 0 0/1 TOEN1 0/1 Timer output setting Timer output level inversion setting Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP01 register setting * Compare value (N) <2> Count operation starts when TMHE1 = 1. <3> When the values of 8-bit timer counter H1 and the CMP01 register match, the INTTMH1 signal is generated and 8-bit timer counter H1 is cleared to 00H. Interval time = (N +1)/fCNT <4> Subsequently, the INTTMH1 signal is generated at the same interval. To stop the count operation, clear TMHE1 to 0. User's Manual U16898EJ6V0UD 141 CHAPTER 8 8-BIT TIMER H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (01H CMP01 FEH) Count clock Count start 8-bit timer counter H1 00H 01H N 00H 01H N Clear 00H 01H 00H Clear N CMP01 TMHE1 INTTMH1 Interval time TOH1 <2> Level inversion, match interrupt occurrence, 8-bit timer counter H1 clear <1> <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter H1 clear <1> The count operation is enabled by setting the TMHE1 bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1 is cleared, the TOH1 output level is inverted, and the INTTMH1 signal is output. <3> The INTTMH1 signal and TOH1 output become inactive by clearing the TMHE1 bit to 0 during timer H1 operation. If these are inactive from the first, the level is retained. Remark 142 01H N FEH User's Manual U16898EJ6V0UD CHAPTER 8 8-BIT TIMER H1 Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter H1 00H 01H FEH FFH 00H FEH Clear FFH 00H Clear FFH CMP01 TMHE1 INTTMH1 TOH1 Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter H1 00H CMP01 00H TMHE1 INTTMH1 TOH1 Interval time User's Manual U16898EJ6V0UD 143 CHAPTER 8 8-BIT TIMER H1 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited. 8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register during timer operation is possible. The operation in PWM output mode is as follows. TOH1 output becomes active and 8-bit timer counter H1 is cleared to 0 when 8-bit timer counter H1 and the CMP01 register match after the timer count is started. TOH1 output becomes inactive when 8-bit timer counter H1 and the CMP11 register match. (1) Usage In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output. <1> Set each register. Figure 8-8. Register Setting in PWM Output Mode (i) TMHMD1 Setting timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 0 0/1 0/1 0/1 TMMD11 TMMD10 TOLEV1 1 0 0/1 TOEN1 1 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP01 register * Compare value (N): Cycle setting (iii) Setting CMP11 register * Compare value (M): Duty setting Remark 00H CMP11 (M) < CMP01 (N) FFH <2> The count operation starts when TMHE1 = 1. <3> The CMP01 register is the compare register that is to be compared first after count operation is enabled. When the values of 8-bit timer counter H1 and the CMP01 register match, 8-bit timer counter H1 is cleared, an interrupt request signal (INTTMH1) is generated, and TOH1 output becomes active. At the same time, the compare register to be compared with 8-bit timer counter H1 is changed from the CMP01 register to the CMP11 register. 144 User's Manual U16898EJ6V0UD CHAPTER 8 8-BIT TIMER H1 <4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. At this time, 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHE1 = 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. PWM pulse output cycle = (N+1)/fCNT Duty = Active width : Total width of PWM = (M + 1) : (N + 1) Cautions 1. In PWM output mode, the setting value for the CMP11 register can be changed during timer count operation. However, three operation clocks (signal selected using the CKS12 to CKS10 bits of the TMHMD1 register) or more are required to transfer the register value after rewriting the CMP11 register value. 2. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). User's Manual U16898EJ6V0UD 145 CHAPTER 8 8-BIT TIMER H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. 00H CMP11 (M) < CMP01 (N) FFH Figure 8-9. Operation Timing in PWM Output Mode (1/4) (a) Basic operation (00H < CMP11 < CMP01 < FFH) Count clock 8-bit timer counter H1 00H 01H A5H 00H 01H 02H CMP01 A5H CMP11 01H A5H 00H 01H 02H A5H 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <2> <3> <4> TOH1 (TOLEV1 = 1) <1> The count operation is enabled by setting the TMHE1 bit to 1. Start 8-bit timer counter H1 by masking one count clock to count up. At this time, TOH1 output remains inactive (when TOLEV1 = 0). <2> When the values of 8-bit timer counter H1 and the CMP01 register match, the TOH1 output level is inverted, the value of 8-bit timer counter H1 is cleared, and the INTTMH1 signal is output. <3> When the values of 8-bit timer counter H1 and the CMP11 register match, the level of the TOH1 output is returned. At this time, the 8-bit timer counter value is not cleared and the INTTMH1 signal is not output. <4> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive. 146 User's Manual U16898EJ6V0UD CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H CMP01 FFH CMP11 00H FFH 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) (c) Operation when CMP01 = FFH, CMP11 = FEH Count clock 8-bit timer counter H1 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H CMP01 FFH CMP11 FEH FEH FFH 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) User's Manual U16898EJ6V0UD 147 CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP01 01H CMP11 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) 148 User's Manual U16898EJ6V0UD CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H 03H, CMP01 = A5H) Count clock 8-bit timer counter H1 00H 01H 02H 80H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP01 02H CMP11 02H (03H) 03H <2>' <2> TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHE1 = 1. Start 8-bit timer counter H1 by masking one count clock to count up. At this time, the TOH1 output remains inactive (when TOLEV1 = 0). <2> The CMP11 register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1 is cleared, the TOH1 output becomes active, and the INTTMH1 signal is output. <4> If the CMP11 register value is changed, the value is latched and not transferred to the register. When the values of 8-bit timer counter H1 and the CMP11 register before the change match, the value is transferred to the CMP11 register and the CMP11 register value is changed (<2>'). However, three count clocks or more are required from when the CMP11 register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of 8-bit timer counter H1 and the CMP11 register after the change match, the TOH1 output becomes inactive. 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated. <6> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive. User's Manual U16898EJ6V0UD 149 CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 14 RESET FUNCTION. Table 9-1. Loop Detection Time of Watchdog Timer Loop Detection Time During Low-Speed Internal oscillation Clock Operation During System Clock Operation 11 2 /fX (819.2 s) 12 2 /fX (1.64 ms) 13 2 /fX (3.28 ms) 14 2 /fX (6.55 ms) 15 2 /fX (13.11 ms) 16 2 /fX (26.21 ms) 17 2 /fX (52.43 ms) 18 2 /fX (104.86 ms) 13 2 /fRL (4.27 ms) 14 2 /fRL (8.53 ms) 15 2 /fRL (17.07 ms) 16 2 /fRL (34.13 ms) 17 2 /fRL (68.27 ms) 18 2 /fRL (136.53 ms) 19 2 /fRL (273.07 ms) 20 2 /fRL (546.13 ms) Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency 2. fX: Oscillation frequency of system clock 3. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz. The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the on-chip low-speed internal oscillator as shown in Table 9-2. 150 User's Manual U16898EJ6V0UD CHAPTER 9 WATCHDOG TIMER Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Setting Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software * Selectable by software (fX, fRL or stopped) Note 1 Watchdog timer clock Fixed to fRL . * When reset is released: fRL source 18 Operation starts with the maximum interval (2 /fRL). Operation starts with the maximum interval Operation after reset 18 (2 /fRL). Operation mode The interval can be changed only once. selection The clock selection/interval can be changed only once. Features The watchdog timer cannot be stopped. Notes 1. The watchdog timer can be stopped Note 2 . As long as power is being supplied, low-speed internal oscillator cannot be stopped (except in the reset period). 2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer. <1> If the clock source is fX, clock supply to the watchdog timer is stopped under the following conditions. * When fX is stopped * In HALT/STOP mode * During oscillation stabilization time <2> If the clock source is fRL, clock supply to the watchdog timer is stopped under the following conditions. * If the CPU clock is fX and if fRL is stopped by software before execution of the STOP instruction * In HALT/STOP mode Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency 2. fX: Oscillation frequency of system clock User's Manual U16898EJ6V0UD 151 CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 9-1. Block Diagram of Watchdog Timer fRL/22 fX/2 4 211/fRL to 218/fRL Clock input controller 16-bit counter 2 Watchdog timer enable register (WDTE) Selector or 213/fX to 220/fX 1 1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 Watchdog timer mode register (WDTM) Internal bus Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency 2. fX: System clock oscillation frequency 152 Internal reset signal 3 Clear 0 Output controller User's Manual U16898EJ6V0UD Option byte (to set "low-speed internal oscillator cannot be stopped" or "low-speed internal oscillator can be stopped by software") CHAPTER 9 WATCHDOG TIMER 9.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. * Watchdog timer mode register (WDTM) * Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released. Reset signal generation sets this register to 67H. Figure 9-2. Format of Watchdog Timer Mode Register (WDTM) Address: FF48H After reset: 67H R/W Symbol 7 6 5 4 3 2 1 0 WDTM 0 1 1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 WDCS4 Note 1 WDCS3 Note 1 Operation clock selection 0 0 Low-speed internal oscillation clock (fRL) 0 1 System Clock (fX) 1 x Watchdog timer operation stopped WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 Overflow time setting During low-speed internal During system clock operation oscillation clock operation 11 2 /fX (819.2 s) 12 2 /fX (1.64 ms) 13 2 /fX (3.28 ms) 14 2 /fX (6.55 ms) 15 2 /fX (13.11 ms) 16 2 /fX (26.21 ms) 17 2 /fX (52.43 ms) 18 2 /fX (104.86 ms) 0 0 0 2 /fRL (4.27 ms) 0 0 1 2 /fRL (8.53 ms) 0 1 0 2 /fRL (17.07 ms) 0 1 1 2 /fRL (34.13 ms) 1 0 0 2 /fRL (68.27 ms) 1 0 1 2 /fRL (136.53 ms) 1 1 0 2 /fRL (273.07 ms) 1 1 1 2 /fRL (546.13 ms) Notes 1. 13 14 15 16 17 18 19 20 If "low-speed internal oscillator cannot be stopped" is specified by the option byte, this cannot be set. The low-speed internal oscillation clock will be selected no matter what value is written. 2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1). User's Manual U16898EJ6V0UD 153 CHAPTER 9 WATCHDOG TIMER Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values. 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. However, at the first write, if "1" and "x" are set for WDCS4 and WDCS3 respectively and the watchdog timer is stopped, then the internal reset signal does not occur even if the following are executed. * Second write to WDTM * 1-bit memory manipulation instruction to WDTE * Writing of a value other than "ACH" to WDTE 3. WDTM cannot be set by a 1-bit memory manipulation instruction. 4. When using the flash memory programming by self programming, set the overflow time for the watchdog timer so that enough overflow time is secured (Example 1byte writing: 200 s MIN., 1-block deletion: 10 ms MIN.). Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency 2. fX: System clock oscillation frequency 3. x: Don't care 4. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz. (2) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH. Figure 9-3. Format of Watchdog Timer Enable Register (WDTE) Address: FF49H Symbol 7 After reset: 9AH 6 R/W 5 4 3 2 1 0 WDTE Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. 3. The value read from WDTE is 9AH (this differs from the written value (ACH)). 154 User's Manual U16898EJ6V0UD CHAPTER 9 WATCHDOG TIMER 9.4 9.4.1 Operation of Watchdog Timer Watchdog timer operation when "low-speed internal oscillator cannot be stopped" is selected by option byte The operation clock of watchdog timer is fixed to low-speed internal oscillation clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped. The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Low-speed internal oscillation clock * Cycle: 218/fRL (546.13 ms: operation with fRL = 480 kHz (MAX.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2. * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. Notes 1. The operation clock (low-speed internal oscillation clock) cannot be changed. If any value is written to bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored. 2. As soon as WDTM is written, the counter of the watchdog timer is cleared. Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the low-speed internal oscillation clock can be selected as the count source, so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows after STOP instruction execution. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution. A status transition diagram is shown below User's Manual U16898EJ6V0UD 155 CHAPTER 9 WATCHDOG TIMER Figure 9-4. Status Transition Diagram When "Low-Speed Internal Oscillator Cannot Be Stopped" Is Selected by Option Byte Reset WDT clock: fRL Overflow time: 546.13 ms (MAX.) WDTE = "ACH" Clear WDT counter. WDT clock is fixed to fRL. Select overflow time (settable only once). WDT clock: fRL Overflow time: 4.27 ms to 546.13 ms (MAX.) WDT count continues. HALT instruction STOP instruction Interrupt HALT WDT count continues. 156 Interrupt STOP WDT count continues. User's Manual U16898EJ6V0UD CHAPTER 9 WATCHDOG TIMER 9.4.2 Watchdog timer operation when "low-speed internal oscillator can be stopped by software" is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or the system clock. After reset is released, operation is started at the maximum cycle of the low-speed internal oscillation clock (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Low-speed internal oscillation clock * Cycle: 218/fRL (546.13 ms: operation with fRL = 480 kHz (MAX.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2, 3. * Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4). Low-speed internal oscillation clock (fRL) System clock (fX) Watchdog timer operation stopped * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. Notes 1. 2. 3. As soon as WDTM is written, the counter of the watchdog timer is cleared. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values. At the first write, if the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and x, respectively, an internal reset signal is not generated even if the following processing is performed. * WDTM is written a second time. * A 1-bit memory manipulation instruction is executed to WDTE. * A value other than ACH is written to WDTE. Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0 but holds its value. For the watchdog timer operation during STOP mode and HALT mode in each status, see 9.4.3 Watchdog timer operation in STOP mode and 9.4.4 Watchdog timer operation in HALT mode. A status transition diagram is shown below. User's Manual U16898EJ6V0UD 157 CHAPTER 9 WATCHDOG TIMER Figure 9-5. Status Transition Diagram When "Low-Speed Internal Oscillator Can Be Stopped by Software" Is Selected by Option Byte Reset WDT clock: fRL Overflow time: 546.13 ms (MAX.) WDCS4 = 1 WDT clock = fX Select overflow time (settable only once). WDTE = "ACH" Clear WDT counter. WDT clock = fRL Select overflow time (settable only once). WDT operation stops. WDTE = "ACH" Clear WDT counter. WDTE = "ACH" Clear WDT counter. LSRSTOP = 1 WDT clock: fRL Overflow time: 4.27 ms to 546.13 ms (MAX.) LSRSTOP = 0 WDT count continues. WDT clock: fX Overflow time: 213/fX to 220/fX WDT count continues. WDT clock: fRL WDT count stops. HALT instruction HALT instruction Interrupt STOP instruction Interrupt STOP instruction HALT instruction Interrupt STOP instruction Interrupt Interrupt HALT WDT count stops. 158 STOP WDT count stops. HALT WDT count stops. User's Manual U16898EJ6V0UD STOP WDT count stops. Interrupt CHAPTER 9 WATCHDOG TIMER 9.4.3 Watchdog timer operation in STOP mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low-speed internal oscillation clock is being used. (1) When the watchdog timer operation clock is the clock to peripheral hardware (fX) when the STOP instruction is executed When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 34 s (TYP.) (after waiting for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) after operation stops in the case of crystal/ceramic oscillation) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware) <1> CPU clock: Crystal/ceramic oscillation clock Normal CPU operation operation STOP Operation stoppedNote Normal operation Oscillation stabilization time fCPU Oscillation stopped Watchdog timer Oscillation stabilization time (set by OSTS register) Operation stopped Operating Operating <2> CPU clock: High-speed internal oscillation clock or external clock input CPU operation Normal operation STOP Operation stoppedNote Normal operation fCPU Oscillation stopped Watchdog timer Operating Operation stopped Operating Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). User's Manual U16898EJ6V0UD 159 CHAPTER 9 WATCHDOG TIMER (2) When the watchdog timer operation clock is the low-speed internal oscillation clock (fRL) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 34 s (TYP.) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-7. Operation in STOP Mode (WDT Operation Clock: Low-Speed Internal Oscillation Clock) <1> CPU clock: Crystal/ceramic oscillation clock Normal CPU operation operation STOP Operation stoppedNote Oscillation stabilization time Normal operation fCPU Oscillation stopped Oscillation stabilization time (set by OSTS register) fRL Watchdog timer Operating Operating Operation stopped <2> CPU clock: High-speed internal oscillation clock or external clock input CPU operation Normal operation STOP Operation stoppedNote Normal operation fCPU Oscillation stopped fRL Watchdog timer Operating Operation stopped Operating Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). 160 User's Manual U16898EJ6V0UD CHAPTER 9 WATCHDOG TIMER 9.4.4 Watchdog timer operation in HALT mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte) The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of the watchdog timer is the system clock (fX) or low-speed internal oscillation clock (fRL). After HALT mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-8. Operation in HALT Mode CPU operation Normal operation HALT Normal operation fCPU fX or fRL Watchdog timer Operating Operation stopped User's Manual U16898EJ6V0UD Operating 161 CHAPTER 10 A/D CONVERTER 10.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following function. * 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. Figure 10-1 shows the timing of sampling and A/D conversion, and Table 10-1 shows the sampling time and A/D conversion time. Figure 10-1. Timing of A/D Converter Sampling and A/D Conversion ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Note Sampling time Sampling time Conversion time Note 2 or 3 clocks are required from the ADCS rising to sampling start. 162 User's Manual U16898EJ6V0UD Conversion time CHAPTER 10 A/D CONVERTER Table 10-1. Sampling Time and A/D Conversion Time Reference Sampling Conversion Voltage TimeNote 2 TimeNote 3 RangeNote 1 fXP = 8 MHz fXP = 10 MHz Sampling Conversion Sampling Conversion TimeNote 2 TimeNote 3 TimeNote 2 TimeNote 3 FR2 FR1 FR0 AVREF 4.5 V 12/fXP 36/fXP 1.5 s 4.5 s 1.2 s 3.6 s 0 0 0 AVREF 4.0 V 24/fXP 72/fXP 3.0 s 9.0 s 2.4 s 7.2 s 1 0 0 AVREF 2.85 V 96/fXP 144/fXP 12.0 s 18.0 s 9.6 s 14.4 s 1 1 0 48/fXP 96/fXP 6.0 s 12.0 s 4.8 s 9.6 s 1 0 1 48/fXP 72/fXP 6.0 s 9.0 s 4.8 s 7.2 s 0 1 0 24/fXP 48/fXP 3.0 s 6.0 s 0 0 1 AVREF 2.7 V Notes 1. Setting Setting prohibited prohibited Note 4 Note 4 (2.4 s) (4.8 s) 176/fXP 224/fXP 22.0 s 28.0 s 17.6 s 22.4 s 1 1 1 88/fXP 112/fXP 11.0 s 14.0 s Setting Setting 0 1 1 prohibited prohibited Note 4 Note 4 (8.8 s) (11.2 s) Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 2 and 3 below are satisfied. Example When AVREF 2.7 V, fXP = 8 MHz * The sampling time is 11.0 s or more and the A/D conversion time is 14.0 s or more and 100 s or less. * Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1. 2. Set the sampling time as follows. * AVREF 4.5 V: 1.0 s or more * AVREF 4.0 V: 2.4 s or more * AVREF 2.85 V: 3.0 s or more * AVREF 2.7 V: 3. 11.0 s or more Set the A/D conversion time as follows. * AVREF 4.5 V: 3.0 s or more and less than 100 s * AVREF 4.0 V: 4.8 s or more and less than 100 s * AVREF 2.85 V: 6.0 s or more and less than 100 s * AVREF 2.7 V: 4. 14.0 s or more and less than 100 s Setting is prohibited because the values do not satisfy the condition of Notes 2 or 3. Caution The above sampling time and conversion time do not include the clock frequency error. Select the sampling time and conversion time such that Notes 2 and 3 above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the highspeed internal oscillator). Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware 2. The conversion time refers to the total of the sampling time and the time from successively comparing with the sampling value until the conversion result is output. User's Manual U16898EJ6V0UD 163 CHAPTER 10 A/D CONVERTER Figure 10-2 shows the block diagram of A/D converter. Figure 10-2. Block Diagram of A/D Converter ANI0/P20 Selector Sample & hold circuit ANI1/P21 ANI2/P22 Voltage comparator AVREF D/A converter VSS VSS ANI3/P23 Successive approximation register (SAR) Controller 2 ADS1 ADS0 A/D conversion result register (ADCR, ADCRH) 3 ADCS FR2 FR1 Analog input channel specification register (ADS) INTAD FR0 ADCE A/D converter mode register (ADM) Internal bus Caution In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 10.2 Configuration of A/D Converter The A/D converter consists of the following hardware. (1) ANI0 to ANI3 pins These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification register (ADS) can be used as I/O port pins. (2) Sample & hold circuit The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled analog input voltage value during A/D conversion. (3) D/A converter The D/A converter is connected between AVREF and VSS, and generates a voltage to be compared with the analog input signal. (4) Voltage comparator The voltage comparator compares the sampled analog input voltage and the output voltage of the D/A converter. 164 User's Manual U16898EJ6V0UD CHAPTER 10 A/D CONVERTER (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the D/A converter, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR). (6) 10-bit A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its lower 10 bits (the higher 6 bits are fixed to 0). (7) 8-bit A/D conversion result register (ADCRH) The result of A/D conversion is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register holds the result of A/D conversion in its higher 8 bits. (8) Controller When A/D conversion has been completed, INTAD is generated. (9) AVREF pin This pin inputs an analog power/reference voltage to the A/D converter. When the A/D converter is not used, connect this pin to VDD. The signal input to ANI0 to ANI3 is converted into a digital signal, based on the voltage applied across AVREF and VSS. (10) VSS pin This is the ground potential pin. In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). (11) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) Analog input channel specification register (ADS) This register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (13) Port mode control register 2 (PMC2) This register is used when the P20/ANI0 to P23/ANI3 pins are used as the analog input pins of the A/D converter. User's Manual U16898EJ6V0UD 165 CHAPTER 10 A/D CONVERTER 10.3 Registers Used by A/D Converter The A/D converter uses the following six registers. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) * Port mode control register 2 (PMC2) * Port mode register 2 (PM2) 166 User's Manual U16898EJ6V0UD CHAPTER 10 A/D CONVERTER (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-3. Format of A/D Converter Mode Register (ADM) Address: FF80H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 <0> ADM ADCS 0 FR2 FR1 FR0 0 0 ADCE ADCS A/D conversion operation control 0 1 Stops conversion operation Note 1 FR2 Starts conversion operation FR1 FR0 Reference Voltage Sampling Note 3 Time Conversion Time Note 4 RangeNote 2 0 0 0 AVREF fXP = 8 MHz fXP = 10 MHz Sampling Conversion Sampling Conversion TimeNote 3 TimeNote 4 TimeNote 3 TimeNote 4 12/fXP 36/fXP 1.5 s 4.5 s 1.2 s 3.6 s 24/fXP 72/fXP 3.0 s 9.0 s 2.4 s 7.2 s 18.0 s 9.6 s 14.4 s 4.5 V 1 0 0 AVREF 4.0 V 1 1 0 AVREF 96/fXP 144/fXP 12.0 s 2.85 V 1 0 1 48/fXP 96/fXP 6.0 s 12.0 s 4.8 s 9.6 s 0 1 0 48/fXP 72/fXP 6.0 s 9.0 s 4.8 s 7.2 s 0 0 1 24/fXP 48/fXP 3.0 s 6.0 s Setting Setting prohibited prohibited Note5 Note5 (2.4 s) (4.8 s) 17.6 s 22.4 s 1 1 0 1 1 AVREF 176/fXP 224/fXP 22.0 s 28.0 s 1 2.7 V 88/fXP 112/fXP 11.0 s 14.0 s ADCE 0 Note 1 1 Comparator operation control Setting Setting prohibited prohibited Note5 Note5 (8.8 s) (11.2 s) Note6 Stops operation of comparator Enables operation of comparator Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware 2. The conversion time refers to the total of the sampling time and the time from successively comparing with the sampling value until the conversion result is output. Note 1. Even when the ADCE = 0 (comparator operation stopped), the A/D conversion operation starts if the ADCS is set to 1. However, the first conversion data is out of the guaranteed-value range, so ignore it. User's Manual U16898EJ6V0UD 167 CHAPTER 10 A/D CONVERTER Notes 2. Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 2 and 3 below are satisfied. Example When AVREF 2.7 V, fXP = 8 MHz * The sampling time is 11.0 s or more and the A/D conversion time is 14.0 s or more and 100 s or less. * Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1. 3. Set the sampling time as follows. * AVREF 4.5 V: 1.0 s or more * AVREF 4.0 V: 2.4 s or more * AVREF 2.85 V: 3.0 s or more * AVREF 2.7 V: 11.0 s or more 4. Set the A/D conversion time as follows. * AVREF 4.5 V: 3.0 s or more and less than 100 s * AVREF 4.0 V: 4.8 s or more and less than 100 s * AVREF 2.85 V: 6.0 s or more and less than 100 s * AVREF 2.7 V: 14.0 s or more and less than 100 s 5. Setting is prohibited because the values do not satisfy the condition of Notes 3 or 4. 6. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. If the ADCS is set to 1 without waiting for 1 s or longer, ignore the first conversion data. Table 10-2. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation 0 0 Stop status (DC power consumption path does not exist) 0 1 Conversion waiting mode (only comparator consumes power) 1 x Conversion mode Figure 10-4. Timing Chart When Comparator Is Used Comparator operating ADCE Comparator Conversion operation Conversion waiting Conversion operation Conversion stopped ADCS Note Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 s or longer to stabilize the internal circuit. Caution 1. The above sampling time and conversion time do not include the clock frequency error. Select the sampling time and conversion time such that Notes 2 and 3 above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). 168 User's Manual U16898EJ6V0UD CHAPTER 10 A/D CONVERTER Cautions 2. If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0) and then A/D conversion is started, execute two NOP instructions or an instruction equivalent to two machine cycles, and set ADCS to 1. 3. A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2. 4. Be sure to clear bits 6, 2, and 1 to 0. (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-5. Format of Analog Input Channel Specification Register (ADS) Address: FF81H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS 0 0 0 0 0 0 ADS1 ADS0 ADS1 ADS0 0 0 ANI0 0 1 ANI1 1 0 ANI2 1 1 ANI3 Analog input channel specification Caution Be sure to clear bits 2 to 7 of ADS to 0. (3) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The higher six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from bit 1 of FF19H. FF19H indicates the higher 2 bits of the conversion result, and FF18H indicates the lower 8 bits of the conversion result. ADCR can be read by a 16-bit memory manipulation instruction. Reset signal generation makes ADCR undefined. Figure 10-6. Format of 10-bit A/D Conversion Result Register (ADCR) Address: FF18H, FF19H R FF19H Symbol ADCR After reset: Undefined 0 0 0 0 0 FF18H 0 Caution When writing to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using timing other than the above may cause an incorrect conversion result to be read. User's Manual U16898EJ6V0UD 169 CHAPTER 10 A/D CONVERTER (4) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation makes ADCRH undefined. Figure 10-7. Format of 8-bit A/D Conversion Result Register (ADCRH) Address: FF1AH Symbol After reset: Undefined 7 6 R 5 4 3 2 1 0 ADCRH (5) Port mode control register 2 (PMC2) and port mode register 2 (PM2) When using the P20/ANI0 to P23/ANI3 pins for analog input, set PMC20 to PMC23 and PM20 to PM23 to 1. At this time, the output latches of P20 to P23 may be 0 or 1. PMC2 and PM2 are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears PMC2 to 00H and sets PM2 to FFH. Figure 10-8. Format of Port Mode Control Register 2 (PMC2) Address: FF84H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Operation mode specification (n = 0 to 3) 0 Port mode 1 A/D converter mode Caution When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot be used as port pins. Be sure to set the pull-up resistor option registers (PU20 to PU23) to 0 for the pins set to A/D converter mode. Figure 10-9. Format of Port Mode Register 2 (PM2) Address: FF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 PM2n 170 P2n pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U16898EJ6V0UD CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Set ADCE to 1. <2> Select one channel for A/D conversion using the analog input channel specification register (ADS), and select the conversion time using FR2 to FR0. <3> Execute two NOP instructions or an instruction equivalent to two machine cycles. <4> Set ADCS to 1 and start the conversion operation. (<5> to <11> are operations performed by hardware.) <5> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <6> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the A/D conversion operation has ended. <7> Bit 9 of the successive approximation register (SAR) is set. The D/A converter voltage tap is set to (1/2) AVREF by the tap selector. <8> The voltage difference between the D/A converter voltage tap and analog input is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB is reset to 0. <9> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The D/A converter voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <10> Comparison is continued in this way up to bit 0 of SAR. <11> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. <12> Repeat steps <5> to <11>, until ADCS is cleared to 0. To stop the A/D converter, clear ADCS to 0. To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the status of ADCE = 0, however, start from <1> (when not changing the channel and conversion time, skip step <2>). Cautions 1. 2. Remark Make sure the period of <1> to <4> is 1 s or more. It is no problem if the order of <1> and <2> is reversed. The following two types of A/D conversion result registers can be used. * ADCR (16 bits): Stores a 10-bit A/D conversion value. * ADCRH (8 bits): Stores an 8-bit A/D conversion value. User's Manual U16898EJ6V0UD 171 CHAPTER 10 A/D CONVERTER Figure 10-10. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion Conversion result SAR Undefined ADCR, ADCRH Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to ADM or the analog input channel specification register (ADS) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. Reset signal generation makes the A/D conversion result register (ADCR, ADCRH) undefined. 172 User's Manual U16898EJ6V0UD CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( VAIN AVREF x 1024 + 0.5) or (ADCR - 0.5) x where, INT( ): AVREF 1024 VAIN < (ADCR + 0.5) x AVREF 1024 Function which returns integer part of value in parentheses VAIN: Analog input voltage AVREF: AVREF pin voltage ADCR: 10-bit A/D conversion result register (ADCR) value Figure 10-11 shows the relationship between the analog input voltage and the A/D conversion result. Figure 10-11. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 03FFH 1022 03FEH 1021 03FDH 3 0003H 2 0002H 1 0001H A/D conversion result 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF User's Manual U16898EJ6V0UD 173 CHAPTER 10 A/D CONVERTER 10.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has started and when one A/D conversion has been completed, the next A/D conversion operation is immediately started. The A/D conversion operations are repeated until new data is written to ADS. If ADM or ADS is written during A/D conversion, the A/D conversion operation under execution is stopped and restarted from the beginning. If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the conversion result is undefined. Figure 10-12. A/D Conversion Operation Rewriting ADM ADCS = 1 A/D conversion ANIn Rewriting ADS ANIn ANIn ADCS = 0 ANIm ANIm Conversion is stopped Conversion result is not retained ADCR, ADCRH ANIn INTAD Remarks 1. n = 0 to 3 2. m = 0 to 3 174 User's Manual U16898EJ6V0UD ANIn Stopped ANIm CHAPTER 10 A/D CONVERTER The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <3> Execute two NOP instructions or an instruction equivalent to two machine cycles. <4> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion. <5> An interrupt request signal (INTAD) is generated. <6> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Change the channel> <7> Change the channel using bits 1 and 0 (ADS1, ADS0) of ADS. <8> An interrupt request signal (INTAD) is generated. <9> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Complete A/D conversion> <10> Clear ADCS to 0. <11> Clear ADCE to 0. Cautions 1. Make sure the period of <1> to <4> is 1 s or more. 2. It is no problem if the order of <1> and <2> is reversed. 3. <1> can be omitted. However, ignore the data resulting from the first conversion after <4> in this case. 4. The period from <5> to <8> differs from the conversion time set using bits 5 to 3 (FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time set using FR2 to FR0. User's Manual U16898EJ6V0UD 175 CHAPTER 10 A/D CONVERTER 10.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 10-13. Overall Error Figure 10-14. Quantization Error 1......1 1......1 Overall error Digital output Digital output Ideal line 1/2LSB Quantization error 1/2LSB 0......0 AVREF 0 0......0 Analog input 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. 176 User's Manual U16898EJ6V0UD CHAPTER 10 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 10-15. Zero-Scale Error Figure 10-16. Full-Scale Error Full-scale error Digital output (Lower 3 bits) Digital output (Lower 3 bits) 111 Ideal line 011 010 001 Zero-scale error 000 111 110 101 Ideal line 000 0 1 2 3 AVREF AVREF-3 0 Analog input (LSB) AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 10-17. Integral Linearity Error Figure 10-18. Differential Linearity Error 1......1 1......1 Ideal 1LSB width Digital output Digital output Ideal line Differential linearity error Integral linearity error 0......0 0 Analog input 0......0 0 AVREF Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time User's Manual U16898EJ6V0UD 177 CHAPTER 10 A/D CONVERTER 10.6 Cautions for A/D Converter (1) Operating current in STOP mode To satisfy the DC characteristics of the supply current in the STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 before executing the STOP instruction. (2) Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AVREF or higher and VSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by instruction upon the end of conversion ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR, ADCRH. <2> Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input channel specification register (ADS) write upon the end of conversion ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. 178 User's Manual U16898EJ6V0UD CHAPTER 10 A/D CONVERTER (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and ANI0 to ANI3 pins. <1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply. <2> Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 10-19, to reduce noise. <3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to their alternate functions during conversion. <4> The conversion accuracy can be improved by setting HALT mode immediately after the conversion starts. Figure 10-19. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than VSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI3 C = 0.01 to 0.1 F VSS (5) ANI0/P20 to ANI3/P23 <1> The analog input pins (ANI0 to ANI3) are also used as I/O port pins (P20 to P23). When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access P20 to P23 while conversion is in progress; otherwise the conversion resolution may be degraded. <2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI3 pins In this A/D converter, the internal sampling capacitor is charged and sampling is performed during sampling time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates both during sampling and otherwise. If the shortest conversion time of the reference voltage is used, to perform sufficient sampling, it is recommended to make the output impedance of the analog input source 1 k or lower, or attach a capacitor of around 0.01 F to 0.1 F to the ANI0 to ANI3 pins (see Figure 10-19). User's Manual U16898EJ6V0UD 179 CHAPTER 10 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 10-20. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) A/D conversion ADCR, ADCRH ANIn ADS rewrite (start of ANIm conversion) ANIn ANIn ADIF is set but ANIm conversion has not ended. ANIm ANIn ANIm ANIm ANIm ADIF Remarks 1. n = 0 to 3 2. m = 0 to 3 (8) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (9) A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an incorrect conversion result to be read. 180 User's Manual U16898EJ6V0UD CHAPTER 10 A/D CONVERTER (10) Operating current at conversion waiting mode The DC characteristic of the operating current during the STOP mode is not satisfied due to the conversion waiting mode (only the comparator consumes power), when bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) are set to 0 and 1 respectively. (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-21. Internal Equivalent Circuit of ANIn Pin ROUT RIN ANIn COUT CIN LSI internal Table 10-3. Resistance and Capacitance Values (Reference Values) of Equivalent Circuit AVREF ROUT RIN COUT CIN 4.5 V AVREF 5.5 V 1 k 3 k 8 pF 15 pF 2.7 V AVREF < 4.5 V 1 k 60 k 8 pF 15 pF Remarks 1. The resistance and capacitance values shown in Table 10-3 are not guaranteed values. 2. n = 0 to 3 3. ROUT: Allowable signal source impedance RIN: Analog input equivalent resistance CIN: Analog input equivalent capacitance COUT: Internal pin capacitance User's Manual U16898EJ6V0UD 181 CHAPTER 11 SERIAL INTERFACE UART6 11.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 11.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 11.4.2 Asynchronous serial interface (UART) mode and 11.4.3 Dedicated baud rate generator. * Two-pin configuration TXD6: Transmit data output pin RXD6: Receive data input pin * Data length of communication data can be selected from 7 or 8 bits. * Dedicated internal 8-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * MSB- or LSB-first communication selectable * Inverted transmission operation * Synchronous break field transmission from 13 to 20 bits * More than 11 bits can be identified for synchronous break field reception (SBF reception flag provided). Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data. 2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. 3. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is incorporated in LIN. 182 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 11-1 and 11-2 outline the transmission and reception operations of LIN. Figure 11-1. LIN Transmission Operation Wakeup signal frame Synchronous break field Synchronous field Identifier field Data field Data field Checksum field LIN bus 8 bits Note 1 13-bitNote 2 SBF transmission 55H Data Data Data Data transmission transmission transmission transmission transmission TxD6 (output) INTST6 Note 3 Notes 1. 2. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode. The synchronous break field is output by hardware. The output width is equal to the bit length set by bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 11.4.2 (2) (h) SBF transmission). 3. Remark INTST6 is output on completion of each transmission. It is also output when SBF is transmitted. The interval between each field is controlled by software. User's Manual U16898EJ6V0UD 183 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-2. LIN Reception Operation Wakeup signal frame Synchronous break field Synchronous field Identifier field Data field Data field Checksum field 13 bits SBF reception SF reception ID reception Data reception Data reception LIN bus <5> <2> RxD6 (input) Disable Data reception Enable <3> Reception interrupt (INTSR6) <1> Edge detection (INTP0) <4> Capture timer Disable Enable The flow for reception processing is described below. <1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. <2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has been detected, it is assumed that SBF reception has been completed correctly, and an interrupt request signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error has occurred. The interrupt request signal is not output and the SBF reception mode is restored. <3> If SBF reception has been completed correctly, an interrupt request signal is output. Start the 16-bit timer/event counter 00 during SBF reception completion interrupt processing, and measure the bit width (pulse width) of the sync field (refer to 6.4.3 Pulse width measurement operations). Detection of errors OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH. <4> Calculate the baud rate error from the bit interval of the synchronous field, disable UART6 after SF reception, and then re-set baud rate generator control register 6 (BRGC6). <5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again. Figure 11-3 illustrates the port configuration for LIN reception operation. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally. 184 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 Selector Figure 11-3. Port Configuration for LIN Reception Operation P44/RXD6 RXD6 input Port mode (PM44) P30/INTP0/TI000 Port mode (PM30) INTP0 input Port input selection control (ISC0) <ISC0> 0: Selects INTP0 (P30). 1: Selects RxD6 (P44). Selector Output latch (P30) Selector Selector Output latch (P44) TI000 input Port input selection control (ISC1) <ISC1> 0: Selects TI000 (P30). 1: Selects RxD6 (P44). Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 11-11) The peripheral functions used in the LIN communication operation are shown below. <Peripheral functions used> * External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication. * 16-bit timer/event counter 00 (TI000); baud rate error detection Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the synchronous field (SF) length and divides it by the number of bits. * Serial interface UART6 User's Manual U16898EJ6V0UD 185 CHAPTER 11 SERIAL INTERFACE UART6 11.2 Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware. Table 11-1. Configuration of Serial Interface UART6 Item Registers Configuration Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Input switch control register (ISC) Port mode register 4 (PM4) Port register 4 (P4) 186 User's Manual U16898EJ6V0UD Figure 11-4. Block Diagram of Serial Interface UART6 TI000, INTP0Note Filter INTSR6 Reception control Asynchronous serial interface operation mode register 6 (ASIM6) fXCLK6 (Base clock) Asynchronous serial interface reception error status register 6 (ASIS6) Baud rate generator Receive shift register 6 (RXS6) User's Manual U16898EJ6V0UD Asynchronous serial interface control register 6 (ASICL6) Receive buffer register 6 (RXB6) Asynchronous serial interface control register 6 (ASICL6) Transmit buffer register 6 (TXB6) Transmission control Transmit shift register 6 (TXS6) Reception unit Internal bus Baud rate generator control register 6 (BRGC6) 8 Asynchronous serial Clock selection interface transmission register 6 (CKSR6) status register 6 (ASIF6) Baud rate generator 8 INTST6 TXD6/ INTP1/P43 Registers Output latch (P43) Transmission unit Note Selectable with input switch control register (ISC). PM43 CHAPTER 11 SERIAL INTERFACE UART6 Selector INTSRE6 fXP fXP/2 fXP/22 fXP/23 fXP/24 fXP/25 fXP/26 fXP/27 fXP/28 fXP/29 fXP/210 fXP/211 RXD6/ P44 187 CHAPTER 11 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0. * In MSB-first reception, the receive data is transferred to bits 7 to 1 of RXB6 and the LSB of RXB6 is always 0. If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6. RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. Reset signal generation sets this register to FFH. Caution Reception enable status is entered, after having set RXE6 to 1 and one clock of the base clock (fXCLK6) has elapsed. (2) Receive shift register 6 (RXS6) This register converts the serial data input to the RXD6 pin into parallel data. RXS6 cannot be directly manipulated by a program. (3) Transmit buffer register 6 (TXB6) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6. If the data length is set to 7 bits: * In LSB-fast transmission, data is transferred to bits 0 to 6 of TXB6, and the MSB of TXB6 is not transmitted. * In MSB-fast transmission, data is transferred to bits 7 to 1 of TXB6, and the LSB of TXB6 is not transmitted. This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Cautions 1. When starting transmission, write transmit data to TXB6, after having set TXE6 to 1 and a wait of one clock or more of the base clock (fXCLK6) has been performed. 2. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. 3. Do not refresh (write the same value to) TXB6 by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). When outputting same values in continuous transmission, be sure to confirm that TXBF6 is 0 before writing the same values to TXB6. (4) Transmit shift register 6 (TXS6) This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6 pin at the falling edge of the base clock. TXS6 cannot be directly manipulated by a program. 188 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 11.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 4 (PM4) * Port register 4 (P4) (1) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial communication operations of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF90H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enabling/disabling operation of internal operation clock Disable operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit 1 Notes 1. Note 3 Note 2 . Enable operation of the internal operation clock The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when POWER6 is cleared to 0 during a transmission. 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. 3. A base clock (fXCLK6) is supplied as the internal operation clock when the POWER6 bit is set to 1 and one clock of the base clock (fXCLK6) has elapsed. User's Manual U16898EJ6V0UD 189 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) Note 1 TXE6 Enabling/disabling transmission 0 Disable transmission (synchronously reset the transmission circuit). 1 Enable transmission Note 2 RXE6 Enabling/disabling reception 0 Disable reception (synchronously reset the reception circuit). 1 Enable reception PS61 PS60 Transmission operation 0 0 Parity bit not output. Reception without parity 0 1 Output 0 parity. Reception as 0 parity 1 0 Output odd parity. Judge as odd parity. 1 1 Output even parity. Judge as even parity. CL6 Reception operation Note 3 Specification of character length of transmit/receive data 0 Character length of data = 7 bits 1 Character length of data = 8 bits SL6 Specification of number of stop bits of transmit data 0 Number of stop bits = 1 1 Number of stop bits = 2 ISRM6 Enabling/disabling occurrence of reception completion interrupt in case of error 0 "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). 1 "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur). Notes 1. TXE6 is synchronized by the base clock (fXCLK6) set by CKSR6. When re-enabling transmission operation, set TXE6 to 1 after having set TXE6 to 0 and one clock of the base clock (fXCLK6) has elapsed. If TXE6 is set to 1 before one clock of the base clock (fXCLK6) has elapsed, the transmission circuit may not able to be initialized. 2. RXE6 is synchronized by the base clock (fXCLK6) set by CKSR6. When re-enabling reception operation, set RXE6 to 1 after having set RXE6 to 0 and one clock of the base clock (fXCLK6) has elapsed. If RXE6 is set to 1 before one clock of the base clock (fXCLK6) has elapsed, the reception circuit may not be able to be initialized. 3. If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Caution 1. At startup, transmission operation is started by setting TXE6 to 1 after having set POWER6 to 1, then setting the transmit data to TXB6 after having waited for one clock or more of the base clock (fXCLK6). When stopping transmission operation, set POWER6 to 0 after having set TXE6 to 0. 190 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 Cautions 2. At startup, reception enable status is entered by setting RXE6 to 1 after having set POWER6 to 1 and one clock of the base clock (fXCLK6) has elapsed. When stopping reception operation, set POWER6 to 0 after having set RXE6 to 0. 3. Set POWER6 = 1 RXE6 = 1 in a state where a high level has been input to the RxD6 pin. If POWER6 = 1 RXE6 = 1 is set during low-level input, reception is started and correct data will not be received. 4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 5. Fix the PS61 and PS60 bits to 0 when the interface is used for LIN communication operation. 6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit. (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this register is read. Figure 11-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) Address: FF93H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIS6 0 0 0 0 0 PE6 FE6 OVE6 PE6 Status flag indicating parity error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If receive data is set to the RXB register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 4. Be sure to read ASIS6 before reading receive buffer register 6 (RXB6). User's Manual U16898EJ6V0UD 191 CHAPTER 11 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0. Figure 11-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) Address: FF95H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIF6 0 0 0 0 0 0 TXBF6 TXSF6 TXBF6 Transmit buffer data flag 0 If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) 1 If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6) TXSF6 0 Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer 1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. 192 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 11-8. Format of Clock Selection Register 6 (CKSR6) Address: FF96H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 0 0 0 0 fXP (10 MHz) 0 0 0 1 fXP/2 (5 MHz) 0 0 1 0 fXP/2 (2.5 MHz) 0 0 1 1 fXP/2 (1.25 MHz) 0 1 0 0 fXP/2 (625 kHz) 0 1 0 1 fXP/2 (312.5 kHz) 0 1 1 0 fXP/2 (156.25 kHz) 0 1 1 1 fXP/2 (78.13 kHz) 1 0 0 0 fXP/2 (39.06 kHz) 1 0 0 1 fXP/2 (19.53 kHz) 1 0 1 0 fXP/2 (9.77 kHz) 1 0 1 1 fXP/2 (4.89 kHz) Other than above Base clock (fXCLK6) selection 2 3 4 5 6 7 8 9 10 11 Setting prohibited Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. Figures in parentheses are for operation with fXP = 10 MHz 2. fXP: Oscillation frequency of clock to peripheral hardware User's Manual U16898EJ6V0UD 193 CHAPTER 11 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 11-9. Format of Baud Rate Generator Control Register 6 (BRGC6) Address: FF97H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8-bit counter 0 0 0 0 0 x x x x Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK6/8 0 0 0 0 1 0 0 1 9 fXCLK6/9 0 0 0 0 1 0 1 0 10 fXCLK6/10 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1 1 1 1 1 1 0 0 252 fXCLK6/252 1 1 1 1 1 1 0 1 253 fXCLK6/253 1 1 1 1 1 1 1 0 254 fXCLK6/254 1 1 1 1 1 1 1 1 255 fXCLK6/255 Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255) 3. x: Don't care 194 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1), if 0 data has been written to ASICL6 by SBRT6 and SBTT6. Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2) Address: FF98H After reset: 16H R/W Note Symbol <7> <6> 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DIR6 TXDLV6 SBRF6 SBF reception status flag 0 If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly 1 SBF reception in progress SBRT6 SBF reception trigger - 0 1 SBF reception trigger SBTT6 SBF transmission trigger 0 - 1 SBF transmission trigger Note Bit 7 is read-only. User's Manual U16898EJ6V0UD 195 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control 1 0 1 SBF is output with 13-bit length. 1 1 0 SBF is output with 14-bit length. 1 1 1 SBF is output with 15-bit length. 0 0 0 SBF is output with 16-bit length. 0 0 1 SBF is output with 17-bit length. 0 1 0 SBF is output with 18-bit length. 0 1 1 SBF is output with 19-bit length. 1 0 0 SBF is output with 20-bit length. DIR6 Specification of first bit 0 MSB 1 LSB TXDLV6 Enabling/disabling inverting TXD6 output 0 Normal output of TXD6 1 Inverted output of TXD6 Cautions 1. In the case of an SBF reception error, return to SBF reception mode again. The status of the SBRF6 flag will be held (1). For details on SBF reception refer to (2) - (i) SBF reception in 11.4.2 Asynchronous serial interface (UART) mode described later. 2. Before setting the SBRT6 bit to 1, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. Moreover, after setting the SBRT6 bit to 1, do not clear the SBRT6 bit to 0 before the SBF reception ends (an interrupt request signal is generated). 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1. Moreover, after setting the SBTT6 bit to 1, do not clear the SBTT6 bit to 0 before the SBF transmission ends (an interrupt request signal is generated). 5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of SBF transmission. 6. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. 196 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. By setting 1 to ISC0 and ISC1, the input source to INTP0 and TI000 switches to the input signal from the P44/RxD6 pin. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-11. Format of Input Switch Control Register (ISC) Address: FF8CH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ISC 0 0 0 0 0 0 ISC1 ISC0 ISC1 TI000 input source selection 0 TI000 (P30) 1 RxD6 (P44) ISC0 INTP0 input source selection 0 INTP0 (P30) 1 RxD6 (P44) (8) Port mode register 4 (PM4) This register sets port 4 input/output in 1-bit units. When using the P43/TxD6/INTP1 pin for serial interface data output, clear PM43 to 0 and set the output latch of P43 to 1. When using the P44/RxD6 pin for serial interface data input, set PM44 to 1. The output latch of P44 at this time may be 0 or 1. PM4 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 11-12. Format of Port Mode Register 4 (PM4) Address: FF24H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40 PM4n P4n pin I/O mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U16898EJ6V0UD 197 CHAPTER 11 SERIAL INTERFACE UART6 11.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 11.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6). ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Address: FF90H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enabling/disabling operation of internal operation clock Disable operation of the internal operation clock (fix the clock to low level) and asynchronously reset the internal circuit Note 2 . TXE6 0 Enabling/disabling transmission Disable transmission operation (synchronously reset the transmission circuit). RXE6 0 Enabling/disabling reception Disable reception (synchronously reset the reception circuit). Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface POWER6 = 0 during a transmission. transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode. To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1. Remark To use the RxD6/P44 and TxD6/INTP1/P43 pins as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS. 198 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 11.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 4 (PM4) * Port register 4 (P4) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the CKSR6 register (see Figure 11-8). <2> Set the BRGC6 register (see Figure 11-9). <3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 11-5). <4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 11-10). <5> Set bit 7 (POWER6) of the ASIM6 register to 1. <6> Set bit 6 (TXE6) of the ASIM6 register to 1. Transmission is enabled. Set bit 5 (RXE6) of the ASIM6 register to 1. Reception is enabled. <7> Write data to transmit buffer register 6 (TXB6). Data transmission is started. Caution Take the relationship with the other party of communication into consideration for the port mode register and port register setting procedures. In order to avoid the generation of unintended start bits (falling signals), set PM43 to 0 (output) after having set P43 to 1. User's Manual U16898EJ6V0UD 199 CHAPTER 11 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 11-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM43 P43 PM44 P44 UART6 Operation 0 0 0 x Note x Note 1 0 1 x Note x Note 1 0 0 1 1 1 0 1 x Note 1 x Note 1 x Note Pin Function TxD6/INTP1/P43 Stop P43 P44 Reception P43 RxD6 Note Transmission TxD6 P44 x Transmission/ TxD6 RxD6 x x reception Note Can be set as port function. Remark x: don't care POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) 200 TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 PM4x: Port mode register P4x: Port output latch RxD6/P44 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data. Figure 11-13. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit D1 D0 Parity bit Stop bit Character bits 2. MSB-first transmission/reception 1 data frame Start bit D7 D6 D5 D4 D3 D2 Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (ASIM6). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6). Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6. User's Manual U16898EJ6V0UD 201 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop 5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start 202 D0 D1 D2 D3 D4 D5 User's Manual U16898EJ6V0UD D6 D7 Stop Stop CHAPTER 11 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the interface is used for LIN communication operation. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. User's Manual U16898EJ6V0UD 203 CHAPTER 11 SERIAL INTERFACE UART6 (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1, and then bit 6 (TXE6) of ASIM6 is set to 1 after one clock of the base clock (fXCLK6) has elapsed, transmission enable status is entered. Transmission operation can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that, the data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated. Transmission is stopped until the data to be transmitted next is written to TXB6. Figure 11-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt occurs as soon as the last stop bit has been output. Figure 11-15. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Start D0 D1 D2 D6 D7 Parity Stop INTST6 2. Stop bit length: 2 TXD6 (output) INTST6 204 User's Manual U16898EJ6V0UD Stop CHAPTER 11 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. In addition, the next transmit data can be written to the TXB6 register without having to wait for the transmission time of one data frame, by confirming bit 0 (TXSF6) of asynchronous serial interface transmission status register 6 (ASIF6) after a transmission completion interrupt has occurred. To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and whether the TXB6 register can be written, and then write the data. For the continuous transmission procedure, refer to Figure 11-16 Example of Continuous Transmission Processing Flow. Cautions 1. Use the value of the TXBF flag to judge whether continuous transmission is possible. Do not write the next transmit data, by making a judgment only by the fact that the TXSF6 flag has been set to 1. 2. When the interface is used for LIN communication operation, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. The communication status can be checked using the TXSF6 flag. TXSF6 Transmission Status 0 Transmission is completed. 1 Transmission is in progress. Caution To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. User's Manual U16898EJ6V0UD 205 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-16 shows an example of the continuous transmission processing flow. Figure 11-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Yes No Read ASIF6 TXBF6 = 0? No Yes Write TXB6. Transmission completion interrupt occurred? No Yes Transfer executed necessary number of times? Yes No Read ASIF6 TXSF6 = 0? Yes Yes of Completion transmission processing Remark TXB6: Transmit buffer register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 (transmit buffer data flag) TXSF6: Bit 0 of ASIF6 (transmit shift register data flag) 206 User's Manual U16898EJ6V0UD No CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-17 shows the timing of starting continuous transmission, and Figure 11-18 shows the timing of ending continuous transmission. Figure 11-17. Timing of Starting Continuous Transmission Start TXD6 Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6 TXB6 FF TXS6 FF Data (1) Data (2) Data (1) Data (3) Data (2) Data (3) TXBF6 Note TXSF6 Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6 bit. Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 User's Manual U16898EJ6V0UD 207 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-18. Timing of Ending Continuous Transmission TXD6 Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop INTST6 TXB6 Data (n - 1) Data (n) Data (n - 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6 Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6) TXE6: 208 Bit 6 of asynchronous serial interface operation mode register (ASIM6) User's Manual U16898EJ6V0UD FF CHAPTER 11 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( in Figure 11-19). If the RXD6 pin is low level at this time, it is recognized as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error (OVE6) occurs, however, the receive data is not written to RXB6. Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception. Figure 11-19. Reception Completion Interrupt Request Timing RXD6 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR6 RXB6 Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. User's Manual U16898EJ6V0UD 209 CHAPTER 11 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt servicing (INTSR6/INTSRE6) (see Figure 11-6). The contents of ASIS6 are reset to 0 when ASIS6 is read. Table 11-3. Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data. Framing error Stop bit is not detected. Overrun error Reception of the next data is completed before data is read from receive buffer register 6 (RXB6). The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0. Figure 11-20. Reception Error Interrupt 1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are separated) (a) No error during reception (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 2. If ISRM6 is set to 1 (error interrupt is included in INTSR6) (a) No error during reception 210 (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock (fXCLK6) output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 11-21, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 11-21. Noise Filter Circuit Base clock RXD6/P44 In Internal signal A Q In Internal signal B Q LD_EN Match detector (h) SBF transmission When the interface is used for LIN communication operation, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 111 LIN Transmission Operation. When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TxD6 pin outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered, and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6 (ASICL6) to 1. Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored. Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6), or until SBTT6 is set to 1. Figure 11-22. SBF Transmission 1 TXD6 2 3 4 5 6 7 8 9 10 11 12 13 Stop INTST6 SBTT6 Remark TXD6: TXD6 pin (output) INTST6: Transmission completion interrupt request SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6) User's Manual U16898EJ6V0UD 211 CHAPTER 11 SERIAL INTERFACE UART6 (i) SBF reception When the interface is used for LIN communication operation, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 11-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and SBRT6 bits are not cleared. Figure 11-23. SBF Reception 1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits) 1 RXD6 2 3 4 5 6 7 8 9 10 SBRT6 /SBRF6 INTSR6 2. SBF reception error (stop bit is detected with a width of 10.5 bits or less) 1 RXD6 2 3 4 5 6 7 8 9 SBRT6 /SBRF6 INTSR6 Remark RXD6: "0" RXD6 pin (input) SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6) SBRF6: Bit 7 of ASICL6 INTSR6: Reception completion interrupt request 212 User's Manual U16898EJ6V0UD 10 CHAPTER 11 SERIAL INTERFACE UART6 11.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level when POWER6 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when POWER6 = 1 and TXE6 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. User's Manual U16898EJ6V0UD 213 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-24. Configuration of Baud Rate Generator POWER6 fXP Baud rate generator fXP/2 fXP/22 POWER6, TXE6 (or RXE6) fXP/23 fXP/24 fXP/25 Selector fXP/26 fXP/27 fXP/28 fXP/29 fXP/210 Match detector fXP/211 CKSR6: TPS63 to TPS60 Remark 214 8-bit counter fXCLK6 (Base clock) 1/2 Baud rate BRGC6: MDL67 to MDL60 POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 CKSR6: Clock selection register 6 BRGC6: Baud rate generator control register 6 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter. (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK6 2xk [bps] fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate = 10 M/(2 x 33) = 10000000/(2 x 33) = 151,515 [bps] Error = (151515/153600 - 1) x 100 = -1.357 [%] User's Manual U16898EJ6V0UD 215 CHAPTER 11 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 11-4. Set Data of Baud Rate Generator Baud Rate [bps] fXP = 10.0 MHz TPS63 to k TPS60 fXP = 8.38 MHz Calculated ERR[%] TPS63 to Value TPS60 k fXP = 4.19 MHz Calculated ERR[%] TPS63 to Value TPS60 k Calculated ERR[%] Value 600 6H 130 601 0.16 6H 109 601 0.11 5H 109 601 0.11 1200 5H 130 1202 0.16 5H 109 1201 0.11 4H 109 1201 0.11 2400 4H 130 2404 0.16 4H 109 2403 0.11 3H 109 2403 0.11 4800 3H 130 4808 0.16 3H 109 4805 0.11 2H 109 4805 0.11 9600 2H 130 9615 0.16 2H 109 9610 0.11 1H 109 9610 0.11 10400 1H 240 10417 0.16 1H 201 10423 0.22 1H 101 10475 -0.28 19200 1H 130 19231 0.16 1H 109 19220 0.11 0H 109 19220 0.11 31250 0H 160 31250 0.00 0H 134 31268 0.06 0H 67 31268 0.06 38400 0H 130 38462 0.16 0H 109 38440 0.11 0H 55 38090 -0.80 76800 0H 65 76923 0.16 0H 55 76182 -0.80 0H 27 77693 1.03 115200 0H 43 116279 0.94 0H 36 116389 1.03 0H 18 116389 1.03 153600 0H 33 151515 -1.36 0H 27 155185 1.03 0H 14 149643 -2.58 230400 0H 22 227272 -1.36 0H 18 232778 1.03 0H 9 232778 1.03 Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6)) k: Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k = 8, 9, 10, ..., 255) 216 fXP: Oscillation frequency of clock to peripheral hardware ERR: Baud rate error User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 11-25. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART6 Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 11-25, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART6 k: Set value of BRGC6 FL: 1-bit data length Margin of latch timing: 2 clocks User's Manual U16898EJ6V0UD 217 CHAPTER 11 SERIAL INTERFACE UART6 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission source is as follows. 22k BRmax = (FLmin/11)-1 = Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - FLmax = 21k - 2 20k k+2 2xk x FL = 21k - 2 2xk FL FL x 11 Therefore, the minimum receivable baud rate at the transmission source is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART6 and the transmission source can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 11-5. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 +3.53% -3.61% 20 +4.26% -4.31% 50 +4.56% -4.58% 100 +4.66% -4.67% 255 +4.72% -4.73% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC6 218 User's Manual U16898EJ6V0UD CHAPTER 11 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of the base clock (fXCLK6) from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 11-26. Data Frame Length During Continuous Transmission Start bit of second byte 1 data frame Start bit FL Bit 0 Bit 1 Bit 7 FL FL FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following expression is satisfied. FLstp = FL + 2/fXCLK6 Therefore, the data frame length during continuous transmission is: Data frame length = 11 x FL + 2/fXCLK6 User's Manual U16898EJ6V0UD 219 CHAPTER 12 INTERRUPT FUNCTIONS 12.1 Interrupt Function Types There are two types of interrupts: maskable interrupts and resets. * Maskable interrupts These interrupts undergo mask control. When an interrupt request occurs, the standby release signal occurs, and if an interrupt can be acknowledged then the program corresponding to the address written in the vector table address is executed (vector interrupt servicing). When several interrupt requests are generated at the same time, processing takes place in the priority order of the vector interrupt servicing. For details on the priority order, see Table 12-1. There are nine internal sources and four external sources of maskable interrupts. * Reset The CPU and SFR are returned to their initial states by the reset signal. The causes for reset signal occurrences are shown in Table 12-1. When a reset signal occurs, program execution starts from the programs at the addresses written in addresses 0000H and 0001H. 12.2 Interrupt Sources and Configuration There are a total of 13 maskable interrupt sources, and up to four reset sources (see Table 12-1). 220 User's Manual U16898EJ6V0UD CHAPTER 12 INTERRUPT FUNCTIONS Table 12-1. Interrupt Sources Interrupt Type Note 1 Priority Interrupt Source Name Trigger Internal/ Vector Table Basic External Address Configuration Note 2 Type Maskable Note 3 1 INTLVI Low-voltage detection 2 INTP0 Pin input edge detection 3 INTP1 4 INTTMH1 5 INTTM000 Internal 0006H (A) External 0008H (B) 000AH Match between TMH1 and CMP01 Internal Match between TM00 and CR000 000CH (A) 000EH (when compare register is specified), TI010 pin valid edge detection (when capture register is specified) 6 INTTM010 Match between TM00 and CR010 0010H (when compare register is specified), TI000 pin valid edge detection (when capture register is specified) Reset 7 INTAD End of A/D conversion 0012H 8 INTP2 Pin input edge detection 9 INTP3 10 INTTM80 Match between TM80 and CR80 11 INTSRE6 UART6 reception error occurrence 001CH 12 INTSR6 End of UART6 reception 001EH 13 INTST6 End of UART6 transmission 0020H - RESET Reset input POC Power-on-clear LVI Low-voltage detection WDT WDT overflow External 0016H (B) 0018H Internal - 001AH 0000H (A) - Note 4 Notes 1. Priority is the vector interrupt servicing priority order when several maskable interrupt requests are generated at the same time. 1 is the highest and 13 is the lowest. 2. Basic configuration types (A) and (B) correspond to (A) and (B) in Figure 12-1. 3. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 0 is selected. 4. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 1 is selected. Caution No interrupt sources correspond to the vector table address 0014H. User's Manual U16898EJ6V0UD 221 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (B) External maskable interrupt Internal bus External interrupt mode register (INTM0, INTM1) Interrupt request Edge detector MK IE IF Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag 222 User's Manual U16898EJ6V0UD CHAPTER 12 INTERRUPT FUNCTIONS 12.3 Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers. * Interrupt request flag registers (IF0, IF1) * Interrupt mask flag registers (MK0, MK1) * External interrupt mode registers (INTM0, INTM1) * Program status word (PSW) Table 12-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags. Table 12-2. Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag INTLVI LVIIF LVIMK INTP0 PIF0 PMK0 INTP1 PIF1 PMK1 INTTMH1 TMIFH1 TMMKH1 INTTM000 TMIF000 TMMK000 INTTM010 TMIF010 TMMK010 INTAD ADIF ADMK INTP2 PIF2 PMK2 INTP3 PIF3 PMK3 INTTM80 TMIF80 TMMK80 INTSRE6 SREIF6 SREMK6 INTSR6 SRIF6 SRMK6 INTST6 STIF6 STMK6 User's Manual U16898EJ6V0UD 223 CHAPTER 12 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0, IF1) An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is acknowledged or when a reset signal is input. IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears IF0 and IF1 to 00H. Figure 12-2. Format of Interrupt Request Flag Registers (IF0, IF1) Address: FFE0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> 0 IF0 ADIF TMIF010 TMIF000 TMIFH1 PIF1 PIF0 LVIIF 0 Address: FFE1H After reset: 00H R/W Symbol 7 <6> <5> <4> <3> <2> <1> 0 IF1 0 STIF6 SRIF6 SREIF6 TMIF80 PIF3 PIF2 0 xxIFx Interrupt request flag 0 No interrupt request signal has been issued. 1 An interrupt request signal has been issued; an interrupt request status. Caution Because P30, P31, P41, and P43 have an alternate function as external interrupt inputs, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. 224 User's Manual U16898EJ6V0UD CHAPTER 12 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0, MK1) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets MK0 and MK1 to FFH. Figure 12-3. Format of Interrupt Mask Flag Registers (MK0, MK1) Address: FFE4H Symbol <7> MK0 ADMK Address: FFE5H After reset: FFH <6> R/W <5> <4> TMMK010 TMMK000 TMMKH1 After reset: FFH <3> <2> <1> 0 PMK1 PMK0 LVIMK 1 R/W Symbol 7 <6> <5> <4> <3> <2> <1> 0 MK1 1 STMK6 SRMK6 SREMK6 TMMK80 PMK3 PMK2 1 xxMKx Interrupt servicing control 0 Enables interrupt servicing. 1 Disables interrupt servicing. Caution Because P30, P31, P41, and P43 have an alternate function as external interrupt inputs, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. User's Manual U16898EJ6V0UD 225 CHAPTER 12 INTERRUPT FUNCTIONS (3) External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. Reset signal generation clears INTM0 to 00H. Figure 12-4. Format of External Interrupt Mode Register 0 (INTM0) Address: FFECH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 INTM0 ES21 ES20 ES11 ES10 ES01 ES00 0 0 ES21 ES20 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES11 ES10 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES01 ES00 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges INTP2 valid edge selection INTP1 valid edge selection INTP0 valid edge selection Cautions 1. Be sure to clear bits 0 and 1 to 0. 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag (xxMKx = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt request flag (xxIFx = 0), then clear the interrupt mask flag (xxMKx = 0), which will enable interrupts. 226 User's Manual U16898EJ6V0UD CHAPTER 12 INTERRUPT FUNCTIONS (4) External interrupt mode register 1 (INTM1) INTM1 is used to specify the valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. Reset signal generation clears INTM1 to 00H. Figure 12-5. Format of External Interrupt Mode Register 1 (INTM1) Address: FFEDH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 INTM1 0 0 0 0 0 0 ES31 ES30 ES31 ES30 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges INTP3 valid edge selection Cautions 1. Be sure to clear bits 2 to 7 to 0. 2. Before setting INTM1, set PMK3 to 1 to disable interrupts. To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0. (5) Program status word (PSW) The program status word is used to hold the instruction execution result and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW. PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically saved to a stack, and the IE flag is reset to 0. Reset signal generation sets PSW to 02H. Figure 12-6. Program Status Word (PSW) Configuration Symbol 7 6 5 4 3 2 1 0 After reset PSW IE Z 0 AC 0 0 1 CY 02H Used in the execution of ordinary instructions Whether to enable/disable interrupt acknowledgment IE 0 Disabled 1 Enabled User's Manual U16898EJ6V0UD 227 CHAPTER 12 INTERRUPT FUNCTIONS 12.4 Interrupt Servicing Operation 12.4.1 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. If the interrupt enabled status is in effect (when the IE flag is set to 1), then the request is acknowledged as a vector interrupt. The time required to start the vectored interrupt servicing after a maskable interrupt request has been generated is shown in Table 12-3. See Figures 12-8 and 12-9 for the interrupt request acknowledgment timing. Table 12-3. Time from Generation of Maskable Interrupt Request to Servicing Note Minimum Time 9 clocks Maximum Time 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instructions. Remark 1 clock: 1 (fCPU: CPU clock) fCPU When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. A pending interrupt is acknowledged when a status in which it can be acknowledged is set. Figure 12-7 shows the algorithm of interrupt request acknowledgment. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt servicing, use the RETI instruction. 228 User's Manual U16898EJ6V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-7. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (Interrupt request generated) xxMK = 0? No Yes Interrupt request pending No IE = 1? Yes Interrupt request pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag IE: Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable) Figure 12-8. Interrupt Request Acknowledgment Timing (Example of MOV A, r) 8 clocks Clock CPU MOV A, r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set before an instruction clock n (n = 4 to 10) under execution becomes n - 1, the interrupt is acknowledged after the instruction under execution is complete. Figure 12-8 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the instruction fetch starts, the interrupt acknowledgment processing is performed after the MOV A, r instruction is executed. User's Manual U16898EJ6V0UD 229 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-9. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock CPU NOP MOV A, r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed. Figure 12-9 shows an example of the interrupt request acknowledgment timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A, r instruction after the NOP instruction is executed, and then the interrupt acknowledgment processing is performed. Caution Interrupt requests will be held pending while the interrupt request flag registers (IF0, IF1) or interrupt mask flag registers (MK0, MK1) are being accessed. 12.4.2 Multiple interrupt servicing In order to perform multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced, the interrupt mask function must be used to mask interrupts for which a low priority is to be set. 230 User's Manual U16898EJ6V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-10. Example of Multiple Interrupts (1/2) Example 1. Multiple interrupts are acknowledged INTxx servicing Main processing EI IE = 0 EI INTyy servicing IE = 0 INTyy INTxx RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated. Before each interrupt request acknowledgment, the EI instruction is issued, the interrupt mask is released, and the interrupt request acknowledgment enable state is set. Caution Multiple interrupts can be acknowledged even for low-priority interrupts. Example 2. Multiple interrupts are not generated because interrupts are not enabled INTxx servicing Main processing EI IE = 0 INTyy servicing INTyy is held pending INTyy RETI INTxx IE = 0 RETI Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is held pending and acknowledged after the INTxx servicing is performed. IE = 0: Interrupt request acknowledgment disabled User's Manual U16898EJ6V0UD 231 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-10. Example of Multiple Interrupts (2/2) Example 3. A priority is controlled by the multiple interrupts The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1. (Interrupt priority INTP0 > INTP1 > INTTMH1 (refer to Table12-1)) INTTNH1 servicing Main processing EI INTP1 servicing IE = 0 PMK0 = 1 EI IE = 0 INTTMH1 INTP0 INTP1 RETI INTP0 servicing PMK0 = 0 IE = 0 RETI RETI In the interrupt INTTMH1 servicing, servicing is performed such that the INTP1 interrupt is given priority, since the INTP0 interrupt was first masked. Afterwards, once the interrupt mask for INTP0 is released, INTP0 processing through multiple interrupts is performed. IE = 0: Interrupt request acknowledgment disabled 12.4.3 Interrupt request pending Some instructions may keep pending the acknowledgment of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated during the execution. The following shows such instructions (interrupt request pending instruction). * Manipulation instruction for interrupt request flag registers (IF0, IF1) * Manipulation instruction for interrupt mask flag registers (MK0, MK1) 232 User's Manual U16898EJ6V0UD CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration 13.1.1 Standby function Table 13-1. Relationship Between Operation Clocks in Each Operation Status Status Low-Speed Internal Oscillator Note 1 Operation Mode Reset LSRSTOP = 0 Oscillating Oscillating Note 3 Hardware LSRSTOP = 1 Stopped Stopped Oscillating Oscillating Stopped HALT Notes 1. Clock Supplied to Peripheral Note 2 Stopped STOP System Clock When "Cannot be stopped" is selected for low-speed internal oscillator by the option byte. 2. When it is selected that the low-speed internal oscillator "can be stopped by software", oscillation of the 3. If the operating clock of the watchdog timer is the low-speed internal oscillation clock, the watchdog low-speed internal oscillator can be stopped by LSRSTOP. timer is stopped. Caution The LSRSTOP setting is valid only when "Can be stopped by software" is set for the low-speed internal oscillator by the option byte. Remark LSRSTOP: Bit 0 of the low-speed internal oscillation mode register (LSRCM) The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. Oscillation of the system clock oscillator continues. If the low-speed internal oscillator is operating before the HALT mode is set, oscillation of the clock of the low-speed internal oscillator continues (refer to Table 13-1. Oscillation of the low-speed internal oscillation clock (whether it cannot be stopped or can be stopped by software) is set by the option byte). In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and frequently carrying out intermittent operations. User's Manual U16898EJ6V0UD 233 CHAPTER 13 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, select the HALT mode if processing must be immediately started by an interrupt request when the operation stop timeNote is generated after the STOP mode is released (because an additional wait time for stabilizing oscillation elapses when crystal/ceramic oscillation is used). Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction (except the peripheral hardware that operates on the low-speed internal oscillation clock). 2. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 3. If the low-speed internal oscillator is operating before the STOP mode is set, oscillation of the low-speed internal oscillation clock cannot be stopped in the STOP mode (refer to Table 13-1). 234 User's Manual U16898EJ6V0UD CHAPTER 13 STANDBY FUNCTION 13.1.2 Registers used during standby The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time select register (OSTS). Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS. (1) Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released. If the high-speed internal oscillation or external clock input is selected as the system clock source, no wait time elapses. The system clock oscillator and the oscillation stabilization time that elapses after power application or release of reset are selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. OSTS is set by using the 8-bit memory manipulation instruction. Figure 13-1. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFF4H After reset: Undefined R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 0 0 2 /fX (102.4 s) 0 1 2 /fX (409.6 s) 1 0 2 /fX (3.27 ms) 1 1 2 /fX (13.1 ms) Selection of oscillation stabilization time 10 12 15 17 Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows. Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS 2. The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset signal generation or interrupt generation. STOP mode is released Voltage waveform of X1 pin a 3. The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Remarks 1. ( ): fX = 10 MHz 2. Determine the oscillation stabilization time of the resonator by checking the characteristics of the resonator to be used. User's Manual U16898EJ6V0UD 235 CHAPTER 13 STANDBY FUNCTION 13.2 Standby Function Operation 13.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag clear, the standby mode is immediately cleared if set. Table 13-2. Operating Statuses in HALT Mode Setting of HALT Mode Low-Speed Internal Oscillator Cannot Be Low-Speed Internal Oscillator Can Be Stopped Note When Low-Speed Internal When Low-Speed Internal Oscillation Continues Oscillation Stops Note Stopped Item System clock Clock supply to CPU is stopped. CPU Operation stops. Port (latch) Holds status before HALT mode was set. 16-bit timer/event counter 00 Operable 8-bit timer 80 8-bit timer Operable Sets count clock to fXP to fXP/2 H1 Sets count clock to fRL/2 Watchdog System clock selected as timer operating clock 12 7 Operable Operable Operable Setting prohibited Operation stops. "Low-speed internal oscillation Operable (Operation Operation stops. clock" selected as operating continues.) Operation stops. clock A/D converter Operable Serial interface UART6 Operable Power-on-clear circuit Always operates. Low-voltage detector Operable External interrupt Operable Note "Cannot be stopped" or "Stopped by software" is selected for low-speed internal oscillator by the option byte (for the option byte, see CHAPTER 17 OPTION BYTE). 236 User's Manual U16898EJ6V0UD CHAPTER 13 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 13-2. HALT Mode Release by Interrupt Request Generation Interrupt request HALT instruction Wait Standby release signal Status of CPU Operating mode HALT mode Wait Operating mode Oscillation System clock oscillation Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is carried out: 11 to 13 clocks * When vectored interrupt servicing is not carried out: 3 to 5 clocks User's Manual U16898EJ6V0UD 237 CHAPTER 13 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 13-3. HALT Mode Release by Reset Signal Generation (1) When CPU clock is high-speed internal oscillation clock or external input clock HALT instruction Reset signal CPU status Operation mode Reset period HALT mode Oscillates System clock oscillation Operation stopsNote Oscillation stops Operation mode Oscillates Note Operation is stopped (277 s (MIN.), 544 s (TYP.), 1.075 ms (MAX.)) because the option byte is referenced. (2) When CPU clock is crystal/ceramic oscillation clock HALT instruction Reset signal CPU status Operation mode Oscillation Reset Operation Operation period stopsNote stabilization waits mode HALT mode Oscillates System clock oscillation Oscillation stops Oscillates Oscillation stabilization time (210/fX to 217/fX) Note Operation is stopped (276 s (MIN.), 544 s (TYP.), 1.074 ms (MAX.)) because the option byte is referenced. Remark fX: System clock oscillation frequency Table 13-3. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt request Reset signal generation MKxx IE Operation 0 0 Next address instruction execution 0 1 Interrupt servicing execution 1 x HALT mode held - x Reset processing x: don't care 238 User's Manual U16898EJ6V0UD CHAPTER 13 STANDBY FUNCTION 13.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, in the STOP mode, the normal operation mode is restored after the STOP instruction is executed and then the operation is stopped for 34 s (TYP.) (after an additional wait time for stabilizing the oscillation set by the oscillation stabilization time select register (OSTS) has elapsed when crystal/ceramic oscillation is used). The operating statuses in the STOP mode are shown below. Table 13-4. Operating Statuses in STOP Mode Setting of HALT Mode Low-Speed Internal Oscillator Cannot Be Low-Speed Internal Oscillator Can Be Stopped Note When Low-Speed Internal When Low-Speed Internal Oscillation Continues Oscillation Stops Note Stopped Item System clock Oscillation stops. CPU Operation stops. Port (latch) Holds status before STOP mode is set. 16-bit timer/event counter 00 Operation stops. 8-bit timer 80 8-bit timer Operation stops. Sets count clock to fXP to fXP/2 12 H1 Sets count clock to fRL/2 Watchdog "Clock to peripheral hardware" timer selected as operating clock 7 Operation stops. Operable Operable Setting prohibited Operation stops. "Low-speed internal oscillation Operable (Operation Operation stops. clock" selected as operating continues.) Operation stops. clock A/D converter Operation stops. Serial interface UART6 Operation stops. Power-on-clear circuit Always operates. Low-voltage detector Operable External interrupt Operable Note "Cannot be stopped" or "Stopped by software" is selected for low-speed internal oscillator by the option byte (for the option byte, see CHAPTER 17 OPTION BYTE). User's Manual U16898EJ6V0UD 239 CHAPTER 13 STANDBY FUNCTION (2) STOP mode release Figure 13-4. Operation Timing When STOP Mode Is Released <1> If high-speed internal oscillation clock or external input clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation CPU clock Operation stopsNote. High-speed internal oscillation clock or external clock input <2> If crystal/ceramic oscillation clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation CPU clock Operation stopsNote. HALT status (oscillation stabilization time set by OSTS) Crystal/ceramic oscillation clock Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). The STOP mode can be released by the following two sources. 240 User's Manual U16898EJ6V0UD CHAPTER 13 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request (8-bit timer H1Note, low-voltage detector, external interrupt request) is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Note Only when sets count clock to fRL/27 Figure 13-5. STOP Mode Release by Interrupt Request Generation (1) If CPU clock is high-speed internal oscillation clock or external input clock Interrupt request STOP instruction Standby release signal CPU status System clock oscillation Operation mode Oscillation Operation stopsNote. STOP mode Oscillation stops. Operation mode Oscillation (2) If CPU clock is crystal/ceramic oscillation clock Interrupt request STOP instruction Standby release signal CPU status Operation mode System clock Oscillation STOP mode Operation Waiting for stabilization stopsNote. of oscillation (HALT mode status) Oscillation stops. Operation mode Oscillation Oscillation stabilization time (set by OSTS) Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. User's Manual U16898EJ6V0UD 241 CHAPTER 13 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 13-6. STOP Mode Release by Reset Signal Generation (1) If CPU clock is high-speed internal oscillation clock or external input clock STOP instruction Reset signal CPU status System clock oscillation Operation mode Oscillation Operation stopsNote. Reset period STOP mode Oscillation stops. Operation mode Oscillation Note Operation is stopped (277 s (MIN.), 544 s (TYP.), 1.075 ms (MAX.)) because the option byte is referenced. (2) If CPU clock is crystal/ceramic oscillation clock STOP instruction Reset signal CPU status System clock oscillation Operation mode Reset period STOP mode Oscillation Oscillation Operation Operation stopsNote. stabilization waits mode Oscillation stops. Oscillation Oscillation stabilization time (210/fX to 217/fX) Note Operation is stopped (276 s (MIN.), 544 s (TYP.), 1.074 ms (MAX.)) because the option byte is referenced. Remark fX: System clock oscillation frequency Table 13-5. Operation in Response to Interrupt Request in STOP Mode Release Source Maskable interrupt request Reset signal generation MKxx IE Operation 0 0 Next address instruction execution 0 1 Interrupt servicing execution 1 x STOP mode held - x Reset processing x: don't care 242 User's Manual U16898EJ6V0UD CHAPTER 14 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer overflows (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts from the programs at the address written in addresses 0000H and 0001H when the reset signal is generated. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Table 14-1. Each pin is high impedance during reset signal generation or during the oscillation stabilization time just after reset release, except for P130, which is low-level output. When a low level is input to the RESET pin, a reset occurs, and when a high level is input to the RESET pin, the reset is released and the CPU starts program execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). A reset generated by the watchdog timer source is automatically released after the reset, and the CPU starts program execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). (see Figures 14-2 to 14-4). Reset by POC and LVI circuit power supply detection is automatically released when VDD > VPOC or VDD > VLVI after the reset, and the CPU starts program execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected) (see CHAPTER 15 POWER-ON-CLEAR CIRCUIT and CHAPTER 16 LOW-VOLTAGE DETECTOR). Cautions 1. For an external reset, input a low level for 2 s or more to the RESET pin. 2. During reset signal generation, the system clock and low-speed internal oscillation clock stop oscillating. 3. When the RESET pin is used as an input-only port pin (P34), the 78K0S/KA1+ is reset if a low level is input to the RESET pin after reset is released by the POC circuit, the LVI circuit and the watchdog timer and before the option byte is referenced again. The reset status is retained until a high level is input to the RESET pin. User's Manual U16898EJ6V0UD 243 CHAPTER 14 RESET FUNCTION Figure 14-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF Reset signal of WDT Set LVIRF Set Clear Clear Reset signal to LVIM/LVIS register RESET Reset signal of POC Internal reset signal Reset signal of LVI Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit. Remarks 1. LVIM: Low-voltage detect register 2. LVIS: Low-voltage detection level select register 244 User's Manual U16898EJ6V0UD CHAPTER 14 RESET FUNCTION Figure 14-2. Timing of Reset by RESET Input <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input CPU clock Normal operation in progress Reset period (oscillation stops) Normal operation (reset processing, CPU clock) RESET Operation stops because option byte is referencedNote 1. Internal reset signal Delay 100 ns (TYP.) Delay 100 ns (TYP.) Hi-Z Port pin (except P130) Port pin (P130) Notes 1. 2. Remark Note 2 The operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). Set high level output using software. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. <2> With crystal/ceramic oscillation clock Crystal/ceramic oscillation clock Normal operation in progress Reset period (oscillation stops) Oscillation stabilization time (210/fX to 217/fX) RESET Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote 1. Internal reset signal Delay 100 ns (TYP.) Delay 100 ns (TYP.) Hi-Z Port pin (except P130) Port pin (P130) Notes 1. 2. Note 2 The operation stop time is 276 s (MIN.), 544 s (TYP.), and 1.074 ms (MAX.). Set high level output using software. Remarks 1. fX: System clock oscillation frequency 2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. User's Manual U16898EJ6V0UD 245 CHAPTER 14 RESET FUNCTION Figure 14-3. Timing of Reset by Overflow of Watchdog Timer <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input CPU clock Reset period (oscillation stops) Normal operation in progress Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote 1. Watchdog overflow Internal reset signal Hi-Z Port pin (except P130) Port pin (P130) Notes 1. 2. Note 2 The operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). Set high level output using software. Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer. Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. <2> With crystal/ceramic oscillation clock Crystal/ceramic oscillation clock CPU clock Normal operation in progress Reset period (oscillation stops) Oscillation stabilization time (210/fX to 217/fX) Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote 1. Watchdog overflow Internal reset signal Hi-Z Port pin (except P130) Port pin (P130) Notes 1. 2. Note 2 The operation stop time is 276 s (MIN.), 544 s (TYP.), and 1.074 ms (MAX.). Set high level output using software. Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer. Remarks 1. fX: System clock oscillation frequency 2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. 246 User's Manual U16898EJ6V0UD CHAPTER 14 RESET FUNCTION Figure 14-4. Reset Timing by RESET Input in STOP Mode <1> With high-speed internal oscillation clock or external clock input STOP instruction is executed. High-speed internal oscillation clock or external clock input CPU clock Normal operation in progress Stop status (oscillation stops) Reset period (oscillation stops) RESET Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote 1. Internal reset signal Delay 100 ns (TYP.) Delay 100 ns (TYP.) Hi-Z Port pin (except P130) Port pin (P130) Notes 1. 2. Remark Note 2 The operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). Set high level output using software. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. <2> With crystal/ceramic oscillation clock STOP instruction is executed. High-speed internal oscillation clock or external clock input CPU clock Normal operation in progress Stop status (oscillation stops) Reset period (oscillation stops) RESET Oscillation stabilization time (210/fX to 217/fX) Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote 1. Internal reset signal Delay 100 ns (TYP.) Delay 100 ns (TYP.) Hi-Z Port pin (except P130) Port pin (P130) Notes 1. 2. Note 2 The operation stop time is 276 s (MIN.), 544 s (TYP.), and 1.074 ms (MAX.). Set high level output using software. User's Manual U16898EJ6V0UD 247 CHAPTER 14 RESET FUNCTION Remarks 1. For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 15 POWER-ON-CLEAR CIRCUIT and CHAPTER 16 LOW-VOLTAGE DETECTOR. 2. fX: System clock oscillation frequency 3. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU. Table 14-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Program counter (PC) Note 1 Status After Reset Contents of reset vector table (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined General-purpose registers Undefined Ports (P2 to P4, P12, P13) (output latches) 00H Port mode registers (PM2 to PM4, PM12) FFH Port mode control register (PMC2) 00H Pull-up resistor option registers (PU2, PU3, PU4, PU12) 00H Processor clock control register (PCC) 02H Preprocessor clock control register (PPCC) 02H Low-speed internal oscillation mode register (LSRCM) 00H Oscillation stabilization time select register (OSTS) Undefined 16-bit timer 00 Timer counter 00 (TM00) 0000H Capture/compare registers 000, 010 (CR000, CR010) 0000H Mode control register 00 (TMC00) 00H Prescaler mode register 00 (PRM00) 00H Capture/compare control register 00 (CRC00) 00H Timer output control register 00 (TOC00) 00H Timer counter 80 (TM80) 00H Compare register (CR80) Undefined Mode control register 80 (TMC80) 00H Compare registers (CMP01, CMP11) 00H Mode register 1 (TMHMD1) 00H Watchdog timer Mode register (WDTM) 67H Enable register (WDTE) 9AH A/D converter Conversion result registers (ADCR, ADCRH) Undefined Mode register (ADM) 00H Analog input channel specification register (ADS) 00H 8-bit timer 80 8-bit timer H1 Notes 1. 248 Note 2 Only the contents of PC are undefined while reset signal generation and while the oscillation stabilization time elapses. The statuses of the other hardware units remain unchanged. 2. Note 2 The status after reset is held in the standby mode. User's Manual U16898EJ6V0UD CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Serial interface UART6 Status After Reset Receive buffer register 6 (RXB6) FFH Transmit buffer register 6 (TXB6) FFH Asynchronous serial interface operation mode register 6 (ASIM6) 01H Asynchronous serial interface reception error status register 6 00H (ASIS6) Asynchronous serial interface transmission error status register 6 00H (ASIF6) Clock select register 6 (CKSR6) 00H Baud rate generator control register 6 (BRGC6) FFH Asynchronous serial interface control register 6 (ASICL6) 16H Input select control register (ISC) 00H Reset function Reset control flag register (RESF) 00H Low-voltage detector Low-voltage detection register (LVIM) 00H Low-voltage detection level select register (LVIS) 00H Request flag registers (IF0, IF1) 00H Mask flag registers (MK0, MK1) FFH External interrupt mode registers (INTM0, INTM1) 00H Flash protect command register (PFCMD) Undefined Flash status register (PFS) 00H Interrupt Flash memory Note Note Note Flash programming mode control register (FLPMC) Undefined Flash programming command register (FLCMD) 00H Flash address pointer L (FLAPL) Undefined Flash address pointer H (FLAPH) Flash address pointer H compare register (FLAPHC) 00H Flash address pointer L compare register (FLAPLC) 00H Flash write buffer register (FLW) 00H Note These values change as follows depending on the reset source. Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Register RESF WDTRF Cleared (0) Cleared (0) LVIRF LVIM Cleared (00H) Cleared (00H) Set (1) Held Held Set (1) Cleared (00H) Held LVIS User's Manual U16898EJ6V0UD 249 CHAPTER 14 RESET FUNCTION 14.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0S/KA1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H. Figure 14-5. Format of Reset Control Flag Register (RESF) Address: FF54H After reset: 00H Note R Symbol 7 6 5 4 3 2 1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer (WDT) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. LVIRF Internal reset request by low-voltage detector (LVI) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. Note The value after reset varies depending on the reset source. Caution Do not read data by a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 14-2. Table 14-2. RESF Status When Reset Request Is Generated Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Flag WDTRF LVIRF 250 Cleared (0) Cleared (0) Set (1) Held Held Set (1) User's Manual U16898EJ6V0UD CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. * Generates internal reset signal at power on. * Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V (TYP.)), and generates internal reset signal when VDD < VPOC. * Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V (TYP.)), and releases internal reset signal when VDD VPOC. Cautions 1. If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. 2. Use these products in the following voltage range because the detection voltage (VPOC) of the POC circuit is the supply voltage range. Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT) or low-voltage-detection (LVI) circuit. RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI. For details of RESF, see CHAPTER 14 RESET FUNCTION. User's Manual U16898EJ6V0UD 251 CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 15-1. Figure 15-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal - Reference voltage source 15.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC = 2.1 V (TYP.)) are compared, and an internal reset signal is generated when VDD < VPOC, and an internal reset is released when VDD VPOC. Figure 15-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit Supply voltage (VDD) POC detection voltage (VPOC = 2.1 V (TYP.)) Time Internal reset signal 252 User's Manual U16898EJ6V0UD CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. <Action> After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. Figure 15-3. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Reset ; Check reset sourceNote 2 Initialization of ports Setting WDT Initialization processing <1> Power-on-clear ; fXP = High-speed internal oscillation clock (8.4 MHz (MAX.))/22 (default value) Setting 8-bit timer H1 (50 ms is measured) Source: fXP (2.1 MHz (MAX.))/212, 51 ms when the compare value is 25 Timer starts (TMHE1 = 1) Clears WDT Note 1 No 50 ms has passed? (TMIFH1 = 1?) Yes Initialization processing <2> Notes 1. 2. ; Setting the division ratio of the system clock, timer, A/D converter, etc. If reset is generated again during this period, initialization processing <2> is not started. A flowchart is shown on the next page. User's Manual U16898EJ6V0UD 253 CHAPTER 15 POWER-ON-CLEAR CIRCUIT Figure 15-3. Example of Software Processing After Release of Reset (2/2) * Checking reset cause Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on-clear/external reset generated 254 User's Manual U16898EJ6V0UD CHAPTER 16 LOW-VOLTAGE DETECTOR 16.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. * Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or internal reset signal when VDD < VLVI. * Detection levels (ten levels) of supply voltage can be changed by software. * Interrupt or reset function can be selected by software. * Operable in STOP mode. When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, refer to CHAPTER 14 RESET FUNCTION. 16.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 16-1. Figure 16-1. Block Diagram of Low-Voltage Detector Low-voltage detection level selector VDD VDD N-ch Selector Internal reset signal + - INTLVI Reference voltage source 4 LVION LVIMD LVIS3 LVIS2 LVIS1 LVIS0 Low-voltage detection level select register (LVIS) LVIF Low-voltage detect register (LVIM) Internal bus User's Manual U16898EJ6V0UD 255 CHAPTER 16 LOW-VOLTAGE DETECTOR 16.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. * Low-voltage detect register (LVIM) * Low-voltage detection level select register (LVIS) (1) Low-voltage detect register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00HNote 1. Figure 16-2. Format of Low-Voltage Detect Register (LVIM) After reset: 00HNote 1 Address: FF50H R/WNote 2 Symbol <7> 6 5 4 3 2 <1> <0> LVIM LVION 0 0 0 0 0 LVIMD LVIF Note 3 LVION Enabling low-voltage detection operation 0 Disable operation 1 Enable operation LVIMD Low-voltage detection operation mode selection 0 Generate interrupt signal when supply voltage (VDD) < detection voltage (VLVI) 1 Generate internal reset signal when supply voltage (VDD) < detection voltage (VLVI) Note 4 LVIF Low-voltage detection flag 0 Supply voltage (VDD) detection voltage (VLVI), or when operation is disabled 1 Supply voltage (VDD) < detection voltage (VLVI) Notes 1. For a reset by LVI, the value of LVIM is not initialized. 2. Bit 0 is a read-only bit. 3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is confirmed at LVIF. 4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and LVIMD = 0. Cautions 1. To stop LVI, follow either of the procedures below. * When using 8-bit manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. 2. Be sure to set bits 2 to 6 to 0. 256 User's Manual U16898EJ6V0UD CHAPTER 16 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. Reset input clears this register to 00HNote. Figure 16-3. Format of Low-Voltage Detection Level Select Register (LVIS) Address: FF51H, After reset: 00H Note R/W Symbol 7 6 5 4 3 2 1 0 LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0 LVIS3 LVIS2 LVIS1 LVIS0 0 0 0 0 VLVI0 (4.3 V 0.2 V) 0 0 0 1 VLVI1 (4.1 V 0.2 V) 0 0 1 0 VLVI2 (3.9 V 0.2 V) 0 0 1 1 VLVI3 (3.7 V 0.2 V) 0 1 0 0 VLVI4 (3.5 V 0.2 V) 0 1 0 1 VLVI5 (3.3 V 0.15 V) 0 1 1 0 VLVI6 (3.1 V 0.15 V) 0 1 1 1 VLVI7 (2.85 V 0.15 V) 1 0 0 0 VLVI8 (2.6 V 0.1 V) 1 0 0 1 VLVI9 (2.35 V 0.1 V) Other than above Detection level Setting prohibited Note For a reset by LVI, the value of LVIM is not initialized. Cautions 1. Bits 4 to 7 must be set to 0. 2. If values other than same values are written during LVI operation, the value becomes undefined at the very moment it is written, and thus be sure to stop LVI (bit 7 of LVIM register (LVION) = 0) before writing. User's Manual U16898EJ6V0UD 257 CHAPTER 16 LOW-VOLTAGE DETECTOR 16.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. * Used as reset Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when VDD < VLVI, and releases internal reset when VDD VLVI. * Used as interrupt Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI) when VDD < VLVI. The operation is set as follows. (1) When used as reset * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to instigate a wait of at least 0.2 ms. <5> Wait until "supply voltage (VDD) detection voltage (VLVI)" at bit 0 (LVIF) of LVIM is confirmed. <6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)). Figure 16-4 shows the timing of generating the internal reset signal of the low-voltage detector. Numbers <1> to <6> in this figure correspond to <1> to <6> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <3>. 2. If supply voltage (VDD) detection voltage (VLVI) when LVIM is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed. 258 * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and LVION to 0 in that order. User's Manual U16898EJ6V0UD CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) <2> LVIMK flag (set by software) H Time <1> Note 1 LVION flag (set by software) Not cleared Not cleared <3> Clear <4> 0.2 ms or longer LVIF flag <5> Clear Note 2 LVIMD flag (set by software) Not cleared Not cleared <6> Clear LVIRF flagNote 3 LVI reset signal Cleared by software Cleared by software POC reset signal Internal reset signal Notes 1. The LVIMK flag is set to "1" by reset input. 2. The LVIF flag may be set (1). 3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 14 RESET FUNCTION. Remark <1> to <6> in Figure 16-4 above correspond to <1> to <6> in the description of "when starting operation" in 16.4 (1) When used as reset. User's Manual U16898EJ6V0UD 259 CHAPTER 16 LOW-VOLTAGE DETECTOR (2) When used as interrupt * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to instigate a wait of at least 0.2 ms. <5> Wait until "supply voltage (VDD) detection voltage (VLVI)" at bit 0 (LVIF) of LVIM is confirmed. <6> Clear the interrupt request flag of LVI (LVIIF) to 0. <7> Release the interrupt mask flag of LVI (LVIMK). <8> Execute the EI instruction (when vector interrupts are used). Figure 16-5 shows the timing of generating the interrupt signal of the low-voltage detector. Numbers <1> to <7> in this figure correspond to <1> to <7> above. * When stopping operation Either of the following procedures must be executed. 260 * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. User's Manual U16898EJ6V0UD CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) Time <2> LVIMK flag (set by software) <1> Note 1 LVION flag (set by software) <7> Cleared by software <3> <4> 0.2 ms or longer LVIF flag <5> Note 2 INTLVI Note 2 LVIIF flag Note 2 <6> Cleared by software Internal reset signal Notes 1. 2. Remark The LVIMK flag is set to "1" by reset signal generation. An interrupt request signal (INTLVI) may be generated, and the LVIF and LVIIF flags may be set to 1. <1> to <7> in Figure 16-5 above correspond to <1> to <7> in the description of "when starting operation" in 16.4 (2) When used as interrupt. User's Manual U16898EJ6V0UD 261 CHAPTER 16 LOW-VOLTAGE DETECTOR 16.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. <1> When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. <2> When used as interrupt Interrupt requests may be frequently generated. Take (b) of action (2) below. In this system, take the following actions. <Action> (1) When used as reset After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports (see Figure 16-6). (2) When used as interrupt (a) Perform the processingNote for low voltage detection. Check that "supply voltage (VDD) detection voltage (VLVI)" in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of interrupt request flag register 0 (IF0) to 0. (b) In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for the supply voltage fluctuation period, check that "supply voltage (VDD) detection voltage (VLVI)" using the LVIF flag and clear LVIIF flag to 0. Note For low voltage detection processing, the CPU clock speed is switched to slow speed and the A/D converter is stopped, etc. 262 User's Manual U16898EJ6V0UD CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-6. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset ; Check reset sourceNote Initialization of ports Setting WDT Initialization processing <1> LVI reset ; The detection level is set with LVIS. The low-voltage detector is operated (LVION = 1) Setting LVI ; fXP = High-speed internal oscillation clock (8.4 MHz (MAX.))/22 (default value) Setting 8-bit timer H1 (50 ms is measured) Source: fXP (2.1 MHz (MAX.))/212, 51 ms when the compare value is 25 Timer starts (TMHE1 = 1) Clears WDT Detection voltage or more (LVIF = 0 ?) Yes No LVIF = 0 Restarting the timer H1 (TMHE1 = 0 TMHE1 = 1) No ; Clear low-voltage detection flag. ; Clear timer counter and timer starts. 50 ms has passed? (TMIFH1 = 1?) Yes Initialization processing <2> Note ; Setting the division ratio of the system clock, timer, A/D converter, etc. A flowchart is shown on the next page. User's Manual U16898EJ6V0UD 263 CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-6. Example of Software Processing After Release of Reset (2/2) * Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector 264 User's Manual U16898EJ6V0UD CHAPTER 17 OPTION BYTE 17.1 Functions of Option Byte The address 0080H of the flash memory of the 78K0S/KA1+ is an option byte area. When power is supplied or when starting after a reset, the option byte is automatically referenced, and settings for the specified functions are performed. When using the product, be sure to set the following functions by using the option byte. (1) Selection of system clock source * High-speed internal oscillation clock * Crystal/ceramic oscillation clock * External clock input (2) Low-speed internal oscillation clock oscillation * Cannot be stopped. * Can be stopped by software. (3) Control of RESET pin * Used as RESET pin * RESET pin is used as an input port pin (P34) (refer to 17.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34)). (4) Oscillation stabilization time on power application or after reset release * 210/fX * 212/fX 15 * 2 /fX * 217/fX Figure 17-1. Positioning of Option Byte Flash memory 0080H Option byte 1 0000H DEF DEF OSTS1 OSTS0 User's Manual U16898EJ6V0UD 1 RMCE OSCSEL1 OSCSEL0 LIOCP 265 CHAPTER 17 OPTION BYTE 17.2 Format of Option Byte Format of option bytes is shown below. Figure 17-2. Format of Option Byte (1/2) Address: 0080H 7 6 5 4 3 2 1 0 1 DEFOSTS1 DEFOSTS0 1 RMCE OSCSEL1 OSCSEL0 LIOCP DEFOSTS1 DEFOSTS0 Oscillation stabilization time on power application or after reset release 0 0 2 /fx (102.4 s) 0 1 2 /fx (409.6 s) 1 0 2 /fx (3.27 ms) 1 1 2 /fx (13.1 ms) 10 12 15 17 Caution The setting of this option is valid only when the crystal/ceramic oscillation clock is selected as the system clock source. No wait time elapses if the high-speed internal oscillation clock or external clock input is selected as the system clock source. RMCE Control of RESET pin 1 RESET pin is used as is. 0 RESET pin is used as input port pin (P34). Caution Because the option byte is referenced after reset release, if a low level is input to the RESET pin before the option byte is referenced, then the reset state is not released. Also, when setting 0 to RMCE, connect the pull-up resistor. OSCSEL1 OSCSEL0 Selection of system clock source 0 0 Crystal/ceramic oscillation clock 0 1 External clock input 1 x High-speed internal oscillation clock Caution Because the X1 and X2 pins are also used as the P121 and P122 pins, the conditions under which the X1 and X2 pins can be used differ depending on the selected system clock source. (1) Crystal/ceramic oscillation clock is selected The X1 and X2 pins cannot be used as I/O port pins because they are used as clock input pins. (2) External clock input is selected Because the X1 pin is used as an external clock input pin, P121 cannot be used as an I/O port pin. (3) High-speed internal oscillation clock is selected P121 and P122 can be used as I/O port pins. Remark 266 x : don't care User's Manual U16898EJ6V0UD CHAPTER 17 OPTION BYTE Figure 17-2. Format of Option Byte (2/2) LIOCP Low-speed internal oscillates 1 Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit) 0 Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit) Cautions 1. If it is selected that low-speed internal oscillator cannot be stopped, the count clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation clock. 2. If it is selected that low-speed internal oscillator can be stopped by software, supply of the count clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of bit 0 (LSRSTOP) of the low-speed internal oscillation mode register (LSRCM). Similarly, clock supply is also stopped when a clock other than the low-speed internal oscillation clock is selected as a count clock to WDT. While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can be supplied to the 8-bit timer H1 even in the STOP mode. Remarks 1. ( ): fX = 10 MHz 2. For the oscillation stabilization time of the resonator, refer to the characteristics of the resonator to be used. 3. An example of software coding for setting the option bytes is shown below. OPB OSEG AT 0080H DB 10010001B ; Set to option byte ; Low-speed internal oscillator cannot be stopped ; The system clock is a crystal or ceramic resonator. ; The RESET pin is used as an input-only port pin (P34). ; Minimum oscillation stabilization time (210/fX) 4. For details on the timing at which the option byte is referenced, see CHAPTER 14 RESET FUNCTION. 17.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34) Be aware of the following when re-erasing/-writing (by on-board programming using a dedicated flash memory programmer) an already-written device which has been set as "The RESET pin is used as an input-only port pin (P34)" by the option byte function. Before supplying power to the target system, connect a dedicated flash memory programmer and turn its power on. If the power is supplied to the target system beforehand, the flash memory programming mode cannot be switched to. User's Manual U16898EJ6V0UD 267 CHAPTER 18 FLASH MEMORY 18.1 Features The internal flash memory of the 78K0S/KA1+ has the following features. { Erase/write even without preparing a separate dedicated power supply { Capacity: 2 KB/4 KB/8 KB * Erase unit: 1 block (256 bytes) * Write unit: 1 block (at on-board/off-board programming time), 1 byte (at self programming time) { Rewriting method * Rewriting by communication with dedicated flash memory programmer (on-board/off-board programming) * Rewriting flash memory by user program (self programming) { Supports rewriting of the flash memory at on-board/off-board programming time through security functions { Supports security functions in block units at self programming time through protect bytes 268 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY 18.2 Memory Configuration The 2/4/8 KB internal flash memory area is divided into 8/16/32 blocks and can be programmed/erased in block units. All the blocks can also be erased at once, by using a dedicated flash memory programmer. <R> Figure 18-1. Flash Memory Mapping * PD78F9224 1FFFH FFFFH Block 31 (256 bytes) Special function resister (256 byte) Block 30 (256 bytes) FF00H FEFFH * PD78F9222 Internal high-speed RAM (128/256 byte) 1F00H 1EFFH 1E00H 1DFFH 1000H 0FFFH Block 15 (256 bytes) Block 15 (256 bytes) Block 14 (256 bytes) Block 14 (256 bytes) 0F00H 0EFFH 0E00H 0DFFH * PD78F9221 0800H 07FFH Use prohibited Block 7 (256 bytes) Block 7 (256 bytes) Block 7 (256 bytes) Block 6 (256 bytes) Block 6 (256 bytes) Block 6 (256 bytes) Block 5 (256 bytes) Flash memory (2/4/8 KB) Block 5 (256 bytes) Block 4 (256 bytes) Block 4 (256 bytes) Block 4 (256 bytes) Block 3 (256 bytes) Block 3 (256 bytes) Block 3 (256 bytes) Block 2 (256 bytes) Block 1 (256 bytes) 0000H Block 5 (256 bytes) Block 2 (256 bytes) 0700H 06FFH 0600H 05FFH 0500H 04FFH 0400H 03FFH 0300H 02FFH Block 2 (256 bytes) 0200H 01FFH Block 1 (256 bytes) Block 1 (256 bytes) 0100H 00FFH Block 0 (256 bytes) Block 0 (256 bytes) Block 0 (256 bytes) 2 KB 4 KB 8 KB 0000H User's Manual U16898EJ6V0UD 269 CHAPTER 18 FLASH MEMORY 18.3 Functional Outline The internal flash memory of the 78K0S/KA1+ can be rewritten by using the rewrite function of the dedicated flash memory programmer, regardless of whether the 78K0S/KA1+ has already been mounted on the target system or not (on-board/off-board programming). The function for rewriting a program with the user program (self programming), which is ideal for an application when it is assumed that the program is changed after production/shipment of the target system, is provided. Refer to Table 18-1 for the flash memory writing control function. In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also supported, so that the program cannot be changed by an unauthorized person. Refer to 18.7.3 Security settings for details on the security function. Table 18-1. Rewrite Method Rewrite Method On-board programming Off-board programming Functional Outline Operation Mode Flash memory can be rewritten after the device is mounted on the Flash memory target system, by using a dedicated flash memory programmer. programming mode Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash memory programmer and a dedicated program adapter board (FA series). Self programming Flash memory can be rewritten by executing a user program that has Self programming mode been written to the flash memory in advance by means of on-board/offboard programming. Remarks 1. The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. 2. Refer to the following sections for details on the flash memory writing control function. * 18.7 On-Board and Off-Board Flash Memory Programming * 18.8 Flash Memory Programming by Self Programming 270 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY 18.4 Writing with Flash Memory Programmer The following two types of dedicated flash memory programmers can be used for writing data to the internal flash memory of the 78K0S/KA1+. * FlashPro5 (PG-FP5, FL-PR5) <R> * QB-MINI2 Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0S/KA1+ has been mounted on the target system. The connectors that connect the dedicated flash memory programmer and the test pad must be mounted on the target system. The test pad is required only when writing data with the crystal/ceramic resonator mounted (refer to Figure 18-4 for mounting of the test pad). (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0S/KA1+ is mounted on the target system. <R> Remark The FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd. User's Manual U16898EJ6V0UD 271 CHAPTER 18 FLASH MEMORY 18.5 Programming Environment The environment required for writing a program to the flash memory is illustrated below. <R> Figure 18-2. Environment for Writing Program to Flash Memory (FlashPro5/QB-MINI2) VDD FlashPro5 Host machine <R> Remark QB-MINI2 VSS RS-232-C RESET USB SO/TxD Dedicated flash memory programmer CLK 78K0S/KA1+ For QB-MINI2, the name of the SO/TxD signal is DATA. A host machine that controls the dedicated flash memory programmer is necessary. When using the PG-FP5 or FL-PR5, data can be written with just the dedicated flash memory programmer after downloading the program from the host machine. UART is used for manipulation such as writing and erasing when interfacing between the dedicated flash memory programmer and the 78K0S/KA1+. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. Download the latest firmware for flash memory programmer, programming GUI, and parameter file from the download site for development tools (http://www.necel.com/micro/en/ods/). 272 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY <R> Table 18-2. Wiring Between 78K0S/KA1+ and FlashPro5/QB-MINI2 FlashPro5/QB-MINI2 Connection Pin Pin Name I/O 78K0S/KA1+ Connection Pin Pin Function Pin Name Pin No. CLK Output Clock to 78K0S/KA1+ X1/P121 2 SO/TxD Output Receive signal/on-board mode signal X2/P122 3 /RESET Output Reset signal RESET/P34 6 VDD - VDD voltage generation/voltage monitor VDD 5 GND - Ground VSS 1 <R> Figure 18-3. Wiring diagram with FlashPro5/QB-MINI2 FlashPro5/QB-MINI2 signal name CLK SO/TxD /RESET VDD GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 78K0S/KA1+ <R> Remark For QB-MINI2, the name of the SO/TxD signal is DATA. User's Manual U16898EJ6V0UD 273 CHAPTER 18 FLASH MEMORY 18.6 Pin Connection on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be processed as described below. The state of the pins in the self programming mode is the same as that in the HALT mode. 18.6.1 X1 and X2 pins The X1 and X2 pins are used as the serial interface of flash memory programming. Therefore, if the X1 and X2 pins are connected to an external device, a signal conflict occurs. To prevent the conflict of signals, isolate the connection with the external device. Similarly, when a capacitor is connected to the X1 and X2 pins, the waveform during communication is changed, and thus communication may be disabled depending on the capacitor capacitance. Make sure to isolate the connection with the capacitor during flash programming. Perform the following processing (1) and (2) when on-board programming is performed with the resonator mounted, when it is difficult to isolate the resonator, while a crystal or ceramic resonator is selected as the system clock. (1) Mount the minimum-possible test pads between the device and the resonator, and connect the programmer via the test pad. Keep the wiring as short as possible (refer to Figure 18-4 and Table 18-3). (2) Set the oscillation frequency of the communication clock for writing using the programming GUI of the dedicated flash memory programmer. Research the series/parallel resonant and antiresonant frequencies of the resonator used, and set the oscillation frequency so that it is outside the range of the resonant frequency 10% (refer to Figure 18-5 and Table 18-4). Figure 18-4. Example of Mounting Test Pads Test pad VSS X1 X2 Table 18-3. Clock to Be Used and Mounting of Test Pads Clock to Be Used High-speed internal oscillation clock Mounting of Test Pads Not required External clock 274 Crystal/ceramic oscillation Before resonator is mounted clock After resonator is mounted User's Manual U16898EJ6V0UD Required CHAPTER 18 FLASH MEMORY Figure 18-5. PG-FP5 Programming GUI Setting Example Set oscillation frequency Click (Standard tab in Device setup window) (Main window) Table 18-4. Oscillation Frequency and PG-FP5 Programming GUI Setting Value Example Oscillation Frequency PG-FP5 Programming GUI Setting Value Example (Communication Frequency) 2 MHz fX < 4 MHz 8 MHz 4 MHz fX < 8 MHz 9 MHz 8 MHz fX < 9 MHz 10 MHz 9 MHz fX 10 MHz 8 MHz Caution The above values are recommended values. Depending on the usage environment these values may change, so set them after having performed sufficient evaluations. 18.6.2 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash memory programmer. User's Manual U16898EJ6V0UD 275 CHAPTER 18 FLASH MEMORY Figure 18-6. Signal Collision (RESET Pin) 78K0S/KA1+ Signal collision RESET Dedicated flash memory programmer connection signal Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash memory programmer. Therefore, isolate the signal of the reset signal generator. 18.6.3 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to VDD or VSS via a resistor. The state of the pins in the self programming mode is the same as that in the HALT mode. 18.6.4 Power supply Connect the VDD pin to VDD of the flash memory programmer, and the VSS pin to VSS of the flash memory programmer. Supply AVREF with the same power supply as that in the normal operation mode. 276 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY 18.7 On-Board and Off-Board Flash Memory Programming 18.7.1 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0S/KA1+ in the flash memory programming mode. When the 78K0S/KA1+ is connected to the flash memory programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in the flash memory programming mode. Change the mode by using a jumper when writing the flash memory on-board. 18.7.2 Communication commands The dedicated flash memory programmer controls the 78K0S/KA1+ by using commands. The signals sent from the flash memory programmer to the 78K0S/KA1+ are called communication commands, and the commands sent from the 78K0S/KA1+ to the dedicated flash memory programmer are called response. <R> Figure 18-7. Communication Commands FlashPro5 QB-MINI2 Communication Command Response 78K0S/KA1+ Dedicated flash memory programmer Communication commands are listed in the table below. All these communication commands are issued from the flash memory programmer and the 78K0S/KA1+ performs processing corresponding to the respective communication commands. Table 18-5. Communication Commands Classification Command Name Function Erase Batch erase (chip erase) command Erases the contents of the entire memory Block erase command Erases the contents of the memory of the specified block Write Write command Writes to the specified address range and executes a verify check of the contents. Checksum Reads the checksum of the specified address range and Checksum command compares with the written data. Blank check Blank check command Confirms the erasure status of the entire memory. Security Security setting command Prohibits batch erase (chip erase) command, block erase command, and write command to prevent operation by third parties. The 78K0S/KA1+ returns a response for the communication command issued by the dedicated flash memory programmer. The response names sent from the 78K0S/KA1+ are listed below. User's Manual U16898EJ6V0UD 277 CHAPTER 18 FLASH MEMORY Table 18-6. Response Name Response Name Function ACK Acknowledges command/data. NAK Acknowledges illegal command/data. 18.7.3 Security settings The operations shown below can be prohibited using the security setting command. * Batch erase (chip erase) is prohibited Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is prohibited. Once execution of the batch erase (chip erase) command is prohibited, all the prohibition settings can no longer be cancelled. Caution After the security setting of the batch erase is set, erasure cannot be performed for the device. In addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written because the erase command is disabled. * Block erase is prohibited Execution of the block erase command in the flash memory is prohibited. This prohibition setting can be cancelled using the batch erase (chip erase) command. * Write is prohibited Execution of the write and block erase commands for entire blocks in the flash memory is prohibited. This prohibition setting can be cancelled using the batch erase (chip erase) command. Remark The security setting is valid when the programming mode is set next time. The batch erase (chip erase), block erase, and write commands are enabled by the default setting when the flash memory is shipped. The above security settings are possible only for on-board/off-board programming. Each security setting can be used in combination. Table 18-7 shows the relationship between the erase and write commands when the 78K0S/KA1+ security function is enabled. Table 18-7. Relationship Between Commands When Security Function Is Enabled Command Security When batch erase (chip erase) security Batch Erase (Chip Block Erase Erase) Command Command Disabled Disabled Write Command Enabled Note operation is enabled When block erase security operation is Enabled Enabled enabled When write security operation is enabled Disabled Note Since the erase command is disabled, data different from that which has already been written to the flash memory cannot be written. 278 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY Table 18-8 shows the relationship between the security setting and the operation in each programming mode. Table 18-8. Relationship Between Security Setting and Operation In Each Programming Mode Programming Mode On-Board/Off-Board Programming Security Setting Security Setting Batch erase (chip erase) Possible Self Programming Security Operation Security Setting Note 1 Valid Security Operation Note 2 Impossible Invalid Block erase Write Notes 1. Execution of each command is prohibited by the security setting. 2. Execution of self programming command is possible regardless of the security setting. 18.8 Flash Memory Programming by Self Programming The 78K0S/KA1+ supports a self programming function that can be used to rewrite the flash memory via a user program, making it possible to upgrade programs in the field. Caution Self programming processing must be included in the program before performing self programming. Remarks 1. For usage of self programming, refer to the examples from 18.8.4. onward. 2. To use the internal flash memory of the 78K0S/KA1+ as the external EEPROMTM for storing data, refer to 78K0S/Kx1+ EEPROM Emulation Application Note (U17379E). 18.8.1 Outline of self programming To execute self programming, shift the mode from the normal operation of the user program (normal mode) to the self programming mode. Write/erase processing for the flash memory, which has been set to the register in advance, is performed by executing the HALT instruction during self programming mode. The HALT state is automatically released when processing is completed. To shift to the self programming mode, execute a specific sequence for a specific register. Refer to 18.8.4 Example of shifting normal mode to self programming mode for details. Remark Data written by self programming can be referenced with the MOV instruction. Table 18-9. Self Programming Mode Mode User Program Execution Execution of Write/erase for Flash Memory with HALT Instruction Normal mode Self programming mode - Enabled Enabled Note Enabled Note Maskable interrupt servicing is disabled during self programming mode. Figure 18-8 shows a block diagram for self programming, Figure 18-9 shows the self programming state transition diagram, Table 18-10 lists the commands for controlling self programming. User's Manual U16898EJ6V0UD 279 280 Figure 18-8. Block Diagram of Self Programming Internal bus Flash programming command register (FLCMD) Protect byte PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 FLCMD2 FLCMD1 FLCMD0 Flash programming mode control register (FLPMC) Self programming mode setting sequencer Flash protect command register (PFCMD) Self programming mode setting register 5 3 HALT signal User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY Self programming command execution Flash memory controller Increment circuit Erase circuit Write circuit Verify circuit HALT release signal Flash address pointer H (FLAPH) Flash memory Match Flash address pointer L (FLAPL) Unmatch Match Flash address pointer H compare register (FLAPHC) Flash address pointer L compare register (FLAPLC) Flash write buffer register (FLW) WEPRERR VCERR FPRERR Flash status register (PFS) Internal bus CHAPTER 18 FLASH MEMORY Figure 18-9. Self Programming State Transition Diagram User program Operation setting Normal mode Specific sequence Operation setting Self programming mode Self programming command completion/error Register for self programming Self programming command execution by HALT instruction Flash memory control block (hardware) Self programming command under execution Operation reference Flash memory Table 18-10. Self Programming Controlling Commands Command Name Function Time Taken from HALT Instruction Execution to Command Execution End Internal verify 1 This command is used to check if data has been Internal verify for 1 block (internal verify correctly written to the flash memory. It is used to command executed once): 6.8 ms check whether data has been written to an entire block. Internal verify 2 This command is used to check if data has been Internal verify of 1 byte: 27 s correctly written to the flash memory. It is used to check whether data has been written to multiple addresses in the same block. Block erasure Note This command is used to erase a specified block. 8.5 ms Specify the block number before execution. Block blank check This command is used to check if data in a specified 480 s block has been erased. Specify the block number, then execute this command. This command is used to write 1-byte data to the Byte write 150 s specified address in the flash memory. Specify the write address and write data, then execute this command. Note Set the number of retrials larger than the block erasure time divided by the time (8.5 ms) for one erase, in accordance with the time (MAX. value) required for flash memory block erasures. Remark The internal verify 1 command can be executed by specifying an address in the same block, but internal verify 2 is recommended if data is written to multiple addresses in the same block. User's Manual U16898EJ6V0UD 281 CHAPTER 18 FLASH MEMORY 18.8.2 Cautions on self programming function * No instructions can be executed while a self programming command is being executed. Therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming. Refer to Table 18-10 for the time taken for the execution of self programming. * Interrupts that occur during self programming can be acknowledged after self programming mode ends. To avoid this operation, disable interrupt servicing (by setting MK0 and MK1 to FFH, and executing the DI instruction) before the mode is shifted from the normal mode to the self programming mode by a specific sequence. * RAM is not used while a self programming command is being executed. * If the supply voltage drops or the reset signal is input while the flash memory is being written or erased, writing/erasing is not guaranteed. * The value of the blank data set during block erasure is FFH. * Set the CPU clock beforehand so that it is 1 MHz or higher during self programming. * Execute self programming after executing the NOP and HALT instructions immediately after executing a specific sequence to set self programming mode. At this time, the HALT instruction is automatically released after 10 s (MAX.) + 2 CPU clocks (fCPU). * If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT instructions immediately after executing a specific sequence to set self programming mode, wait for 8 s after releasing the HALT status, and then execute self programming. * Check FPRERR using a 1-bit memory manipulation instruction. * The state of the pins in self programming mode is the same as that in HALT mode. * Since the security function set via on-board/off-board programming is disabled in self programming mode, the self programming command can be executed regardless of the security function setting. To disable write or erase processing during self programming, set the protect byte. * Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register (FLAPHC) to 0 before executing the self programming command. If the self programming command is executed with these bits set to 1, the device may malfunction. * Clear the value of the FLCMD register to 00H immediately before setting to self programming mode and normal mode. 18.8.3 Registers used for self programming function The following registers are used for the self programming function. * Flash programming mode control register (FLPMC) * Flash protect command register (PFCMD) * Flash status register (PFS) * Flash programming command register (FLCMD) * Flash address pointers H and L (FLAPH and FLAPL) * Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and FLAPLC) * Flash write buffer register (FLW) The 78K0S/KA1+ has an area called a protect byte at address 0081H of the flash memory. (1) Flash programming mode control register (FLPMC) This register is used to set the operation mode when data is written to the flash memory in the self programming mode, and to read the set value of the protect byte. Data can be written to FLPMC only in a specific sequence (refer to 18.8.3 (2) Flash protect command register (PFCMD)) so that the application system does not stop by accident because of malfunctions due to noise or program hang-ups. 282 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY This register is set with an 8-bit memory manipulation instruction. Reset signal generation makes the contents of this register undefined. Figure 18-10. Format of Flash Programming Mode Control Register (FLPMC) After reset: UndefinedNote 1 Address: FFA2H Symbol 7 FLPMC 0 6 4 3 2 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 FLSPM 0 5 R/WNote 2 1 0 0 FLSPM Selection of operation mode during self programming mode Normal mode This is the normal operation status. Executing the HALT instruction sets standby status. 1 Self programming mode Self programming commands can be executed by executing the specific sequence to change modes while in normal mode. Set a command, an address, and data to be written, then execute the HALT instruction to execute self programming. PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 The set value of the protect byte is read to these bits. Notes 1. Bit 0 (FLSPM) is cleared to 0 when reset is released. The set value of the protect byte is read to bits 2 to 6 (PRSELF0 to PRSELF4) after reset is released. 2. Bits 2 to 6 (PRSELF0 to PRSELF4) are read-only. Cautions 1. For cautions in case of setting the self programming mode, refer to 18.8.2 Cautions on self programming function. 2. Set the CPU clock beforehand so that it is 1 MHz or higher during self programming. 3. Execute self programming after executing the NOP and HALT instructions immediately after executing a specific sequence to set self programming mode. At this time, the HALT instruction is automatically released after 10 s (MAX.) + 2 CPU clocks (fCPU). 4. If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT instructions immediately after executing a specific sequence to set self programming mode, wait for 8 s after releasing the HALT status, and then execute self programming. 5. Clear the value of the FLCMD register to 00H immediately before setting to self programming mode and normal mode. (2) Flash protect command register (PFCMD) If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop inadvertently. Writing FLPMC is enabled only when a write operation is performed in the following specific sequence. <1> Write a specific value to PFCMD (A5H) <2> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is invalid) User's Manual U16898EJ6V0UD 283 CHAPTER 18 FLASH MEMORY <3> Write the inverted value of the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is invalid) <4> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is valid) Caution Interrupt servicing cannot be executed in self programming mode. Disable interrupt servicing (by executing the DI instruction while MK0 and MK1 = FFH) between the points before executing the specific sequence that sets self programming mode and after executing the specific sequence that changes the mode to the normal mode. This rewrites the value of the register, so that the register cannot be written illegally. Occurrence of an illegal write operation can be checked by bit 0 (FPRERR) of the flash status register (PFS). Check FPRERR using a 1-bit memory manipulation instruction. A5H must be written to PFCMD each time the value of FLPMC is changed. PFCMD can be set with an 8-bit memory manipulation instruction. Reset signal generation makes PFCMD undefined. Figure 18-11. Format of Flash Protect Command Register (PFCMD) Address: FFA0H After reset: Undefined W Symbol 7 6 5 4 3 2 1 0 PFCMD REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0 (3) Flash status register (PFS) If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1. When FPRERR is 1, it can be cleared to 0 by writing 0 to it. Errors that may occur during self programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. VCERR or WEPRERR can be cleared by writing 0 to them. All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly. PFS can be set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears PFS to 00H. Caution Check FPRERR using a 1-bit memory manipulation instruction. Figure 18-12. Format of Flash Status Register (PFS) Address: FFA1H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PFS 0 0 0 0 0 WEPRERR VCERR FPRERR 1. Operating conditions of FPRERR flag <Setting conditions> * If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to write a specific value (A5H) to FLPMC * If the first store instruction operation after <1> is on a peripheral register other than FLPMC * If the first store instruction operation after <2> is on a peripheral register other than FLPMC 284 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY * If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction after <2> * If the first store instruction operation after <3> is on a peripheral register other than FLPMC * If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction after <3> Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command register (PFCMD). <Reset conditions> * If 0 is written to the FPRERR flag * If the reset signal is generated 2. Operating conditions of VCERR flag <Setting conditions> * Erasure verification error * Internal writing verification error If VCERR is set, it means that the flash memory has not been erased or written correctly. Erase or write the memory again in the specified procedure. Remark The VCERR flag may also be set if an erase or write protect error occurs. <Reset conditions> * When 0 is written to the VCERR flag * When the reset signal is generated 3. Operating conditions of WEPRERR flag <Setting conditions> * If the area specified by the protect byte to be protected from erasing or writing is specified by the flash address pointer H (FLAPH) and a command is executed to this area * If 1 is written to a bit that has not been erased (a bit for which the data is 0). <Reset conditions> * When 0 is written to the WEPRERR flag * When the reset signal is generated (4) Flash programming command register (FLCMD) This register is used to specify whether the flash memory is erased, written, or verified in the self programming mode. This register is set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. User's Manual U16898EJ6V0UD 285 CHAPTER 18 FLASH MEMORY Figure 18-13. Format of Flash Programming Command Register (FLCMD) Address: FFA3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 FLCMD 0 0 0 0 0 FLCMD2 FLCMD1 FLCMD0 FLCMD2 FLCMD1 FLCMD0 0 0 1 Command Name Internal verify 1 Function This command is used to check if data has been correctly written to the flash memory. It is used to check whether data has been written to an entire block. If an error occurs, bit 1 (VCERR) or bit 2 (WEPRERR) of the flash status register (PFS) is set to 1. 0 1 0 Internal verify 2 This command is used to check if data has been correctly written to the flash memory. It is used to check whether data has been written to multiple addresses in the same block. If an error occurs, bit 1 (VCERR) or bit 2 (WEPRERR) of the flash status register (PFS) is set to 1. 0 1 1 Block erase This command is used to erase specified block. It is used both in the on-board mode and self programming mode. 1 0 0 Block blank check This command is used to check if the 1 0 1 Byte write This command is used to write 1-byte specified block has been erased. data to the specified address in the flash memory. Specify the write address and write data, then execute this command. If 1 is written to a bit that has not been erased (a bit for which the data is 0), then bit 2 (WEPRERR) of the flash status register (PFS) becomes 1. Note Other than above Setting prohibited Note If any command other than those above is executed, command execution may immediately be terminated, and bits 1 and 2 (WEPRERR and VCERR) of the flash status register (PFS) may be set to 1. (5) Flash address pointers H and L (FLAPH and FLAPL) These registers are used to specify the start address of the flash memory when the memory is erased, written, or verified in the self programming mode. FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of FLAPHC and FLAPLC when the programming command is not executed. When the programming command is executed, therefore, set the value again. These registers are set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation makes these registers undefined. 286 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY Figure 18-14. Format of Flash Address Pointer H/L (FLAPH/FLAPL) Address: FFA4H, FFA5H After reset: Undefined R/W FLAPH (FFA5H) 0 0 Caution 0 0 FLAPL (FFA4H) FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register (FLAPHC) to 0 before executing the self programming command. If the self programming command is executed with these bits set to 1, the device may malfunction. (6) Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and FLAPLC) These registers are used to specify the address range in which the internal sequencer operates when the flash memory is verified in the self programming mode. Set FLAPHC to the same value as that of FLAPH. Set the last address of the range in which verification is to be executed to FLAPLC. These registers are set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 18-15. Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC) Address: FFA6H, FFA7H After reset: 00H R/W FLAPHC (FFA6H) 0 0 0 0 FLAPLC (FFA7H) FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Cautions 1. Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register (FLAPHC) to 0 before executing the self programming command. If the self programming command is executed with these bits set to 1, the device may malfunction. 2. Set the number of the block subject to a block erase, verify, or blank check (same value as FLAPH) to FLAPHC. 3. Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank check is performed. User's Manual U16898EJ6V0UD 287 CHAPTER 18 FLASH MEMORY (7) Flash write buffer register (FLW) This register is used to store the data to be written to the flash memory. This register is set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 18-16. Format of Flash Write Buffer Register (FLW) Address: FFA8H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 FLW FLW7 FLW6 FLW5 FLW4 FLW3 FLW2 FLW1 FLW0 (8) Protect byte This protect byte is used to specify the area that is to be protected from writing or erasing. The specified area is valid only in the self programming mode. Because self programming of the protected area is invalid, the data written to the protected area is guaranteed. 288 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY Figure 18-17. Format of Protect Byte (1/2) Address: 0081H 7 6 5 4 3 2 1 0 1 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 1 1 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 0 1 1 0 0 Blocks 7 to 0 are protected. 0 1 1 0 1 Blocks 5 to 0 are protected. Blocks 6 and 7 can be written or erased. 0 1 1 1 0 Blocks 3 to 0 are protected. Blocks 4 to 7 can be written or erased. 0 1 1 1 1 Blocks 1 and 0 are protected. Blocks 2 to 7 can be written or erased. 1 1 1 1 1 All blocks can be written or erased. * PD78F9221 Other than above Status Setting prohibited * PD78F9222 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 0 1 0 0 0 Blocks 15 to 0 are protected. 0 1 0 0 1 Blocks 13 to 0 are protected. Blocks 14 and 15 can be written or erased. 0 1 0 1 0 Blocks 11 to 0 are protected. Blocks 12 to 15 can be written or erased. 0 1 0 1 1 Blocks 9 to 0 are protected. Blocks 10 to 15 can be written or erased. 0 1 1 0 0 Blocks 7 to 0 are protected. Blocks 8 to 15 can be written or erased. 0 1 1 0 1 Blocks 5 to 0 are protected. Blocks 6 to 15 can be written or erased. 0 1 1 1 0 Blocks 3 to 0 are protected. Blocks 4 to 15 can be written or erased. 0 1 1 1 1 Blocks 1 and 0 are protected. Blocks 2 to 15 can be written or erased. 1 1 1 1 1 All blocks can be written or erased. Other than above User's Manual U16898EJ6V0UD Status Setting prohibited 289 CHAPTER 18 FLASH MEMORY Figure 18-17. Format of Protect Byte (2/2) * PD78F9224 <R> PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 0 0 0 0 0 Blocks 31 to 0 are protected. 0 0 0 0 1 Blocks 29 to 0 are protected. Blocks 30 and 31 can be written or erased. 0 0 0 1 0 Blocks 27 to 0 are protected. Blocks 28 to 31 can be written or erased. 0 0 0 1 1 Blocks 25 to 0 are protected. Blocks 26 and 31 can be written or erased. 0 0 1 0 0 Blocks 23 to 0 are protected. Blocks 24 to 31 can be written or erased. 0 0 1 0 1 Blocks 21 to 0 are protected. Blocks 22 to 31 can be written or erased. 0 0 1 1 0 Blocks 19 to 0 are protected. Blocks 20 to 31 can be written or erased. 0 0 1 1 1 Blocks 17 to 0 are protected. Blocks 18 to 31 can be written or erased. 0 1 0 0 0 Blocks 15 to 0 are protected. Blocks 16 to 31 can be written or erased. 0 1 0 0 1 Blocks 13 to 0 are protected. Blocks 14 to 31 can be written or erased. 0 1 0 1 0 Blocks 11 to 0 are protected. Blocks 12 to 31 can be written or erased. 0 1 0 1 1 Blocks 9 to 0 are protected. Blocks 10 to 31 can be written or erased. 0 1 1 0 0 Blocks 7 to 0 are protected. Blocks 8 to 31 can be written or erased. 0 1 1 0 1 Blocks 5 to 0 are protected. Blocks 6 to 31 can be written or erased. 0 1 1 1 0 Blocks 3 to 0 are protected. Blocks 4 to 31 can be written or erased. 0 1 1 1 1 Blocks 1 and 0 are protected. Blocks 2 to 31 can be written or erased. 1 1 1 1 1 All blocks can be written or erased. Other than above 290 User's Manual U16898EJ6V0UD Status Setting prohibited CHAPTER 18 FLASH MEMORY 18.8.4 Example of shifting normal mode to self programming mode The operating mode must be shifted from normal mode to self programming mode before performing self programming. An example of shifting to self programming mode is explained below. <1> Disable interrupts if the interrupt function is used (by setting the interrupt mask flag registers (MK0, MK1) to FFH and executing the DI instruction). <2> Clear FLCMD (FLCMD = 00H). <3> Clear the flash status register (PFS). <4> Set self programming mode using a specific sequenceNote. * Write a specific value (A5H) to PFCMD. * Write 01H to FLPMC (writing in this step is invalid). * Write 0FEH (inverted value of 01H) to FLPMC (writing in this step is invalid). * Write 01H to FLPMC (writing in this step is valid). <5> Execute NOP instruction and HALT instruction. <6> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFS. Abnormal <3>, normal <7> <7> Mode shift is completed. Note If the CPU clock is lower than 1 MHz, set it to be 1 MHz or higher. Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. User's Manual U16898EJ6V0UD 291 CHAPTER 18 FLASH MEMORY Figure 18-18. Example of Shifting to Self Programming Mode Shift to self programming mode <1> Disable interrupts (by setting MK0 and MK1 to FFH and executing DI instruction) ; When interrupt function is used <2> Clear FLCMD (FLCMD = 00H) <3> Clear PFS If the CPU clock is lower than 1 MHz, set it to be 1 MHz or higher. PFCMD = A5H FLPMC = 01H (set value) ; Set value is invalid <4> FLPMC = 0FEH (inverted set value) FLPMC = 01H (set value) ; Set value is valid NOP instruction <5> HALT instruction <6> Check execution result (FPRERR flag) Abnormal Normal <7> Termination Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. Remark 292 <1> to <7> in Figure 18-18 correspond to <1> to <7> in 18.8.4 (previous page). User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY An example of the program that shifts the mode to self programming mode is shown below. ;---------------------------;START ;---------------------------MOV MK0,#11111111B ; Masks all interrupts MOV MK1,#11111111B MOV FLCMD,#00H ; Clear FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode with FLPMC register DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: ; control (sets value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. ;---------------------------;END ;---------------------------- User's Manual U16898EJ6V0UD 293 CHAPTER 18 FLASH MEMORY 18.8.5 Example of shifting self programming mode to normal mode The operating mode must be returned from self programming mode to normal mode after performing self programming. An example of shifting to normal mode is explained below. <1> Clear FLCMD (FLCMD = 00H). <2> Clear the flash status register (PFS). <3> Set normal mode using a specific sequence. * Write the specific value (A5H) to PFCMD. * Write 00H to FLPMC (writing in this step is invalid) * Write 0FFH (inverted value of 00H) to FLPMC (writing in this step is invalid) * Write 00H to FLPMC (writing in this step is valid) <4> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFSNote. Abnormal <2>, normal <5> <5> Enable interrupt servicing (by executing the EI instruction and changing MK0 and MK1) to restore the original state. <6> Mode shift is completed Note Restore the CPU clock to its setting before self programming, after normal execution of the specific sequence. Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. 294 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY Figure 18-19. Example of Shifting to Normal Mode Shift to normal mode <1> Clear FLCMD (FLCMD = 00H) <2> Clear PFS PFCMD = A5H FLPMC = 00H (set value) ; Set value is invalid <3> FLPMC = 0FFH (inverted set value) FLPMC = 00H (set value) <4> Check execution result (FPRERR flag) ; Set value is valid Abnormal Normal Restore the CPU clock to its setting before the self programming <5> Enable interrupts (by executing EI instruction and changing MK0 and MK1) ; When interrupt function is used <6> Termination Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. Remark <1> to <6> in Figure 18-19 correspond to <1> to <6> in 18.8.5 (previous page). User's Manual U16898EJ6V0UD 295 CHAPTER 18 FLASH MEMORY An example of a program that shifts the mode to normal mode is shown below. ;---------------------------;START ;---------------------------MOV FLCMD,#00H ; Clear FLCMD register ModeOffLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs ; Restore the CPU clock to its setting before the self ; programming, after normal completion of the specific ; sequence MOV MK0,#INT_MK0 MOV MK1,#INT_MK1 ; Restores interrupt mask flag EI ;---------------------------;END ;---------------------------- 296 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY 18.8.6 Example of block erase operation in self programming mode An example of the block erase operation in self programming mode is explained below. <1> Set 03H (block erase) to the flash program command register (FLCMD). <2> Set the block number to be erased, to flash address pointer H (FLAPH). <3> Set flash address pointer L (FLAPL) to 00H. <4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC). <5> Set the flash address pointer L compare register (FLAPLC) to 00H. <6> Clear the flash status register (PFS). <7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note 1. <8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFSNote 2. Abnormal <10> Normal <R> <12> <10> If the number of times the erase command can be executed has not been exceeded, return to step <6> and re-execute the command. If the number of times the erase command can be executed has been exceeded, block erasure ends abnormally. <11> Block erase processing is abnormally terminated. <12> Block erase processing is normally terminated. Notes 1. <R> 2. This setting is not required when the watchdog timer is not used. Separately check the WEPRERR bit to check for errors in executing the erase command on a writeprohibited area. User's Manual U16898EJ6V0UD 297 CHAPTER 18 FLASH MEMORY <R> Figure 18-20. Example of Block Erase Operation in Self Programming Mode Block erasure <1> Set erase command (FLCMD = 03H) <2> Set no. of block to be erased to FLAPH <3> Set FLAPL to 00H <4> Set the same value as that of FLAPH to FLAPHC <5> Set FLAPLC to 00H <6> Clear PFS <7> Clear & restart WDT counter (WDTE = ACH)Note <8> Execute HALT instruction <9> Check execution result Abnormal The erase command can be re-executed. <10> Check the number of executions of the erase command Normal <12> Normal termination The erase command cannot be re-executed. <11> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark 298 <1> to <12> in Figure 18-20 correspond to <1> to <12> in 18.8.6 (previous page). User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY An example of a program that performs a block erase in self programming mode is shown below. ;---------------------------;START ;---------------------------- <R> MOV B,#48 ; Specifies the number of times the erase command can be ; executed. ; (4.0 V to 5.5 V Time for executing block erasure 100 times) FlashBlockErase: MOV FLCMD,#03H ; Sets flash control command (block erase) MOV FLAPH,#07H ; Sets number of block to be erased (block 7 is specified here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets erase block compare number (same value as that of FLAPH) MOV FLAPLC,#00H ; Fixes FLAPLC to "00H" MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT EraseRetry: HALT <R> ; Self programming is started MOV A,PFS CMP A,#00H ; Checks execution result BZ $StatusNormal ; Normal termination DBNZ B,$EraseRetry ; Checks whether to re-execute the erase command. ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: User's Manual U16898EJ6V0UD 299 CHAPTER 18 FLASH MEMORY 18.8.7 Example of block blank check operation in self programming mode An example of the block blank check operation in self programming mode is explained below. <1> Set 04H (block blank check) to the flash program command register (FLCMD). <2> Set the number of block for which a blank check is performed, to flash address pointer H (FLAPH). <3> Set flash address pointer L (FLAPL) to 00H. <4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC). <5> Set the flash address pointer L compare register (FLAPLC) to FFH. <6> Clear the flash status register (PFS). <7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note. <8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. Abnormal <10> Normal <11> <10> Block blank check is abnormally terminated. <11> Block blank check is normally terminated. Note This setting is not required when the watchdog timer is not used. 300 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY Figure 18-21. Example of Block Blank Check Operation in Self Programming Mode Block blank check <1> Set block blank check command (FLCMD = 04H) <2> Set no. of block for blank check to FLAPH <3> Set FLAPL to 00H <4> Set the same value as that of FLAPH to FLAPHC <5> Set FLAPLC to 00H <6> Clear PFS <7> Clear & restart WDT counter (WDTE = ACH)Note <8> Execute HALT instruction <9> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <11> Normal termination <10> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark <1> to <11>in Figure 18-21 correspond to <1> to <11> in 18.8.7 (previous page). User's Manual U16898EJ6V0UD 301 CHAPTER 18 FLASH MEMORY An example of a program that performs a block blank check in self programming mode is shown below. ;---------------------------;START ;---------------------------- FlashBlockBlankCheck: MOV FLCMD,#04H ; Sets flash control command (block blank check) MOV FLAPH,#07H ; Sets number of block for blank check (block 7 is specified ; here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets blank check block compare number (same value as that of MOV FLAPLC,#0FFH ; Fixes FLAPLC to "FFH" MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT ; FLAPH) HALT ; Self programming is started MOV A,PFS MOV CmdStatus,A ; Execution result is stored in variable ; (CmdStatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------;END ;---------------------------- 302 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY 18.8.8 Example of byte write operation in self programming mode An example of the byte write operation in self programming mode is explained below. <1> Set 05H (byte write) to the flash program command register (FLCMD). <2> Set the number of block to which data is to be written, to flash address pointer H (FLAPH). <3> Set the address at which data is to be written, to flash address pointer L (FLAPL). <4> Set the data to be written, to the flash write buffer register (FLW). <5> Clear the flash status register (PFS). <6> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note. <7> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <8> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. Abnormal <9> Normal <10> <9> Byte write processing is abnormally terminated. <10> Byte write processing is normally terminated. Note This setting is not required when the watchdog timer is not used. Caution If a write results in failure, erase the block once and write to it again. User's Manual U16898EJ6V0UD 303 CHAPTER 18 FLASH MEMORY Figure 18-22. Example of Byte Write Operation in Self Programming Mode Byte write <1> Set byte write command (FLCMD = 05H) <2> Set no. of block to be written, to FLAPH <3> Set address at which data is to be written, to FLAPL <4> Set data to be written to FLW <5> Clear PFS <6> Clear & restart WDT counter (WDTE = ACH)Note <7> Execute HALT instruction <8> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <10> Normal termination <9> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark 304 <1> to <10> in Figure 18-22 correspond to <1> to <10> in 18.8.8 (previous page). User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY An example of a program that performs a byte write in self programming mode is shown below. ;---------------------------;START ;---------------------------FlashWrite: MOV FLCMD,#05H ; Sets flash control command (byte write) MOV FLAPH,#07H ; Sets address to which data is to be written, with MOV FLAPL,#20H ; Sets address to which data is to be written, with MOV FLW,#10H ; Sets data to be written (10H is specified here) MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT ; FLAPH (block 7 is specified here) ; FLAPL (address 20H is specified here) HALT ; Self programming is started MOV A,PFS MOV CmdStatus,A ; Execution result is stored in variable ; (CmdStatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------;END ;---------------------------- User's Manual U16898EJ6V0UD 305 CHAPTER 18 FLASH MEMORY 18.8.9 Example of internal verify operation in self programming mode Examples of the internal verify 1 and 2 operations in self programming mode are explained below. * Internal verify 1 <1> Set 01H (internal verify) to the flash program command register (FLCMD). <2> Set the block number for which internal verify is performed, to flash address pointer H (FLAPH). <3> Set 00H to the flash address pointer L (FLAPL). <4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC). <5> Set FFH to the flash address pointer L compare register (FLAPLC). <6> Clear the flash status register (PFS). <7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note. <8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. Abnormal <10> Normal <11> <10> Internal verify processing is terminated abnormally. <11> Internal verify processing is terminated normally. * Internal verify 2 <1> Set 02H (internal verify 2) to the flash program command register (FLCMD). <2> Set the block number for which internal verify is performed, to flash address pointer H (FLAPH). <3> Set the verify start address to the flash address pointer L (FLAPL). <4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC). <5> Set the verify end address to the flash address pointer L compare register (FLAPLC). <6> Clear the flash status register (PFS). <7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note. <8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. Abnormal <10> Normal <11> <10> Internal verify processing is terminated abnormally. <11> Internal verify processing is terminated normally. Note This setting is not required when the watchdog timer is not used. 306 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY Figure 18-23. Example of Internal Verify 1 Operation in Self Programming Mode Internal verify 1 <1> Set internal verify 1 command (FLCMD = 01H) <2> Set no. of block for internal verify, to FLAPH <3> Set 00H to FLAPL <4> Set the same value as that of FLAPH to FLAPHC <5> Set FFH to FLAPLC <6> Clear PFS <7> Clear & restart WDT counter (WDTE = ACH)Note <8> Execute HALT instruction <9> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <11> Normal termination <10> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark <1> to <11> in Figure 18-23 correspond to <1> to <11> of internal verify 1 in 18.8.9 (previous page). User's Manual U16898EJ6V0UD 307 CHAPTER 18 FLASH MEMORY Figure 18-24. Example of Internal Verify 2 Operation in Self Programming Mode Internal verify 2 <1> Set internal verify 2 command (FLCMD = 02H) <2> Set block no. for internal verify, to FLAPH <3> Sets FLAPL to the start address <4> Set the same value as that of FLAPH to FLAPHC <5> Sets FLAPLC to the end address <6> Clear PFS <7> Clear & restart WDT counter (WDTE = ACH)Note <8> Execute HALT instruction <9> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <11> Normal termination <10> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark <1> to <11> in Figure 18-24 correspond to <1> to <11> of internal verify 2 in 18.8.9 (the page before last). 308 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY Example programs that perform internal verify 1 and 2 in self programming mode are shown below. * Internal verify 1 ;---------------------------;START ;---------------------------FlashVerify: MOV FLCMD,#01H ; Sets flash control command (internal verify 1) MOV FLAPH,#07H ; Sets block number for which internal verify is performed, ; to FLAPH (Example: Block 7 is specified here) MOV FLAPL,#00H MOV FLAPHC,#07H MOV FLAPLC,#FFH ; Sets FFH MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Sets 00H ; Self programming is started MOV A,PFS MOV CmdStatus,A ; Execution result is stored in variable ; (CmdStatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------;END ;---------------------------- * Internal verify 2 ;---------------------------;START ;---------------------------FlashVerify: MOV FLCMD,#02H ; Sets flash control command (internal verify 2) MOV FLAPH,#07H ; Sets block number for which internal verify is MOV FLAPL,#00H ; Sets FLAPL to the start address for verify (Example: Address MOV FLAPHC,#07H MOV FLAPLC,#20H ; performed, to FLAPH (Example: Block 7 is specified here) ; 00H is specified here) ; Sets FLAPLC to the end address for verify (Example: Address ; 20H is specified here) MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Self programming is started MOV A,PFS MOV CmdStatus,A ; Execution result is stored in variable ; (CmdStatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------;END ;---------------------------- User's Manual U16898EJ6V0UD 309 CHAPTER 18 FLASH MEMORY 18.8.10 Examples of operation when command execution time should be minimized in self programming mode Examples of operation when the command execution time should be minimized in self programming mode are explained below. (1) Erasure to blank check <1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 18.8.4) <2> Execution of block erase Error check (<1> to <12> in 18.8.6) <3> Execution of block blank check Error check (<1> to <11> in 18.8.7) <4> Mode is shifted from self programming mode to normal mode (<1> to <6> in 18.8.5) Figure 18-25. Example of Operation When Command Execution Time Should Be Minimized (from Erasure to Blank Check) Erasure to blank check Figure 18-18 <1> to <7> <1> Shift to self programming mode <2> Execute block erase Figure 18-20 <1> to <12> <2> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <3> Execute block blank check Figure 18-21 <1> to <11> <3> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 18-19 <1> to <6> <4> Shift to normal mode Normal termination Abnormal terminationNote Note Perform processing to shift to normal mode in order to return to normal processing. Remark 310 <1> to <4> in Figure 18-25 correspond to <1> to <4> in 18.8.10 (1) above. User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY An example of a program when the command execution time (from erasure to black check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------;START ;--------------------------------------------------------------------MOV MK0,#11111111B MOV MK1,#11111111B MOV FLCMD,#00H ; Masks all interrupts ; Clears FLCMD register DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode with FLPMC register control (sets ; value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs FlashBlockErase: MOV FLCMD,#03H ; Sets flash control command (block erase) MOV FLAPH,#07H ; Sets number of block to be erased (block 7 is specified MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets erase block compare number (same value as that of ; here) ; FLAPH) MOV FLAPLC,#00H MOV WDTE,#0ACH HALT ; Fixes FLAPLC to "00H" ; Clears & restarts WDT ; Self programming is started MOV A,PFS CMP A,#00H BNZ $StatusError ; Checks erase error ; Performs abnormal termination processing when an error ; occurs. FlashBlockBlankCheck: MOV FLCMD,#04H ; Sets flash control command (block blank check) MOV FLAPH,#07H ; Sets number of block for blank check (block 7 is specified ; here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" User's Manual U16898EJ6V0UD 311 CHAPTER 18 FLASH MEMORY MOV FLAPHC,#07H ; Sets blank check block compare number (same value as of ; FLAPH) MOV FLAPLC,#0FFH ; Fixes FLAPLC to "FFH" MOV WDTE,#0ACH ; Clears & restarts WDT HALT MOV ; Self programming is started A,PFS CMP A,#00H BNZ $StatusError ; Checks blank check error ; Performs abnormal termination processing when an error ; occurs. MOV FLCMD,#00H ; Clears FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ModeOffLoop: ; Repeats the same processing when an error occurs ; Restore the CPU clock to its setting before the self ; programming, after normal completion of the specific ; sequence MOV MK0,#INT_MK0 MOV MK1,#INT_MK1 ; Restores interrupt mask flag EI BR StatusNormal ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: 312 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY (2) Write to internal verify <1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 18.8.4) <2> Specification of source data for write <3> Execution of byte write Error check (<1> to <10> in 18.8.8) <4> <3> is repeated until all data are written. <5> Execution of internal verify Error check (<1> to <11> in 18.8.9) <6> Mode is shifted from self programming mode to normal mode (<1> to <6> in 18.8.5) Figure 18-26. Example of Operation When Command Execution Time Should Be Minimized (from Write to Internal Verify) Write to internal verify Figure 18-18 <1> to <7> <1> Shift to self programming mode <2> Set source data for write <3> Execute byte write command Figure 18-22 <1> to <10> <3> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Yes <4> All data written? No <5> Execute internal verify command Figure 18-23 <1> to <11> <5> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 18-19 <1> to <6> <6> Shift to normal mode Normal termination Abnormal terminationNote Note Perform processing to shift to normal mode in order to return to normal processing. Remark <1> to <6> in Figure 18-26 correspond to <1> to <6> in 18.8.10 (2) above. User's Manual U16898EJ6V0UD 313 CHAPTER 18 FLASH MEMORY An example of a program when the command execution time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------;START ;--------------------------------------------------------------------MOV MK0,#11111111B MOV MK1,#11111111B MOV FLCMD,#00H ; Masks all interrupts ; Clears FLCMD register DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode with FLPMC register control ; (sets value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs FlashWrite: MOVW HL,#DataAdrTop ; Sets address at which data to be written is located MOVW DE,#WriteAdr ; Sets address at which data is to be written MOV FLCMD,#05H ; Sets flash control command (byte write) MOV A,D MOV FLAPH,A MOV A,E MOV FLAPL,A MOV A,[HL] MOV FLW,A MOV WDTE,#0ACH FlashWriteLoop: HALT ; Sets address at which data is to be written ; Sets address at which data is to be written ; Sets data to be written ; Clears & restarts WDT ; Self programming is started MOV A,PFS CMP A,#00H BNZ $StatusError ; Checks write error ; Performs abnormal termination processing when an error ; occurs. 314 INCW HL MOVW AX,HL ; Address at which data to be written is located + 1 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY CMPW AX,#DataAdrBtm ; Performs internal verify processing BNC $FlashVerify ; if write of all data is completed INCW DE ; Address at which data is to be written + 1 BR FlashWriteLoop FlashVerify: MOVW HL,#WriteAdr ; Sets verify address MOV FLCMD,#02H ; Sets flash control command (internal verify 2) MOV A,H MOV FLAPH,A MOV A,L MOV FLAPL,A MOV A,D MOV FLAPHC,A ; Sets verify start address ; Sets verify start address ; Sets verify end address MOV A,E MOV FLAPLC,A ; Sets verify end address MOV WDTE,#0ACH ; Clears & restarts WDT HALT MOV ; Self programming is started A,PFS CMP A,#00H BNZ $StatusError ; Checks internal verify error ; Performs abnormal termination processing when an error ; occurs. MOV FLCMD,#00H ; Clears FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ModeOffLoop: ; Repeats the same processing when an error occurs ; Restore the CPU clock to its setting before the self ; programming, after normal completion of the specific ; sequence MOV MK0,#INT_MK0 MOV MK1,#INT_MK1 ; Restores interrupt mask flag EI BR StatusNormal User's Manual U16898EJ6V0UD 315 CHAPTER 18 FLASH MEMORY ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: ;--------------------------------------------------------------------; Data to be written ;--------------------------------------------------------------------DataAdrTop: DB XXH DB XXH DB XXH DB XXH : : DB XXH DataAdrBtm: ;--------------------------------------------------------------------- Remark 316 Internal verify 2 is used in the above program example. Use internal verify 1 to verify a whole block. User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY 18.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode Examples of operation when the interrupt-disabled time should be minimized in self programming mode are explained below. (1) Erasure to blank check <1> Specification of block erase command (<1> to <5> in 18.8.6) <2> Mode is shifted from normal mode to self programming mode (<1> to <7> in 18.8.4) <3> Execution of block erase command Error check (<6> to <12> in 18.8.6) <4> Mode is shifted from self programming mode to normal mode (<1> to <6> in 18.8.5) <5> Specification of block blank check command (<1> to <5> in 18.8.7) <6> Mode is shifted from normal mode to self programming mode (<1> to <7> in 18.8.4) <7> Execution of block blank check command Error check (<6> to <11> in 18.8.7) <8> Mode is shifted from self programming mode to normal mode (<1> to <6> in 18.8.5) User's Manual U16898EJ6V0UD 317 CHAPTER 18 FLASH MEMORY <R> Figure 18-27. Example of Operation When Interrupt-Disabled Time Should Be Minimized (from Erasure to Blank Check) Erasure to blank check Figure 18-20 <1> to <5> <1> Specify block erase command Figure 18-18 <1> to <7> <2> Shift to self programming mode <3> Execute block erase command Figure 18-20 <6> to <12> <3> Check execution result Abnormal Normal Figure 18-19 <1> to <6> <4> Shift to normal mode Figure 18-21 <1> to <5> <5> Specify block blank check command Figure 18-18 <1> to <7> <6> Shift to self programming mode <7> Execute block blank check command Figure 18-21 <6> to <11> <7> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 18-19 <1> to <6> <8> Shift to normal mode Normal termination Abnormal terminationNote Note Perform processing to shift to normal mode in order to return to normal processing. Remark 318 <1> to <8> in Figure 18-27 correspond to <1> to <8> in 18.8.11 (1) (previous page). User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY An example of a program when the interrupt-disabled time (from erasure to blank check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------;START ;--------------------------------------------------------------------- <R> MOV B,#48 ; Specifies the number of times the erase command can be ; executed. ; (4.0 V to 5.5 V Time for executing block erasure 100 times) FlashBlockErase: ; Sets erase command MOV FLCMD,#03H ; Sets flash control command (block erase) MOV FLAPH,#07H ; Sets number of block to be erased (block 7 is specified here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets erase block compare number (same value as that of FLAPH) MOV FLAPLC,#00H ; Fixes FLAPLC to "00H" CALL !ModeOn ; Shift to self programming mode EraseRetry: ; Execution of erase command MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Self programming is started MOV A,PFS CMP A,#00H ; Checks execution result BNZ $RetryCheck ; Checks erase error ; Performs abnormal termination processing when an error ; occurs. CALL !ModeOff ; Shift to normal mode ; Sets blank check command MOV FLCMD,#04H ; Sets flash control command (block blank check) MOV FLAPH,#07H ; Sets block number for blank check (block 7 is specified here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets blank check block compare number (same value as that of MOV FLAPLC,#0FFH ; Fixes FLAPLC to "FFH" CALL !ModeOn ; Shift to self programming mode ; FLAPH) ; Execution of blank check command MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT MOV ; Self programming is started A,PFS User's Manual U16898EJ6V0UD 319 CHAPTER 18 FLASH MEMORY CMP A,#00H ; Checks execution result BNZ $StatusError ; Checks blank check error ; Performs abnormal termination processing when an error occurs <R> CALL !ModeOff BR StatusNormal ; Shift to normal mode RetryCheck: DBNZ B,$EraseRetry ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: ;--------------------------------------------------------------------;Processing to shift to self programming mode ;--------------------------------------------------------------------ModeOn: MOV MK0,#11111111B MOV MK1,#11111111B MOV FLCMD,#00H ; Masks all interrupts ; Clears FLCMD register DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode via FLPMC register control (sets ; value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs RET 320 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY ;--------------------------------------------------------------------; Processing to shift to normal mode ;--------------------------------------------------------------------ModeOffLoop: MOV FLCMD,#00H ; Clears FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs ; Restore the CPU clock to its setting before the self ; programming, after normal completion of the specific ; sequence MOV MK0,#INT_MK0 MOV MK1,#INT_MK1 ; Restores interrupt mask flag EI RET User's Manual U16898EJ6V0UD 321 CHAPTER 18 FLASH MEMORY (2) Write to internal verify <1> Specification of source data for write <2> Specification of byte write command (<1> to <4> in 18.8.8) <3> Mode is shifted from normal mode to self programming mode (<1> to <7> in 18.8.4) <4> Execution of byte write command Error check (<5> to <10> in 18.8.8) <5> Mode is shifted from self programming mode to normal mode (<1> to <6> in 18.8.5) <6> <2> to <5> is repeated until all data are written. <7> The internal verify command is specified (<1> to <5> in 18.8.9) <8> Mode is shifted from normal mode to self programming mode (<1> to <7> in 18.8.4) <9> Execution of internal verify command Error check (<6> to <11> in 18.8.9) <10> Mode is shifted from self programming mode to normal mode (<1> to <6> in 18.8.5) 322 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY Figure 18-28. Example of Operation When Interrupt-Disabled Time Should Be Minimized (from Write to Internal Verify) Write to internal verify <1> Set source data for write Figure 18-22 <1> to <4> <2> Specify byte write command Figure 18-18 <1> to <7> <3> Shift to self programming mode <4> Execute byte write command Figure 18-22 <5> to <10> <4> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 18-19 <1> to <6> <5> Shift to normal mode Yes <6> All data written? No Figure 18-23 <1> to <5> <7> Specify internal verify command Figure 18-18 <1> to <7> <8> Shift to self programming mode <9> Execute internal verify command Figure 18-23 <6> to <11> <9> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 18-19 <1> to <6> <10> Shift to normal mode Normal termination Abnormal terminationNote Note Perform processing to shift to normal mode in order to return to normal processing. Remark <1> to <10> in Figure 18-28 correspond to <1> to <10> in 18.8.11 (2) (previous page). User's Manual U16898EJ6V0UD 323 CHAPTER 18 FLASH MEMORY An example of a program when the interrupt-disabled time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------;START ;--------------------------------------------------------------------; Sets write command FlashWrite: MOVW HL,#DataAdrTop ; Sets address at which data to be written is located MOVW DE,#WriteAdr ; Sets address at which data is to be written MOV FLCMD,#05H ; Sets flash control command (byte write) MOV A,D MOV FLAPH,A MOV A,E MOV FLAPL,A MOV A,[HL] MOV FLW,A ; Sets data to be written CALL !ModeOn ; Shift to self programming mode FlashWriteLoop: ; Sets address at which data is to be written ; Sets address at which data is to be written ; Execution of write command MOV PFS,#00H MOV WDTE,#0ACH HALT ; Clears flash status register ; Clears & restarts WDT ; Self programming is started MOV A,PFS CMP A,#00H BNZ $StatusError ; Checks write error ; Performs abnormal termination processing when an error ; occurs. CALL !ModeOff ; Shift to normal mode MOV MK0,#INT_MK0 ; Restores interrupt mask flag MOV MK1,#INT_MK1 EI ; Judgment of writing all data 324 INCW HL MOVW AX,HL ; Address at which data to be written is located + 1 CMPW AX,#DataAdrBtm ; Performs internal verify processing BNC $FlashVerify ; if write of all data is completed INCW DE ; Address at which data is to be written + 1 BR FlashWriteLoop User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY ; Setting internal verify command FlashVerify: MOVW HL,#WriteAdr ; Sets verify address MOV FLCMD,#02H ; Sets flash control command (internal verify 2) MOV A,H MOV FLAPH,A MOV A,L MOV FLAPL,A MOV A,D MOV FLAPHC,A MOV A,E MOV FLAPLC,A ; Sets verify end address CALL !ModeOn ; Shift to self programming mode ; Sets verify start address ; Sets verify start address ; Sets verify end address ; Execution of internal verify command MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Self programming is started MOV A,PFS CMP A,#00H BNZ $StatusError ; Checks internal verify error ; Performs abnormal termination processing when an error occurs CALL !ModeOff BR StatusNormal ; Shift to normal mode ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: User's Manual U16898EJ6V0UD 325 CHAPTER 18 FLASH MEMORY ;--------------------------------------------------------------------;Processing to shift to self programming mode ;--------------------------------------------------------------------ModeOn: MOV MK0,#11111111B ; Masks all interrupts MOV MK1,#11111111B MOV FLCMD,#00H ; Clears FLCMD register DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode via FLPMC register control (sets ; value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs RET ;--------------------------------------------------------------------; Processing to shift to normal mode ;--------------------------------------------------------------------ModeOffLoop: MOV FLCMD,#00H ; Clears FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs ; Restore the CPU clock to its setting before the self ; programming, after normal completion of the specific ; sequence MOV MK0,#INT_MK0 MOV MK1,#INT_MK1 ; Restores interrupt mask flag EI 326 User's Manual U16898EJ6V0UD CHAPTER 18 FLASH MEMORY RET ;--------------------------------------------------------------------;Data to be written ;--------------------------------------------------------------------DataAdrTop: DB XXH DB XXH DB XXH DB XXH : : DB XXH DataAdrBtm: ;--------------------------------------------------------------------- Remark Internal verify 2 is used in the above program example. Use internal verify 1 to verify a whole block. User's Manual U16898EJ6V0UD 327 CHAPTER 19 ON-CHIP DEBUG FUNCTION 19.1 Connecting QB-MINI2 to 78K0S/KA1+ The 78K0S/KA1+ uses RESET, X1, X2, INTP3, VDD, and GND pins to communicate with the host machine via an on-chip debug emulator (QB-MINI2). Caution The 78K0S/KA1+ has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is not liable for problems occurring when the on-chip debug function is used. Figure 19-1. Recommended Circuit Connection VDD VDD Target connector GND RESET_OUT DATA VDD DATA R.F.U. R.F.U. H/SNote 4 CLK R.F.U. R.F.U. INTP R.F.U. CLK RESET_IN R.F.U. Target device 3 to 10 k 1 2 RESETNote 1 3 X2Note 2 4 5 Note 3 VDD 6 VDD 7 1 k 8 9 10 X1Note 2 Note 3 VDD GND 11 12 INTP3Note 5 13 14 15 10 k 1 to 10 k VDD 16 1 k Reset circuit RESET signal Caution The constants described in the circuit connection example are reference values. If you perform flash programming aiming at mass production, thoroughly evaluate whether the specifications of the target device are satisfied. Notes 1. The RESET pin is used to download the monitor program at debugger startup or to implement forced reset. Therefore, a pin that alternately functions as the RESET pin cannot be used. For reset pin connection, refer to QB-MINI2 User's Manual (U18371E). 2. This is the pin connection when the X1 and X2 pins are not used in the target system. When using the X1 and X2 pins, refer to 19.1.2 Connection of X1 and X2 pins. 3. No problem will occur if the dashed line portions are connected. 4. This pin is connected to enhance the accuracy of time measurement between run and break during debugging. Debugging is possible even if this pin is left open, but measurement error occurs in several ms units. 328 User's Manual U16898EJ6V0UD CHAPTER 19 ON-CHIP DEBUG FUNCTION Note 5. The INTP3 pin is used for communication between QB-MINI2 and the target device during debugging. When debugging is performed with QB-MINI2, therefore, the INTP3 pin and its alternate-function pin cannot be used. For INTP3 pin connection, refer to 19.1.1 Connection of INTP3 pin. Pins for communication depend on whether the monitor program has been written or not. (refer to Table 19-1) X1 and X2 pins can be used as I/O port pins or the pins for oscillation, after the monitor program has been written. Table 19-1. Pins for communication with QB-MINI2 Before writing the monitor program After writing the monitor program X1, X2, RESET, INTP3, VDD, VSS RESET, INTP3, VDD, VSS 19.1.1 Connection of INTP3 pin The INTP3 pin is used only for communication between QB-MINI2 and the target device during debugging. Design circuits appropriately according to the relevant case among the cases shown below. (1) INTP3 pin is not used in target system (as is illustrated in Figure 19-1. Recommended Circuit Connection) See Figure 19-2. (2) QB-MINI2 is used only for programming, not for debugging See Figure 19-3. (3) QB-MINI2 is used for debugging and debugging of the INTP3 pin is performed only with a real machine See Figure 19-4. Figure 19-2. Circuit Connection for the Case Where INTP3 Pin Is Not Used in Target System VDD Target device Target connector 1 k INTP 12 INTP3 Figure 19-3. Circuit Connection for the Case Where QB-MINI2 Is Used Only for Programming Target device Target connector INTP 12 User's Manual U16898EJ6V0UD INTP3 329 CHAPTER 19 ON-CHIP DEBUG FUNCTION Figure 19-4. Circuit Connection for the Case Where QB-MINI2 Is Used for Debugging and Debugging of INTP3 Pin Is Performed Only with Real Machine VDD Target connector 1 k INTP Target device 1 12 2 3 INTP3 External device I/O to INTP3 * Jumper setting Caution When debugging with QB-MINI2 connected: 1-2 shorted Other than above: 2-3 shorted If debugging is performed with a real machine running, without using QB-MINI2, write the user program using the QB-Programmer. Programs downloaded by the debugger include the monitor program, and such a program malfunctions if it is not controlled via QB-MINI2. 19.1.2 Connection of X1 and X2 pins The X1 and X2 pins are used when the debugger is started for the first time (when downloading the monitor program) and when programming is performed with the QB-Programmer. Figure 19-5. Circuit Connection for the Case Where X1 and X2 Pins Are Used in Target System Target device Target connector X2 3 1 2 3 X1 9 X2 1 2 X1 3 External components Oscillator or external device * Jumper setting When debugger is started for the first time (downloading the monitor program) or when 330 programming is performed with QB-Programmer: 1-2 shorted Other than above: 2-3 shorted User's Manual U16898EJ6V0UD CHAPTER 19 ON-CHIP DEBUG FUNCTION 19.2 Securing of user resources The user must prepare the following to perform communication between QB-MINI2 and the target device and implement each debug function. For details of the setting, refer to QB-MINI2 User's Manual (U18371E). * Securement of memory space The shaded portions in Figure 19-6 are the areas reserved for placing the debug monitor program, so user programs cannot be allocated in these spaces. Figure 19-6. Memory Spaces Where Debug Monitor Programs Are Allocated Internal ROM space 304 bytes Internal RAM space Internal RAM end address Internal ROM end address Stack area for debugging (5 bytes) for software break (2 bytes) 0x7EH INTP3 interrupt vector (2 bytes) 0x18H * Securement of serial interface for communication The register settings, concerning the INTP3 pin used for communication between QB-MINI2 and the target device, performed by the debug monitor program must not be changed. User's Manual U16898EJ6V0UD 331 CHAPTER 20 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the 78K0S/KA1+. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E). 20.1 Operation 20.1.1 Operand identifiers and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are described as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 20-1. Operand Identifiers and Description Methods Identifier Description Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp sfr AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels (even addresses only) addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) addr5 0040H to 007FH Immediate data or labels (even addresses only) word 16-bit immediate data or label byte bit 8-bit immediate data or label 3-bit immediate data or label Remark 332 For symbols of special function registers, see Table 3-3 Special Function Registers. User's Manual U16898EJ6V0UD CHAPTER 20 INSTRUCTION SET OVERVIEW 20.1.2 Description of "Operation" column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag ( ): Memory contents indicated by address or register contents in parentheses xH, xL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : : Exclusive logical sum (exclusive OR) Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 20.1.3 Description of "Flag" column (Blank): Unchanged 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is stored User's Manual U16898EJ6V0UD 333 CHAPTER 20 INSTRUCTION SET OVERVIEW 20.2 Operation List Mnemonic Operand Bytes Clocks Operation Flag Z MOV XCH r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte A, r Note 1 2 4 Ar r, A Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL + byte] 2 6 A (HL + byte) [HL + byte], A 2 6 (HL + byte) A 1 4 AX 2 6 Ar A, saddr 2 6 A (saddr) A, sfr 2 6 A sfr A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL, byte] 2 8 A (HL + byte) A, X A, r Note 2 AC CY x x x x x x Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 334 User's Manual U16898EJ6V0UD CHAPTER 20 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z MOVW rp, #word 3 6 rp word AX, saddrp 2 6 AX (saddrp) AC CY 2 8 (saddrp) AX AX, rp Note 1 4 AX rp rp, AX Note 1 4 rp AX XCHW AX, rp Note 1 8 AX rp ADD A, #byte 2 4 A, CY A + byte x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte x x x A, r 2 4 A, CY A + r x x x A, saddr 2 4 A, CY A + (saddr) x x x A, !addr16 3 8 A, CY A + (addr16) x x x A, [HL] 1 6 A, CY A + (HL) x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) x x x A, #byte 2 4 A, CY A + byte + CY x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte + CY x x x A, r 2 4 A, CY A + r + CY x x x A, saddr 2 4 A, CY A + (saddr) + CY x x x A, !addr16 3 8 A, CY A + (addr16) + CY x x x A, [HL] 1 6 A, CY A + (HL) + CY x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) + CY x x x A, #byte 2 4 A, CY A - byte x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte x x x A, r 2 4 A, CY A - r x x x A, saddr 2 4 A, CY A - (saddr) x x x A, !addr16 3 8 A, CY A - (addr16) x x x A, [HL] 1 6 A, CY A - (HL) x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) x x x saddrp, AX ADDC SUB Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U16898EJ6V0UD 335 CHAPTER 20 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z SUBC AND OR XOR Remark A, #byte 2 4 A, CY A - byte - CY x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte - CY x x x A, r 2 4 A, CY A - r - CY x x x A, saddr 2 4 A, CY A - (saddr) - CY x x x A, !addr16 3 8 A, CY A - (addr16) - CY x x x A, [HL] 1 6 A, CY A - (HL) - CY x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) - CY x x x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 336 AC CY User's Manual U16898EJ6V0UD CHAPTER 20 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z AC CY A, #byte 2 4 A - byte x x x saddr, #byte 3 6 (saddr) - byte x x x A, r 2 4 A-r x x x A, saddr 2 4 A - (saddr) x x x A, !addr16 3 8 A - (addr16) x x x A, [HL] 1 6 A - (HL) x x x A, [HL + byte] 2 6 A - (HL + byte) x x x ADDW AX, #word 3 6 AX, CY AX + word x x x SUBW AX, #word 3 6 AX, CY AX - word x x x CMPW AX, #word 3 6 AX - word x x x INC r 2 4 rr+1 x x saddr 2 4 (saddr) (saddr) + 1 x x r 2 4 rr-1 x x saddr 2 4 (saddr) (saddr) - 1 x x INCW rp 1 4 rp rp + 1 DECW rp 1 4 rp rp - 1 ROR A, 1 1 2 (CY, A7 A0, Am-1 Am) x 1 x ROL A, 1 1 2 (CY, A0 A7, Am+1 Am) x 1 x RORC A, 1 1 2 (CY A0, A7 CY, Am-1 Am) x 1 x ROLC A, 1 1 2 (CY A7, A0 CY, Am+1 Am) x 1 x SET1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 A.bit 2 4 A.bit 1 PSW.bit 3 6 PSW.bit 1 [HL].bit 2 10 (HL).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 A.bit 2 4 A.bit 0 PSW.bit 3 6 PSW.bit 0 [HL].bit 2 10 (HL).bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x CMP DEC CLR1 Remark x x x x x x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U16898EJ6V0UD 337 CHAPTER 20 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z CALL !addr16 3 6 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLT [addr5] 1 8 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 RET 1 6 PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 8 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 PSW 1 2 (SP - 1) PSW, SP SP - 1 rp 1 4 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 1 4 PSW (SP), SP SP + 1 rp 1 6 rpH (SP + 1), rpL (SP), SP SP + 2 PUSH POP SP, AX 2 8 SP AX AX, SP 2 6 AX SP !addr16 3 6 PC addr16 $addr16 2 6 PC PC + 2 + jdisp8 AX 1 6 PCH A, PCL X BC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 1 BNC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 0 BZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 1 BNZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 0 BT saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 1 saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 0 B, $addr16 2 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 C C - 1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 NOP 1 2 No Operation EI 3 6 IE 1 (Enable Interrupt) DI 3 6 IE 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode MOVW BR BF DBNZ Remark R R R R R R One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 338 AC CY User's Manual U16898EJ6V0UD CHAPTER 20 INSTRUCTION SET OVERVIEW 20.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 1 None 1st Operand A r ADD MOVNote MOV MOV ADDC XCHNote XCH SUB ADD ADD SUBC ADDC ADDC AND SUB OR XOR CMP MOV MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD ADD RORC ADDC ADDC ADDC ROLC SUB SUB SUB SUB SUBC SUBC SUBC SUBC SUBC AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP XCH MOV MOV MOV INC DEC B, C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC DEC ADD ADDC SUB SUBC AND OR XOR CMP !addr16 MOV PSW MOV MOV PUSH POP [DE] MOV [HL] MOV [HL + byte] MOV Note Except r = A. User's Manual U16898EJ6V0UD 339 CHAPTER 20 INSTRUCTION SET OVERVIEW (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rp Note saddrp SP None 1st Operand AX rp ADDW SUBW MOVW CMPW XCHW MOVW MOVW MOVW Note MOVW INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand $addr16 None 1st Operand A.bit sfr.bit saddr.bit PSW.bit BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 [HL].bit SET1 CLR1 CY SET1 CLR1 NOT1 340 User's Manual U16898EJ6V0UD CHAPTER 20 INSTRUCTION SET OVERVIEW (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand AX !addr16 [addr5] $addr16 1st Operand Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User's Manual U16898EJ6V0UD 341 CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Symbol Conditions Ratings Unit VDD -0.3 to +6.5 V VSS -0.3 to +0.3 V AVREF -0.3 to VDD + 0.3 VI1 -0.3 to VDD + 0.3 VI2 P30, P31, P34, P40 to P45, P121 to P123 P20 to P23 Note Note -0.3 to AVREF + 0.3 Note V V V and -0.3 to VDD + 0.3 Note Output voltage VO -0.3 to VDD + 0.3 Analog input voltage VAN -0.3 to AVREF + 0.3 Note Note V V and -0.3 to VDD + 0.3 Note Output current, high Output current, low Operating ambient IOH IOL TA temperature Storage temperature Per pin -10.0 mA Total of pins other than P20 to P23 -44.0 mA Total of P20 to P23 -44.0 mA Per pin 20.0 mA Total of all pins 44.0 mA -40 to +85 C Flash memory blank status -65 to +150 C Flash memory programming already performed -40 to +125 C In normal operation mode During flash memory programming Tstg Note Must be 6.5 V or lower Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 342 User's Manual U16898EJ6V0UD CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C X1 Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator Ceramic Recommended Circuit VSS X1 X2 Oscillation VSS X1 MAX. Unit 2.0 10.0 MHz X2 Oscillation 2.0 10.0 MHz MHz Note 2 frequency (fX) C1 C2 X1 2.7 V VDD 5.5 V 2.0 10.0 frequency (fX) 2.0 V VDD < 2.7 V 2.0 5.0 X1 input high- 2.7 V VDD 5.5 V 0.045 0.25 2.0 V VDD < 2.7 V 0.09 0.25 X1 input Note 2 /low-level width (tXH, tXL) Notes 1. TYP. C2 resonator clock MIN. frequency (fX) C1 External Conditions Note 2 resonator Crystal Parameter s Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V 0.1 V. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U16898EJ6V0UD 343 CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C High-Speed Internal Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator Parameter Conditions High-speed internal Oscillation frequency (fX = 8 oscillator MHz 2.7 V VDD 5.5 V Note 2 ) deviation Oscillation frequency (fX) Notes 1. MAX. Unit TA = -10 to +80C 3 % TA = -40 to +85C 5 % 2.0 V VDD < 2.7 V Note 2 MIN. TYP. 5.5 MHz Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V 0.1 V. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Low-Speed Internal Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote, VSS = 0 V) Resonator Low-speed internal Parameter Conditions Oscillation frequency (fRL) MIN. TYP. MAX. Unit 120 240 480 kHz oscillator Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.1 V 0.1 V. 344 User's Manual U16898EJ6V0UD CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote, VSS = 0 V) (1/2) Parameter Output current, high Symbol IOH1 IOH2 Output current, low Input voltage, high Input voltage, low Output voltage, high IOL Conditions MIN. TYP. MAX. Unit Pins other than Per pin 2.0 V VDD 5.5 V -5 mA P20 to P23 Total 4.0 V VDD 5.5 V -25 mA 2.0 V VDD < 4.0 V -15 mA Per pin 2.0 V AVREF 5.5 V -5 mA Total 2.0 V AVREF 5.5 V -15 mA Per pin 2.0 V VDD 5.5 V 10 mA Total of all pins 4.0 V VDD 5.5 V 30 mA 2.0 V VDD < 4.0 V 15 mA 0.8VDD VDD V P20 to P23 VIH1 P30, P31, P34, P40 to P45, P123 VIH2 P20 to P23 0.7AVREF AVREF V VIH3 P121, P122 0.8VDD VDD V VIL1 P30, P31, P34, P40 to P45, P123 0 0.2VDD V VIL2 P20 to P23 0 0.3AVREF V VIL3 P121, P122 0 0.2VDD V VOH1 Total of pins other than 4.0 V VDD 5.5 V P20 to P23 IOH1 = -5 mA VDD - 1.0 V VDD - 0.5 V IOH1 = -15 mA VOH2 IOH1 = -100 A 2.0 V VDD < 4.0 V Total of pins P20 to P23 4.0 V AVREF 5.5 V AVREF - 1.0 IOH2 = -5 mA V AVREF - 0.5 V IOH2 = -10 mA 2.0 V AVREF < 4.0 V IOH2 = -100 A Output voltage, low VOL Total of pins 4.0 V VDD 5.5 V IOL = 30 mA IOL = 10 mA 2.0 V VDD 4.0 V 1.3 V 0.4 V IOL = 400 A Input leakage current, high ILIH VI = VDD Pins other than X1 1 A Input leakage current, low VI = 0 V Pins other than X1 -1 A Output leakage current, high ILOH VO = VDD Pins other than X2 1 A Output leakage current, low ILOL VO = 0 V Pins other than X2 -1 A Pull-up resistance RPU VI = 0 V 10 30 100 k Pull-down resistance RPD P121, P122, reset status 10 30 100 k ILIL Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.1 V 0.1 V. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U16898EJ6V0UD 345 CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) (2/2) Parameter Note 3 Supply current Symbol IDD1 Note 2 Conditions Crystal/ceramic fX = 10 MHz oscillation, external VDD = 5.0 V 10% fX = 6 MHz clock input oscillation operating mode Note 6 MIN. TYP. MAX. Unit When A/D converter is stopped 6.1 12.2 Note 8 When A/D converter is operating 7.6 15.2 When A/D converter is stopped 5.5 11.0 Note 4 VDD = 5.0 V 10% When A/D converter is operating fX = 5 MHz When A/D converter is stopped 3.0 6.0 Note 8 Note 4 Note 8 IDD2 When A/D converter is operating 4.5 9.0 Crystal/ceramic fX = 10 MHz When peripheral functions are stopped 1.7 3.8 oscillation, external VDD = 5.0 V 10% When peripheral functions are operating fX = 6 MHz When peripheral functions are stopped clock input HALT mode Note 6 mA 14.0 VDD = 3.0 V 10% Note 5 mA mA mA Note 4 VDD = 5.0 V 10% When peripheral functions are operating fX = 5 MHz When peripheral functions are stopped 6.7 1.3 3.0 mA Note 4 6.0 0.48 1 VDD = 3.0 V 10% When peripheral functions are operating High-speed internal fX = 8 MHz When A/D converter is stopped 5.0 10.0 oscillation operating VDD = 5.0 V 10% Note 8 When A/D converter is operating 6.5 13.0 High-speed internal fX = 8 MHz When peripheral functions are stopped 1.4 3.2 oscillation HALT VDD = 5.0 V 10% When peripheral functions are operating VDD = 5.0 V 10% When low-speed internal mA Note 5 Note 3 IDD3 Note 4 Note 7 2.1 mA mode IDD4 mA Note 4 Note 7 5.9 mode IDD5 STOP mode 3.5 20.0 17.5 32.0 3.5 15.5 11.0 26.0 A oscillation is stopped When low-speed internal oscillation is operating VDD = 3.0 V 10% When low-speed internal A oscillation is stopped When low-speed internal oscillation is operating Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V 0.1 V. 2. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 3. These currents include peripheral operation currents. 4. When the processor clock control register (PCC) is set to 00H. 5. When the processor clock control register (PCC) is set to 02H. 6. When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using the option byte. 7. When the high-speed internal oscillation clock is selected as the system clock source using the option byte. 8. 346 The current that flows through the AVREF pin is included. User's Manual U16898EJ6V0UD CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Parameter Symbol Cycle time (minimum TCY instruction execution time) TI000 input high-level width, tTIH, low-level width tTIL Conditions MIN. tINTH, tINTL RESET input low-level tRSL Unit 4.0 V VDD 5.5 V 0.2 16 s clock, external clock input 3.0 V VDD < 4.0 V 0.33 16 s 2.7 V VDD < 3.0 V 0.4 16 s 2.0 V VDD < 2.7 V 1 16 s High-speed internal 4.0 V VDD 5.5 V 0.23 4.22 s oscillation clock 2.7 V VDD < 4.0 V 0.47 4.22 s 2.0 V VDD < 2.7 V 0.95 4.22 s 4.0 V VDD 5.5 V s 2/fsam+ 0.1 Note 2 s 2/fsam+ 0.2 width, low-level width MAX. Crystal/ceramic oscillation 2.0 V VDD < 4.0 V Interrupt input high-level TYP. Note 2 1 s 2 s width Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V 0.1 V. 2. Selection of fsam = fXP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP. CPU Clock Frequency, Peripheral Clock Frequency Parameter Conditions CPU Clock (fCPU) Ceramic resonator, 4.0 V VDD 5.5 V 125 kHz fCPU 10 MHz crystal resonator, 3.0 V VDD < 4.0 V 125 kHz fCPU 6 MHz external clock 2.7 V VDD < 3.0 V 2.0 V VDD < 2.7 V High-speed internal 4.0 V VDD 5.5 V oscillator 2.7 V VDD < 4.0 V 2.0 V VDD < 2.7 V Peripheral Clock (fXP) 500 kHz fXP 10 MHz 125 kHz fCPU 5 MHz Note 125 kHz fCPU 2 MHz 500 kHz fXP 5 MHz 500 kHz (TYP.) fCPU 8 MHz (TYP.) 2 MHz (TYP.) fXP 8 MHz (TYP.) 500 kHz (TYP.) fCPU 4 MHz (TYP.) Note 500 kHz (TYP.) fCPU 2 MHz (TYP.) 2 MHz (TYP.) fXP 4 MHz (TYP.) Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.1 V 0.1 V. User's Manual U16898EJ6V0UD 347 CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C TCY vs. VDD (Crystal/Ceramic Oscillation Clock, External Clock Input) 60 16 Cycle time TCY [s] 10 Guaranteed operation range 1.0 0.4 0.33 0.1 1 2 3 4 5 6 5.5 2.7 Supply voltage VDD [V] TCY vs. VDD (High-Speed Internal Oscillation Clock) 60 Cycle time TCY [s] 10 4.22 Guaranteed operation range 1.0 0.95 0.47 0.23 0.1 1 348 2 3 4 5 6 2.7 5.5 Supply voltage VDD [V] User's Manual U16898EJ6V0UD CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C (2) Serial interface (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote, VSS = 0 V) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions MIN. Transfer rate TYP. MAX. Unit 312.5 kbps Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.1 V 0.1 V. AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH X1 input TI000 Timing tTIL tTIH TI000 Interrupt Input Timing tINTL tINTH INTP0 to INTP3 RESET Input Timing tRSL RESET User's Manual U16898EJ6V0UD 349 CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C A/D Converter Characteristics (TA = -40 to +85C, 2.7 V AVREF VDD 5.5 V, VSS = 0 VNote 1) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 bit 4.0 V AVREF 5.5 V 0.2 0.4 %FSR 2.7 V AVREF < 4.0 V 0.3 0.6 %FSR Resolution Notes 2, 3 Overall error AINL Conversion time tCONV Notes 2, 3 Zero-scale error Full-scale error Ezs Notes 2, 3 Efs Note 2 Integral non-linearity error Differential non-linearity error Analog input voltage Notes 1. Note 2 ILE DLE 4.5 V AVREF 5.5 V 3.0 100 s 4.0 V AVREF < 4.5 V 4.8 100 s 2.85 V AVREF < 4.0 V 6.0 100 s 2.7 V AVREF < 2.85 V 14.0 100 s 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 4.0 V AVREF 5.5 V 2.5 LSB 2.7 V AVREF < 4.0 V 4.5 LSB 4.0 V AVREF 5.5 V 1.5 LSB 2.7 V AVREF < 4.0 V 2.0 LSB AVREF V Note 1 VAIN VSS In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 2. Excludes quantization error (1/2 LSB). 3. This value is indicated as a ratio (%FSR) to the full-scale value. Caution The conversion accuracy may be degraded when the analog input pin is used as an alternate I/O port or if a port is changed during A/D conversion. 350 User's Manual U16898EJ6V0UD CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C POC Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Conditions VPOC Detection voltage MIN. TYP. MAX. Unit 2.0 2.1 2.2 V s tPTH VDD: 0 V 2.1 V Response delay time 1 Note 1 tPTHD When power supply rises, after reaching detection voltage (MAX.) 3.0 ms Response delay time 2 Note 2 tPD When power supply falls 1.0 ms Power supply boot time Minimum pulse width Notes 1. 2. 1.5 tPW 0.2 ms Time required from voltage detection to internal reset release. Time required from voltage detection to internal reset signal generation. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time User's Manual U16898EJ6V0UD 351 CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C LVI Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Detection voltage Note 1 Response time TYP. MAX. Unit VLVI0 4.1 4.3 4.5 V VLVI1 3.9 4.1 4.3 V VLVI2 3.7 3.9 4.1 V VLVI3 3.5 3.7 3.9 V VLVI4 3.3 3.5 3.7 V VLVI5 3.15 3.3 3.45 V VLVI6 2.95 3.1 3.25 V VLVI7 2.7 2.85 3.0 V VLVI8 2.5 2.6 2.7 V VLVI9 2.25 2.35 2.45 V 0.2 2.0 ms tLW Operation stabilization wait time 2. MIN. tLD Minimum pulse width Notes 1. Conditions Note 2 0.2 tLWAIT ms 0.1 0.2 ms Time required from voltage detection to interrupt output or internal reset signal generation. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9 2. VPOC < VLVIm (m = 0 to 9) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION tLD 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Conditions MIN. Data retention supply voltage VDDDR 2.0 Release signal set time tSREL 0 352 User's Manual U16898EJ6V0UD TYP. MAX. Unit 5.5 V s CHAPTER 21 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) Standard product, (A) grade product TA = -40 to +85C Flash Memory Programming Characteristics (TA = -40 to +85C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Note 1 Erasure count Symbol Conditions IDD VDD = 5.5 V NERASE TA = -40 to +85C MIN. TYP. MAX. Unit 7.0 mA 1000 Times (per 1 block) Chip erase time Block erase time TCERASE TBERASE TA = -10 to +85C, 4.5 V VDD 5.5 V 0.8 s NERASE 100 3.5 V VDD < 4.5 V 1.0 s 2.7 V VDD < 3.5 V 1.2 s TA = -10 to +85C, 4.5 V VDD 5.5 V 4.8 s NERASE 1000 3.5 V VDD < 4.5 V 5.2 s 2.7 V VDD < 3.5 V 6.1 s TA = -40 to +85C, 4.5 V VDD 5.5 V 1.6 s NERASE 100 3.5 V VDD < 4.5 V 1.8 s 2.7 V VDD < 3.5 V 2.0 s TA = -40 to +85C, 4.5 V VDD 5.5 V 9.1 s NERASE 1000 3.5 V VDD < 4.5 V 10.1 s 2.7 V VDD < 3.5 V 12.3 s TA = -10 to +85C, 4.5 V VDD 5.5 V 0.4 s NERASE 100 3.5 V VDD < 4.5 V 0.5 s 2.7 V VDD < 3.5 V 0.6 s TA = -10 to +85C, 4.5 V VDD 5.5 V 2.6 s NERASE 1000 3.5 V VDD < 4.5 V 2.8 s 2.7 V VDD < 3.5 V 3.3 s 4.5 V VDD 5.5 V 0.9 s TA = -40 to +85C, NERASE 100 3.5 V VDD < 4.5 V 1.0 s 2.7 V VDD < 3.5 V 1.1 s TA = -40 to +85C, 4.5 V VDD 5.5 V 4.9 s NERASE 1000 3.5 V VDD < 4.5 V 5.4 s 2.7 V VDD < 3.5 V 6.6 s Byte write time TWRITE TA = -40 to +85C, NERASE 1000 150 s Internal verify TVERIFY Per 1 block 6.8 ms Per 1 byte 27 s Blank check TBLKCHK Retention years Per 1 block 480 , NERASE 1000 Note 2 TA = 85C 10 s Years Notes 1. Depending on the erasure count (NERASE), the erase time varies. Refer to the chip erase time and block erase time parameters. 2. When the average temperature when operating and not operating is 85C. Remark When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. User's Manual U16898EJ6V0UD 353 CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Symbol Conditions Ratings Unit VDD -0.3 to +6.5 V VSS -0.3 to +0.3 V AVREF -0.3 to VDD + 0.3 VI1 -0.3 to VDD + 0.3 VI2 P30, P31, P34, P40 to P45, P121 to P123 P20 to P23 Note 1 Note 1 -0.3 to AVREF + 0.3 Note 1 V V V and -0.3 to VDD + 0.3 Note 1 Output voltage VO -0.3 to VDD + 0.3 Analog input voltage VAN -0.3 to AVREF + 0.3 Note 1 Note 1 V V and -0.3 to VDD + 0.3 Note 1 Output current, high Output current, low IOH IOL Total loss PT Operating ambient TA Note 2 Per pin -7.0 mA Total of pins other than P20 to P23 -30.0 mA Total of P20 to P23 -30.0 mA Per pin 14.0 mA Total of all pins 30.0 mA TA = -40 to +85C 120 mW TA = +85 to +125C temperature Storage temperature Note 1. Tstg 110 mW In normal operation mode -40 to +125 C During flash memory programming -40 to +105 C Flash memory blank status -65 to +150 C Flash memory programming already performed -40 to +125 C Must be 6.5 V or lower Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. (Note 2 is listed on the next page.) 354 User's Manual U16898EJ6V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C This varies depending on the allowable total loss (see the figure below). Total loss PT [mW] Note 2. 150 120 110 100 50 -40 0 +40 +80 Temperature [C] +120 +85 +125 Use the following formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss PT (use at 80% or less of the rated value is recommended). * Total power consumption = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOH x IOL) When guaranteeing the internal pull-up resistor, use the following formula to calculate its power consumption, and add the result to the result above. * Power consumption of internal pull-up resistor = (VDD/RPU x VDD) User's Manual U16898EJ6V0UD 355 CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C X1 Oscillator Characteristics (TA = -40 to +125C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator Ceramic Recommended Circuit VSS X1 X2 Oscillation VSS X1 MAX. Unit 2.0 8.0 MHz X2 Oscillation 2.0 8.0 MHz MHz Note 2 frequency (fX) C1 C2 X1 2.7 V VDD 5.5 V 2.0 8.0 frequency (fX) 2.0 V VDD < 2.7 V 2.0 5.0 X1 input high- 2.7 V VDD 5.5 V 0.057 0.25 2.0 V VDD < 2.7 V 0.09 0.25 X1 input Note 2 /low-level width (tXH, tXL) Notes 1. TYP. C2 resonator clock MIN. frequency (fX) C1 External Conditions Note 2 resonator Crystal Parameter s Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.26 V (MAX.). 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 356 User's Manual U16898EJ6V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C High-Speed Internal Oscillator Characteristics (TA = -40 to +125C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator Parameter Conditions High-speed internal Oscillation frequency (fX = 8 oscillator MHz 2.7 V VDD 5.5 V Note 2 ) deviation Oscillation frequency (fX) Notes 1. MAX. Unit TA = -10 to +80C 3 % TA = -40 to +125C 5 % 2.0 V VDD < 2.7 V Note 2 MIN. TYP. 5.5 MHz Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.26 V (MAX.). 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Low-Speed Internal Oscillator Characteristics (TA = -40 to +125C, VDD = 2.0 to 5.5 VNote, VSS = 0 V) Resonator Low-speed internal Parameter Conditions Oscillation frequency (fRL) MIN. TYP. MAX. Unit 120 240 495 kHz oscillator Note Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.26 V (MAX.). User's Manual U16898EJ6V0UD 357 CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C DC Characteristics (TA = -40 to +125C, VDD = 2.0 to 5.5 VNote, VSS = 0 V) (1/2) Parameter Output current, high Symbol IOH1 IOH2 Output current, low Input voltage, high Input voltage, low Output voltage, high IOL Conditions MIN. TYP. MAX. Unit Pins other than Per pin 2.0 V VDD 5.5 V -3.5 mA P20 to P23 Total 4.0 V VDD 5.5 V -17.5 mA 2.0 V VDD < 4.0 V -10.5 mA P20 to P23 Per pin 2.0 V AVREF 5.5 V -3.5 mA Total 2.0 V AVREF 5.5 V -10.5 mA Per pin 2.0 V VDD 5.5 V 7.0 mA Total of all pins 4.0 V VDD 5.5 V 21.0 mA 2.0 V VDD < 4.0 V 10.5 mA 0.8VDD VDD V VIH1 P30, P31, P34, P40 to P45, P123 VIH2 P20 to P23 0.7AVREF AVREF V VIH3 P121, P122 0.8VDD VDD V VIL1 P30, P31, P34, P40 to P45, P123 0 0.2VDD V VIL2 P20 to P23 0 0.3AVREF V VIL3 P121, P122 0 0.2VDD V VOH1 Total of pins other than 4.0 V VDD 5.5 V P20 to P23 IOH1 = -3.5 mA VDD - 1.0 V VDD - 0.5 V IOH1 = -10.5 mA VOH2 IOH1 = -100 A 2.0 V VDD < 4.0 V Total of pins P20 to P23 4.0 V AVREF 5.5 V AVREF - 1.0 IOH2 = -3.5 mA V AVREF - 0.5 V IOH2 = -7 mA 2.0 V AVREF < 4.0 V IOH2 = -100 A Output voltage, low VOL Total of pins 4.0 V VDD 5.5 V IOL = 21 mA IOL = 7 mA 2.0 V VDD 4.0 V 1.3 V 0.4 V IOL = 400 A Input leakage current, high ILIH VI = VDD Pins other than X1 10 A Input leakage current, low VI = 0 V Pins other than X1 -10 A Output leakage current, high ILOH VO = VDD Pins other than X2 10 A Output leakage current, low ILOL VO = 0 V Pins other than X2 -10 A Pull-up resistance RPU VI = 0 V 10 30 120 k Pull-down resistance RPD P121, P122, reset state 10 30 120 k ILIL Note Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.26 (MAX.). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 358 User's Manual U16898EJ6V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C DC Characteristics (TA = -40 to +125C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) (2/2) Parameter Note 3 Supply current Symbol IDD1 Note 2 Conditions Crystal/ceramic fX = 8 MHz oscillation, external VDD = 5.0 V 10% fX = 6 MHz clock input oscillation operating mode Note 6 MIN. TYP. MAX. Unit When A/D converter is stopped 5.8 12.8 Note 8 When A/D converter is operating 7.3 15.8 When A/D converter is stopped 5.5 12.2 Note 4 VDD = 5.0 V 10% When A/D converter is operating fX = 5 MHz When A/D converter is stopped Note 4 Note 8 IDD2 3.0 6.6 When A/D converter is operating 4.5 9.6 Crystal/ceramic fX = 8 MHz When peripheral functions are stopped 1.5 4.6 oscillation, external VDD = 5.0 V 10% When peripheral functions are operating fX = 6 MHz When peripheral functions are stopped clock input HALT mode Note 6 Note 8 mA 15.2 VDD = 3.0 V 10% Note 5 mA mA mA Note 4 VDD = 5.0 V 10% When peripheral functions are operating fX = 5 MHz When peripheral functions are stopped 7.6 1.3 4.2 mA Note 4 7.2 0.48 1.6 VDD = 3.0 V 10% When peripheral functions are operating High-speed internal fX = 8 MHz When A/D converter is stopped 5.0 12.2 oscillation operating VDD = 5.0 V 10% Note 8 When A/D converter is operating 6.5 15.2 High-speed internal fX = 8 MHz When peripheral functions are stopped 1.4 4.4 oscillation HALT VDD = 5.0 V 10% When peripheral functions are operating VDD = 5.0 V 10% When low-speed internal mA Note 5 Note 3 IDD3 Note 4 Note 7 2.7 mA mode IDD4 mA Note 4 Note 7 7.1 mode IDD5 STOP mode 3.5 1200 A oscillation is stopped When low-speed internal 17.5 1300 oscillation is operating VDD = 3.0 V 10% When low-speed internal 3.5 600 11.0 700 A oscillation is stopped When low-speed internal oscillation is operating Notes 1. Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.26 V (MAX.). 2. Total current flowing through the internal power supply (VDD). Peripheral operation current is included 3. IDD1 includes peripheral operation current. 4. When the processor clock control register (PCC) is set to 00H. 5. When the processor clock control register (PCC) is set to 02H. (however, the current that flows through the pull-up resistors of ports is not included). 6. When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using the option byte. 7. When the high-speed internal oscillation clock is selected as the system clock source using the option byte. 8. The current that flows through the AVREF pin is included. User's Manual U16898EJ6V0UD 359 CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C AC Characteristics (1) Basic operation (TA = -40 to +125C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Parameter Symbol Cycle time (minimum TCY instruction execution time) TI000 input high-level width, tTIH, low-level width tTIL Conditions MIN. tINTH, tINTL RESET input low-level tRSL Unit 4.0 V VDD 5.5 V 0.25 16 s clock, external clock input 3.0 V VDD < 4.0 V 0.33 16 s 2.7 V VDD < 3.0 V 0.4 16 s 2.0 V VDD < 2.7 V 1 16 s High-speed internal 4.0 V VDD 5.5 V 0.23 4.22 s oscillation clock 2.7 V VDD < 4.0 V 0.47 4.22 s 2.0 V VDD < 2.7 V 0.95 4.22 s 4.0 V VDD 5.5 V s 2/fsam+ 0.1 Note 2 s 2/fsam+ 0.2 width, low-level width MAX. Crystal/ceramic oscillation 2.0 V VDD < 4.0 V Interrupt input high-level TYP. Note 2 1 s 2 s width Notes 1. Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.26 V (MAX.). 2. Selection of fsam = fXP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP. CPU Clock Frequency, Peripheral Clock Frequency Parameter Conditions CPU Clock (fCPU) Ceramic resonator, 4.0 V VDD 5.5 V 125 kHz fCPU 8 MHz crystal resonator, 3.0 V VDD < 4.0 V 125 kHz fCPU 6 MHz external clock 2.7 V VDD < 3.0 V 2.0 V VDD < 2.7 V High-speed internal 4.0 V VDD 5.5 V oscillator 2.7 V VDD < 4.0 V 2.0 V VDD < 2.7 V Peripheral Clock (fXP) 500 kHz fXP 8 MHz 125 kHz fCPU 5 MHz Note 125 kHz fCPU 2 MHz 500 kHz fXP 5 MHz 500 kHz (TYP.) fCPU 8 MHz (TYP.) 2 MHz (TYP.) fXP 8 MHz (TYP.) 500 kHz (TYP.) fCPU 4 MHz (TYP.) Note 500 kHz (TYP.) fCPU 2 MHz (TYP.) 2 MHz (TYP.) fXP 4 MHz (TYP.) Note Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.26 V (MAX.). 360 User's Manual U16898EJ6V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C TCY vs. VDD (Crystal/Ceramic Oscillation Clock, External Clock Input) 60 16 Cycle time TCY [s] 10 Guaranteed operation range 1.0 0.4 0.33 0.25 0.1 1 2 3 4 5 6 5.5 2.7 Supply voltage VDD [V] TCY vs. VDD (High-Speed Internal Oscillation Clock) 60 Cycle time TCY [s] 10 4.22 Guaranteed operation range 1.0 0.95 0.47 0.23 0.1 1 2 3 4 5 6 2.7 5.5 Supply voltage VDD [V] User's Manual U16898EJ6V0UD 361 CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C (2) Serial interface (TA = -40 to +125C, VDD = 2.0 to 5.5 VNote, VSS = 0 V) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions MIN. Transfer rate TYP. MAX. Unit 312.5 kbps Note Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.26 V (MAX.). AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH X1 input TI000 Timing tTIL tTIH TI000 Interrupt Input Timing tINTL tINTH INTP0 to INTP3 RESET Input Timing tRSL RESET 362 User's Manual U16898EJ6V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C A/D Converter Characteristics (TA = -40 to +125C, 2.7 V AVREF VDD 5.5 V, VSS = 0 VNote 1) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 bit 4.0 V AVREF 5.5 V 0.2 0.7 %FSR 2.7 V AVREF < 4.0 V 0.3 0.9 %FSR Resolution Notes 2, 3 Overall error AINL Conversion time tCONV Notes 2, 3 Zero-scale error Full-scale error Ezs Notes 2, 3 Efs Note 2 Integral non-linearity error Differential non-linearity error Analog input voltage Notes 1. Note 2 ILE DLE 4.5 V AVREF 5.5 V 3.0 30 s 4.0 V AVREF < 4.5 V 4.8 30 s 2.85 V AVREF < 4.0 V 6.0 30 s 2.7 V AVREF < 2.85 V 14.0 30 s 4.0 V AVREF 5.5 V 0.7 %FSR 2.7 V AVREF < 4.0 V 0.9 %FSR 4.0 V AVREF 5.5 V 0.7 %FSR 2.7 V AVREF < 4.0 V 0.9 %FSR 4.0 V AVREF 5.5 V 5.5 LSB 2.7 V AVREF < 4.0 V 7.5 LSB 4.0 V AVREF 5.5 V 2.5 LSB 2.7 V AVREF < 4.0 V 3.0 LSB AVREF V Note 1 VAIN VSS In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 2. Excludes quantization error (1/2 LSB). 3. This value is indicated as a ratio (%FSR) to the full-scale value. Caution The conversion accuracy may be degraded when the analog input pin is used as an alternate I/O port or if a port is changed during A/D conversion. User's Manual U16898EJ6V0UD 363 CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C POC Circuit Characteristics (TA = -40 to +125C) Parameter Symbol Conditions VPOC Detection voltage MIN. TYP. MAX. Unit 2.0 2.1 2.26 V s tPTH VDD: 0 V 2.1 V Response delay time 1 Note 1 tPTHD When power supply rises, after reaching detection voltage (MAX.) 3.0 ms Response delay time 2 Note 2 tPD When power supply falls 1.0 ms Power supply boot time Minimum pulse width Notes 1. 2. 1.5 tPW 0.2 ms Time required from voltage detection to internal reset release. Time required from voltage detection to internal reset signal generation. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time 364 User's Manual U16898EJ6V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C LVI Circuit Characteristics (TA = -40 to +125C) Parameter Symbol Detection voltage Note 1 Response time TYP. MAX. Unit VLVI0 4.1 4.3 4.65 V VLVI1 3.9 4.1 4.45 V VLVI2 3.7 3.9 4.25 V VLVI3 3.5 3.7 4.05 V VLVI4 3.3 3.5 3.85 V VLVI5 3.15 3.3 3.60 V VLVI6 2.95 3.1 3.40 V VLVI7 2.7 2.85 3.15 V VLVI8 2.5 2.6 2.85 V VLVI9 2.25 2.35 2.60 V 0.2 2.0 ms tLW Operation stabilization wait time 2. MIN. tLD Minimum pulse width Notes 1. Conditions Note 2 0.2 tLWAIT ms 0.1 0.2 ms Time required from voltage detection to interrupt output or internal reset signal generation. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9 2. VPOC < VLVIm (m = 0 to 9) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION tLD 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +125C) Parameter Symbol Conditions MIN. Data retention supply voltage VDDDR 2.0 Release signal set time tSREL 0 User's Manual U16898EJ6V0UD TYP. MAX. Unit 5.5 V s 365 CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C Flash Memory Programming Characteristics (TA = -40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Note 1 Erasure count Symbol Conditions MIN. TYP. MAX. Unit 7.0 mA IDD VDD = 5.5 V NERASE TA = -40 to +105C TCERASE TA = -10 to +105C, 4.5 V VDD 5.5 V 0.8 s NERASE 100 3.5 V VDD < 4.5 V 1.0 s 2.7 V VDD < 3.5 V 1.2 s 1000 Times (per 1 block) Chip erase time Block erase time TBERASE TA = -10 to +105C, 4.5 V VDD 5.5 V 4.8 s NERASE 1000 3.5 V VDD < 4.5 V 5.2 s 2.7 V VDD < 3.5 V 6.1 s TA = -40 to +105C, 4.5 V VDD 5.5 V 1.6 s NERASE 100 3.5 V VDD < 4.5 V 1.8 s 2.7 V VDD < 3.5 V 2.0 s TA = -40 to +105C, 4.5 V VDD 5.5 V 9.1 s NERASE 1000 3.5 V VDD < 4.5 V 10.1 s 2.7 V VDD < 3.5 V 12.3 s TA = -10 to +105C, 4.5 V VDD 5.5 V 0.4 s NERASE 100 3.5 V VDD < 4.5 V 0.5 s 2.7 V VDD < 3.5 V 0.6 s TA = -10 to +105C, 4.5 V VDD 5.5 V 2.6 s NERASE 1000 3.5 V VDD < 4.5 V 2.8 s 2.7 V VDD < 3.5 V 3.3 s TA = -40 to +105C, 4.5 V VDD 5.5 V 0.9 s NERASE 100 3.5 V VDD < 4.5 V 1.0 s 2.7 V VDD < 3.5 V 1.1 s TA = -40 to +105C, 4.5 V VDD 5.5 V 4.9 s NERASE 1000 3.5 V VDD < 4.5 V 5.4 s 2.7 V VDD < 3.5 V 6.6 s Byte write time TWRITE TA = -40 to +105C, NERASE 1000 150 s Internal verify TVERIFY Per 1 block 6.8 ms Per 1 byte 27 s Per 1 block 480 s TA = -40 to +105C 120 mW Blank check TBLKCHK Total loss PT Note 3 Retention years , NERASE 1000 Note 2 TA = 85C 10 Years Notes 1. Depending on the erasure count (NERASE), the erase time varies. Refer to the chip erase time and block erase time parameters. 2. When the average temperature when operating and not operating is 85C. Remark When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. (Note 3 is listed on the next page.) 366 User's Manual U16898EJ6V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS ((A2) grade product) (A2) grade product TA = -40 to +125C Note 3. When guaranteeing the flash self programming, use the following formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss PT (use at 80% or less of the rated value is recommended). * Total power consumption = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOH x IOL) When guaranteeing the internal pull-up resistor, use the following formula to calculate its power consumption, and add the result to the result above. * Power consumption of internal pull-up resistor = (VDD/RPU x VDD) Remark During flash memory programming, IDD = 7.0 mA (MAX.). User's Manual U16898EJ6V0UD 367 CHAPTER 23 PACKAGE DRAWING <R> * PD78F9221MC-5A4-A, 78F9222MC-5A4-A, 78F9224MC-5A4-A, 78F9221MC(A)-5A4-A, 78F9222MC(A)-5A4-A, 78F9221MC(A2)-5A4-A, 78F9222MC(A2)-5A4-A 20-PIN PLASTIC SSOP (7.62 mm (300)) 20 11 detail of lead end F G T P L U E 1 10 A H J I S N S K C D M M B NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 6.650.15 B 0.475 MAX. C 0.65 (T.P.) D 0.24 +0.08 -0.07 E 0.10.05 F 1.30.1 G 1.2 H 8.10.2 I 6.10.2 J 1.00.2 K 0.170.03 L 0.5 M 0.13 N 0.10 P 3 +5 -3 T 0.25 U 0.60.15 S20MC-65-5A4-2 368 User's Manual U16898EJ6V0UD CHAPTER 23 PACKAGE DRAWING * PD78F9221MC(A)-CAA-AX, 78F9222MC(A)-CAA-AX, 78F9221MC(A2)-CAA-AX, 78F9222MC(A2)-CAA-AX 20-PIN PLASTIC SSOP (7.62 mm (300)) V 11 20 detail of lead end T I P L 10 1 U V W A W H F G J S C E D N M M K S (UNIT:mm) B ITEM A B NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 6.500.10 0.325 C 0.65 (T.P.) D 0.22 +0.10 -0.05 E 0.100.05 F 1.300.10 G 1.20 H 8.100.20 I 6.100.10 J 1.000.20 K 0.15 +0.05 -0.01 L 0.50 M 0.13 N 0.10 P 3 +5 -3 T 0.25(T.P) U 0.600.15 V W User's Manual U16898EJ6V0UD DIMENSIONS 0.25 MAX. 0.15 MAX. P20MC-65-CAA 369 CHAPTER 23 PACKAGE DRAWING * PD78F9221CS-CAC-A, 78F9222CS-CAC-A 20-PIN PLASTIC SDIP (7.62mm (300)) D 11 20 E 10 1 B A e1 A2 C L A1 b2 b1 Z b e x M c C A B A (UNIT:mm) ITEM DIMENSIONS D 17.57 MAX. E 6.60 A A1 A2 e 3.70 MAX. 0.65 0.10 2.80 1.778 e1 7.62 b 0.52 0.10 b1 1.02 0.10 b2 0.77 0.10 c 0.27 0.07 L 2.86 0.20 x 0.25 Z 0 to 5 0.609 P20CS-70-CAC 370 User's Manual U16898EJ6V0UD CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Cautions 1. Products with -A or -AX at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 24-1. Surface Mounting Type Soldering Conditions (1/2) * 20-pin plastic SSOP (lead-free products) <R> PD78F9221MC-5A4-A, 78F9222MC-5A4-A, 78F9224MC-5A4-A, 78F9221MC(A)-5A4-A, 78F9222MC(A)-5A4-A, PD78F9221MC(A2)-5A4-A, 78F9222MC(A2)-5A4-A Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Note Count: 3 times or less, Exposure limit: 7 days 20 to 72 hours) IR60-207-3 (after that, prebake at 125C for Wave soldering For details, contact an NEC Electronics sales representative. - Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Notes After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). User's Manual U16898EJ6V0UD 371 CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS Table 24-1. Surface Mounting Type Soldering Conditions (2/2) * 20-pin plastic SSOP (lead-free products) PD78F9221MC(A)-CAA-AX, 78F9222MC(A)-CAA-AX, 78F9221MC(A2)-CAA-AX, 78F9222MC(A2)-CAA-AX Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Note Count: 3 times or less, Exposure limit: 7 days 10 to 72 hours) Wave soldering Recommended Condition Symbol IR60-107-3 (after that, prebake at 125C for Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, WS60-107-1 Preheating temperature: 120C max. (package surface temperature), Exposure Note limit: 7 days (after that, prebake at 125C for 10 to 72 hours) Partial heating Notes Pin temperature: 350C max., Time: 3 seconds max. (per pin row) After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). * 20-pin plastic SDIP (lead-free products) PD78F9221CS-CAC-A, 78F9222CS-CAC-A Soldering Method Soldering Conditions Wave soldering (only for pins) Solder bath temperature: 260C, Time: 10 seconds max. Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per one pin) Caution Only the pins of the THD are heated when performing wave soldering. Make sure that flow solder does not come in contact with the package. 372 - User's Manual U16898EJ6V0UD <R> APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the 78K0S/KA1+. Figure A-1 shows the development tool configuration. User's Manual U16898EJ6V0UD 373 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) (1) When using the in-circuit emulator QB-78K0SKX1 Software package * Software package Debugging software Language processing software * Assembler package * Integrated debuggerNote 1 * C compiler package * System simulatorNote 2 * Device fileNote 1 Control software * Project manager (Windows only)Note 3 Host machine (PC or EWS) USB interface cableNote 4 Power supply unit QB-78K0SKX1Note 4 < Flash memory write environment > Flash memory programmerNote 4 Off-board programming Emulation probe On-board programming Conversion adapter Flash memory write adapter 78K0/Kx1+ Target connector Target system Notes 1. Download the device file for 78K0S/Kx1+ microcontrollers (DF789234) and the integrated debugger ID78K0S-QB from the download site for development tools (http://www.necel.com/micro/en/ods/). 2. SM+ for 78K0S (instruction simulation version) is included in the software package. SM+ for 78K0S/Kx1+ (instruction + peripheral simulation version) is not included. 3. The project manager PM+ is included in the assembler package. PM+ cannot be used other than with WindowsTM. 4. QB-78K0SKX1 is supplied with the integrated debugger ID78K0S-QB, a USB interface cable, the onchip debug emulator with programming function QB-MINI2, a connection cable, and a target cable. Any other products are sold separately. 374 User's Manual U16898EJ6V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using the on-chip debug emulator with programming function QB-MINI2 Software package * Software package Debugging software Language processing software * Assembler package * Integrated debuggerNote 1 * C compiler package * System simulatorNote 2 * Device fileNote 1 Control software * Project manager (Windows only)Note 3 Host machine (PC or EWS) USB interface cableNote 4 QB-MINI2Note 4 Connection cableNote 4 Target connector Target system Notes 1. Download the device file for 78K0S/Kx1+ microcontrollers (DF789234) and the integrated debugger ID78K0S-QB from the download site for development tools (http://www.necel.com/micro/en/ods/). 2. SM+ for 78K0S (instruction simulation version) is included in the software package. SM+ for 78K0S/Kx1+ (instruction + peripheral simulation version) is not included. 3. The project manager PM+ is included in the assembler package. PM+ cannot be used other than with Windows. 4. QB-MINI2 is supplied with USB interface cable and connection cable. Any other products are sold separately. In addition, download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/). User's Manual U16898EJ6V0UD 375 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package Development tools (software) common to the 78K0S microcontrollers are combined in this package. SP78K0S 78K0S microcontroller software package A.2 Language Processing Software RA78K0S Note 1 This assembler converts programs written in mnemonics into object codes executable with a Assembler package microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF789234). <Precaution when using RA78K0S in PC environment> This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (PM+) on Windows. PM+ is included in assembler package. CC78K0S Note 1 This compiler converts programs written in C language into object codes executable with a C compiler package microcontroller. This compiler should be used in combination with an assembler package and device file. <Precaution when using CC78K0S in PC environment> This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (PM+) on Windows. PM+ is included in assembler package. Note 2 DF789234 This file contains information peculiar to the device. Device file This device file should be used in combination with a tool (RA78K0S, CC78K0S, ID78K0S-QB, and the system simulator). The corresponding OS and host machine differ depending on the tool to be used. Notes 1. If the versions of RA78K0S and CC78K0S are Ver.2.00 or later, different versions of RA78K0S and 2. The DF789234 can be used in common with the RA78K0S, CC78K0S, ID78K0S-QB, and the system CC78K0S can be installed on the same machine. simulator. Download the DF789234 from the download site for development tools (http://www.necel.com/micro/en/ods/). 376 User's Manual U16898EJ6V0UD APPENDIX A DEVELOPMENT TOOLS A.3 Flash Memory Writing Tools A.3.1 When using flash memory programmer PG-FP5 and FL-PR5 FL-PR5, PG-FP5 This is a flash memory programmer dedicated to microcontrollers incorporating a flash Flash memory programmer memory. FA-78F9222MC-5A4-RX Flash memory writing adapter This is a flash memory writing adapter which is used in connection with the flash memory programmer. Remarks 1. FL-PR5 and FA-78F9222MC-5A4-RX are products of Naito Densei Machida Mfg. Co., Ltd (http://www.ndk-m.co.jp/, TEL: +81-42-750-4172). 2. Use the latest version of the flash memory programming adapter. A.3.2 When using on-chip debug emulator with programming function QB-MINI2 QB-MINI2 This is a flash memory programmer dedicated to microcontrollers with on-chip flash On-chip debug emulator with memory. It is available also as on-chip debug emulator which serves to debug hardware programming function and software when developing application systems using the 78K0S/Kx1+ microcontrollers. When using this as flash memory programmer, it should be used in combination with a connection cable and a USB interface cable that is used to connect the host machine. Target connector specifications 16-pin general-purpose connector (2.54 mm pitch) Remark Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/). A.4 Debugging Tools (Hardware) A.4.1 When using in-circuit emulator QB-78K0SKX1 QB-78K0SKX1 This in-circuit emulator serves to debug hardware and software when developing application In-circuit emulator systems using the 78K0S/Kx1+ microcontrollers. It supports the integrated debugger (ID78K0S-QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine. Note QB-50-EP-01T This is a flexible type emulation probe and is used to connect the in-circuit emulator and target Emulation probe system. Note QB-20MC-EA-01T Exchange adapter This exchange adapter is used to perform pin conversion from the in-circuit emulator to target connector. Note QB-20MC -NQ-01T This target connector is used to mount on the target system. Target connector Specifications of pin header on 0.635 mm x 0.635 mm (height: 6 mm) target system (Note and Remarks are listed on the next page or later.) User's Manual U16898EJ6V0UD 377 APPENDIX A DEVELOPMENT TOOLS Note The part numbers of the exchange adapter and target connector and the packages of the target device are described below. Package Exchange Adapter 20-pin plastic SSOP Target Connector QB-20MC-EA-01T QB-20MC-NQ-01T None None (MC-5A4 and MC-CAA types) 20-pin plastic SDIP (CS-CAC type) Remarks 1. For the SDIP package, use the target cable. 2. The QB-78K0SKX1 is supplied with the integrated debugger ID78K0S-QB, a USB interface cable, the on-chip debug emulator QB-MINI2, and a connection cable. Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/) when using the QB-MINI2. 3. The packed contents of QB-78K0SKX1 differ depending on the part number, as follows. Packed Contents In-Circuit Emulator Emulation Probe Exchange Adapter Target Connector Part Number QB-78K0SKX1-ZZZ QB-78K0SKX1 QB-78K0SKX1-T20MC None QB-50-EP-01T QB-20MC-EA-01T QB-20MC-NQ-01T A.4.2 When using on-chip debug emulator with programming function QB-MINI2 QB-MINI2 This on-chip debug emulator serves to debug hardware and software when developing On-chip debug emulator with application systems using the 78K0/Kx1+ microcontrollers. It is available also as flash programming function memory programmer dedicated to microcontrollers with on-chip flash memory. When using this as on-chip debug emulator, it should be used in combination with a connection cable and a USB interface cable that is used to connect the host machine. Target connector specifications 16-pin general-purpose connector (2.54 mm pitch) Remark Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/). 378 User's Manual U16898EJ6V0UD APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) ID78K0S-QB Note This debugger supports the in-circuit emulators for the 78K0S/Kx1+ microcontrollers. The (supporting ID78K0S-QB is Windows-based software. QB-78K0SKX1, QB-MINI2) Provided with the debug function supporting C language, source programming, disassemble Integrated debugger display, and memory display are possible. It should be used in combination with the device file (DF789234). SM+ for 78K0S SM+ for 78K0S/Kx1+ System simulator System simulator is Windows-based software. Note It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of system simulator allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. System simulator should be used in combination with the device file (DF789234). The following two types of system simulators supporting the 78K0S/Kx1+ microcontrollers are available. * SM+ for 78K0S (instruction simulation version) This can only simulate a CPU. It is included in the software package. * SM+ for 78K0S/Kx1+ (instruction + peripheral simulation version) This can simulate a CPU and peripheral hardware (ports, timers, serial interfaces, etc.). Note Download the ID78K0S-QB from the download site for development tools (http://www.necel.com/micro/en/ods/). User's Manual U16898EJ6V0UD 379 APPENDIX B NOTES ON DESIGNING TARGET SYSTEM This chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the QB-78K0SKX1 is used. For the package drawings of the target connector, exchange adapter, and emulation probe, see the following website. http://www.necel.com/micro/en/development/asia/iecube/outline_QB.html Figure B-1. When using the 78K0S/Kx1+ emulation probe (For 20-Pin MC Package) Top view Unit : mm 8.2 7.1 16.0 : 1pin Center point of Target connector 4.2 8.1 14.5 : Exchange adapter tip area Components up to 11.0 mm high can be mounted. : Exchange adapter mounted-component area Components up to 2.0 mm high can be mounted. : Target connector area <Overview> Viewing direction IECUBE TC EP EA Note EP: Emulation probe EA: Exchange adapter TC: Target connector 380 User's Manual U16898EJ6V0UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. When using the 78K0S/Kx1+ target cable (single track) Top view Unit : mm 2.54 2.54 : A interval pin header More than 2.54mm : A contact area of a pin header 0.635 x 0.635mm (Height: 6mm) <Overview> Viewing direction IECUBE Target cable Pin header User's Manual U16898EJ6V0UD 381 APPENDIX C REGISTER INDEX C.1 Register Index (Register Name) 8-bit A/D conversion result register (ADCRH) ... 170 8-bit compare register 80 (CR80) ... 130 8-bit timer counter 80 (TM80) ... 130 8-bit timer H compare register 01 (CMP01) ... 137 8-bit timer H compare register 11 (CMP11) ... 137 8-bit timer H mode register 1 (TMHMD1) ... 138 8-bit timer mode control register 80 (TMC80) ... 131 10-bit A/D conversion result register (ADCR) ... 169 16-bit timer capture/compare register 000 (CR000) ... 89 16-bit timer capture/compare register 010 (CR010) ... 91 16-bit timer counter 00 (TM00) ... 89 16-bit timer mode control register 00 (TMC00) ... 92 16-bit timer output control register 00 (TOC00) ... 95 [A] A/D converter mode register (ADM) ... 167 Analog input channel specification register (ADS) ... 169 Asynchronous serial interface control register 6 (ASICL6) ... 195 Asynchronous serial interface operation mode register 6 (ASIM6) ... 189 Asynchronous serial interface reception error status register 6 (ASIS6) ... 191 Asynchronous serial interface transmission status register 6 (ASIF6) ... 192 [B] Baud rate generator control register 6 (BRGC6) ... 194 [C] Capture/compare control register 00 (CRC00) ... 94 Clock selection register 6 (CKSR6) ... 193 [E] External interrupt mode register 0 (INTM0) ... 226 External interrupt mode register 1 (INTM1) ... 227 [F] Flash address pointer H (FLAPH) ... 286 Flash address pointer L (FLAPL) ... 286 Flash address pointer H compare register (FLAPHC) ... 287 Flash address pointer L compare register (FLAPLC) ... 287 Flash status register (PFS) ... 284 Flash programming command register (FLCMD) ... 285 Flash programming mode control register (FLPMC) ... 282 Flash protect command register (PFCMD) ... 283 Flash write buffer register (FLW) ... 288 382 User's Manual U16898EJ6V0UD APPENDIX C REGISTER INDEX [I] Input switch control register (ISC) ... 197 Interrupt mask flag register 0 (MK0) ... 225 Interrupt mask flag register 1 (MK1) ... 225 Interrupt request flag register 0 (IF0) ... 224 Interrupt request flag register 1 (IF1) ... 224 [L] Low voltage detect register (LVIM) ... 256 Low voltage detection level select register (LVIS) ... 257 Low-speed internal oscillation mode register (LSRCM) ... 75 [O] Oscillation stabilization time select register (OSTS) ... 76, 235 [P] Port mode control register 2 (PMC2) ... 67, 170 Port mode register 2 (PM2) ... 65, 170 Port mode register 3 (PM3) ... 65, 97 Port mode register 4 (PM4) ... 65, 140, 197 Port mode register 12 (PM12) ... 65 Port register 2 (P2) ... 66 Port register 3 (P3) ... 66 Port register 4 (P4) ... 66 Port register 12 (P12) ... 66 Port register 13 (P13) ... 66 Preprocessor clock control register (PPCC) ... 74 Prescaler mode register 00 (PRM00) ... 96 Processor clock control register (PCC) ... 74 Pull-up resistor option register 2 (PU2) ... 69 Pull-up resistor option register 3 (PU3) ... 69 Pull-up resistor option register 4 (PU4) ... 69 Pull-up resistor option register 12 (PU12) ... 69 [R] Receive buffer register 6 (RXB6) ... 188 Reset control flag register (RESF) ... 250 [T] Transmit buffer register 6 (TXB6) ... 188 [W] Watchdog timer enable register (WDTE) ... 154 Watchdog timer mode register (WDTM) ... 153 User's Manual U16898EJ6V0UD 383 APPENDIX C REGISTER INDEX C.2 Register Index (Symbol) [A] ADCR: 10-bit A/D conversion result register ... 169 ADCRH: 8-bit A/D conversion result register ... 170 ADM: A/D converter mode register ... 167 ADS: Analog input channel specification register ... 169 ASICL6: Asynchronous serial interface control register 6 ... 195 ASIF6: Asynchronous serial interface transmission status register 6 ... 192 ASIM6: Asynchronous serial interface operation mode register 6 ... 189 ASIS6: Asynchronous serial interface reception error status register 6 ... 191 [B] BRGC6: Baud rate generator control register 6 ... 194 [C] CKSR6: Clock selection register 6 ... 193 CMP01: 8-bit timer H compare register 01 ... 137 CMP11: 8-bit timer H compare register 11 ... 137 CR000: 16-bit timer capture/compare register 000 ... 89 CR010: 16-bit timer capture/compare register 010 ... 91 CR80: 8-bit compare register 80 ... 130 CRC00: Capture/compare control register 00 ... 94 [F] FLAPH: Flash address pointer H ... 286 FLAPHC: Flash address pointer H compare register ... 287 FLAPL: Flash address pointer L ... 286 FLAPLC: Flash address pointer L compare register ... 287 FLCMD: Flash programming command register ... 285 FLPMC: Flash programming mode control register ... 282 FLW: Flash write buffer register ... 288 [I] IF0: Interrupt request flag register 0 ... 224 IF1: Interrupt request flag register 1 ... 224 INTM0: External interrupt mode register 0 ... 226 INTM1: External interrupt mode register 1 ... 227 ISC: Input switch control register ... 197 [L] LSRCM: Low-speed internal oscillation mode register ... 75 LVIM: Low voltage detect register ... 256 LVIS: Low voltage detection level select register ... 257 [M] MK0: Interrupt mask flag register 0 ... 225 MK1: Interrupt mask flag register 1 ... 225 384 User's Manual U16898EJ6V0UD APPENDIX C REGISTER INDEX [O] OSTS: Oscillation stabilization time select register ... 76, 235 [P] P2: Port register 2 ... 66 P3: Port register 3 ... 66 P4: Port register 4 ... 66 P12: Port register 12 ... 66 P13: Port register 13 ... 66 PCC: Processor clock control register ... 74 PFCMD: Flash protect command register ... 283 PFS: Flash status register ... 284 PM2: Port mode register 2 ... 65, 170 PM3: Port mode register 3 ... 65, 97 PM4: Port mode register 4 ... 65, 140, 197 PM12: Port mode register 12 ... 65 PMC2: Port mode control register 2 ... 67, 170 PPCC: Preprocessor clock control register ... 74 PRM00: Prescaler mode register 00 ... 96 PU2: Pull-up resistor option register 2 ... 69 PU3: Pull-up resistor option register 3 ... 69 PU4: Pull-up resistor option register 4 ... 69 PU12: Pull-up resistor option register 12 ... 69 [R] RESF: Reset control flag register ... 250 RXB6: Receive buffer register 6 ... 188 [T] TM00: 16-bit timer counter 00 ... 89 TM80: 8-bit timer counter 80 ... 130 TMC00: 16-bit timer mode control register 00 ... 92 TMC80: 8-bit timer mode control register 80 ... 131 TMHMD1: 8-bit timer H mode register 1 ... 138 TOC00: 16-bit timer output control register 00 ... 95 TXB6: Transmit buffer register 6 ... 188 [W] WDTE: Watchdog timer enable register ... 154 WDTM: Watchdog timer mode register ... 153 User's Manual U16898EJ6V0UD 385 APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. "Classification (hard/soft)" in table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs Hard Classification Soft Hard Chapter 3 Chapter 2 Chapter (1/19) Function Details of Function Cautions Page Pin functions P121/X1, P122/X2 The P121/X1 and P122/X2 pins are pulled down during reset. pp. 21, Memory space Vector table address No interrupt sources correspond to the vector table address 0014H. p. 30 SP: stack pointer Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack memory. p. 35 SP: Stack pointer Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits can be actually set. p. 35 22, 24, 25 Thus, if the stack pointer is specified to 0FF00H, it is converted to 0FB00H in the high-speed RAM area, since 0FF00H is in the SFR area and not in the highspeed RAM area. Hard Chapter 4 When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to become 0FAFFH, but since that value is not in the high-speed RAM area, it is converted to 0FEFFH, which is the same value as when 0FF00H is set to the stack pointer. Port functions P121/X1, P122/X2 The P121/X1 and P122/X2 pins are pulled down during reset. p. 54 P34 Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Also, since the option byte is referenced after the reset release, if low level is input to the RESET pin before the referencing, then the reset state is not released. When it is used as an input port pin, connect the pull-up resistor. p. 58 P31, P31, P43 Because P30, P31, and P43 are also used as external interrupt pins, the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. To use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance. p. 65 PMC2: Port mode control register 2 When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot be p. 68 used as port pins. Be sure to set the pull-up resistor option registers (PU20 to PU23) to 0 for the pins set to A/D converter mode. - 386 Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and outputs. User's Manual U16898EJ6V0UD p. 70 APPENDIX D LIST OF CAUTIONS Soft Classification Hard Chapter 5 Chapter (2/19) Function Main clock Crystal/ ceramic oscillator Details of Function OSTS: Oscillation stabilization time select register - Cautions Page To set and then release the STOP mode, set the oscillation stabilization time as p. 76 follows. Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset input or interrupt generation. p. 76 The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. p. 76 When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken lines in Figure 5-6 to avoid an adverse effect from wiring capacitance. p. 77 * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. Hard Soft Hard Chapter 6 * Do not fetch signals from the oscillator. 16-bit timer/ TM00: 16-bit event timer counter counter 00 00 CR000: 16-bit timer capture/ compare register 000 Even if TM00 is read, the value is not captured by CR010. pp. 89, 121 When TM00 is read, count misses do not occur, since the input of the count clock is temporarily stopped and then resumed after the read. pp. 89, 121 Set CR000 to other than 0000H in the clear & start mode entered on match between TM00 and CR000. This means a 1-pulse count operation cannot be performed when this register is used as an external event counter. pp. 90, 121 In the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H following overflow (FFFFH). pp. 90, 121 If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR000 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR000 is changed. pp. 90, 121 The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed. pp. 90, 122 The capture operation may not be performed for CR000 set in compare mode even if a capture trigger is input. pp. 90, 124 When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge. pp. 90, 126 If the register read period and the input of the capture trigger conflict when pp. 90, CR000 is used as a capture register, the capture trigger input takes precedence 124 and the read data is undefined. Also, if the count stop of the timer and the input of the capture trigger conflict, the capture trigger is undefined. User's Manual U16898EJ6V0UD 387 APPENDIX D LIST OF CAUTIONS Soft Classification 16-bit timer/ event counter 00 Details of Function Cautions Page CR000: 16-bit timer capture/ compare register 000 Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. p. 90 CR010: 16-bit timer capture/ compare register 010 In the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010 changes from 0000H to 0001H following overflow (FFFFH). pp. 91, 121 If the new value of CR010 is less than the value of 16-bit timer counter 0 (TM00), TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR010 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR010 is changed. pp. 91, 121 The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed. pp. 91, 122 The capture operation may not be performed for CR010 set in compare mode even if a capture trigger is input. pp. 91, 124 Hard Chapter 6 Chapter (3/19) Function Soft If the register read period and the input of the capture trigger conflict when pp. 91, CR010 is used as a capture register, the capture trigger input takes precedence 124 and the read data is undefined. Also, if the timer count stop and the input of the capture trigger conflict, the capture data is undefined. Soft Hard TMC00: 16-bit timer mode control register 00 Changing the CR010 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. p. 91 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the operation. pp. 92, 121 The timer operation must be stopped before writing to bits other than the OVF00 pp. 93, flag. 122 If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to the TI000/TI010 pins. pp. 93, 121 Except when the valid edge of the TI000 pin is selected as the count clock, stop pp. 93, the timer operation before setting STOP mode or system clock stop mode; 126 otherwise the timer may malfunction when the system clock starts. Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 (PRM00) after stopping the timer operation. pp. 93, 122 If the clear & start mode entered on a match between TM00 and CR000, clear & pp. 93, start mode at the valid edge of the TI000 pin, or free-running mode is selected, 123 when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. CRC00: Capture/ compare control register 00 388 Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is disabled. pp. 93, 123 The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n0), however, occurs at the rise of the next count clock. pp. 93, 124 The timer operation must be stopped before setting CRC00. pp. 94, 122 User's Manual U16898EJ6V0UD APPENDIX D LIST OF CAUTIONS Soft Classification Hard Soft Soft Hard Hard Chapter 6 Chapter (4/19) Function Details of Function Cautions Page 16-bit timer/ event counter 00 CRC00: Capture/ compare control register 00 When the clear & start mode entered on a match between TM00 and CR000 is selected by 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. pp. 94, 121 To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00) (refer to Figure 6-17). pp. 94, 124 TOC00: 16-bit timer output control register 00 The timer operation must be stopped before setting other than OSPT00. pp. 95, 122 If LVS00 and LVR00 are read, 0 is read. pp. 95, 122 OSPT00 is automatically cleared after data is set, so 0 is read. pp. 95, 122 Do not set OSPT00 to 1 other than in one-shot pulse output mode. pp. 95, 122 A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively. pp. 95, 122 When TOE00 is 0, set TOE00, LVS00, and LVR00 at the same time with the 8- p. 95 bit memory manipulation instruction. When TOE00 is 1, LVS00 and LVR00 can be set with the 1-bit memory manipulation instruction. Always set data to PRM00 after stopping the timer operation. PRM00: Prescaler mode register 00 If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin. pp. 97, 122 In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. pp. 97, 126 pp. 97, 124 <1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. <2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled after a low level is input to the TI0n0 pin If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is enabled. <3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then enabled after a high level is input to the TI0n0 pin If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. The sampling clock used to eliminate noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fXP, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse width. pp. 97, 126 When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge. pp. 97, 126 User's Manual U16898EJ6V0UD 389 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 6 Chapter (5/19) Function Details of Function 16-bit timer/ Interval timer event counter 00 External event counter Cautions Page Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. p. 98 When reading the external event counter count value, TM00 should be read. pp. 102, 126 To use two capture registers, set the TI000 and TI010 pins. pp. 103, 124 The measurable pulse width in this operation example is up to 1 cycle of the timer counter. pp. 104, 106, 107, 109 Square-wave output Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. p. 111 PPG output Changing the CRC0n0 setting during TM00 operation may cause a malfunction. p. 113 To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Pulse width measurement Values in the following range should be set in CR000 and CR010. 0000H < CR010 < CR000 FFFFH pp. 114, 126 The cycle of the pulse generated through PPG output (CR000 setting value + 1) pp. 114, has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). 126 Hard Do not set the CR000 and CR010 registers to 0000H. pp. 117, 122 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC003 and TMC002 bits. pp. 118, 121 Hard When using the one-shot pulse output of 16-bit timer/event counter 00 with a pp. 116, software trigger, do not change the level of the TI000 pin or its alternate-function 122 port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. One-shot pulse Do not input the external trigger again while the one-shot pulse is output. To output: external output the one-shot pulse again, wait until the current one-shot pulse output is trigger completed. pp. 118, 123 pp. 119, 123 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC002 and TMC003 bits. pp. 120, 121 Hard Do not set the CR000 and CR010 registers to 0000H. Timer start errors Soft Soft 390 pp. 116, 122 Soft One-shot pulse Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. output: software To output the one-shot pulse again, wait until the current one-shot pulse output trigger is completed. One-shot pulse One-shot pulse output normally operates only in the free-running mode or in the p. 122 output clear & start mode at the valid edge of the TI000 pin. Because an overflow does not occur in the clear & start mode on a match between TM00 and CR000, oneshot pulse output is not possible. An error of up to one clock may occur in the time required for a match signal to p. 121 be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock. User's Manual U16898EJ6V0UD APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 6 Chapter (6/19) Function Details of Function 16-bit timer/ Capture event operation counter 00 Changing compare register during timer operation Cautions Page When the CRC001 bit value is 1, capture is not performed in the CR000 register p. 124 if both the rising and falling edges have been selected as the valid edges of the TI000 pin. When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at that timing. p. 124 With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare p. 125 register, when changing CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the timing of the match, so the operation is not guaranteed in such cases. To change CR0n0 during timer counting, INTTM000 interrupt servicing performs the following operation. If CR010 is changed during timer counting without performing processing <1> p. 125 above, the value in CR010 may be rewritten twice or more, causing an inversion of the output level of the TO00 pin at each rewrite. External event counter The timing of the count start is after two valid edge detections. p. 126 External clock limitation <1> When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the AC characteristics. For the AC characteristics, refer to CHAPTER 21 and CHAPTER 22 ELECTRICAL SPECIFICATIONS. p. 127 Soft CR80: compare When changing the value of CR80, be sure to stop the timer operation. If the register 80 value of CR80 is changed with the timer operation enabled, a match interrupt request signal is generated immediately and the timer may be cleared. p. 130 TMC80: 8-bit timer mode control register 80 Be sure to set TMC80 after stopping the timer operation. p. 131 Be sure to clear bits 0 and 6 to 0. p. 131 Interval timer When changing the value of CR80, be sure to stop the timer operation. If the value of CR80 is changed with the timer operation enabled, a match interrupt request signal may be generated immediately. p. 132 If the count clock of TMC80 is set and the operation of TM80 is enabled at the same time by using an 8-bit memory manipulation instruction, the error of one cycle after the timer is started may be 1 clock or more (refer to 7.5 (1) Error when timer starts). Therefore, be sure to follow the above sequence when using TM80 as an interval timer. p. 132 Hard 8-bit timer 80 Error when timer start Soft Chapter 7 <2> When an external waveform is input to 16-bit timer/event counter 00, it is sampled by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device. CR80: compare 8-bit compare register 80 (CR80) can be set to 00H. register 80 Setting STOP mode The time from starting the timer to generation of the match signal includes an p. 134 error of up to 1.5 clocks. This is because, if the timer is started while the count clock is high, the rising edge may be immediately detected and the counter may be incremented (refer to Figure 7-6). Before executing the STOP instruction, be sure to stop the timer operation (TCE80 = 0). User's Manual U16898EJ6V0UD p. 134 p. 134 391 APPENDIX D LIST OF CAUTIONS Soft Classification Details of Function 8-bit timer H1 CMP01: 8-bit timer H compare register 01 CMP01 cannot be rewritten during timer count operation. p. 137 CMP11: 8-bit timer H compare register 11 In the PWM output mode, be sure to set CMP11 when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). p. 137 TMHMD1: 8-bit When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. timer H mode In the PWM output mode, be sure to set 8-bit timer H compare register 11 register 1 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). p. 139 PWM output p. 145 Soft Hard Chapter 8 Chapter (7/19) Function Cautions In PWM output mode, the setting value for the CMP11 register can be changed during timer count operation. However, three operation clocks (signal selected using the CKS12 to CKS10 bits of the TMHMD1 register) or more are required to transfer the register value after rewriting the CMP11 register value. Page p. 139 Be sure to set the CMP11 register when starting the timer count operation p. 145 (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. p. 146 Soft Chapter 9 00H CMP11 (M) < CMP01 (N) FFH Watchdog timer WDTM: Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values. Watchdog timer After reset is released, WDTM can be written only once by an 8-bit memory mode register manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. However, at the first write, if "1" and "x" are set for WDCS4 and WDCS3 respectively and the watchdog timer is stopped, then the internal reset signal does not occur even if the following are executed. p. 154 p. 154 * Second write to WDTM * 1-bit memory manipulation instruction to WDTE * Writing of a value other than "ACH" to WDTE WDTM cannot be set by a 1-bit memory manipulation instruction. p. 154 When using the flash memory self programming by self programming, set the overflow time for the watchdog timer so that enough overflow time is secured (Example 1-byte writing: 200 s MIN., 1-block deletion: 10 ms MIN.). p. 154 Hard WDTE: If a value other than ACH is written to WDTE, an internal reset signal is Watchdog timer generated. enable register If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. 392 When "lowspeed internal oscillator cannot be stopped" is selected by option byte p. 154 p. 154 The value read from WDTE is 9AH (this differs from the written value (ACH)). p. 154 In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the lowspeed internal oscillation clock can be selected as the count source, so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows after STOP instruction execution. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution. p. 155 User's Manual U16898EJ6V0UD APPENDIX D LIST OF CAUTIONS Hard Classification Soft Soft Hard Details of Function Cautions Page Watchdog timer When "lowspeed internal oscillator can be stopped by software" is selected by option byte In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0 but holds its value. p. 157 A/D converter Sampling time The above sampling time and conversion time do not include the clock and A/D frequency error. Select the sampling time and conversion time such that Notes conversion time 2 and 3 above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). p. 163 Block diagram In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). p. 164 ADM: A/D The above sampling time and conversion time do not include the clock converter mode frequency error. Select the sampling time and conversion time such that Notes register 2 and 3 above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). p. 168 If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped p. 169 (ADCS = 0) and then A/D conversion is started, execute two NOP instructions or an instruction equivalent to two machine cycles, and set ADCS to 1. ADS: Analog input channel specification register A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2. p. 169 Be sure to clear bits 6, 2, and 1 to 0. p. 169 Be sure to clear bits 2 to 7 of ADS to 0. p. 169 ADCR: 10-bit When writing to the A/D converter mode register (ADM) and analog input A/D conversion channel specification register (ADS), the contents of ADCR may become result register undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using timing other than the above may cause an incorrect conversion result to be read. p. 169 PMC2: Port mode control register 2 When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot be p. 170 used as port pins. Be sure to set the pull-up resistor option registers (PU20 to PU23) to 0 for the pins set to A/D converter mode. A/D converter operations Make sure the period of <1> to <4> is 1 s or more. pp. 171, 175 It is no problem if the order of <1> and <2> is reversed. pp. 171, 175 <1> can be omitted. However, ignore the data resulting from the first conversion after <4> in this case. p. 175 The period from <5> to <8> differs from the conversion time set using bits 5 to 3 p. 175 (FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time set using FR2 to FR0. Hard Chapter 10 Chapter 9 Chapter (8/19) Function Operating current in STOP mode To satisfy the DC characteristics of the supply current in the STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 before executing the STOP instruction. User's Manual U16898EJ6V0UD p. 178 393 APPENDIX D LIST OF CAUTIONS Hard Classification Hard Soft Chapter 10 Chapter (9/19) Function A/D converter Details of Function Cautions Page Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AVREF p. 178 or higher and VSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. Conflicting operations Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by instruction upon the end of conversion ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR, ADCRH. p. 178 Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input channel specification register (ADS) write upon the end of conversion ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. p. 178 To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and ANI0 to ANI3 pins. p. 179 Noise countermeasures <1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply. <2> Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 9-19, to reduce noise. <3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to their alternate functions during conversion. <4> The conversion accuracy can be improved by setting HALT mode immediately after the conversion starts. ANI0/P20 to ANI3/P23 The analog input pins (ANI0 to ANI3) are also used as I/O port pins (P20 to P23). p. 179 When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access P20 to P23 while conversion is in progress; otherwise the conversion resolution may be degraded. If a digital pulse is applied to the pins adjacent to the pins currently used for A/D p. 179 conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. Input impedance of ANI0 to ANI3 pins In this A/D converter, the internal sampling capacitor is charged and sampling is p. 179 performed during sampling time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates both during sampling and otherwise. If the shortest conversion time of the reference voltage is used, to perform sufficient sampling, it is recommended to make the output impedance of the analog input source 1 k or lower, or attach a capacitor of around 0.01 F to 0.1 F to the ANI0 to ANI3 pins (see Figure 10-19). 394 User's Manual U16898EJ6V0UD APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 10 Chapter (10/19) Function A/D converter Details of Function Interrupt request flag (ADIF) Cautions The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Page p. 180 Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change analog input has not ended. Hard Soft Chapter 11 When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Serial interface UART6 Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not p. 180 fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an incorrect conversion result to be read. p. 180 Operating current at conversion waiting mode The DC characteristic of the operating current during the STOP mode is not satisfied due to the conversion waiting mode (only the comparator consumes power), when bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) are set to 0 and 1 respectively. p. 181 UART mode The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data. p. 182 If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. p. 182 If data is continuously transmitted, the communication timing from the stop bit to p. 182 the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is incorporated in LIN. RXB: Receive Reception enable status is entered, after having set RXE6 to 1 and one clock of p. 188 buffer register 6 the base clock (fXCLK6) has elapsed. TXB6: Transmit When starting transmission, write transmit data to TXB6, after having set TXE6 buffer register 6 to 1 and a wait of one clock or more of the base clock (fXCLK6) has been performed. p. 188 Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. p. 188 Do not refresh (write the same value to) TXB6 by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). When outputting same values in continuous transmission, be sure to confirm that TXBF6 is 0 before writing the same values to TXB6. p. 188 User's Manual U16898EJ6V0UD 395 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 11 Chapter (11/19) Function Serial interface UART6 Details of Function ASIM6: Registers controlling serial interface UART6 Cautions Page p. 190 At startup, transmission operation is started by setting TXE6 to 1 after having set POWER6 to 1, then setting the transmit data to TXB6 after having waited for one clock or more of the base clock (fXCLK6). When stopping transmission operation, set POWER6 to 0 after having set TXE6 to 0. At startup, reception enable status is entered by setting RXE6 to 1 after having set POWER6 to 1 and one clock of the base clock (fXCLK6) has elapsed. When stopping reception operation, set POWER6 to 0 after having set RXE6 to 0. p. 191 Set POWER6 = 1 RXE6 = 1 in a state where a high level has been input to the RxD6 pin. If POWER6 = 1 RXE6 = 1 is set during low-level input, reception is started and correct data will not be received. p. 191 Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. p. 191 Soft Hard p. 191 Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. p. 191 Make sure that RXE6 = 0 when rewriting the ISRM6 bit. p. 191 The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). p. 191 The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. p. 191 If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. p. 191 Be sure to read ASIS6 before reading receive buffer register 6 (RXB6). pp. 191, 209 ASIF6: Asynchronous serial interface transmission status register 6 To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. p. 192 To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. p. 192 CKSR6: Clock selection register 6 Make sure POWER6 = 0 when rewriting TPS63 to TPS60. p. 193 BRGC6: Baud rate generator control register 6 Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. p. 194 The baud rate is the output clock of the 8-bit counter divided by 2. p. 194 ASICL6: Asynchronous serial interface control register 6 ASICL6 can be refreshed (the same value is written) by software during a p. 195 communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1), if 0 data has been written to ASICL6 by SBRT6 and SBTT6. ASIS6: Asynchronous serial interface reception error status register 6 396 Fix the PS61 and PS60 bits to 0 when the interface is used for LIN communication operation. In the case of an SBF reception error, return to SBF reception mode again. The p. 196 status of the SBRF6 flag will be held (1). For details on SBF reception refer to (2) - (i) SBF reception in 11.4.2 Asynchronous serial interface (UART) mode described later. User's Manual U16898EJ6V0UD APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 11 Chapter (12/19) Function Serial interface UART6 Details of Function ASICL6: Asynchronous serial interface control register 6 Cautions Page Before setting the SBRT6 bit to 1, make sure that bit 7 (POWER6) and bit 5 p. 196 (RXE6) of ASIM6 = 1. Moreover, after setting the SBRT6 bit to 1, do not clear the SBRT6 bit to 0 before the SBF reception ends (an interrupt request signal is generated). The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to p. 196 0 after SBF reception has been correctly completed. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1. Moreover, after setting the SBTT6 bit to 1, do not clear the SBTT6 bit to 0 before the SBF transmission ends (an interrupt request signal is generated). p. 196 The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of SBF transmission. p. 196 Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. p. 196 POWER6, Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation TXE6, and stop mode. RXE6: 7, 6, and To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1. 5 of ASIM6 p. 198 UART mode Take the relationship with the other party of communication into consideration for the port mode register and port register setting procedure. In order to avoid the generation of unintended start bits (falling signals), set PM43 to 0 (output) after having set P43 to 1. p. 199 Parity types and operation Fix the PS61 and PS60 bits to 0 when the interface is used for LIN communication operation. p. 203 Continuous transmission Use the value of the TXBF flag to judge whether continuous transmission is p. 205 possible. Do not write the next transmit data, by making a judgment only by the fact that the TXSF6 flag has been set to 1. When the interface is used for LIN communication operation, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). p. 205 TXBF6 during continuous transmission: Bit 1 of ASIF6 To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. p. 205 TXSF6 during continuous transmission: Bit 0 of ASIF6 To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. p. 205 Normal reception Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs. p. 209 Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. Generation of serial clock Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. p. 209 Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. p. 209 Keep the baud rate error during transmission to within the permissible error range at the reception destination. p. 215 Make sure that the baud rate error during reception satisfies the range shown in p. 215 (4) Permissible baud rate range during reception. User's Manual U16898EJ6V0UD 397 APPENDIX D LIST OF CAUTIONS Soft Classification Soft Hard Chapter 12 Chapter 11 Chapter (13/19) Function Serial interface UART6 Interrupt functions Details of Function Cautions Permissible Make sure that the baud rate error during reception is within the permissible baud rate range error range, by using the calculation expression shown below. during reception Vector table No interrupt sources correspond to the vector table address 0014H. address IF0, IF1: Interrupt request flag registers, Page p. 217 p. 221 Because P30, P31, P41, and P43 have an alternate function as external pp. 224, interrupt inputs, when the output level is changed by specifying the output mode 225 of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. MK0, MK1: Interrupt mask flag registers INTM0: External interrupt mode register 0 Be sure to clear bits 0 and 1 to 0. p. 226 Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag (xxMKx = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt request flag (xxIFx = 0), then clear the interrupt mask flag (xxMKx = 0), which will enable interrupts. p. 226 Be sure to clear bits 2 to 7 to 0. p. 227 Before setting INTM1, set PMK3 to 1 to disable interrupts. To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0. p. 227 Interrupt requests are held pending Interrupt requests will be held pending while the interrupt request flag registers (IF0, IF1) or interrupt mask flag registers (MK0, MK1) are being accessed. p. 230 Interrupt request pending Multiple interrupts can be acknowledged even for low-priority interrupts. p. 231 Soft Hard Soft Chapter 13 INTM1: External interrupt mode register 1 398 Standby function - The LSRSTOP setting is valid only when "Can be stopped by software" is set for p. 233 the low-speed internal oscillator by the option byte. STOP mode When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction (except the peripheral hardware that operates on the low-speed internal oscillation clock). p. 234 STOP mode, HALT mode The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. p. 234 STOP mode If the low-speed internal oscillator is operating before the STOP mode is set, oscillation of the low-speed internal oscillation clock cannot be stopped in the STOP mode (refer to Table 13-1). p. 234 OSTS: Oscillation stabilization time select register To set and then release the STOP mode, set the oscillation stabilization time as p. 235 follows. Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS User's Manual U16898EJ6V0UD APPENDIX D LIST OF CAUTIONS Hard Classification Standby function Soft Chapter 13 Chapter (14/19) Function Details of Function Cautions Page OSTS: Oscillation stabilization time select register The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset signal generation or interrupt generation. p. 235 The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. p. 235 HALT mode Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag clear, the standby mode is immediately cleared if set. p. 236 Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, in the STOP mode, the normal operation mode is restored after the STOP instruction is executed and then the operation is stopped for 34 s (TYP.) (after an additional wait time for stabilizing the oscillation set by the oscillation stabilization time select register (OSTS) has elapsed when crystal/ceramic oscillation is used). p. 239 For an external reset, input a low level for 2 s or more to the RESET pin. p. 243 During reset signal generation, the system clock and low-speed internal oscillation clock stop oscillating. p. 243 setting and operating statuses Hard Chapter 14 STOP mode setting and operating statuses Reset function - When the RESET pin is used as an input-only port pin (P34), the 78K0S/KA1+ p. 243 is reset if a low level is input to the RESET pin after reset is released by the POC circuit, the LVI circuit and the watchdog timer and before the option byte is referenced again. The reset status is retained until a high level is input to the RESET pin. The LVI circuit is not reset by the internal reset signal of the LVI circuit. p. 244 Soft Hard Power-onclear circuit RESF: Reset control flag register Do not read data by a 1-bit memory manipulation instruction. p. 250 Functions of power-on-clear circuit If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. p. 251 Use these products in the following voltage range because the detection voltage p. 251 (VPOC) of the POC circuit is the supply voltage range. Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V Soft Chapter 15 Timing of reset The watchdog timer is also reset in the case of an internal reset of the watchdog p. 246 by overflow of timer. watchdog timer Cautions for power-on-clear circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the p. 253 vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. User's Manual U16898EJ6V0UD 399 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 16 Chapter (15/19) Function Details of Function Low-voltage LVIM: Lowdetector voltage detect register Cautions To stop LVI, follow either of the procedures below. Page p. 256 * When using 8-bit manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. Be sure to set bits 2 to 6 to 0. p. 256 LVIS: Lowvoltage detection level select register Bits 4 to 7 must be set to 0. p. 257 If values other than same values are written during LVI operation, the value becomes undefined at the very moment it is written, and thus be sure to stop LVI (bit 7 of LVIM register (LVION) = 0) before writing. p. 257 When used as reset <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <3>. p. 258 If supply voltage (VDD) detection voltage (VLVI) when LVIM is set to 1, an internal reset signal is not generated. p. 258 In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. p. 262 Cautions for low-voltage detector <1> When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. <2> When used as interrupt Hard Chapter 17 Interrupt requests may be frequently generated. Take (b) of action (2) below. Option byte Oscillation stabilization time on power application or after reset release The setting of this option is valid only when the crystal/ceramic oscillation clock is selected as the system clock source. No wait time elapses if the high-speed internal oscillation clock or external clock input is selected as the system clock source. p. 266 Control of RESET pin Because the option byte is referenced after reset release, if a low level is input to the RESET pin before the option byte is referenced, then the reset state is not released. p. 266 Also, when setting 0 to RMCE, connect the pull-up resistor. Selection of system clock source Because the X1 and X2 pins are also used as the P121 and P122 pins, the conditions under which the X1 and X2 pins can be used differ depending on the selected system clock source. p. 266 (1) Crystal/ceramic oscillation clock is selected The X1 and X2 pins cannot be used as I/O port pins because they are used as clock input pins. (2) External clock input is selected Because the X1 pin is used as an external clock input pin, P121 cannot be used as an I/O port pin. (3) High-speed internal oscillation clock is selected P121 and P122 can be used as I/O port pins. Low-speed internal oscillates 400 If it is selected that low-speed internal oscillator cannot be stopped, the count clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation clock. User's Manual U16898EJ6V0UD p. 267 APPENDIX D LIST OF CAUTIONS Hard Classification Option byte Soft Chapter 17 Chapter (16/19) Function Details of Function Cautions Page Low-speed internal oscillates If it is selected that low-speed internal oscillator can be stopped by software, p. 267 supply of the count clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of bit 0 (LSRSTOP) of the low-speed internal oscillation mode register (LSRCM). Similarly, clock supply is also stopped when a clock other than the low-speed internal oscillation clock is selected as a count clock to WDT. While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can be supplied to the 8-bit timer H1 even in the STOP mode. Caution when the RESET pin is used as an input-only port pin (P34) Be aware of the following when re-erasing/-writing (by on-board programming using a dedicated flash memory programmer) an already-written device which has been set as "The RESET pin is used as an input-only port pin (P34)" by the option byte function. p. 267 Before supplying power to the target system, connect a dedicated flash memory programmer and turn its power on. Soft Chapter 18 If the power is supplied to the target system beforehand, the flash memory programming mode cannot be switched to. Flash memory PG-FP5 programming GUI setting value example The above values are recommended values. Depending on the usage environment these values may change, so set them after having performed sufficient evaluations. p. 275 Security settings After the security setting of the batch erase is set, erasure cannot be performed for the device. In addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written because the erase command is disabled. p. 278 Self programming function Self programming processing must be included in the program before performing self programming. p. 279 No instructions can be executed while a self programming command is being p. 282 executed. Therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming. Refer to Table 18-10 for the time taken for the execution of self programming. Interrupts that occur during self programming can be acknowledged after self programming mode ends. To avoid this operation, disable interrupt servicing (by setting MK0 and MK1 to FFH, and executing the DI instruction) before the mode is shifted from the normal mode to the self programming mode by a specific sequence. p. 282 RAM is not used while a self programming command is being executed. p. 282 If the supply voltage drops or the reset signal is input while the flash memory is being written or erased, writing/erasing is not guaranteed. p. 282 The value of the blank data set during block erasure is FFH. p. 282 Set the CPU clock beforehand so that it is 1 MHz or higher during self programming. p. 282 Execute self programming after executing the NOP and HALT instructions immediately after executing a specific sequence to set self programming mode. At this time, the HALT instruction is automatically released after 10 s (MAX.) + 2 CPU clocks (fCPU). p. 282 If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT instructions immediately after executing a specific sequence to set self programming mode, wait for 8 s after releasing the HALT status, and then execute self programming. p. 282 Check FPRERR using a 1-bit memory manipulation instruction. p. 282 The state of the pins in self programming mode is the same as that in HALT mode. p. 282 User's Manual U16898EJ6V0UD 401 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 18 Chapter (17/19) Function Flash memory Details of Function Self programming function Page Since the security function set via on-board/off-board programming is disabled in self programming mode, the self programming command can be executed regardless of the security function setting. To disable write or erase processing during self programming, set the protect byte. p. 282 Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register (FLAPHC) to 0 before executing the self programming command. If the self programming command is executed with these bits set to 1, the device may malfunction. p. 282 Clear the value of the FLCMD register to 00H immediately before setting to self programming mode and normal mode. p. 282 For cautions in case of setting the self programming mode, refer to 18.8.2 Cautions on self programming function. p. 283 Set the CPU clock beforehand so that it is 1 MHz or higher during self programming. p. 283 Execute self programming after executing the NOP and HALT instructions immediately after executing a specific sequence to set self programming mode. At this time, the HALT instruction is automatically released after 10 s (MAX.) + 2 CPU clocks (fCPU). p. 283 If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT instructions immediately after executing a specific sequence to set self programming mode, wait for 8 s after releasing the HALT status, and then execute self programming. p. 283 Clear the value of the FLCMD register to 00H immediately before setting to self programming mode and normal mode. p. 283 PFCMD: Flash protect command register Interrupt servicing cannot be executed in self programming mode. Disable interrupt servicing (by executing the DI instruction while MK0 and MK1 = FFH) between the points before executing the specific sequence that sets self programming mode and after executing the specific sequence that changes the mode to the normal mode. p. 284 PFS: Flash status register Check FPRERR using a 1-bit memory manipulation instruction. p. 284 FLAPH, FLAPL: Flash address pointers H and L Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register (FLAPHC) to 0 before executing the self programming command. If the self programming command is executed with these bits set to 1, the device may malfunction. p. 287 FLAPHC, FLAPLC: Flash address pointer H/L compare registers Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register (FLAPHC) to 0 before executing the self programming command. If the self programming command is executed with these bits set to 1, the device may malfunction. p. 287 Set the number of the block subject to a block erase, verify, or blank check (same value as FLAPH) to FLAPHC. p. 287 Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank check is performed. p. 287 FLPMC: Flash programming mode control register 402 Cautions User's Manual U16898EJ6V0UD APPENDIX D LIST OF CAUTIONS Soft Classification Flash memory Details of Function Shifting to self programming mode Cautions Page Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. pp. 291, 292, 294, 295 Byte write If a write results in failure, erase the block once and write to it again. p. 303 Connecting QB-MINI2 to 78K0S/KA1+ The 78K0S/KA1+ has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is not liable for problems occurring when the on-chip debug function is used. p. 328 Shifting to normal mode Hard Chapter 19 Chapter 18 Chapter (18/19) Function On-chip debug function Hard Chapter 21 The constants described in the circuit connection example are reference values. p. 328 If you perform flash programming aiming at mass production, thoroughly evaluate whether the specifications of the target device are satisfied. Electrical specifications (Standard product, (A) grade product) Circuit Connection for the Case Where QBMINI2 Is Used for Debugging and Debugging of INTP3 Pin Is Performed Only with Real Machine If debugging is performed with a real machine running, without using QB-MINI2, p. 330 write the user program using the QB-Programmer. Programs downloaded by the debugger include the monitor program, and such a program malfunctions if it is not controlled via QB-MINI2. Absolute maximum ratings Product quality may suffer if the absolute maximum rating is exceeded even p. 342 momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. X1 oscillator characteristics When using the X1 oscillator, wire as follows in the area enclosed by the broken p. 343 lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. A/D converter The conversion accuracy may be degraded when the analog input pin is used as an alternate I/O port or if a port is changed during A/D conversion. User's Manual U16898EJ6V0UD p. 350 403 APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 22 Chapter (19/19) Function Electrical specifications ((A2) grade product) Details of Function Cautions Page Absolute maximum ratings Product quality may suffer if the absolute maximum rating is exceeded even p. 354 momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. X1 oscillator characteristics When using the X1 oscillator, wire as follows in the area enclosed by the broken p. 356 lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 404 Hard Chapter 24 A/D converter Recommended soldering conditions Lead-free products - The conversion accuracy may be degraded when the analog input pin is used as an alternate I/O port or if a port is changed during A/D conversion. p. 363 Products with -A or -AX at the end of the part number are lead-free products. p. 371 For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. p. 371 Do not use different soldering methods together (except for partial heating). pp. 371, 372 Only the pins of the THD are heated when performing wave soldering. Make sure that flow solder does not come in contact with the package. p. 372 User's Manual U16898EJ6V0UD APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition Page Throughout Description Addition of PD78F9224 Deletion of PD78F9221MC-5A4, 78F9222MC-5A4, 78F9221MC(A)-5A4, 78F9222MC(A)-5A4, 78F9221MC(A2)-5A4, 78F9222MC(A2)-5A4 p. 6 Modification of Documents Related to Development Software Tools (User's Manuals) p. 18 Modification of 1.4 78K0S/Kx1+ Product Lineup pp. 39 to 42 Modification of Table 3-3 Special Function Registers p. 271 18.4 Writing with Flash Memory Programmer * Deletion of FlashPro4 and addition of QB-MINI2 * Modification of Remark p. 272 Modification of and addition of Remark to Figure 18-2 Environment for Writing Program to Flash Memory (FlashPro5/QB-MINI2) p. 273 Modification of Table 18-2 Wiring Between 78K0S/KA1+ and FlashPro5/QB-MINI2 p. 273 Modification of and addition of Remark to Figure 18-3 Wiring diagram with FlashPro5/QB-MINI2 p. 277 Modification of Figure 18-7 Communication Commands pp. 297 to 299 18.8.6 Example of block erase operation in self programming mode * Modification of description and addition of Note 2 * Modification of Figure 18-20 Example of Block Erase Operation in Self Programming Mode * Modification of an example of a program pp. 318 to 320 18.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode * Modification of Figure 18-27 Example of Operation When Interrupt-Disabled Time Should Be Minimized (from Erasure to Blank Check) * Modification of an example of a program p. 373 Modification of APPENDIX A DEVELOPMENT TOOLS User's Manual U16898EJ6V0UD 405 APPENDIX E REVISION HISTORY E.2 Revision History up to Previous Editions The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/10) Edition 2nd edition Description Addition of lead-free products Applied to: Throughout * PD78F9221MC-5A4-A * PD78F9222MC-5A4-A Modification of watchdog timer operation clock * Low-voltage internal oscillation clock (fRL) or clock to peripheral hardware (fXP) Low-voltage internal oscillation clock (fRL) or system clock (fX) Deletion of high-speed internal oscillation mode register (HSRCM) Deletion of INTFLC (interrupt request) Addition of Caution to 2.1 Pin Function List, 2.2.4 P121 to P123 (Port 12), and 2.2.7 CHAPTER 2 PIN X1 and X2 FUNCTIONS Modification of the following pin connections in Table 2-1 Types of Pin I/O Circuits and Connection of Unused Pins * P20/ANI0 to P23/ANI3 * P34/RESET * P121/X1 * P122/X2 Modification of Figure 3-1 Memory Map (PD78F9221) and Figure 3-2 Memory Map CHAPTER 3 CPU (PD78F9222) ARCHITECTURE Addition of Caution to and modification of Table 3-2 Vector Table Addition of (4) Protect byte area to 3.1.1 Internal program memory space Addition of Note 3 to Table 3-3 Special Function Registers (1/2) Addition of registers to be used for the self programming function to Table 3-3 Special Function Registers (2/2) Addition of Caution and modification of Remark 2 in Table 4-1 Port Functions CHAPTER 4 PORT Addition of Figure 4-4 Block Diagram of P31 FUNCTIONS Modification of Figure 4-9 Block Diagram of P43 Modification of Figure 5-1 Block Diagram of Clock Generators CHAPTER 5 CLOCK Modification of operation stop time in the following figures. GENERATORS * Figure 5-8 Timing Chart of Default Start by High-Speed Internal Oscillator * Figure 5-10 Timing Chart of Default Start by Crystal/Ceramic Oscillator * Figure 5-12 Timing of Default Start by External Clock Input Modification of Note in Figure 5-14 Status Transition of Low-Speed Internal oscillator Addition of Cautions to 6.2 Configuration of 16-bit Timer/Event Counter 00 (1) 16-bit CHAPTER 6 16-BIT timer counter 00 (TM00), (2) 16-bit timer capture/compare register 000 (CR000), and TIMER/EVENT (3) 16-bit capture/compare register 010 (CR010) COUNTER 00 Addition of Cautions in Figure 6-5 Format of 16-bit Timer Mode Control Register 00 (TMC00) Addition of Caution 6 to Figure 6-7 Format of 16-bit Timer Output Control Register 00 (TOC00) Modification of Caution 3 and addition of Caution 4 in Figure 6-8 Format of Prescaler Mode Register 00 (PRM00) 406 User's Manual U16898EJ6V0UD APPENDIX E REVISION HISTORY (2/10) Edition 2nd edition Description Applied to: Modification of output width of INTTM010 and INTTM000 in the following figures CHAPTER 6 16-BIT * Figure 6-17 CR010 Capture Operation with Rising Edge Specified TIMER/EVENT * Figure 6-20 Timing of Pulse Width Measurement Operation by Free-Running COUNTER 00 Counter and One Capture Register (with Both Edges Specified) * Figure 6-22 Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) * Figure 6-24 Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) * Figure 6-26 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) Modification of Caution 1 in Figure 6-29 Control Register Settings for PPG Output Operation Modification of Figure 6-33 Timing of One-Shot Pulse Output Operation with Software Trigger Modification and addition to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 Addition of Caution 2 to Figure 7-4 Format of 8-bit Timer Mode Control Register 80 CHAPTER 7 8-BIT (TMC80) TIMER 80 Modification of Table 9-1 Loop Detection Time of Watchdog Timer CHAPTER 9 Addition of Caution 4 and modification to Figure 9-2 Format of Watchdog Timer Mode WATCHDOG TIMER Register (WDTM) Modification of Figure 9-4 Status Transition Diagram When "Low-Speed Internal Oscillator Cannot Be Stopped" Is Selected by Option Byte Modification of Figure 9-5 Status Transition Diagram When "Low-Speed Internal Oscillator Can Be Stopped by Software" Is Selected by Option Byte Addition of Note to and modification of Figure 10-1 Timing of A/D Converter Sampling CHAPTER 10 A/D and A/D Conversion CONVERTER Addition of Note 1, Caution, and Remark 2 to and modification of Table 10-1 Sampling Time and A/D Conversion Time Modification of Figure 10-2 Block Diagram of A/D Converter Modification of Note 5, addition of Notes 1, 2, Cautions 1, 2, 4 and Remark 2 to, and modification of Figure 10-3 Format of A/D Converter Mode Register (ADM) Modification of Note in Figure 10-4 Timing Chart When Comparator Is Used Addition of explanation <3> to 10.4.1 Basic operations of A/D converter Modification of Figure 10-11 Relationship Between Analog Input Voltage and A/D Conversion Result Addition of explanation <3> to 10.4.3 A/D converter operation mode Partial modification of 10.6 (1) Operating current in STOP mode and (6) Input impedance of ANI0 to ANI3 pins Modification of capacitor value in Figure 10-19 Analog Input Pin Connection Modification of Figure 10-21 Internal Equivalent Circuit of ANIn Pin and Table 10-4 Resistance and Capacitance Values (Reference Values) of Equivalent Circuit Addition of description to 11.2 (3) Transmit buffer register 6 (TXB6) CHAPTER 11 SERIAL Modification of Note 1 in Figure 11-5 Format of Asynchronous Serial Interface INTERFACE UART6 Operation Mode Register 6 (ASIM6) (1/2) Modification of Caution in 11.3 (6) Asynchronous serial interface control register 6 (ASICL6) Modification of Caution 1 in 11.4.2 (2) (d) Continuous transmission User's Manual U16898EJ6V0UD 407 APPENDIX E REVISION HISTORY (3/10) Edition 2nd edition Description Applied to: Modification of 11.4.2 (2) (h) SBF transmission CHAPTER 11 SERIAL Modification of Table 11-4 Set Data of Baud Rate Generator INTERFACE UART6 Addition of Caution to and modification of Table 12-1 Interrupt Sources CHAPTER 12 INTERRUPT FUNCTIONS Modification of description on operation stop time in 13.1.1 (2) STOP mode CHAPTER 13 Modification of Table 13-2 Operating Statuses in HALT Mode STANDBY FUNCTION Modification of Remark 2 in Figure 13-2 HALT Mode Release by Interrupt Request Generation Modification of Note in Figure 13-3 HALT Mode Release by Reset Input Modification of Caution in 13.2.2 (1) STOP mode setting and operating statuses Modification of Table 13-4 Operating Statuses in STOP Mode Modification of operation stop time in the following figures. * Figure 13-4 Operation Timing When STOP Mode Is Released * Figure 13-5 STOP Mode Release by Interrupt Request Generation Modification of the following figures CHAPTER 14 RESET * Figure 14-1 Block Diagram of Reset Function FUNCTION * Figure 14-2 Timing of Reset by RESET Input * Figure 14-3 Timing of Reset by Overflow of Watchdog Timer * Figure 14-4 Reset Timing by RESET Input in STOP Mode Addition of registers to be used for self programming function in Table 14-1 Hardware Statuses After Reset Acknowledgment Addition of Note 1 to Figure 16-2 Format of Low-Voltage Detect Register (LVIM) CHAPTER 16 LOW- Addition of Note to Figure 16-3 Format of Low-Voltage Detection Level Select VOLTAGE DETECTOR Register (LVIS) Addition of Notes 1 and 2 to and modification of Figure 16-4 Timing of Low-Voltage Detector Internal Reset Signal Generation Addition of Notes 1 and 2 to and modification of Figure 16-5 Timing of Low-Voltage Detector Interrupt Signal Generation Addition of Note to 16.5 Cautions for Low-Voltage Detector <Action> (2) When used as interrupt Revision of CHAPTER 18 FLASH MEMORY CHAPTER 18 FLASH MEMORY Modification or addition of values in the following characteristics in CHAPTER 20 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ELECTRICAL * Absolute maximum ratings SPECIFICATIONS Output current high, output current low, and operating ambient temperature * X1 oscillator characteristics * Low-speed internal oscillator characteristics * DC characteristics * AC characteristics (1) Basic operation cycle time (minimum instruction execution time), RESET input low-level width * POC circuit characteristics Condition for power supply boot time * Flash memory programming characteristics 408 User's Manual U16898EJ6V0UD (TARGET VALUES) APPENDIX E REVISION HISTORY (4/10) Edition 2nd edition Description Applied to: Modification of Figure A-1 Development Tools APPENDIX A Modification of device file names and Remark in A.2 Language Processing Software DEVELOPMENT Addition of project manager name to A.3 Control Software TOOLS Addition of PG-FPL2 to A.4 Flash Memory Writing Tools Modification of emulation board name used when the IE-78K0S-NS or IE-78K0S-NS-A is used, and deletion of NP-20GS and EV-9500GS-20, and addition of Specification of pin header on target system to A.5.1 When using in-circuit emulator IE-78K0S-NS or IE78K0S-NS-A Addition of A.5.2 When using in-circuit emulator QB-78K0KX1MINI Modification of system simulator name, device file name, and Remark in and addition of ID78K0S-QB to A.6 Debugging Tools (Software) Modification of Figure B-1 Distance Between In-Circuit Emulator IE-78K0S-NS/IE- APPENDIX B NOTES 78K0S-NS-A and Conversion Connector NP-30MC and Figure B-2 Condition for ON TARGET SYSTEM Connecting Target System (When Using In-Circuit Emulator IE-78K0S-NS, IE- DESIGN 78K0S-NS-A) Addition of APPENDIX D REVISION HISTORY APPENDIX D REVISION HISTORY 3rd edition Addition of part number to 1.3 Ordering Information CHAPTER 1 OVERVIEW Addition of Note to P34/RESET, P121/X1, and P122/X2 in 2.1 Pin Function List CHAPTER 2 PIN Addition of description to 2.2.2 P30, P31, and P34 (Port 3) FUNCTIONS Addition of description to 2.2.4 P121 to P123 (Port 12) Addition of description to 2.2.6 RESET Addition of description to 2.2.7 X1 and X2 Modification of description example in 3.4.1 Direct addressing CHAPTER 3 CPU Modification of description and description example in 3.4.2 Short direct addressing ARCHITECTURE Addition of Illustration to 3.4.6 Based addressing Addition of Illustration to 3.4.7 Stack addressing Addition of Note to P34/RESET, P121/X1, and P122/X2 in Table 4-1 Port Functions CHAPTER 4 PORT Addition of description to and modification of Cautions in 4.2.2 Port 3 FUNCTIONS Modification of Figure 4-10 Block Diagram of P121 and P122 Addition of description to (2) In input mode in 4.4.1 Writing to I/O port and 4.4.3 Operations on I/O port Modification of description in (2) External event counter in 6.1 Functions of 16-bit CHAPTER 6 16-BIT Timer/Event Counter 00 TIMER/EVENT Modification of Caution 2 in Figure 6-2 Format of 16-bit Timer Counter 00 (TM00) COUNTER 00 Modification of Caution 2 in Figure 6-5 Format of 16-bit Timer Mode Control Register 00 (TMC00) Addition of (1) INTTM000 generation timing immediately after operation starts to Figure 6-16 External Event Counter Operation Timing (with Rising Edge Specified) Addition of Caution to (1), (2), (3), and (4) in 6.4.3 Pulse width measurement operations Modification of Figure 6-19 Configuration Diagram for Pulse Width Measurement by Free-Running Counter User's Manual U16898EJ6V0UD 409 APPENDIX E REVISION HISTORY (5/10) Edition 3rd edition Description Applied to: Modification of Figure 6-20 Timing of Pulse Width Measurement Operation by Free- CHAPTER 6 16-BIT Running Counter and One Capture Register (with Both Edges Specified) and Note TIMER/EVENT Modification of Figure 6-22 Timing of Pulse Width Measurement Operation with Free- COUNTER 00 Running Counter (with Both Edges Specified) and Note Modification of Note in Figure 6-23 Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Modification of Figure 6-24 Timing of Pulse Width Measurement Operation by FreeRunning Counter and Two Capture Registers (with Rising Edge Specified) and Note Modification of Figure 6-26 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) 6.4.6 One-shot pulse output operation * Modification of Caution 1 in (1) One-shot pulse output with software trigger * Modification of Caution in (2) One-shot pulse output with external trigger Modification of <3> and <4> in (2) 16-bit timer counter 00 (TM00) operation of 6.5 Cautions Related to 16-bit Timer/Event Counter 00 Modification of <1> in (11) One-shot pulse output by software of 6.5 Cautions Related to 16-bit Timer/Event Counter 00 Modification of <1> in (12) One-shot pulse output with external trigger of 6.5 Cautions Related to 16-bit Timer/Event Counter 00 Modification of <3> in (15) Capture operation of 6.5 Cautions Related to 16-bit Timer/Event Counter 00 Modification of <1> in (19) External event counter of 6.5 Cautions Related to 16-bit Timer/Event Counter 00 Modification of Caution in (1) 8-bit compare register 80 (CR80) of 7.2 Configuration of CHAPTER 7 8-BIT 8-bit Timer 80 TIMER 80 Modification of description in (2) 8-bit timer H compare register 11 (CMP11) of 8.2 CHAPTER 8 8-BIT Configuration of 8-bit Timer H1 TIMER H1 Modification of Caution 1 in 8.4.2 Operation as PWM output mode Modification of (e) Operation by changing CMP11 (CMP11 = 02H 03H, CMP01 = A5H) in Figure 8-9 Operation Timing in PWM Output Mode Addition of description to Caution 2 in Figure 9-2 Format of Watchdog Timer Mode CHAPTER 9 Register (WDTM) WATCHDOG TIMER Modification of Figure 10-1 Timing of A/D Converter Sampling and A/D Conversion CHAPTER 10 A/D Modification of Table 10-1 Sampling Time and A/D Conversion Time and Note 1 CONVERTER Modification of Figure 10-3 Format of A/D Converter Mode Register (ADM) and Note 2 Modification of (4) Noise countermeasures in 10.6 Cautions for A/D Converter Modification of (6) Input impedance of ANI0 to ANI3 pins in 10.6 Cautions for A/D Converter Modification of Figure 11-1 LIN Transmission Operation CHAPTER 11 SERIAL Modification of Figure 11-2 LIN Reception Operation and description INTERFACE UART6 Addition of description to (7) Input switch control register (ISC) in 11.3 Registers Controlling Serial Interface UART6 Modification of value in Table 11-4 Set Data of Baud Rate Generator 410 User's Manual U16898EJ6V0UD APPENDIX E REVISION HISTORY (6/10) Edition 3rd edition Description Applied to: Modification of 12.1 Interrupt Function Types CHAPTER 12 Modification of 12.4.2 Multiple interrupt servicing INTERRUPT Addition of Caution to Example 1 in Figure 12-10 Example of Multiple Interrupts (1/2) FUNCTIONS Addition of Example 3 to Figure 12-10 Example of Multiple Interrupts (1/2) Modification of reset signal in Figure 13-3 HALT Mode Release by Reset Signal CHAPTER 13 Generation STANDBY FUNCTION Modification of description in External interrupt of Table 13-4 Operating Statuses in STOP Mode Modification of description in and addition of Note to (a) Release by unmasked interrupt request in (2) of 13.2.2 STOP mode Modification of reset signal in Figure 13-6 STOP Mode Release by Reset Signal Generation Modification of Figure 14-1 Block Diagram of Reset Function CHAPTER 14 RESET Addition of delay time of internal reset signal generation to Figure 14-2 Timing of Reset FUNCTION by RESET Input and Figure 14-4 Reset Timing by RESET Input in STOP Mode Modification of Figure 15-3 Example of Software Processing After Release of Reset CHAPTER 15 POWER- (1/2) ON-CLEAR CIRCUIT Modification of Figure 16-1 Block Diagram of Low-Voltage Detector CHAPTER 16 LOW- Modification of Note 1 in Figure 16-2 Format of Low-Voltage Detect Register (LVIM) VOLTAGE DETECTOR Modification of Note in Figure 16-3 Format of Low-Voltage Detection Level Select Register (LVIS) Modification of INTLVI and Note 2 in Figure 16-5 Timing of Low-Voltage Detector Interrupt Signal Generation Modification of (2) in <Action> of 16.5 Cautions for Low-Voltage Detector Modification of Figure 16-6 Example of Software Processing After Release of Reset (1/2) Modification of description and configuration in CHAPTER 17 OPTION BYTE CHAPTER 17 OPTION Modification of Caution in Figure 17-2 Format of Option Byte (1/2) BYTE Addition of Remarks 3, 4 to Figure 17-2 Format of Option Byte (2/2) Modification of and addition to 18.1 Features CHAPTER 18 FLASH Figure 18-2 Environment for Writing Program to Flash Memory is divided into two MEMORY figures, in the case of FlashPro4 and in the case of PG-FPL2 Modification of Caution in Table 18-5 Oscillation Frequency and PG-FP4 GUI Software Setting Value Example Deletion of 18.7.1 Flash memory programming mode Modification of 18.7.2 Communication commands Modification of and addition to 18.8.2 Cautions on self programming function Addition of <Setting conditions> in 3. Operating conditions of WEPRERR flag of 18.8.3 Registers used for self programming function (3) Addition of description to Figure 18-15 Format of Flash Programming Command Register (FLCMD) User's Manual U16898EJ6V0UD 411 APPENDIX E REVISION HISTORY (7/10) Edition 3rd edition Description Applied to: Modification of Caution in Figure 18-16 Format of Flash Address Pointer H/L CHAPTER 18 FLASH (FLAPH/FLAPL) MEMORY Modification of Cautions 1, 2 in Figure 18-17 Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC) Complete revision of CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET CHAPTER 20 VALUES), and addition of chapters ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) to CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) Addition of CHAPTER 24 PACKAGE MARKING INFORMATION CHAPTER 24 PACKAGE MARKING INFORMATION Addition of CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS Addition of included software tools to A.1 Software Package APPENDIX A DEVELOPMENT TOOLS Addition of APPENDIX D LIST OF CAUTIONS APPENDIX D LIST OF CAUTIONS 4th edition Deletion of description on (T) product, (S) product, (R) product, (T2) product Throughout Modification of 1.4 78K0S/Kx1+ Product Lineup CHAPTER 1 OVERVIEW Addition of Caution 2 to 3.2.1 (3) Stack pointer (SP) CHAPTER 3 CPU ARCHITECTURE Addition of Caution to Figure 4-15 Format of Port Mode Control Register 2 CHAPTER 4 PORT FUNCTIONS Addition of 6.5 (23) External clock limitation CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Correction of description in 10.2 (1) ANI0 to ANI3 pins CHAPTER 10 A/D Addition of Caution to Figure 10-8 Format of Port Mode Control Register 2 (PMC2) CONVERTER Addition of 10.6 (10) Operating current at conversion waiting mode Addition of Caution to 11.2 (1) Receive buffer register 6 (RXB6) CHAPTER 11 SERIAL Addition of Caution 1 to and modification of Caution 3 in 11.2 (3) Transmit buffer INTERFACE UART6 register 6 (TXB6) Correction of Note 3 in Figure 11-5 Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Addition of Notes 1 and 2 to and modification of Cautions 1, 2 and 3 in Figure 11-5 Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) 412 User's Manual U16898EJ6V0UD APPENDIX E REVISION HISTORY (8/10) Edition 4th edition Description Applied to: Modification of Caution in 11.3 (6) Asynchronous serial interface control register 6 CHAPTER 11 SERIAL (ASICL6) INTERFACE UART6 Modification of Caution 1 in Figure 11-10 Format of Asynchronous Serial Interface Control Register 6 (ASICL6) Modification of Caution in 11.4.2 (1) Registers used Addition of Caution 2 to 16.3 (2) Low-voltage detection level select register (LVIS) CHAPTER 16 LOWVOLTAGE DETECTOR Addition of 17.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin CHAPTER 17 OPTION (P34) BYTE Addition of description to 18.6.1 X1 and X2 pins CHAPTER 18 FLASH Addition of Remark 1 to 18.8 Flash Memory Programming by Self Writing MEMORY Modification of description of internal verify 1 in and addition of description and Remark of internal verify 2 to Table 18-11 Self Programming Controlling Commands Partial modification of and addition to 18.8.2 Cautions on self programming function Addition of Cautions 2, 3 and 5 to and modification of Caution 4 in Figure 18-12 Format of Flash Programming Mode Control Register (FLPMC) Modification of Caution in and addition of description on FPRERR to 18.8.3 (2) Flash protect command register (PFCMD) Addition of Caution to 18.8.3 (3) Flash status register (PFS) Modification of description and Note of internal verify 1 in and addition of description of internal verify 2 to Figure 18-15 Format of Flash Programming Command Register (FLCMD) Modification of Caution in Figure 18-16 Format of Flash Address Pointer H/L (FLAPH/FLAPL) and Caution 1 in Figure 18-17 Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC) Addition of description to 18.8.4 Example of shifting normal mode to self programming mode and 18.8.5 Example of shifting self programming mode to normal mode Addition of description of internal verify 1 and 2 to 18.8.9 Example of internal verify operation in self programming mode Addition of description to 18.8.10 Examples of operation when command execution time should be minimized in self programming mode and 18.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode * Modification of MAX. values of low-level input voltage (VIL3), high-level input leakage CHAPTER 20 current, low-level input leakage current, high-level output leakage current and low-level ELECTRICAL output leakage current SPECIFICATIONS * Modification of conditions of high-level output voltage * Modification of MAX. values of supply current (IDD5) in STOP mode (Standard product, (A) grade product) * Addition of CPU Clock Frequency, Peripheral Clock Frequency * Modification of Caution in A/D Converter Characteristics * Addition of formula to calculate power consumption of internal pull-up resistor CHAPTER 21 * Modification of MAX. values of low-level input voltage (VIL2) ELECTRICAL * Modification of conditions of high-level output voltage * Addition of CPU Clock Frequency, Peripheral Clock Frequency SPECIFICATIONS (TARGET VALUES) ((A2) grade product) * Modification of Caution in A/D Converter Characteristics User's Manual U16898EJ6V0UD 413 APPENDIX E REVISION HISTORY (9/10) Edition 4th edition Description Deletion of CHAPTER 24 PACKAGE MARKING INFORMATION Applied to: CHAPTER 24 PACKAGE MARKING INFORMATION 5th edition Modification of A.4 Flash Memory Writing Tools APPENDIX A Addition of A.5.1 When using in-circuit emulator QB-78K0SKX1 (under development) DEVELOPMENT and A.5.2 When using in-circuit emulator QB-MINI2 TOOLS Addition of SSOP ( PD78F9221MC(A)-CAA-AX, PD78F9222MC(A)-CAA-AX, Throughout PD78F9221MC(A2)-CAA-A, PD78F9222MC(A2)-CAA-A) , SDIP ( PD78F9221CS-CAC-A, PD78F9222CS-CAC-A) and, WLBGA ( PD78F9221FH-2B1-A, PD78F9222FH-2B1-A) packages (A2) grade product Under development mass production Modification of 1.1 Features CHAPTER 1 1.3 Pin Configuration (Top View) OVERVIEW * Modification of description of AVREF Addition of Notes 2 to 5 in 1.4 78K0S/Kx1+ Product Lineup 2.1 Pin Function List CHAPTER 2 * Modification of description of AVREF PIN FUNCTIONS 2.2.8 AVREF * Modification of description 10.1 Functions of A/D Converter CHAPTER 10 * Addition of Note 4 to Table 10-1 Sampling Time and A/D Conversion Time A/D CONVERTER 10.3 Registers Used by A/D Converter * Addition of Note 5 to Figure 10-3 Format of A/D Converter Mode Register (ADM) CHAPTER 14 Modification of Caution 3 RESET FUNCTION 18.4 Writing with Flash Memory Programmer CHAPTER 18 * Addition of FlashPro5 to Dedicated flash memory programmer FLASH MEMORY * Deletion of PG-FPL2 from Dedicated flash memory programmer * Modification of Remark 18.5 Programming Environment * Modification of Figure 18-2 Environment for Writing Program to Flash Memory (FlashPro4/FlashPro5/ QB-MINI2) and Addition of Note * Modification of Table 18-2 Wiring Between 78K0S/KA1+ and FlashPro4/FlashPro5/ QB-MINI2 and Addition of Note 2 * Modification of Figure 18-3 Wiring diagram with FlashPro4/FlashPro5/QB-MINI2 * Deletion of PG-FPL2 from Dedicated flash memory programmer Modification of Figure 18-5 PG-FP5 GUI Software Setting Example Modification of Figure 18-7 Communication Commands Addition of Note in Table 18-10 Self Programming Controlling Commands CHAPTER 19 ON-CHIP Addition of chapter DEBUG FUNCTION 414 User's Manual U16898EJ6V0UD APPENDIX E REVISION HISTORY (10/10) Edition 5th edition Description Applied to: * Modification of numeric value in X1 Oscillator Characteristics CHAPTER 21 * Modification of CPU Clock Frequency, Peripheral Clock Frequency in AC ELECTRICAL Characteristics SPECIFICATIONS (Standard product, (A) grade product) * Modification of X1 Oscillator Characteristics CHAPTER 22 * Modification of MAX. values of low-level input voltage in DC Characteristics ELECTRICAL * Modification of CPU Clock Frequency, Peripheral Clock Frequency in AC Characteristics SPECIFICATIONS ((A2) grade product) CHAPTER 23 Addition of additional products PACKAGE DRAWING CHAPTER 24 Addition of additional products RECOMMENDED SOLDERING CONDITIONS Modification of Figure A-1. Development Tools APPENDIX A A.4 Flash Memory Writing Tools DEVELOPMENT TOOLS * Addition of FlashPro5 * Deletion of PG-FPL2 A.5.1 When using in-circuit emulator QB-78K0SKX1 * Deletion of description of under development Deletion of A.5.3 When using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A and A.5.4 When using in-circuit emulator QB-78K0SKX1MINI Modification of A.6 Debugging Tools (Software) APPENDIX B NOTES Addition of chapter ON DESIGNING TARGET SYSTEM User's Manual U16898EJ6V0UD 415 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. 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