19-5478; Rev 2; 7/11 TION KIT EVALUA BLE IL AVA A High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator Features The MAX15058 high-efficiency, current-mode, synchronous step-down switching regulator with integrated power switches delivers up to 3A of output current. The device operates from 2.7V to 5.5V and provides an output voltage from 0.6V up to 94% of the input voltage, making the device ideal for distributed power systems, portable devices, and preregulation applications. S Internal 30mI (typ) RDS(ON) High-Side and 18mI The MAX15058 utilizes a current-mode control architecture with a high-gain transconductance error amplifier. The current-mode control architecture facilitates easy compensation design and ensures cycle-by-cycle current limit with fast response to line and load transients. S Operates from 2.7V to 5.5V Supply The MAX15058 offers selectable skip-mode functionality to reduce current consumption and achieve a higher efficiency at light output load. The low RDS(ON) integrated switches ensure high efficiency at heavy loads while minimizing critical inductances, making the layout design a much simpler task with respect to discrete solutions. Utilizing a simple layout and footprint assures first-pass success in new designs. S Factory-Trimmed, 1MHz Switching Frequency The MAX15058 features a 1MHz, factory-trimmed, fixedfrequency PWM mode operation. The high switching frequency, along with the PWM current-mode architecture, allows for a compact, all-ceramic capacitor design. The MAX15058 offers a capacitor-programmable softstart reducing inrush current, startup into PREBIAS operations, and a PGOOD open-drain output that can be used as an interrupt and for power sequencing. The MAX15058 is available in a 9-bump (3 x 3 array), 1.5mm x 1.5mm WLP package and is specified over the -40NC to +85NC temperature range. (typ) Low-Side MOSFETs at 5V S Continuous 3A Output Current Over Temperature S 95% Efficiency with 3.3V Output at 3A S 1% Output Voltage Accuracy Over Load, Line, and Temperature S Cycle-by-Cycle Overcurrent Protection S Adjustable Output from 0.6V to Up to 0.94 x VIN S Programmable Soft-Start S Stable with Low-ESR Ceramic Output Capacitors S Safe-Startup Into Prebiased Output S External Reference Input S Skip-Mode Functionality S Enable Input/Power-Good Output S Fully Protected Against Overcurrent and Overtemperature S Input Undervoltage Lockout Ordering Information PART TEMP RANGE PIN-PACKAGE MAX15058EWL+ -40C to +85C 9 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. Typical Operating Circuit Applications Distributed Power Systems Preregulators for Linear Regulators INPUT 2.8V TO 5.5V IN Portable Devices OUTPUT 1.8V/3A MAX15058 GND Notebook Power Server Power IP Phones LX PGOOD FB ENABLE OFF ON EN COMP SKIP SS/REFIN ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX15058 General Description MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator ABSOLUTE MAXIMUM RATINGS IN, PGOOD to GND.................................................-0.3V to +6V LX to GND...................................................-0.3V to (VIN + 0.3V) LX to GND........................................-1V to (VIN + 0.3V) for 50ns EN, COMP, FB, SS/REFIN, SKIP to GND....-0.3V to (VIN + 0.3V) LX Current (Note 1).................................................... -6A to +6A Output Short-Circuit Duration.....................................Continuous Continuous Power Dissipation (TA = +70NC) 9-Bump WLP Multilayer Board (derate 14.1mW/NC above TA = +70NC).....................1127mW Operating Temperature Range........................... -40NC to +85NC Storage Temperature Range............................. -65NC to +150NC Soldering Temperature (reflow).......................................+260NC Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should not exceed the IC's package power dissipation limits. PACKAGE THERMAL CHARACTERISTICS (Note 2) WLP Junction-to-Case Thermal Resistance (BJC)....................26NC/W Junction-to-Ambient Thermal Resistance (BJA)...............71NC/W Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VIN = 5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER IN Voltage Range SYMBOL CONDITIONS VIN IN Shutdown Supply Current MIN TYP 2.7 MAX UNITS 5.5 V VEN = 0V 0.2 2 FA VEN = 5V, VFB = 0.65V, no switching 1.56 2.3 mA VIN Undervoltage Lockout Threshold LX starts switching, VIN rising 2.6 2.7 V VIN Undervoltage Lockout Hysteresis LX stops switching, VIN falling 200 mV mS IN Supply Current IIN ERROR AMPLIFIER Transconductance gMV 1.5 Voltage Gain AVEA 90 FB Set-Point Accuracy VFB Over line, load, and temperature 594 FB Input Bias Current IFB VFB = 0.6V -500 COMP to Current-Sense Transconductance gMC 600 dB 606 mV +500 nA 18 A/V 0.94 V LX On-Resistance, High-Side pMOS 30 mI LX On-Resistance, Low-Side nMOS 18 mI 5 A Low-Side Switch Sink CurrentLimit Threshold 4 A Low-Side Switch Source CurrentLimit Threshold 5 A COMP Clamp Low VFB = 0.65V, VSS = 0.6V POWER SWITCHES High-Side Switch Current-Limit Threshold IHSCL 2 _______________________________________________________________________________________ High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator (VIN = 5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL LX Leakage Current CONDITIONS MIN TYP VEN = 0V RMS LX Output current MAX UNITS 10 FA 3 A OSCILLATOR Switching Frequency fSW Maximum Duty Cycle DMAX 850 Minimum Controllable On-Time Slope Compensation Ramp Valley Slope Compensation Ramp Amplitude VSLOPE Extrapolated to 100% duty cycle 1000 1150 kHz 94 % 70 ns 1.15 V 320 mV ENABLE EN Input High Threshold Voltage EN Input Low Threshold Voltage EN Input Leakage Current VEN rising VEN falling VEN = 5V SKIP Input Leakage Current VSKIP = VEN = 5V 1.45 0.025 V V FA 25 FA 0.4 SOFT-START, PREBIAS, REFIN Soft-Start Current ISS VSS/REFIN = 0.45V, sourcing 10 FA SS/REFIN Discharge Resistance RSS ISS/REFIN = 10mA, sinking 8.3 I VSS/REFIN rising 0.58 V SS/REFIN Prebias Mode Stop Voltage External Reference Input Range 0 IN - 1.8 V HICCUP Number of Consecutive CurrentLimit Events to Hiccup Timeout 8 Events 1024 Clock Cycles POWER-GOOD OUTPUT PGOOD Threshold VFB rising PGOOD Threshold Hysteresis VFB falling 28 PGOOD VOL IPGOOD = 5mA, VFB = 0.5V VPGOOD = 5V, VFB = 0.65V 20 PGOOD Leakage 0.535 0.555 0.575 V mV 60 mV 0.013 FA 150 NC 20 NC THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Temperature falling Note 3: Specifications are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design and characterization. _______________________________________________________________________________________ 3 MAX15058 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VIN = 5V, VOUT = 1.8V, ILOAD = 3A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.) 90 VOUT = 1.8V VOUT = 1.5V 85 100 VOUT = 2.5V 95 VOUT = 1.2V 90 VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 85 80 100 95 80 2.0 2.5 3.0 0 0.5 OUTPUT CURRENT (A) 1.0 1.5 2.0 EFFICIENCY (%) VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 85 80 0.5 1.0 1.5 2.0 1040 1020 1000 980 960 940 900 2.7 3.2 3.7 4.2 4.7 INPUT VOLTAGE (V) OUTPUT VOLTAGE vs. SUPPLY VOLTAGE OUTPUT VOLTAGE vs. OUTPUT CURRENT MAX15058 toc06 OUTPUT CURRENT (A) 1.85 1.83 1.81 1.79 5.2 1.89 1.87 OUTPUT VOLTAGE (V) 1.87 1.5 1060 3.0 2.5 1.89 OUTPUT VOLTAGE (V) 1.0 1.85 VOUT = 3.3V 1.83 1.81 VOUT = 5V 1.79 1.77 IOUT = 0.5A 3.7 4.2 4.7 SUPPLY VOLTAGE (V) 5.2 1.75 2.0 OUTPUT CURRENT (A) 920 75 3.2 0.5 1080 VIN = 3.3V 2.7 0 MAX15058 toc05 95 1.75 3.0 1100 SWITCHING FREQUENCY (kHz) MAX15058 toc04 VOUT = 2.5V 1.77 2.5 70 SWITCHING FREQUENCY vs. INPUT VOLTAGE 100 0 VOUT = 3.3V OUTPUT CURRENT (A) EFFICIENCY vs. OUTPUT CURRENT (SKIP MODE) 90 80 MAX15058 toc07 1.5 VOUT = 1.2V VOUT = 2.5V VIN = 5V 75 1.0 VOUT = 1.5V VOUT = 1.8V 85 VIN = 3.3V 75 0.5 90 75 VIN = 5V 0 MAX15058 toc03 95 EFFICIENCY vs. LOAD CURRENT (SKIP MODE) MAX15058 toc02 VOUT = 2.5V EFFICIENCY (%) VOUT = 3.3V MAX15058 toc01 100 EFFICIENCY vs. OUTPUT CURRENT (FORCED PWM) EFFICIENCY (%) EFFICIENCY vs. LOAD CURRENT (PWM MODE) EFFICIENCY (%) MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT CURRENT (A) 4 _______________________________________________________________________________________ 2.5 3.0 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator LOAD-TRANSIENT RESPONSE SWITCHING WAVEFORMS (IOUT = 3A) MAX15058 toc08 MAX15058 toc09a VOUT 20mV/div AC-COUPLED 50mV/div AC-COUPLED ILX 1AV/div 1A/div 0A 100s/div VLX 5V/div 400ns/div SWITCHING WAVEFORM IN SKIP MODE (IOUT = 10mA) SWITCHING WAVEFORMS (IOUT = 3A) MAX15058 toc10 MAX15058 toc09b VOUT 20mV/div AC-COUPLED VOUT 50mV/div AC-COUPLED ILX 1AV/div ILX 1A/div 0A VLX 5V/div VLX 5V/div VIN = 3.3V 10s/div 400ns/div INPUT AND OUTPUT WAVEFORMS (IOUT = 3A) SHUTDOWN WAVEFORM MAX15058 toc11 MAX15058 toc12 VENABLE 5V/div INPUT 20mV/div AC-COUPLED VOUT 1V/div ILX 1A/div OUTPUT 100mV/div AC-COUPLED VPGOOD 5V/div 400ns/div 10s/div _______________________________________________________________________________________ 5 MAX15058 Typical Operating Characteristics (continued) (VIN = 5V, VOUT = 1.8V, ILOAD = 3A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) (VIN = 5V, VOUT = 1.8V, ILOAD = 3A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.) SOFT-START WAVEFORMS (SKIP MODE) (IOUT = 3A) SOFT-START WAVEFORMS (PWM MODE) (IOUT = 3A) MAX15058 toc13b MAX15058 toc13a VENABLE 5V/div VENABLE 5V/div VOUT 1V/div VOUT 1V/div ILX 1A/div ILX 1A/div VPGOOD 5V/div VPGOOD 5V/div 200s/div 200s/div SHUTDOWN CURRENT vs. INPUT VOLTAGE SHORT-CIRCUIT HICCUP MODE MAX15058 toc15 VEN = 0V 90 SHUTDOWN CURRENT (nA) MAX15058 toc14 100 80 IIN 500mA/div 70 60 VOUT 200mV/div 50 40 30 20 IOUT 5A/div 10 0 2.7 3.2 3.7 4.2 4.7 200s/div 5.2 INPUT VOLTAGE (V) RMS INPUT CURRENT vs. INPUT VOLTAGE FB VOLTAGE vs. TEMPERATURE 120 80 40 MAX15058 toc17 604 FEEDBACK VOLTAGE (V) 160 0 606 MAX15058 toc16 200 RMS INPUT CURRENT (mA) MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator 602 600 598 596 SHORT CIRCUIT ON OUTPUT 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 INPUT VOLTAGE (V) NO LOAD 594 -40 -20 0 20 40 60 80 AMBIENT TEMPERATURE (C) 6 _______________________________________________________________________________________ High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator SOFT-START WAVEFORMS (EXTERNAL REFIN) (PWM MODE) SOFT-START WAVEFORMS (EXTERNAL REFIN) (SKIP MODE) MAX15058 toc18a NO LOAD MAX15058 toc18b VSS/REFIN 500mV/div VOUT 1V/div NO LOAD ILX 1A/div ILX 1A/div VPGOOD 5V/div VPGOOD 5V/div 200s/div 200s/div STARTING INTO A PREBIASED OUTPUT (IOUT = 2A) STARTING INTO A PREBIASED OUTPUT (NO LOAD) MAX15058 toc19 MAX15058 toc20a VENABLE 5V/div VOUT 1V/div VENABLE 5V/div VOUT 1V/div ILX 1A/div VPGOOD 5V/div PWM MODE ILX 1A/div VPGOOD 5V/div PWM MODE 200s/div 200s/div STARTING INTO A PREBIASED OUTPUT (NO LOAD) STARTING INTO A PREBIASED OUTPUT HIGHER THAN SET OUTPUT MAX15058 toc21 MAX15058 toc20b 1.8V VENABLE 5V/div VOUT 1V/div VPGOOD 5V/div 200s/div VOUT 500mV/div IL 1A/div ILX 1A/div SKIP MODE VSS/REFIN 500mV/div VOUT 1V/div VSS/REFIN 500mV/div 10I LOAD AT OUT 400s/div _______________________________________________________________________________________ 7 MAX15058 Typical Operating Characteristics (continued) (VIN = 5V, VOUT = 1.8V, ILOAD = 3A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) (VIN = 5V, VOUT = 1.8V, ILOAD = 3A, Circuit of Figure 5, TA = +25NC, unless otherwise noted.) INPUT CURRENT IN SKIP MODE vs. OUTPUT VOLTAGE CASE TEMPERATURE vs. AMBIENT TEMPERATURE 80 40 20 0 NO LOAD 4.0 INPUT CURRENT (mA) 60 4.5 3.5 3.0 VCC = 5.0V 2.5 2.0 1.5 1.0 -20 MAX15058 toc23 5.0 MAX15058 toc22 100 CASE TEMPERATURE (C) MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator VCC = 3.3V 0.5 -40 0 -40 -20 0 20 40 60 AMBIENT TEMPERATURE (C) 80 1.2 1.7 2.2 2.7 3.2 OUTPUT VOLTAGE (V) 8 _______________________________________________________________________________________ High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator TOP VIEW (BUMPS ON BOTTOM) MAX15058 GND LX IN A1 A2 A3 COMP SKIP EN B1 B2 B3 FB SS/REFIN PGOOD C1 C2 C3 WLP Pin Description BUMP NAME FUNCTION A1 GND Analog Ground/Low-Side Switch Source Terminal. Connect to the PCB copper plane at one point near the input bypass capacitor return terminal. A2 LX Inductor Connection. Connect LX to the switched side of the inductor. LX is high impedance when the IC is in shutdown mode. A3 IN Input Power Supply. Input supply range is from 2.7V to 5.5V. Bypass with a minimum 10FF ceramic capacitor to GND. See Figures 5 and 6. B1 COMP Voltage Error-Amplifier Output. Connect the necessary compensation network from COMP to GND. See the Closing the Loop: Designing the Compensation Circuitry section. B2 SKIP B3 EN Enable Input. EN is a digital input that turns the regulator on and off. Drive EN high to turn on the regulator. Connect to IN for always-on operation. C1 FB Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to set the output voltage from 0.6V up to 94% of VIN. C2 SS/REFIN Soft-Start/External Voltage Reference Input. Connect a capacitor from SS/REFIN to GND to set the startup time. See the Setting the Soft-Start Time section for details on setting the soft-start time. Apply a voltage reference from 0V to VIN - 1.5V to drive soft-start externally. C3 PGOOD Open-Drain Power-Good Output. PGOOD goes high when FB is above 555mV and pulls low if FB is below 527mV. Skip-Mode Input. Connect to EN to select skip mode or leave unconnected for normal operation. _______________________________________________________________________________________ 9 MAX15058 Pin Configuration MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator Block Diagram SKIP EN IN BIAS GENERATOR SHDN EN LOGIC, IN UVLO THERMAL SHDN SKIP-MODE LOGIC HIGH-SIDE CURRENT LIMIT SKPM LX VOLTAGE REFERENCE CURRENT-SENSE AMPLIFIER LX IN STRONG PREBIASED FORCED START IN SKPM 0.58V LX CONTROL LOGIC SS/REFIN IN CK SS/REFIN BUFFER 0.6V GND 10A PWM COMPARATOR ERROR AMPLIFIER LOW-SIDE SOURCE-SINK CURRENT LIMIT AND ZEROCROSSING COMPARATOR SINK SOURCE FB ZX C COMP RAMP OSCILLATOR RAMP GEN CK SKPM MAX15058 PGOOD POWER-GOOD COMPARATOR 0.555V RISING, 0.527V FALLING 10 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator The MAX15058 high-efficiency, current-mode switching regulator can deliver up to 3A of output current. The MAX15058 provides output voltages from 0.6V to 0.94 x VIN from 2.7V to 5.5V input supplies, making the device ideal for on-board point-of-load applications. The MAX15058 delivers current-mode control architecture using a high-gain transconductance error amplifier. The current-mode control architecture facilitates easy compensation design and ensures cycle-by-cycle current limit with fast response to line and load transients. The MAX15058 features a 1MHz fixed switching frequency, allowing for all-ceramic capacitor designs and fast transient responses. The high operating frequency minimizes the size of external components. The MAX15058 is available in a 1.5mm x 1.5mm (3 x 3 array) x 0.5mm pitch WLP package. The MAX15058 offers a selectable skip-mode functionality to reduce current consumption and achieve a higher efficiency at light output loads. The low RDS(ON) integrated switches (30mI high-side and 18mI low-side, typ) ensure high efficiency at heavy loads while minimizing critical inductances, making the layout design a much simpler task with respect to discrete solutions. Utilizing a simple layout and footprint assures first-pass success in new designs. The MAX15058 features 1MHz Q15%, factory-trimmed, fixed-frequency PWM mode operation. The MAX15058 also offers capacitor-programmable, soft-start reducing inrush current, startup into PREBIAS operation, and a PGOOD open-drain output for sequencing with other devices. Controller Function--PWM Logic The controller logic block is the central processor that determines the duty cycle of the high-side MOSFET under different line, load, and temperature conditions. Under normal operation, where the current-limit and temperature protection are not triggered, the controller logic block takes the output from the PWM comparator and generates the driver signals for both high-side and low-side MOSFETs. The control logic block controls the break-before-make logic and all the necessary timing. The high-side MOSFET turns on at the beginning of the oscillator cycle and turns off when the COMP voltage crosses the internal current-mode ramp waveform, which is the sum of the slope compensation ramp and the current-mode ramp derived from inductor current (current-sense block). The high-side MOSFET also turns off if the maximum duty cycle is 94%, or when the current limit is reached. The low-side MOSFET turns on for the remainder of the oscillation cycle. Starting into a Prebiased Output The MAX15058 can soft-start into a prebiased output without discharging the output capacitor. In safe prebiased startup, both low-side and high-side MOSFETs remain off to avoid discharging the prebiased output. PWM operation starts when the voltage on SS/REFIN crosses the voltage on FB. The MAX15058 can start into a prebiased voltage higher than the nominal set point without abruptly discharging the output. Forced PWM operation starts when the SS/ REFIN voltage reaches 0.58V (typ), forcing the converter to start. In case of prebiased output, below or above the output nominal set point, if low-side sink current-limit threshold (set to the reduced value of -0.4A (typ) for the first 32 clock cycles and then set to -5A (typ)) is reached, the low-side switch turns off before the end of the clock period, and the high-side switch turns on until one of the following conditions is satisfied: * High-side source current hits the reduced high-side current limit (0.4A, typ); in this case, the high-side switch is turned off for the remaining time of the clock period. * The clock period ends. Reduced high-side current limit is activated to recirculate the current into the high-side power switch rather than into the internal high-side body diode, which could be damaged. Low-side sink current limit is provided to protect the low-side switch from excessive reverse current during prebiased operation. In skip mode operation, the prebias output needs to be lower than the set point. Enable Input The MAX15058 features independent device enable control and power-good signal that allow for flexible power sequencing. Drive the enable input (EN) high to enable the regulator, or connect EN to IN for always-on operation. Power-good (PGOOD) is an open-drain output that asserts when VFB is above 555mV (typ), and deasserts low if VFB is below 527mV (typ). Programmable Soft-Start (SS/REFIN) The MAX15058 utilizes a soft-start feature to slowly ramp up the regulated output voltage to reduce input inrush current during startup. Connect a capacitor from SS/ REFIN to GND to set the startup time (see the Setting the Soft-Start Time section for capacitor selection details). ______________________________________________________________________________________ 11 MAX15058 Detailed Description MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator Error Amplifier A high-gain error amplifier provides accuracy for the voltage-feedback loop regulation. Connect the necessary compensation network between COMP and GND (see the Compensation Design Guidelines section). The error-amplifier transconductance is 1.5mS (typ). COMP clamp low is set to 0.94V (typ), just below the slope ramp compensation valley, helping COMP to rapidly return to the correct set point during load and line transients. PWM Comparator The PWM comparator compares COMP voltage to the current-derived ramp waveform (LX current to COMP voltage transconductance value is 18A/V typ). To avoid instability due to subharmonic oscillations when the duty cycle is around 50% or higher, a slope compensation ramp is added to the current-derived ramp waveform. Confirm the compensation ramp slope (0.3V x 1MHz = 0.3V/Fs) is equivalent to half the inductor current downslope in the worst case (load 3A, current ripple 30% and maximum duty-cycle operation of 94%). The slope compensation ramp valley is set to 1.15V (typ). Overcurrent Protection and Hiccup When the converter output is shorted or the device is overloaded, each high-side MOSFET current-limit event (5A typ) turns off the high-side MOSFET and turns on the low-side MOSFET. On each current-limit event a 3-bit counter is incremented. The counter is reset after three consecutive high-side MOSFETs turn on without reaching current limit. If the current-limit condition persists, the counter fills up reaching eight events. The control logic then discharges SS/REFIN, stops both high-side and low-side MOSFETs, and waits for a hiccup period (1024 clock cycles typ) before attempting a new softstart sequence. The hiccup mode is also enabled during soft-start time. Thermal-Shutdown Protection The MAX15058 contains an internal thermal sensor that limits the total power dissipation to protect the device in the event of an extended thermal fault condition. When the die temperature exceeds +150NC (typ), the thermal sensor shuts down the device, turning off the DC-DC converter to allow the die to cool. After the die temperature falls by 20NC (typ), the device restarts, following the soft-start sequence. Skip Mode Operation The MAX15058 operates in skip mode when SKIP is connected to EN. When in skip mode, LX output becomes high impedance when the inductor current falls below 200mA (typ). The inductor current does not become negative. If during a clock cycle the inductor current falls below the 200mA threshold (during off-time), the low side turns off. At the next clock cycle, if the output voltage is above set point, the PWM logic keeps both high-side and low-side MOSFETs off. If instead the output voltage is below the set point, the PWM logic drives the highside on for a minimum fixed on-time (300ns typ). In this way the system can skip cycles, reducing frequency of operations, and switches only as needed to service load at the cost of an increase in output voltage ripple (see the Skip Mode Frequency and Output Ripple section). In skip mode, power dissipation is reduced and efficiency is improved at light loads because power MOSFETs do not switch at every clock cycle. Applications Information Setting the Output Voltage The MAX15058 output voltage is adjustable from 0.6V up to 94% of VIN by connecting FB to the center tap of a resistor-divider between the output and GND (Figure 1). Choose R1 and R2 so that the DC errors due to the FB input bias current (Q500nA) do not affect the output voltage accuracy. With lower value resistors, the DC error is reduced, but the amount of power consumed in the resistor-divider increases. A typical value for R2 is 10kI, but values between 5kI and 50kI are acceptable. Once R2 is chosen, calculate R1 using: V R1 = R2 x OUT - 1 VFB where the feedback threshold voltage, VFB = 0.6V (typ). When regulating for an output of 0.6V in skip mode, short FB to OUT and keep R2 connected from FB to GND. Inductor Selection A high-valued inductor results in reduced inductor ripple current, leading to a reduced output ripple voltage. However, a high-valued inductor results in either a larger physical size or a high series resistance (DCR) and a lower saturation current rating. Typically, choose an inductor value to produce a current ripple equal to 30% of load current. Choose the inductor with the following formula: V VOUT L= x 1 - OUT fSW x LIR x ILOAD VIN where fSW is the internally fixed 1MHz switching frequency, and LIR is the desired inductor current ratio (typically 12 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator ERROR AMPLIFIER POWER MODULATOR SLOPE COMPENSATION RAMP OUTPUT FILTER AND LOAD VIN VOUT C gMC FB R1 *CFF VFB COMP R2 QHS PWM CONTROL LOGIC VCOMP gMV ROUT DCR VOUT IOUT ESR QLS COMPARATOR RC IL L RLOAD COUT CC VCOMP REF ROUT = 10AVEA(dB)/20/gMV GMOD IOUT NOTE: THE GMOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF THE INDUCTOR, IL, INJECTED INTO THE OUTPUT LOAD, IOUT, e.g., IL = IOUT. THIS CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER STATE CIRCUITRY SHOWN WITHIN THE BOXED AREA. *NOTE: CFF IS OPTIONAL AND DESIGNED TO EXTEND THE REGULATOR'S GAIN BANDWIDTH AND INCREASED PHASE MARGIN FOR SOME LOW-DUTY CYCLE APPLICATIONS. Figure 1. Peak Current-Mode Regulator Transfer Model set to 0.3). In addition, the peak inductor current, IL_PK, must always be below the minimum high-side currentlimit value, IHSCL, and the inductor saturation current rating, IL_SAT. Ensure that the following relationship is satisfied: 1 IL_PK = ILOAD + IL < min IHSCL_, IL_SAT 2 ( ) Input Capacitor Selection The input capacitor reduces the peak current drawn from the input power supply and reduces switching noise in the device. The total input capacitance must be equal to or greater than the value given by the following equation to keep the input ripple voltage within the specification and minimize the high-frequency ripple current being fed back to the input source: CIN = ILOAD V x OUT fSW x VIN_RIPPLE VIN where DVIN_RIPPLE is the maximum-allowed input ripple voltage across the input capacitors and is recommended to be less than 2% of the minimum input voltage, fSW is the switching frequency (1MHz), and ILOAD is the output load. The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source, but are instead shunted through the input capacitor. The input capacitor must meet the ripple current requirement imposed by the switching currents. The RMS input ripple current is given by: V OUT x (VIN - VOUT ) IRIPPLE = ILOAD VIN where IRIPPLE is the input RMS ripple current. Output Capacitor Selection The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage rating. The parameters affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor's ESR, and the voltage drop due to the ______________________________________________________________________________________ 13 MAX15058 FEEDBACK DIVIDER MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator capacitor's ESL. Estimate the output-voltage ripple due to the output capacitance, ESR, and ESL as follows: VOUT = VOUT VOUT 1 x 1 - x R ESR_COUT + fSW x L VIN 8 x fSW x C OUT For ceramic capacitors, ESR contribution is negligible: R ESR_OUT << 1 8 x fSW x C OUT the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to the predetermined value. Use higher COUT values for applications that require light load operation or transition between heavy load and light load, triggering skip mode, causing output undershooting or overshooting. When applying the load, limit the output undershoot by sizing COUT according to the following formula: C OUT For tantalum or electrolytic capacitors, ESR contribution is dominant: R ESR_OUT >> 1 8 x fSW x C OUT Use these equations for initial output-capacitor selection. Determine final values by testing a prototype or an evaluation circuit. A smaller ripple current results in less output-voltage ripple. Since the inductor ripple current is a factor of the inductor value, the output-voltage ripple decreases with larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The ripple voltage due to ESL is negligible when using ceramic capacitors. Load-transient response also depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x DILOAD. Before the controller can respond, the output deviates further, depending on ILOAD 3fCO x VOUT where DILOAD is the total load change, fCO is the regulator unity-gain bandwidth (or zero crossover frequency), and DVOUT is the desired output undershooting. When removing the load and entering skip mode, the device cannot control output overshooting, since it has no sink current capability; see the Skip Mode Frequency and Output Ripple section to properly size COUT. Skip Mode Frequency and Output Ripple In skip mode, the switching frequency (fSKIP) and output ripple voltage (VOUT-RIPPLE) shown in Figure 2 are calculated as follows: tON is a fixed time (300ns, typ); the peak inductor current reached is: V - VOUT I SKIP -LIMIT = IN x t ON L IL ISKIP-LIMIT ILOAD tON tOFF1 tOFF2 = n x tCK VOUT VOUT-RIPPLE Figure 2. Skip Mode Waveform 14 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator t OFF1 = L x I SKIP -LIMIT VOUT During tON and tOFF1, the output capacitor stores a charge equal to (see Figure 2): 1 1 2 + L x (I SKIP -LIMIT - ILOAD ) x - V V V OUT OUT IN Q OUT = 2 During tOFF2 (= n x tCK, number of clock cycles skipped), output capacitor loses this charge: Q OUT t OFF2 = ILOAD 1 1 2 L x (I SKIP - LIMIT - ILOAD ) x + V - V V OUT OUT IN t OFF2 = 2 xILOAD Finally, frequency in skip mode is: fSKIP = 1 t ON + t OFF1 + t OFF2 the inductor's pole frequency is shifted beyond the gain bandwidth of the regulator. System stability is provided with the addition of a simple series capacitor-resistor from COMP to GND. This pole-zero combination serves to tailor the desired response of the closed-loop system. The basic regulator loop consists of a power modulator (comprising the regulator's pulse-width modulator, current sense and slope compensation ramps, control circuitry, MOSFETs, and inductor), the capacitive output filter and load, an output feedback divider, and a voltage-loop error amplifier with its associated compensation circuitry. See Figure 1. The average current through the inductor is expressed as: IL = G MOD x VCOMP where IL is the average inductor current and GMOD is the power modulator's transconductance. For a buck converter: VOUT = R LOAD x IL where RLOAD is the equivalent load resistor value. Combining the above two relationships, the power modulator's transfer function in terms of VOUT with respect to VCOMP is: R xI = LOAD L = RLOAD x G MOD VCOMP IL GMOD VOUT Output ripple in skip mode is: VOUT -RIPPLE = VCOUT -RIPPLE + VESR-RIPPLE -I (I ) x t ON = SKIP -LIMIT LOAD C OUT + R ESR,COUT x (I SKIP -LIMIT - ILOAD ) L x I SKIP -LIMIT VOUT -RIPPLE = + RESR,COUT C OUT x (VIN - VOUT ) x (I SKIP -LIMIT - ILOAD ) To limit output ripple in skip mode, size COUT based on the above formula. All the above calculations are applicable only in skip mode. Compensation Design Guidelines The MAX15058 uses a fixed-frequency, peak-current-mode control scheme to provide easy compensation and fast transient response. The inductor peak current is monitored on a cycle-by-cycle basis and compared to the COMP voltage (output of the voltage error amplifier). The regulator's duty cycle is modulated based on the inductor's peak current value. This cycle-by-cycle control of the inductor current emulates a controlled current source. As a result, The peak current-mode controller's modulator gain is attenuated by the equivalent divider ratio of the load resistance and the current-loop gain's impedance. GMOD becomes: 1 G MOD (DC) = g MC x RLOAD x K S x (1 - D) - 0.5 1 + f x L SW where RLOAD = VOUT/IOUT(MAX), fSW is the switching frequency, L is the output inductance, D is the duty cycle (VOUT/VIN), and KS is a slope compensation factor calculated from the following equation: S V xf x L x g MC K S = 1 + SLOPE = 1 + SLOPE SW SN (VIN - VOUT ) where: V S SLOPE = SLOPE = VSLOPE x fSW t SW SN = (VIN - VOUT ) L x g MC ______________________________________________________________________________________ 15 MAX15058 tOFF1 is the time needed for inductor current to reach the zero-current crossing limit (~0A): MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator 1ST ASYMPTOTE R2 x (R1 + R2)-1 x 10AVEA(dB)/20 x gMC x RLOAD x {1 + RLOAD x [KS x (1 - D) - 0.5] x (L x fSW)-1}-1 2ND ASYMPTOTE R2 x (R1 + R2)-1 x gMV x (2GCC)-1 x gMC x RLOAD x {1 + RLOAD x [KS x (1 - D) - 0.5] x (L x fSW)-1}-1 GAIN 3RD ASYMPTOTE R2 x (R1 + R2)-1 x gMV x (2GCC)-1 x gMC x RLOAD x {1 + RLOAD x [KS x (1 - D) - 0.5] x (L x fSW)-1}-1 x (2GCOUT x {RLOAD-1 + [KS x (1 - D) - 0.5] x (L x fSW)-1}-1)-1 4TH ASYMPTOTE R2 x (R1 + R2)-1 x gMV x RC x gMC x RLOAD x {1 + RLOAD x [KS x (1 - D) - 0.5] x (L x fSW)-1}-1 x (2GCOUT x {RLOAD-1 + [KS x (1 - D) - 0.5] x (L x fSW)-1}-1)-1 3RD POLE (DBL) 2ND ZERO 0.5 x fSW (2GCOUTESR)-1 UNITY 1ST POLE [2GCC x (10AVEA(dB)/20 - gMV-1)]-1 FREQUENCY fCO 2ND POLE fPMOD* 5TH ASYMPTOTE R2 x (R1 + R2)-1 x gMV x RC x gMC x RLOAD x {1 + RLOAD x [KS x (1 - D) - 0.5] x (L x fSW)-1}-1 x (2GCOUT x {RLOAD-1 + [KS x (1 - D) - 0.5] x (L x fSW)-1}-1)-1 x (0.5 x fSW)2 x (2Gf)-2 1ST ZERO (2GCCRC)-1 NOTE: ROUT = 10AVEA(dB)/20 x gMV-1 fPMOD = [2GCOUT x (ESR + {RLOAD-1 + [KS x (1 - D) - 0.5] x (L x fSW)-1}-1)]-1 6TH ASYMPTOTE R2 x (R1 + R2)-1 x gMV x RC x gMC x RLOAD x {1 + RLOAD x [KS x (1 - D) - 0.5] x (L x fSW)-1}-1 x ESR x {RLOAD-1 + [KS x (1 - D) - 0.5] x (L x fSW)-1}-1 x (0.5 x fSW)2 x (2Gf)-2 WHICH FOR ESR << {RLOAD-1 + [KS x (1 - D) - 0.5] x (L x fSW)-1}-1 BECOMES fPMOD = [2GCOUT x {RLOAD-1 + [KS x (1 - D) - 0.5] x (L x fSW)-1}-1]-1 fPMOD = (2GCOUT x RLOAD)-1 + [KS x (1 - D) - 0.5] x (2GCOUT x L x fSW)-1 Figure 3. Asymptotic Loop Response of Current-Mode Regulator As previously mentioned, the power modulator's dominant pole is a function of the parallel effects of the load resistance and the current-loop gain's equivalent impedance: fPMOD = 1 1 K S x (1 - D) - 0.5 + 2 x C OUT x ESR + RLOAD fSW x L -1 And knowing that the ESR is typically much smaller than the parallel combination of the load and the current loop: 1 K S x (1 - D) - 0.5 ESR << + R LOAD fSW x L fPMOD -1 fPMOD K S x (1 - D) - 0.5 + 2 x C OUT x R LOAD 2 x fSW x L x C OUT 1 Note: Depending on the application's specifics, the amplitude of the slope compensation ramp could have a significant impact on the modulator's dominate pole. For low duty-cycle applications, it provides additional damping (phase lag) at/near the crossover frequency (see the Closing the Loop: Designing the Compensation Circuitry section). There is no equivalent effect on the power modulator zero, fZMOD. fZMOD = fZESR = 1 1 K S x (1 - D) - 0.5 + 2 x C OUT x RLOAD fSW x L which can be expressed as: 1 2 x C OUT x ESR -1 16 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator s2 ( x fSW ) 2 + s x fSW x Q C +1 where the sampling effect quality factor, QC, is: 1 x K S x (1 - D) - 0.5 And the resonant frequency is: SAMPLING(s) = x fSW or: f fSAMPLING = SW 2 Having defined the power modulator's transfer function, the total system transfer can be written as follows (see Figure 3): Gain(s) = GFF(s) x GEA(s) x GMOD(DC) x GFILTER(s) x GSAMPLING(s) where: (sC FFR1 + 1) R2 x R1 + R2 sC FF (R1|| R2) + 1 G FF (s) = Leaving CFF empty, GFF(s) becomes: R2 G FF (s) = R1 + R2 Also: GEA (s) = 10 AVEA(dB)/20 x (sC CR C + 1) 10 AVEA(dB)/20 sC C R C + + 1 g MV which simplifies to: GEA (s) = 10 AVEA(dB)/20 x when R C << (sC CR C + 1) 10 AVEA(dB)/20 sC C + 1 g MV 10 AVEA(dB)/20 g MV G FILTER (s) = R LOAD x fP1 = 1 G SAMPLING (s) = QC = The dominant poles and zeros of the transfer loop gain are shown below: (sC OUTESR + 1) -1 K S x (1 - D) - 0.5 1 sC + + 1 OUT R fSW x L LOAD fP2 = gMV AVEA(dB)/20 xC 2 x 10 C 1 K S x (1-D) -0.5 -1 1 + 2 x C OUT fSW x L R LOAD 1 (fSW ) 2 1 fZ1 = 2 x C CR C fP3 = fZ2 = 1 2 x C OUTESR The order of pole-zero occurrence is: fP1 < fP2 fZ1 < fCO fP3 < fZ2 Under heavy load, fP2, approaches fZ1. Figure 3 shows a graphical representation of the asymptotic system closed-loop response, including dominant pole and zero locations. The loop response's fourth asymptote (in bold, Figure 3) is the one of interest in establishing the desired crossover frequency (and determining the compensation component values). A lower crossover frequency provides for stable closed-loop operation at the expense of a slower load- and line-transient response. Increasing the crossover frequency improves the transient response at the (potential) cost of system instability. A standard rule of thumb sets the crossover frequency between 1/10 and 1/5 of the switching frequency. First, select the passive power and decoupling components that meet the application's requirements. Then, choose the small-signal compensation components to achieve the desired closed-loop frequency response and phase margin as outlined in the Closing the Loop: Designing the Compensation Circuitry section. Closing the Loop: Designing the Compensation Circuitry 1) Select the desired crossover frequency. Choose fCO approximately 1/10 to 1/5 of the switching frequency (fSW). 2) Determine RC by setting the system transfer's fourth asymptote gain equal to unity (assuming fCO > fZ1, fP2, and fP1) where: ______________________________________________________________________________________ 17 MAX15058 The effect of the inner current loop at higher frequencies is modeled as a double-pole (complex conjugate) frequency term, GSAMPLING(s), as shown: MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator R LOADK S (1 - D) - 0.5 1 + L x fSW R1 + R2 x 2f C RC = x CO OUT x R2 g MV x g MC x R LOAD 1 ESR + K S (1 - D) - 0.5 1 + R LOAD L x fSW and where the ESR is much smaller than the parallel combination of the equivalent load resistance and the current loop impedance, e.g.,: ESR << 1 1 K S (1 - D) - 0.5 + R LOAD L x fSW RC becomes: RC = R1 + R2 2fCO x C OUT x R2 g MV x g MC 3) Determine CC by selecting the desired first system zero, fZ1, based on the desired phase margin. Typically, setting fZ1 below 1/5 of fCO provides sufficient phase margin. fZ1 = f 1 CO 2 x C CR C 5 therefore: CC 5 2 x fCO x R C 4) For low duty-cycle applications, the addition of a phase-leading capacitor (CFF in Figure 1) helps mitigate the phase lag of the damped half-frequency double pole. Adding a second zero near to but below the desired crossover frequency increases both the closed-loop phase margin and the regulator's unitygain bandwidth (crossover frequency). Select the capacitor as follows: 1 C FF = 2 x fCO x (R1|| R2) This guarantees the additional phase-leading zero occurs at a frequency lower than fCO from: 1 fPHASE_LEAD = 2 x C FF x R1 Using CFF the zero-pole order is adjusted as follows: fP1 < fP2 fZ1 < 1 1 < 2C FFR1 2C FF (R1|| R2) fCO < fP3 < fZ2 Confirm the desired operation of CFF empirically. The phase lead of CFF diminishes as the output voltage is a smaller multiple of the reference voltage, e.g., below about 1V. Do not use CFF when VOUT = VFB. Setting the Soft-Start Time The soft-start feature ramps up the output voltage slowly, reducing input inrush current during startup. Size the CSS capacitor to achieve the desired soft-start time, tSS, using: I xt C SS = SS SS VFB ISS, the soft-start current, is 10FA (typ) and VFB, the output feedback voltage threshold, is 0.6V (typ). When using large COUT capacitance values, the high-side current limit can trigger during the soft-start period. To ensure the correct soft-start time, tSS, choose CSS large enough to satisfy: C SS >> C OUT x VOUT x I SS (IHSCL_ - IOUT ) x VFB IHSCL_ is the typical high-side MOSFET current-limit value. An external tracking reference with steady-state value between 0V and VIN - 1.8V can be applied to SS/REFIN. In this case, connect an RC network from external tracking reference and SS/REFIN, as shown in Figure 4. The recommended value for RSS is approximately 1kI. RSS is needed to ensure that, during hiccup period, SS/ REFIN can be internally pulled down. When an external reference is connected to SS/REFIN, the soft-start must be provided externally. VREF_EXT RSS SS/REFIN CSS MAX15058 Figure 4. RC Network for External Reference at SS/REFIN 18 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator LOUT (ICE IN06142) 1H IN CIN 22F LX 1.2I RPULL 20kI MAX15058 PGOOD ON ENABLE OUTPUT 1.8V AT 3A EN OFF SKIP SS/REFIN CSS 22nF 1nF COUT 22F x 2 CFF 100pF R1 8.06kI GND FB R2 4.02kI COMP RC 5.36kI CC 1nF Figure 5. Application Circuit for PWM Mode Operation Power Dissipation The MAX15058 is available in a 9-bump WLP package and can dissipate up to 1127mW at TA = +70NC. When the die temperature exceeds +150NC, the thermal-shutdown protection is activated (see the Thermal-Shutdown Protection section). Layout Procedure Careful PCB layout is critical to achieve clean and stable operation. It is highly recommended to duplicate the MAX15058 Evaluation Kit layout for optimum performance. If deviation is necessary, follow these guidelines for good PCB layout: 1) Connect the signal and ground planes at a single point immediately adjacent to the GND bump of the IC. 2) Place capacitors on IN and SS/REFIN as close as possible to the IC and the corresponding pad using direct traces. 3) Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by LX, the output capacitors, and the input capacitors. 4) Connect IN, LX, and GND separately to a large copper area to help cool the IC to further improve efficiency. 5) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close as possible to the IC. 6) Route high-speed switching nodes (such as LX) away from sensitive analog areas (such as FB and COMP). ______________________________________________________________________________________ 19 MAX15058 INPUT 2.8V TO 5.5V MAX15058 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator INPUT 2.8V TO 5.5V LOUT (ICE IN06142) 1H IN CIN 22F LX 1.2I RPULL 20kI MAX15058 PGOOD ON ENABLE OUTPUT 1.8V AT 3A EN OFF SKIP SS/REFIN CSS 22nF COUT 22F x 2 1nF CFF 100pF R1 8.06kI GND FB R2 4.02kI COMP RC 5.36kI CC 1nF Figure 6. Application Circuit for Skip Mode Operation Package Information Chip Information PROCESS: BiCMOS For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 9 WLP W91E1Z+1 21-0508 Refer to Application Note 1891 20 High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator REVISION NUMBER REVISION DATE 0 12/10 Initial release -- 1 3/11 Revised Package Information section. 20 7/11 Changed the 1.65mm x 1.65mm, 9-bump package information to 1.5mm x 1.5mm, 9-bump package information. Inserted Typical Operating Circuit on page one. 2 DESCRIPTION PAGES CHANGED 1, 11 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products 21 Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX15058 Revision History