E-L6565D - STMicroelectronics, Inc.

1/17

L6565

January 2003

■QUASI-RESONANT (QR) ZERO-VOLTAGE-

SWITCHING (ZVS) TOPOLOGY

■LINE FEED FORWARD TO DELIVER

CONSTANT P OWER vs. MAINS CHANGE

■FRE QUEN C Y FO L DB ACK FOR OP TI MU M

STAND BY EFFI CI ENC Y

■PULSE-BY-PULSE & HICCUP-MODE OCP

■ULTRA-LOW S TART-UP (< 70µA) AND

QUIESCENT CURRENT (< 3.5mA)

■DISABLE FUNCTION (ON/OFF CO NTROL)

■1% PRECISION (@ Tj = 25°C) INTERNAL

REFERENCE VOLTAGE

■±40 0 mA TOTEM POLE GA TE DRIVE R W I TH

UVLO PULL-DOWN

■BLUE ANGEL, ENERGY STAR, ENERGY

2000 COMPLIANT

APPLICATIONS

■TV/MONITOR SMPS

■AC-DC ADAPTERS/CHA R GERS

■DIGITAL CONSUMER

■PRINTERS, FAX MACHINES,

PHOTOCOPIERS AND SCANNERS

DESCRIPTION

The L6565 is a current-mode primary controller IC,

specifically designed to build offline Quasi-resonant

ZVS (Zero Voltage Switching at switch turn-on) fly-

back converters.

Quasi-resonant operation is achieved by means of a

transformer demagnetization sensing input that trig-

gers MOSFET' s turn-on.

DIP8(Minidip) SO-8

ORDER ING NUMB ERS :

L6565N L6565D

QUASI-RESONANT SMPS CONTROLLER

BLOCK DIAGRAM

VREF2

VOLTAGE

REGULATOR

INTERNAL

SUPPLY

2.5V

DRIVER

ZERO CURRENT

DETECTOR

2.1V

1.6V

VCC8

ZCD

VCC

INV

COMP VFF

GND

20V

40K

5pF

BLANKING

LINE VOLTAGE

FEEDFORWARD

Hiccup-mode

OCP

DISABLE

STARTER

2 V

Hiccup-mode

OCP

Starter

STOP

UVLO

Blanking

START

L6565

2/17

DESCRIPTION

(continued)

Converter's power capability variations with the mains voltage are compensated by line voltage feedforward.

At light load the device features a special function that automatically lowers the operating frequency still main-

taining the operation as close to ZVS as possible. In addition to very low start-up and quiescent currents, this

feature helps keep low the consumption from the mains at light load and be Blue Angel and Energy Star com-

pliant.

The IC includes also a disable function, an on-chip filter on current sense, an error amplifier with a precise ref-

erence voltage for primary regulation and an effective two-level overcurrent protection.

PIN CONNECTION

(Top view, Minidip and SO8)

PIN DESCRIPTION

N° Name Function

1 INV Inverting input of the error amplifier. The information on the output voltage is fed into the pin

through either a resistor divider (primary regulation) or an optocoupler (secondary feedback).

This pin can be grounded in some secondary feedback schemes (see pin 2).

2 COMP Output of the error amplifier. Typically, a compensation network is placed between this pin and

the INV pin to a chieve stability and goo d dy namic per forman ce o f the voltage con trol lo op. With

secondar y feedback, the pin can be also driven directly by an optocoupler to control PWM by

modulating the current sunk from the pin (with the INV pin grounded).

3 VFF Line voltage feedforward. The information on the converter’s input voltage is fed into the pin

through a resistor divider and is used to change the setpoint of the pulse-by-pulse current

limitation (the higher the voltage, the lower the setpoint). If this function is not desired the pin will

be grounded and the current limitation setpoint will be maximum.

4 CS Input to the PWM comparator. The primary current is sensed through a resistor, the resulting

voltage is applied to thi s pin and compared with an internal reference to determine MOSFET’s

turn -off. The inter nal reference is clamped at a value, which defin es the pulse-by-pulse current

limitation setpo int, d epen ding on th e voltage at p in VF F. If th e sig nal a t the pin C S exceeds 2 V,

the gate driver will be disabled (Hiccup-mode OCP).

5 ZCD Transformer’s demagnetization sensing input for Quasi-Resonant operation. Alternately,

synchron ization input for an exter nal signal. A nega tive-going edg e triggers MO SFET’s turn-on.

The trig ger circuit is blanked for a mini mum of 3.5 µs af ter MOSFET turn-o ff, for sa fe operation

under short circuit conditions and frequency foldback. If the pin is grounded the IC will be

disabled.

6 GND Ground. Current return for both the signal part of the IC and the gate driver.

7 GD Gate d river output. The totem pole output stage is able to drive power MOSFET ’s and IGBT’s

with a peak current of 400 mA (source and sink).

8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. An electrolytic capacitor is

connected between this pin and ground. A resistor connected from this pin to the converter’s

input bulk capacitor will be typically used to start up the device.

ZCD

INV

COMP

VFF

Vcc

GND

3/17

L6565

THERMAL DATA

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter SO8 Minidip Unit

Rth j-amb Max. Thermal Resistance, Junction-to-ambient 150 100 °C/W

Symbol Pin Parameter Value Unit

IVcc 8I

CC + IZ30 mA

IGD 7 Output Totem Pole Peak Current (2 µs) ±700 mA

INV, COMP,

VFF, CS 1, 2, 3 4 Analog Inputs & Outputs -0.3 to 7 V

IZCD 5 Zero Current Detector 50 (source)

-10 (sink) mA

Ptot Power Dissipation @Tamb = 50°C (Minidip)

(SO8) 1

0.65 W

TjJunction Temperature Operating range -40 to 150 °C

Tstg Storage Temperature -55 to 150 °C

ELECTRICAL CHARACTERISTCS

= -25 to 125°C, V

= 12V, C

= 1nF; unless otherwise specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY VOLTAGE

Vcc Operating range After turn-on 10.3 18

VCCOn Tur n-on thresh old 12.5 13.5 14 .5 V

VCCOff Tur n-off thresh old 8.7 9.5 10.3 V

Hys Hysteresis 3.65 4 4.3 V

VZZener Voltage Icc = 25 mA 18 20 22 V

SUPPLY CURRENT

Istart-up Start-up Current Before turn-o n, VCC = 12V 45 70 µA

IqQuiescent Current After turn-on 2.3 3.5 mA

ICC Operating Supply Current @ 70 kHz 3.5 5 mA

IqQuiescent Current During Hiccup-mode OCP 1.6 3.5 mA

IqQuiescent Current VZCD < VDIS, VCC>VCCOff 1.4 2.1 mA

LINE FEEDFORWARD

IVFF I nput Bias Curren t VVFF = 0 to 3 V -1 µA

VVFF Operating Range 0 to 3 V

K Gain VVFF = 1.5V, VCOMP = 4V 0.16

ERROR AMPLIFIER

VINV Voltage Feedback Input

Threshold Tamb = 25°C 2.465 2.5 2.535 V

12V < VCC < 18V 2.44 2.56

Line Regulation Vcc = 12 to 18V 2 5 mV

IINV Input Bias Curren t -0.1 - 1 µA

L6565

4/17

GVVoltage Gain Open loop 60 80 dB

GB Gain-B andw idth Produ ct 1 MHz

ICOMP Source Current VCOMP = 4V, VINV = 2.4 V -2 -3.5 -5 mA

Sink Current VCOMP = 4V, VINV = 2.6 V 2.5 4.5 mA

VCOMP Upper Clamp Voltage ISOURCE = 0.5 mA 5 5.5 V

Lower Clamp Voltage ISINK = 0.5 mA 2.25 2.55 V

CURRENT SENSE COMPARATOR

ICS Input Bias Curren t V CS = 0 -0.05 -1 µA

td(H-L) Delay to Ou tput 200 450 ns

VCSx Current Sense Reference Clamp

COMP

= Upper clamp, V

VFF

= 0V

1.28 1.4 1.5 V

COMP

= Upper clamp , V

VFF

= 1.5V

0.62 0.7 0.78

COMP

= Upper clamp , V

VFF

= 3V

00.2

CSdis Hiccup-mode OCP level 1.85 2.0 2.2 V

ZERO CURRENT DETECTOR/ SYNCHRONIZATION

VZCDH Upper Clamp Voltage IZCD = 3mA 4.7 5.2 6.1 V

VZCDL Lower Clamp Voltage IZCD = - 3mA 0.3 0.65 1 V

VZCDA Arming Voltage

(positive-going edge) (1) 2.1 V

VZCDT Triggering Voltage

(nega tive-going edge) 1.6 V

IZCDb Input Bias Curren t VZCD = 1 to 4.5 V 2 µA

IZCDsrc Source Current Capability -3 -10 mA

IZCDsnk Sink Current Capability 3 10 mA

VDIS Disable Threshold 150 200 250 mV

IZCDr Restart Current After Disable VZCD < VDIS, Vcc > Vccoff -70 -150 -230 µA

TBLANK Blanking time after pin 7 high-to-

low transition VCOMP ≥ 3.2 V 3.5 µs

VCOMP = 2.5 V 18

START TIMER

tSTART Start Timer period 250 400 550 µs

GATE DRIVER

VOL Dropout Voltage IGDsource = 200mA 1.2 2 V

IGDsource = 20mA 0.7 1

VOH IGDsink = 200mA 2 V

IGDsink = 20mA 0.3

tfCurrent Fall Time 40 100 ns

trCurrent Rise Time 40 100 ns

IGDoff IGD sink current Vcc = 4 V, VGD = 1 V 5 10 mA

(1) Parameters guar anteed by design, not tes ted in production.

ELECTRICAL CHARACTERISTCS

(continued)

= -25 to 125°C, V

= 12V, C

= 1nF; unless otherwise specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

5/17

L6565

Figure 1. Supply current vs. Supply voltage

Figu re 2. Sta rt -up & U VL O vs. Te m pe ra ture

Figu re 3. Feedbac k ref ere n ce vs. Temperature

Figure 4. Line feedforw ard ch aracteristi cs

Figure 5. Pin 2 (COMP) V-I characteristics

Figure 6. ZCD blanking time vs. C OMP vo ltage

0 5 10 15 20 VCC

(

)

0.005

0.01

0.05

0.1

0.5

ICC

(mA)

CL = 1nF

f = 70K Hz

TA = 25° C

T (°C)

VCC-ON

(V)

VCC-OFF

(V)

-25 0 25 50 75 100 125

-50 0 50 100

2.46

2.48

2.50

T (°C)

VREF

(V)

D94IN048A

Vcsx [V]

0 0.5 1 1.5 2 2.5 3 3.5

0.5

1.5

VVFF [V]

VCOMP = 2.5V

3.0 V

3.5 V

4.0 V

4.5 V

5.0 V

Upper clamp

01234

Regulation

range

VCOMP [V]

ICOMP [mA]

Tj = 25 °C

Vpi n1 = 0

TBLANK [µs]

23456

VCOMP [V]

Tj = 25 °C

L6565

6/17

Figure 7. Gate-dr i ve output satu r ation

Figure 8. Gate-dr i ve output satu r ation

Figu re 9. IC consu m pti on v s. te m per ature

Figure 10. Zener voltage at Vcc pin vs. Tj

Figure 11. Start-up timer period vs. Tj

Vpin7 [V]

0 100 200 300 400 500

0.5

1.5

2.5

IGD [mA]

Tj = 25 °C

Vcc = 14.5 V

SINK

Vpin7 [V]

0 100 200 300 400 500

-2.5

-2

-1.5

-1

-0.5

IGD [mA]

Tj = 25 °C

Vcc = 14.5 V

SOURCE

Vcc - 0.5

Vcc - 1.0

Vcc - 1.5

Vcc - 2.0

Vcc - 0.5

Icc [mA]

-50 0 50 100 150

0.02

0.05

0.1

0.2

0.5

Tj [°C]

Quiescent

Before Start-up

Vcc=12V

Vz [V]

-50 0 50 100 150

Tj [°C]

TSTART [µs]

-50 0 50 100 150

250

300

350

400

450

Tj [°C]

Vcc=12V

7/17

L6565

APPLICATION INFORMATION

Quasi- resonant operation i n offli ne fly back converters lies in s ynchroniz ing MO SFET's turn- on to the transfor m-

er's demagnetization. Detecting the resulting negative-going edge of the voltage across any winding of the

trans former can do this. The L6565 is provid ed with a dedicated pin that allow s doing the job with a very si mple

interface, just one resistor.

Variable frequency operation - as a result of different operating conditions in terms of input voltage and output

current - is inherent in such functionality. The system always works close to the boundary between DCM (Dis-

continuous Conduction Mode) and CCM (Continuous Conduction Mode) operation of the transformer. The op-

eration is then identical to that of the so-called self-oscillating or Ringing Choke Converter (RCC).

Detailed Device Description

Internal Supply Block (see fig. 12)

A linear voltage regulator supplied by V

(pin 8) generates an internal 7V rail used for supplying the entire IC,

except for the gate driver that is supplied directly from Vcc. In addition, a bandgap circuit generates a precis e

internal reference (2.5V±1% @ 25°C) used by the control loop to ensure a good regulation with primary feed-

back technique.

In figure 12 it is also shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the

chip as long as the Vcc voltage is high enough to ensure a reliable operation.

Figure 12. L6 565 internal sup ply block

+Vin

REF.

UVLO

2.5V

7V bus

LIN.

REG.

Vcc

L6565

8/17

Zero Current Detection and Triggering Block (see fig. 13):

The Zero Current Det ection (ZCD) block sw itches on the extern al MOSFET if a negative-going edge falling be-

low 1.6 V i s ap plied to the input (pin 5, ZCD). H owever, to en sure hig h nois e im munity, the tr igge ring blo ck must

be armed first : prior to falling below 1.6V, the voltage on pin 5 must exper ience a positive-going edge exc eeding

2.1 V.

This feature is typically used to detect transformer demagnetization for QR operation, where the signal for the

ZCD in put is obtai ned from the transfor mer's auxil iar y winding us ed also to s upply the IC. A lternativel y, this can

be used to synchronize MOSFET's turn-on to the negative-going edge of an external clock signal, in case the

device is not required to work in QR mode but as a standard PWM controller in a synchronized system (e.g.

monitor SMPS).

The triggering block is blanked for a certain time after the MOSFET has been turned off. This has two goals:

first, to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the

ZCD circuit erroneously; second, to realize the Frequency Foldback function (see the relevant description).

Figure 13. Zero Current Detection and Triggeri ng Block; Disable and Frequen cy Fold back Blocks

A circuit is needed that turns on the external MOSFET at start-up since no signal is coming from the ZCD pin.

This is realized with an internal starter, which forces the driver to deliver a pulse to the gate of the MOSFET.

To minimize the external interface with the synchronization source (either the auxiliary winding or an external

clock), the voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the internal dia-

gram of the ZCD block of figure 13. The upper clamp is typically located at 5.2 V, while the lower clamp is at

one V

above ground. The i nterface wi ll then be made b y just one res istor that has to l imit the c urrent sour ced

by and sunk from the pin within the rated capability of the internal clamps.

Disable Block (see fig. 13):

The ZCD pin is used also to activate the Disable Block. If the voltage on the pin is taken below 150 mV the de-

vice will be shut down. To do so, it is necessary to override the source capability (10 mA max.) of the internal

lower clamp. While in disabl e, the current consumption of the IC will be reduced. To re- enable device operation,

the pull-down on the pin must be released.

Frequency Foldback Block (see fig. 13):

To prev ent the s witching frequenc y from r eac hing too high val ues, which is a typical drawback of QR operation,

1.6V

2.1V

0.2V

0.3V

DISABLE

DRIVER

5.2V

+Vin

ZCD

PWM

150µA

BLANKING

TIME

2.5V

INVCOMP

E/A

to line

FFWD

L6565

STARTER

MONO

STABLE

RZCD

starter STOP

blanking

START

9/17

L6565

the L6565 puts a limit on the minimum OFF-time of the switch. This is done by blanking the tr iggering block of

the ZCD circuit as mentioned before. The duration of the blanking time (3.5µs min.) is a function of the error

amplifier output VCOMP, as shown in the diagram of figure 6.

If the load current and the input voltage are such that the switch OFF-time falls below the minimum blanking

time of 3.5µs, the system will enter the " Frequency Fol dback" mo de, a sort of "ringi ng cycl e ski pping" ill ustrated

schematically in figure 14.

Figure 14. Frequency foldback: ringing cycle skipp ing as the load is progressively redu ced

In this mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that

the OFF-time of the MOSFET is allowed to change with discrete steps (2·Tv), while the OFF-time needed for

cycle-by-cycle energy balance may fall in between. Thus one or more longer switching cycles will be compen-

sated by one or more shorter ones and vice versa. However, this mechanism is absolutely normal and there is

no appreciable effect on the performance of the converter or on its output voltage.

VDS

TFW

TBLANKmin

TV t

VDS

TBLANK

Pin = Pin'

(limit cond iti on) Pin = Pin'' < Pin' Pin = Pin''' < Pin''

VDS

TBLANK

Figure 15. Frequency Foldback: qualitative

frequenc y depen dence on po we r

throughput

Further load reductions involve lower values for

VCOMP, which increases the blanking time. There-

fore, more and more ringing cycles will be skipped.

When the lo ad is low enough , so many ringing cycl es

need to be skipped that their amplitude becomes

very smal l and they can no longer trigger the ZCD cir-

cuit. In that case the internal starter of the IC will be

activated, r esulting in burst-mode operation: a s eries

of few switching cycles spaced out by long periods

where the MOSFET is in OFF state.

Voltage Feedforward block (see fig. 17b):

The power that QR flyback converters with a fixed

overcurrent setpoint (like fixed-frequency systems)

are able to deliver changes with the input voltage

considerably. With wide-range mains, at maximum

line it can be more than twice the value at minimum

line, as shown by the upper curve in the diagram of

figure 16. The L6565 has the Line Feedforward func-

tion available to solve this issue.

Figure 16. Typical power capability change vs.

input voltage in ZVS QR flyback

c onverters

fsw

00000000

00000

00000000

BURST MODE

without freq uency foldback

with frequency fold back

Vin fixe d

Vin

Vinmin

Pinlim @ Vin

Pinlim @ Vinmin

11.522.533.54

0.5

1.5

2.5

system optimall y

compensated

system not

compensated

L6565

10/17

It acts on the clamp level of the control voltage V

csx

, that is on the overcurrent setpoint, so that it is a function

of the converter's input v oltage sensed through a dedi cated pin (#3, VFF): the hi gher the input voltage, the l ower

the setpoint. This is illustrated in the diagram of figure 17a that shows the relationship between the voltage at

the pin VFF and V

csx

(with the error ampli fier saturated high in the attempt of k eeping output voltage regulation) .

The schematic i n figur e 17b shows also how the function is included i n the control loop. With a proper selec tion

of the external divider R1-R2 it is possible to achieve the optimum compensation described by the lower curve

in the diagram of figure 16.

In applications where this function is not w anted, e.g. bec ause of a na rrow input v oltage range, the VFF pin can

be sim ply gro unded, thus sav ing t he resis tor divider . The overcurr ent setpoint will be then fixed at th e maxi mum

value of about 1.4V (1.5V max.).

Line Feedforward is also beneficial to other characteristics of quasi-resonant converters: it improves their input

ripple rejection ability and limits the variation of the power stage's small-signal gain versus the line voltage.

Figu re 17. a) Ov ercurre nt s et po in t vs. VF F vol ta ge; b) Line Feedf o rwa r d fu nction blo ck

Vcsx [V]

0 0.5 1 1.5 2 2.5 3 3.5

0.5

1.5

VVFF [V]

VCOMP = Upper clamp

E/A

PWM

VOLTAGE

FEED

FORWARD

+Vin

2.5V

1DRIVER 7

INV

COMP VFF CS

L6565

2 V

Hiccup DISABLE

ZCD

STARTER

ZCD

(reset-dominant)

starter STOP

11/17

L6565

Error Amplifier Block (see fig. 17b):

The Error Amplifi er (E /A) inverting input is used i n pri mary feedback technique to compare a parti tion of the volt-

age generated by the auxiliary winding with the internal reference, to achieve converter's output voltage regu-

lation ( s ee "Applica tion Ideas ", fig. 24) . With secondary feedback (typi cally usi ng a TL4 31 at the sec ondary s ide

and an optocoupler to transfer output voltage information to the primary side through the isolation barrier) the

E/A can be used as an inverting level-shifter to achieve negative feedback and shape the loop gain (see "Ap-

plication Ideas", fig. 23).

The E/A output is used typically for control loop compensation, realized with an R C network connected to the

inverting input. With other secondary feedback techniques, the output is driven directly by an emitter-grounded

optocoupler to modulate the duty cycle (the inverting input will be grounded in that case - see figure 23 in "Ap-

plication Ideas").

Current Comparator, PWM Latch and Hiccup-mode OCP (see fig. 17b):

The current c omparator senses the voltage ac ross the curr ent sens e resistor ( Rs) and, by com pari ng it with the

programmi ng signal del ivered by the feedfor war d block, determi nes the exact ti me when the external MOSFET

is to be switched off. The PWM latch avoids spurious switching of the MOSFET, which might result from the

noise generated ("double-pulse suppression").

A comparator senses the voltage on the current sense input and disables the gate dr iver if the vo ltage at the pin

exceeds 2 V . Such anomalous condition i s typic ally gene rated by a short cir cuit on the secondar y rectifier or on

the se condary winding. To re-enable the driver, fir st the IC must be turned off and then can be restarted, that is

the Vcc voltage must fall below the UVLO threshold.

When the gate driver is disabled the quiescent current of the IC is unchanged and, since no energy is coming

from the self-supply circuit, the Vcc capacitor will be discharged below the UVLO threshold after some time.

Then the dev ice w ill initi ate a new start-up cyc le. In case of fai lur e of th e seco ndary diode the resul t ing beh avior

will be a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.

Gate Driver (see fig. 18):

A totem pole buffer, with 400mA source and sink capability, drives the external MOSFET. It is made up of a

high-side NPN Darlington and a low-side MOSFET. In this way there is no need of an external diode clamp to

prevent the voltage at the gate drive output (pin 7, GD) from being pulled too negative.

An internal pull-down circuit holds the output low when the device is in UVLO conditions, to ensure that the ex-

ternal MOSFET cannot be turned on accidentally (e.g. at power-on).

Figure 18. Gate driver with UVLO pull-down

UVLO

GND

DRIVER

Vcc

L6565

12/17

TYPICAL APPLICATIONS

Figure 19. 50W Wide Range Mains SMPS for 14" TV

Figure 20. 40W Wide Range Mai ns SMPS for inkjet printer

TRANSFORMER SPECS:

CO RE : ETD29x16x 1 0, N6 7 mat eri al or eq uiv al ent

≈ 1 mm air gap for a primary inductance of 285 µH

N1: 48 T (24T+24T series co nnect ed), 2xAWG28 (∅0.37 mm )

N2: 31 T, AWG28

N3: 5 T, AWG28

Naux: 5 T, A WG32 (∅0.24 mm)

IC1

L6565

105 V

0.35 A

B1 2KBP 04M

150 µF

400 V

180 pF

630V

R6 100

47µF

25V

STP7NB80FI

R8 22

1N4148

R11

0.47

75k

Vin

8 8 to

264 Vac

2A fuse

75k

1N4148

C12

100 µF 25V

R15

1.8 k

C13

100 nF

D3 STT A106

R12

47 k

R13

3.3 k

DZ1

15 V R14

1.5 k

C6 4700pF/ 4KV

4.7M R10

4.7M

C7 4700pF/ 4KV

R18

150 k

R17

4.7 k

220 µF

160 V

100 k

ZCD

Vcc

GNDINV

VFF

COMP +5 V

50 mA

C11

47 µF

25V

IC4

L7805

14 V

1 A

BYW98-100

C10

470 µF

25 V

3 M

16 K

BYT01-400

1 nF

R7 10

8.2 nF

250 V

100 k

IC2 TL431

IC3 PC817

2.2 nF R16

220 k

R20 22 k

1N4148

C22

100 pF

C23

100nF C24

100nF

C25

1nF

C26

1nF

NTC1

16R

15mH

C27

220nF

Naux

L6565

10 nF

250V

47µF

STP4NA80FP

STTA106

1N4148

0.39 Ω

1/2 W

PC817

2200pF 4KV

2 x 470µF

35V

100 nF

28V / 0. 7A

GND

470µF

16V

BYW100-50

BYW98-100

BYW100-200

12V / 1. 5A

5V / 0. 5A

2 x 100 0µF

16V

PC817A

TL431

N4N5

3.3 nF

47 kΩ

75 kΩ

56 kΩ

2 W

10 Ω

3.9 kΩ

5.1 kΩ

270 kΩ

2.7 kΩ

220 Ω

16 kΩ

3 M Ω

10 nF

2KBP04M

Vin

88 to

264 Vac

2A fuse

100nF 100nF 1nF

1nF

16R

15mH 75 kΩ

1N4148

TRANSFORMER SPECS:

CORE: ETD29x16x10, 3C85 material or equivalent

≈1 mm air gap for a primary inductance of 700 µH

N1: 75 T, AWG25 (∅0.51 mm)

N2: 8 T, AWG25

N3: 7 T, AWG20 (∅0. 89 mm)

N4: 3 T, AWG25

N5: 7 T, AWG32 (∅0. 24 mm)

10 Ω

13/17

L6565

APPLICATION IDEAS

Here follows a series of ideas/suggestions aimed at either improving performance or solving common applica-

tion issues of L6565-based power supplies.

Fi gure 21 . En hanc ed t urn-off f or big MOSFET' s dr i ve

Figure 22. Latched shutdown on: a) feedback disconnection; b) overload or short circuit

Figure 23. Second ary Feedback loop configurations

GND

DRIVER

Vcc

L6565 Rs

BC327

Vcc

L6565

COMP

Vcc

L6565

COMP

BC337

BC327 1N4148

BC337

BC327

1N4148

Vout

TL431

L6565

COMP INV

Vcc

Vout

TL431

L6565

COMPINV

ICOMP

Vout

TL431

L6565

INV

Vcc

Roff

a) b) c)

L6565

14/17

Figure 24. Pri mary Feed back loop con figurations

Vcc

GND L6565

E/A

INV

2.5V

COMP

to VFF

block

Vcc

GND L6565

E/A

INV

2.5V

COMP

to VFF

block

Figure 25. Protection against secon dary

feedback discon ne ction by primary

regul ation take-over

Figu re 26. Leading edge bl anking ci rcui t for

enhance d primary reg ulatio n

Figure 27. Remote ON/OFF control

Figure 28. Low-consumption start-up circuit

Vcc

L6565

INV 1

15 V

2.2 kΩCOMP

Vcc

GND

L6565

1N4148BC327

2.7 kΩ

470 pF

L6565

ZCD

OFF BC337

L6565

CSUPPLY

Vac

R1N4148

+Vin

Vcc

GND

CSTART

1N4148