High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 1
DESCRIPTION
The CS18LV10245 is a high performance, high speed and super low power CMOS Static
Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of
4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy
memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable
(/OE).
The CS18LV10245 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin
sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages.
FEATURES
1. Fully static operation and Tri-state output
2. TTL compatible inputs and outputs
3. Ultra low power consumption :
z 2.0V (min) data retention
z Low operation voltage : 4.5 ~ 5.5V ; 5mA＠1MHz (Max.) operating current (Vcc = 5.0V)
4. Standby Typ. = 0.50uA, (Typical value @ Vcc = 5.0V, TA = 25 0C)
5. Standard pin configuration
z 32 - SOP 450mil
z 32 - sTSOP-I - 8X13.4mm
z 32 - TSOP-I 8X20mm
z 32 - PDIP 600mil
Product Family
Part No. Operating Temp Vcc. Range Speed (ns) Standby (Typ.) Package Type
CS18LV10245CC 32 SOP
CS18LV10245DC 32 STSOP
CS18LV10245EC 32 TSOP (I)
CS18LV10245LC
0~70oC 0.50uA
32 PDIP
CS18LV10245CI 32 SOP
CS18LV10245DI 32 STSOP
CS18LV10245EI 32 TSOP (I)
CS18LV10245LI
-40~85oC
4.5 ~ 5.5
55/70
0.80uA
32 PDIP
Note: Green package part no, sees order information.
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 2
PIN CONFIGURATIONS
32 SOP 450 mil
32 PDIP 600 mil
32 STSOP 8x13.4mm
32 TSOP(I) 8x20mm
BLOCK DIAGRAM
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 3
PIN DESCRIPTIONS
Name Function
A0-A16
Address Input
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM.
/CE
Chip Enable Input
CE2
Chip Enable 2 Input
/CE is active LOW and CE2 is active HIGH. Both chip enables must be active
when data read from or write to the device. If either chip enable is not active,
the device is deselected and is in a standby power mode. The DQ pins will be
in the high impedance state when the device is deselected.
/WE
Write Enable Input
The write enable input is active LOW and controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins; when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
/OE
Output Enable Input
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
DQ0-DQ7
Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the
RAM.
Vcc Power Supply
Gnd Ground
TRUTH TABLE
MODE /WE /CE CE2 /OE DQ0~7 Vcc Current
X H X X
Not
Selected X X L X
High Z ICCSB, ICCSB1
Output
Disabled H L H H High Z ICC
Read H L H L DOUT I
CC
Write L L H X DIN I
CC
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 4
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Parameter Rating Unit
VTERM Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 V
TBIAS Temperature Under Bias -40 to +125 OC
TSTG Storage Temperature -60 to +150 OC
PT Power Dissipation 1.0 W
IOUT DC Output Current 20 mA
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Ambient Temperature Vcc
Commercial 0~70oC 4.5V ~5.5V
Industrial -40~85oC 4.5V ~ 5.5V
CAPACITANCE (1) (TA = 25oC, f =1.0 MHz)
Symbol Parameter Conditions MAX. Unit
CIN Input Capacitance VIN=0V 6 pF
CDQ Input/Output Capacitance VI/O=0V 8 pF
1. This parameter is guaranteed and not tested.
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 5
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
Parameter
Name Parameter Test Conduction MIN TYP(1) MAX Unit
VIL Guaranteed Input Low
Voltage (2)
-0.5 0.8
V
VIH Guaranteed Input High
Voltage (2)
2.0 Vcc+0.2
V
IIL Input Leakage Current VCC=MAX, VIN=0 to VCC 1
uA
IOL Output Leakage
Current
VCC=MAX, /CE=VIN, or
/OE=VIN , VIO=0V to VCC
1
uA
VOL Output Low Voltage
VCC=MAX, IOL = 2mA 0.4
V
VOH Output High Voltage VCC=MIN, IOH = -1mA 2.4 V
ICC Operating Power
Supply Current
/CE=VIL, IDQ=0mA, F=FMAX
(3) 35
mA
ICCSB Standby Supply - TTL /CE=VIH, IDQ=0mA, 2
mA
ICCSB1 Standby Current
-CMOS
/CE≧VCC-0.2V, VIN≧
VCC-0.2V or VIN≦0.2V
0.3 10
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester
notice are included.
3. Fmax = 1/tRC.
DATA RETENTION CHARACTERISTICS ( TA = 0 to +70oC )
Parameter
Name Parameter Test Conduction MIN TYP(1) MAX Unit
VRD VCC for Data Retention /CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V 1.5 V
ICCDR Data Retention Current /CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V 0.2 2.0 uA
TCDR Chip Deselect to Data
Retention Time 0 ns
tR Operation Recovery Time
See Retention Waveform
t
RC (2) ns
1. Vcc = 3.0V, TA = + 25oC. 2. tRC= Read Cycle Time.
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 6
LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE Controlled )
LOW Vcc DATA RETENTION WAVEFORM(2) ( CE2 Controlled )
KEY TO SWITCHING WAVEFORMS
WAFEFORM INPUTS OUTPUTS
Must be standby Must be standby
May change for H to L Will be change from H to L
May change for L to H May change for L to H
Don’t care any change permitted Change state unknown
Does not apply Center line is high impedance “OFF” state
AC TEST CONDITIONS
Input Pulse Levels Vcc/0V
Input Rise and Fall Times 5ns
Input and Output
Timing Reference Level 0.5Vcc
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 7
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
< READ CYCLE >
-55 -70 JEDEC
Parameter
Name
Parameter
Name
Description
MIN MAX MIN MAX
Unit
tAVAX t
RC Read Cycle Time 55 70 ns
tAVQ V t
AA Address Access Time 55 70 ns
tELQV t
ACS1 Chip Select Access Time (/CE) 55 70 ns
tELQV t
ACS2 Chip Select Access Time (CE2) 55 70 ns
tGLQV t
OE Output Enable to Output Valid 20 30 ns
tE1LQX t
CLZ1 Chip Select to Output Low Z (/CE) 10 10 ns
tE2LOX t
CLZ2 Chip Select to Output Low Z (CE2) 10 10 ns
tGLQX t
OLZ Output Enable to Output in Low Z 5 5 ns
tEHQZ t
CHZ1 Chip Deselect to Output in High Z (/CE) 0 25 0 30 ns
tEHQZ t
CHZ2 Chip Deselect to Output in High Z (CE2) 0 25 0 30 ns
tGHQZ t
OHZ Output Disable to Output in High Z 0 25 0 30 ns
tAXOX t
OH Out Disable to Address Change 10 10 ns
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 8
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE (1,2,4)
READ CYCLE (1,3,4)
READ CYCLE (1,4)
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 9
AC ELECTRICAL CHARACTERISTICS ( TA = 0~70oC , Vcc = 5.0V )
< WRITE CYCLE >
-55 -70 JEDEC
Parameter
Name
Parameter
Name
Description
MIN MAX MIN MAX
Unit
tAVAX t
WC Write Cycle Time 55 70 ns
tE1LWH t
CW Chip Select to End of Write 55 70 ns
tAVW L t
AS Address Setup Time 0 0 ns
tAVW H t
AW Address Valid to End of Write 55 70 ns
tWLWH t
WP Write Pulse Width 55 70 ns
tWHAX t
WR Write Recovery Time (/CE, /WE) 0 0 ns
tE2LAX t
WR2 Write Recovery Time (CE2, ) 0 0 ns
tWLQZ t
WHZ Write to Output in High Z 0 20 0 25 ns
tDVWH t
DW Data to Write Time Overlap 25 25 ns
tWHDX t
DH Data Hold from Write Time 0 0 ns
tWHOX t
OW End of Write to Output Active 5 5 ns
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 10
SWITCHING WAVEFORMS (WRITE CYCLE)
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 11
NOTES:
1. TAS is measured from the address valid to the beginning of write.
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All
signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of /CE or /WE going high or CE2 going low at the end
of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the
/WE transition, output remain in a high impedance state.
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 12
6. /OE is continuously low (/OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If /CE is low during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of /CE going low to the end of write.
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 13
ORDER INFORMATION
1. NON-GREEN PACKAGE:
CS18LV10245
Package:
C: 32SOP (450mil)
D: 32STSOP I (8x13.4mm)
55: 55NS
Speed:
Grade:
I: -40~85°C
C: 0~70°C
XX XX-
E: 32TSOP I (8x20mm)
L: 32PDIP (600mil)
70: 70ns
2. GREEN PACKAGE:
CS18LV10245
Package:
C: 32SOP (450mil)
D: 32STSOP I (8x13.4mm) 55: 55ns
Speed:
Grade:
I: -40~85°C
C: 0~70°C
XXXX
A: Pb Free + Halogen Free (SOP / TSOP Types)
Green Code
E: 32TSOP I (8x20mm)
X
70: 70ns
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 14
PACKAGE DIMENSIONS
- 32 pin SOP (450 mil) :
0.006
A
UNIT
0.118
Max.
Nom.
Min.
Max.
Nom.
Min.
inch
mm
2.997
0.104
0.111
2.821
2.645
SYMBOL
c
b1bA2A1
0.020
0.014
_
0.50
_
0.35
0.11100.014
0.1000
0.1055
2.820
2.680
2.540
0.356
0.004
0.009
0.229
0.102
0.0120.018
0.46
0.014
_
0.35
_
0.32
0.006
_
_
0.15
0.043
0.023
0.033
1.084
0.584
0.834
e
E1EDc1
0.450
0.440
0.445
11.430
11.176
11.303
0.8100.011
0.800
0.805
20.574
20.447
20.320
0.28
_
0.15
_
0.0560.567
14.402
0.543
0.555
13.792
14.097
1.422
0.044
0.050
1.118
1.270
y
L1L
0.0040.063
0.047
0.055
1.600
1.397
1.194
0.1
_
_
_
_
10°
10°
0°
_
0°
_
BASE METAL
WITH PLATING
cc1
SECTION A-A
b1
b
- 32 pin STSOP I ( 8x13.4 mm) :
1
16
16
D
1
HD
L
c
b
b1
32
SECTION A-A
BASE METAL
WITH PLATING
cc1
12°(2x)
Seating Plane
"A" DATAIL VIEW
A
17
"A"
17
A1A2
SEATING PLANE
32
12°(2x)
be
12°(2X) L
L1
A
A
12°(2X)
y
E
GAUGE PLANE
0
0.254
A
UNIT
Max. 0.0473
Min.
Nom.
Max.
Min.
Nom.inch
mm
1.20
0.0433
0.0393
1.00
1.10
SYMBOL
A1 A2 b b1 c
0.17
0.22
0.27
0.009
0.007
0.0110.006 0.041
1.00
1.05
0.039
0.037
0.15
0.004
0.002
0.05
0.10
0.95
0.009 0.008
0.008
0.007
0.23
0.17
0.20
0.21
_
0.004
0.10
_0.50
0.40
0.70
0.0197
0.0157
0.0277
c1 D E eHD
8.00
7.90
8.10
0.315
0.311
0.3190.006 0.469
11.70
11.80
11.90
0.465
0.461
0.16
0.004
_
0.10
_
0.024 0.536
0.60
0.020
0.016
0.50
0.40
13.60
0.528
0.520
13.40
13.20
LL1y
0.0355 0.004
0.70
0.80
0.90
0.0315
0.0275
0.1
_
_
_
_
8°
8°
0°
_
0°
_
-
High Speed Super Low Power SRAM
128K-Word By 8 Bit CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . P 15
- 32 pin TSOP(I) ( 8x20mm)
A
UNIT
0.0473
Max.
Nom.
Min.
Max.
Nom.
Min.
inch
mm
1.20
0.0393
0.0433
1.10
1.00
SYMBOL
c
b1bA2A1
0.011
0.007
0.009
0.27
0.22
0.17
0.006 0.041
0.95
0.037
0.039
1.05
1.00
0.15
0.002
0.004
0.05
0.10
0.0080.009
0.007
0.008
0.23
0.17
0.20
0.21
0.004
_
_
0.10
0.0277
0.0157
0.0197
0.70
0.40
0.50
HD
e
EDc1
0.319
0.311
0.315
8.10
7.90
8.00
0.7280.006
0.720
0.724
18.50
18.40
18.30
0.16
0.004
_
0.10
_
0.024 0.795
0.60
0.016
0.020
0.40
0.50
20.20
0.779
0.787
19.80
20.00
y
L1
L
0.0040.0355
0.0275
0.0315
0.90
0.80
0.70
0.1
_
_
_
_
8°
8°
0°
_
0°
_
1
16
16
D
1
C
L
HD
SECTION A-A
32 BASE METAL
WITH PLATING
cc1
b1
b
E
Seating Plane
A
17
"A"
17
"A" DETAIL VIEW
A1A2
SEATING PLANE
32
b
12°(2X)
e12°(2X)
12°(2x)
L1
A
L
A
12°(2x)
y
GAUGE PLANE
0
0.254
- 32 pin PDIP ( 600 mil)
41.783
41.910
1.650
1.645
42.037
1.655
0.254
_
_
0.010
_
_
A1
Max.
inch
mm
UNIT
Max.
Min.
Nom.
Min.
Nom.
SYMBOL
A2 BB1 cD
0.159 0.023
3.785
3.912
0.154
0.149
4.039 0.584
0.018
0.013
0.330
0.457
0.0140.055
0.254
0.152
0.010
0.006
0.3561.397
0.050
0.045
1.143
1.270
EE1 eeB L
(TYP)
0.100
(TYP)
2.540
0.610 0.548
15.494
0.600
0.590
15.240
14.986
13.920
0.544
0.540
13.716
13.818
0.1400.670
16.510
16.002
0.650
0.630
17.018 3.556
0.120
0.130
3.302
3.048
SQ1
0.0750.085
1.778
1.9052.159
0.065
0.075
1.905
1.651
0.065
0.070
1.651
