TPS259251DRCR - TEXAS INSTRUMENTS

TBD

MAPBGA–225

15 mm x 15 mm QFN12

##_mm_x_##mm

SOT-343R

##_mm_x_##mm PKG-TBD

## mm x ## mm

257 MAPBGA

(14 x 14 x 0.8 mm)

(20 x 20 x 1.4 mm)

144 LQFP

Freescale Semiconductor

Data Sheet: Advance Information Document Number: MPC5643L

Rev. 9, 6/2013

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

MPC5643L

• High-performance e200z4d dual core

— 32-bit Power Architecture® technology CPU

— Core frequency as high as 120 MHz

— Dual issue five-stage pipeline core

— Variable Length Encoding (VLE)

— Memory Management Unit (MMU)

— 4 KB instruction cache with error detection code

— Signal processing engine (SPE)

• Memory available

— 1 MB flash memory with ECC

— 128 KB on-chip SRAM with ECC

— Built-in RWW capabilities for EEPROM emulation

• SIL3/ASILD innovative safety concept: LockStep mode and

Fail-safe protection

— Sphere of replication (SoR) for key components (such as

CPU core, eDMA, crossbar switch)

— Fault collection and control unit (FCCU)

— Redundancy control and checker unit (RCCU) on outputs

of the SoR connected to FCCU

— Boot-time Built-In Self-Test for Memory (MBIST) and

Logic (LBIST) triggered by hardware

— Boot-time Built-In Self-Test for ADC and flash memory

triggered by software

— Replicated safety enhanced watchdog

— Replicated ju nction temperature sensor

— Non-maskable interrupt (NMI)

— 16-region memory protection unit (MPU)

— Clock monitoring units (CMU)

— Power management unit (PMU)

Qorivva MPC5643L

Microcontroller Data Sheet

— Cyclic redundancy check (CRC) unit

• Decoupled Parallel mode for high-perfo rmance use of

replicated cores

• Nexus Class 3+ interface

• Interrupts

— Replicated 16-priority controller

— Replicated 16-channel eDMA controller

• GPIOs individually programmable as input, output or

special function

• Three 6-channel general-purpose eTimer units

• 2 FlexPWM units

— Four 16-bit channels per module

• Communications interfaces

— 2 LINFlexD channels

— 3 DSPI channels with automatic chip selec t

generation

— 2 FlexCAN interfaces (2.0B Active) with 32

message objects

— FlexRay module (V2.1 Rev. A) with 2 channels,

64 message buffers and d ata rates up to 10 Mbit/s

• Two 12-bit analog-to-digital co nverters (ADCs)

— 16 input channels

— Programmable cross triggering unit (CTU) to

synchronize ADCs conversion with timer and

PWM

• Sine wave generator (D/A with low pass filter)

• On-chip CAN/UART bootstrap loader

•Single 3.0 V to 3.6 V voltage supply

• Ambient temperature range –40 °C to 125 °C

• Junction temperature range –40 °C to 150 °C

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor2

Table of Contents

1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.5.1 High-performance e200z4d core. . . . . . . . . . . . .7

1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8

1.5.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . .8

1.5.4 Enhanced Direct Memory Access (eDMA) . . . . .8

1.5.5 On-chip flash memory with ECC . . . . . . . . . . . . .9

1.5.6 On-chip SRAM with ECC. . . . . . . . . . . . . . . . . . .9

1.5.7 Platform flash memory controller. . . . . . . . . . . . .9

1.5.8 Platform Static RAM Controller (SRAMC) . . . . .10

1.5.9 Memory subsystem access time . . . . . . . . . . . .10

1.5.10 Error Correction Status Module (ECSM) . . . . . .11

1.5.11 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .11

1.5.12 Interrupt Controller (INTC). . . . . . . . . . . . . . . . .11

1.5.13 System clocks and clock generation . . . . . . . . .12

1.5.14 Frequency-Modulated Phase-Locked Loop

(FMPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.5.15 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.5.16 Internal Reference Clock (RC) oscillator . . . . . .13

1.5.17 Clock, reset, power, mode and test control

modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)

1.5.18 Periodic Interrupt Timer Module (PIT) . . . . . . . .13

1.5.19 System Timer Module (STM). . . . . . . . . . . . . . .13

1.5.20 Software Watchdog Timer (SWT) . . . . . . . . . . .14

1.5.21 Fault Collection and Control Unit (FCCU) . . . . .14

1.5.22 System Integration Unit Lite (SIUL). . . . . . . . . .14

1.5.23 Non-Maskable Interrupt (NMI). . . . . . . . . . . . . .14

1.5.24 Boot Assist Module (BAM). . . . . . . . . . . . . . . . .14

1.5.25 System Status and Configuration Module

(SSCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1.5.26 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1.5.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.5.28 Serial communication interface module

(LINFlexD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.5.29 Deserial Serial Peripheral Interface (DSPI). . . .17

1.5.30 FlexPWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

1.5.31 eTimer module. . . . . . . . . . . . . . . . . . . . . . . . . .18

1.5.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . .19

1.5.33 Analog-to-Digital Converter module (ADC) . . . .19

1.5.34 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . .19

1.5.35 Cyclic Redundancy Checker (CRC) Unit. . . . . .20

1.5.36 Redundancy Control and Checker Unit (RCCU)20

1.5.37 Junction temperature sensor. . . . . . . . . . . . . . .20

1.5.38 Nexus Port Controller (NPC) . . . . . . . . . . . . . . .20

1.5.39 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . .21

1.5.40 Voltage regulator / Power Management Unit

(PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.5.41 Built-In Self-Test (BIST) capability . . . . . . . . . . 22

2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . 23

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.3 System pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.4 Pin muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 76

3.3 Recommended operating conditions. . . . . . . . . . . . . . 77

3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 78

3.4.1 General notes for specifications at maximum

junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.5 Electromagnetic Interference (EMI) characteristics. . . 81

3.6 Electrostatic discharge (ESD) characteristics . . . . . . . 82

3.7 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.8 Voltage regulator electrical characteristics . . . . . . . . . 83

3.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 86

3.10 Supply current characteristics . . . . . . . . . . . . . . . . . . . 87

3.11 Temperature sensor electrical characteristics . . . . . . . 90

3.12 Main oscillator electrical characteristics . . . . . . . . . . . 90

3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 92

3.14 16 MHz RC oscillator electrical characteristics . . . . . . 94

3.15 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 94

3.15.1 Input Impedance and ADC Accuracy. . . . . . . . 94

3.16 Flash memory electrical characteristics. . . . . . . . . . . . 99

3.17 SWG electrical characteristics. . . . . . . . . . . . . . . . . . 100

3.18 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.18.1 Pad AC specifications . . . . . . . . . . . . . . . . . . 101

3.19 Reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.19.1 Reset sequence duration . . . . . . . . . . . . . . . . 102

3.19.2 Reset sequence description. . . . . . . . . . . . . . 102

3.19.3 Reset sequence trigger mapping . . . . . . . . . . 105

3.19.4 Reset sequence — start condition . . . . . . . . . 106

3.19.5 External watchdog window. . . . . . . . . . . . . . . 107

3.20 AC timing characteristics. . . . . . . . . . . . . . . . . . . . . . 107

3.20.1 RESET pin characteristics . . . . . . . . . . . . . . . 108

3.20.2 WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . 109

3.20.3 IEEE 1149.1 JTAG interface timing . . . . . . . . 109

3.20.4 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . .111

3.20.5 External interrupt timing (IRQ pin) . . . . . . . . . 114

3.20.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 120

5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 126

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 3

1 Introduction

1.1 Document overview

This document describes the features of the family and options available within the family members, and highlights important

electrical and physical characteristics of the devices.

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5643L series of

microcontroller units (MCUs). For functional characteristics, see the MPC5 643L Microcontroller Reference Manual. For use

of the MPC5643Lin a fail-safe system according to safety standard ISO26262, see the Safety Application Guide for MPC5643L.

1.2 Description

The MPC5643L series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain

enhancements that improve the architecture’s fit in embedded applicati ons, inclu de addit ion al instruction support for digital

signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital

converter, Controller Area Network, and an enhanced modular input-output system.

The MPC5643L family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It

belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS),

electric power steering (EPS) and airbag applications . The advanced and cost-efficient host processor core of the MPC5643L

automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as

120 MHz and offers high-performance processing optim ized for low power consumption. It capitalizes on the available

development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and

configuration code to assist with users’ implementations.

1.3 Device comparison

Table 1. MPC5643L device summary

Feature MPC5643L

CPU Type 2 × e200z4

(in lock-step or decoupled operation)

Architecture Harvard

Execution speed 0–120 MHz (+2% FM)

DMIPS intrinsic performance >240 MIPS

SIMD (DSP + FPU) Yes

MMU 16 entry

Instruction set PPC Yes

Instruction set VLE Yes

Instruction cache 4 KB, EDC

MPU-16 regions Yes, replicated module

Semaphore unit (SEMA4) Yes

Buses Core bus AHB, 32-bit address, 64-bit data

Internal periphery bus 32-bit address, 32-bit data

Crossbar Master × slave ports Lock Step Mode: 4 × 3

Decoupled Parallel Mode: 6 × 3

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor4

Memory Flash 1 MB, ECC, RWW

Static RAM (SRAM) 128 KB, ECC

Modules Interrupt Controller (INTC) 16 interrupt levels, replicated module

Periodic Interrupt Timer (PIT) 1 × 4 channels

System Timer Module (STM) 1 × 4 channels, replicated module

Software Watchdog Timer (SWT) Yes, replicated module

eDMA 16 channels, replicated mo dule

FlexRay 1 × 64 message buffers, dual channel

FlexCAN 2 × 32 message buffers

LINFlexD (UART and LIN with DMA suppo rt) 2

Clock out Yes

Fault Collection and Control Unit (FCCU) Yes

Cross Triggering Unit (CTU) Yes

eTimer 3 × 6 channels1

FlexPWM 2 Module 4 × (2 + 1) channels2

Analog-to-Digital Converter (ADC) 2 × 12-bit ADC, 16 channels per ADC

(3 internal, 4 shared and 9 external)

Sine Wave Generator (SWG) 32 point

Modules

(cont.) Deserial Serial Peripheral Interface (DSPI) 3 × DSPI

as many as 8 chip selects

Cyclic Redundancy Checker (CRC) unit Yes

Junction temperature sensor (TSENS) Yes, replicated module

Digital I/Os 16

Supply Device power supply

3.3 V with integrated bypassable ballast transistor

External ballast transistor not needed for bare die

Analog reference voltage 3.0 V – 3.6 V and 4.5 V – 5.5 V

Clocking Frequency-modulated phase-locked loop (FMPLL) 2

Internal RC oscillator 16 MHz

External crystal oscillator 4 – 40 MHz

Debug Nexus Level 3+

Table 1. MPC5643L dev ice summary (continued)

Feature MPC5643L

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 5

1.4 Block diagram

Figure 1 shows a top-level block diagram of the MPC5643L device.

Packages LQFP 144 pins

MAPBGA 257 MAPBGA

Temperature Temperature range (junction) –40 to 150 °C

Ambient temperature range using external ball ast

transistor (LQFP) –40 to 125 °C

Ambient temperature range using external ball ast

transistor (BGA) –40 to 125 °C

1The third eT imer (eTimer_2) is available with external I/O access only in the BGA package, on the LQFP p ackage

eTimer_2 is available internally only without any external I/O access.

2The second FlexPWM module is available only in the BGA package.

Table 1. MPC5643L dev ice summary (continued)

Feature MPC5643L

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor6

Figure 1. MPC5643L block diagram

ADC – Analog-to-Digital Converter

BAM – Boot Assist Module

CMU – Clock Monitoring Unit

CRC – Cyclic Redundancy Check unit

CTU – Cross Triggering Unit

DSPI – Serial Peripherals Interface

ECC – Error Correction Code

ECSM – Error Correction Status Module

eDMA – Enhanced Direct Memory Access controller

FCCU – Fault Collection and Control Unit

FlexCAN – Controller Area Network controller

FMPLL – Frequency Modulated Phase Locked Loop

INTC – Interrupt Controller

IRCOSC – Internal RC Oscillator

JTAG – Joint Test Action Group interface

LINFlexD – LIN controller with DMA support

MC – Mode Entry, Clock, Reset, & Power

PBRIDGE – Peripheral bridge

PIT – Periodic Interrupt Timer

PMU – Power Management Unit

RC – Redundancy Checker

RTC – Real Time Clock

SEMA4 – Semaphor e Unit

SIUL – System Integration Unit Lite

SSCM – System Status and Configuration Module

STM – System Timer Module

SWG – Sine Wave Generator

SWT – Software Watchdog Timer

TSENS – Temperature Sensor

XOSC – Crystal Oscillator

SRAM

PMU

SWT

ECSM

STM

INTC

eDMA

Crossbar Switch

VLE

MMU

I-CACHE

SPE

e200z4

VLE

MMU

I-CACHE

SPE

e200z4

Memory Protection Unit Crossbar Switch

Memory Protection Unit

PBRIDGE

JTAG

Nexus

JTAG

Nexus

FlexRay

PBRIDGE

TSENS TSENS

ECC bits

Flash memory

ECC bits + logic

SIUL

WakeUp

ADC

XOSC

BAM

SSCM

Secondary FMPLL

FMPLL

IRCOSC

CMU

CTU

PIT

FCCU

FlexPWM

eTimer

FlexCAN

LINFlexD

DSPI

DSPI CRC

CMU

SEMA4

SWT

ECSM

STM

INTC

eDMA

SEMA4

SWG

ECC logic for SRAM ECC logic for SRAM

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 7

1.5 Feature details

1.5.1 High-performance e200z4d core

The e200z4d Power Architecture® core provides the following features:

• 2 independent execution units, both supporting fixed-point and floating-point operations

• Dual issue 32-bit Power Architecture technology compliant

— 5-stage pipeline (IF, DEC, EX1, EX2, WB)

— In-order execution and instruction retireme nt

• Full supp ort for Power Architecture instruction set and Variable Length Encoding (VLE)

— Mix of classic 32-bit and 16 -bit instruction allowed

— Optimization of code size possib le

• Thirty-two 64-bit general purpose registers (GPRs)

• Harvard bus (32-bit address, 64-bit data)

— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return

— D-Bus interface capable of two transactions outstanding to fill AHB pipe

• I-cache and I-cache controller

— 4 KB, 256-bit cache line (programmable for 2- or 4-way)

• No data cache

• 16-entry MMU

• 8-entry branch table buffer

• Branch look-ahead instruction buffer to accelerate branching

• Dedicated branch address calculator

• 3 cycles worst case for missed branch

• Load/store unit

— Fully pipelined

— Single-cycle load latency

— Big- and little-endian modes supported

— Misaligned access support

— Single stall cycle on load to use

• Single-cycle throughput (2-cycl e latency) integer 32 × 32 multiplication

• 4 – 14 cycles int e ger 32 × 32 division (average division on various benchmark of nine cycles)

• Single precision float ing-point unit

— 1 cycle throughput (2-cycle latency) floating-point 32 × 32 mult iplication

— Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division

— Special square root and min/max function imp lemented

• Signal processing support: APU-SPE 1.1

— Support for vectorized mode: as many as two floating-point instructio ns per clock

• Vectored interrupt support

• Reservat ion instruction to support read-modify -write constructs

• Extensive system development and tracing su pport via Nexus debug port

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor8

1.5.2 Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The

crossbar supports a 32-bit address bus wi dth and a 64-bi t data bus wid th.

The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers

must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master

port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting

that slave port are stalled until the higher priority master completes its transactio ns.

The crossbar provides the following features:

• 4 masters and 3 slaves supported per each replicated crossbar

— Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D

access (2 masters), one eDMA, one FlexRay

— Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum

flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1

redundant peripheral bus bridge

• 32-bit address bus and 64-bi t data bus

• Programmable arbitration priority

— Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method,

based upon the ID of the last master to be granted access or a priority order can be assigned by software at

application run time

• Temporary dy namic priority elevation of masters

The XBAR is replicated for each processing channel.

1.5.3 Memory Protection Unit (MPU)

The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay , CPU) can be

assigned different access rights to each region.

• 16-region MPU with concurrent checks against each master access

• 32-byte granu larity for protected address region

The memory protection unit is replicated for each processing channel.

1.5.4 Enhanced Direct Memory Access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data

movements via 16 programmable channels, with minimal intervention from the host processor . The hardware microarchitecture

includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,

along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation

is used to minimize the overall block size.

The eDMA module provides the following features:

• 16 chan nels supporting 8-, 16-, and 32-bit value single or block transfers

• Support variable sized queues and circular buffered queue

• Source and destinati on address registers independently configured to post-increment or stay constan t

• Support major and minor loop offset

• Support minor and major loop done signals

• DMA task in iti ated either by hardware requestor or by software

• Each DMA task can opti onally generate an interrupt at completion and retirement of the task

• Signal to indicate closure of last minor loop

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 9

• Transfer control descriptors mapped inside the SRAM

The eDMA controller is replicated for each processing channel.

1.5.5 On-chip flash memory with ECC

This device includes programmable, non-volatile flash memory. The non-volatile me mory (NVM) can be used for instruction

storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory

array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.

The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait

state response at 120 MHz.

The flash memory module provides the following features

• 1 MB of fl ash memory in unique multi-partitioned hard macro

• Sectori zation: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB

• EEPROM em ulation (in software) within same module but on different partition

• 16 KB test sector and 16 KB shadow block for test, censorship device and user opt ion bits

• Wait states:

— 3 wait states for frequencies =< 120 MHz

— 2 wait states for frequencies =< 80 MHz

— 1 wait state for frequencies =< 60 MHz

• Fla sh mem ory line 128-bit wide with 8-bit ECC on 64-b it word (total 144 bits)

• Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations

• 1-bit error correction, 2-bit error detection

1.5.6 On-chip SRAM with ECC

The MPC5643L SRAM provides a general-purpose single port memory.

ECC handling is done on a 32-bit boundary for data and it is extended to the address to have th e highest po ssi ble diagnostic

coverage including the array internal address decoder.

The SRAM module provides the following features:

• System SRAM: 128 KB

• ECC on 32-bit word (syndrome of 7 bits)

— ECC covers SRAM bus address

• 1-bit error correction, 2-bit error detection

• Wait states:

— 1 wait state for frequencies =< 120 MHz

— 0 wait states for frequencies =< 80 MHz

1.5.7 Platform flash memory controller

The following list summarizes the key features of the flash memory controller:

• Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container

are supported. Only aligned wo rd writes are supported.

• Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.

• Code flash (bank0) interface provides configurable read buffering and page prefetch support.

— Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized

flash access.

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor10

• Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a

least-recently-used replacement algorithm to maximize performance.

• Programmable response for read-while-write sequences inclu ding support for stall-while-writ e, optional stall

notification interrupt, optional flash operation abort , and optional abort notification interrupt.

• Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of

platforms and frequencies.

• Support of address-based read access timing for emulation of other memory types.

• Su pport for reporting of single- and multi-bit err or events.

• Typical operatin g configuration loaded into programming model by system reset.

The platform flash controller is replicated for each processor.

1.5.8 Platform Static RAM Controller (SRAMC)

The SRAMC module is the platform SRAM array controller, with integrated error detection and correction.

The main features of the SRAMC provide connectivity for the following interfaces:

• XBAR Slave Port (64-bit data path)

• ECSM (ECC Error Reporting, error injection and configuration)

• SRAM array

The following functions are implemented :

• ECC encodi ng (32-bit boundary for data and complete address bus)

• ECC decodi ng (32-bit boundary and entire address)

• Address translation from the AHB protocol on the XBAR to the SRAM array

The platform SRAM controller is replicated for each processor.

1.5.9 Memory subsystem access time

Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower

memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the

slave being accessed is not parked on the requesting master in the crossbar.

Table 2 shows the number of additional data phase wait states required for a range of memory accesses.

Table 2. Platform memory access time summary

AHB transfer Data phase

wait states Description

e200z4d instruction fetch 0 Flash memory prefetch buffer hit (page hit)

e200z4d instruction fetch 3 Flash memory prefetch buffer miss

(based on 4-cycle random flash array access time)

e200z4d data read 0–1 SRAM read

e200z4d data write 0 SRAM 32-bit write

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 11

1.5.10 Error Correction Status Module (ECSM)

The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM).

It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported

to the FCCU. The following errors and indications are reported into the ECSM dedicated registers:

• ECC error status and configuration for flash memory and SRAM

• ECC error reporting for flash memory

• ECC error reporting for SRAM

• ECC error injection for SRAM

1.5.11 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

• Duplicated periphery

• Master access privilege level per peripheral (per master: read access enable; write access enable)

• Checker ap plied on PBRIDGE outpu t toward peri phery

• Byte endianess swap capability

1.5.12 Interrupt Controller (INTC)

The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard re al-tim e

systems.

For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor

is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt

request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that

lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of

interrupt request, the priority of each interrupt request is software configurable.

The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can

be raised temporarily so that all tasks which share the resource can not preempt each other.

The INTC provides the following features:

• Duplicated periphery

• Unique 9-bit vector per interrupt source

• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

• Priority elevation for shared resource

The INTC is replicated for each processor.

e200z4d data write 0 SRAM 64-bit write (executed as 2 x 32-bit writes)

e200z4d data write 0–2 SRAM 8-,16-bit write

(Read-modify-Write for ECC)

e200z4d flash memory read 0 Flash memory prefetch buffer hit (page hit)

e200z4d flash memory read 3 Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle

of program flash memory controller arbitration)

Table 2. Platform memory access time summary (continued)

AHB transfer Data phase

wait states Description

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor12

1.5.13 System clocks and clock generation

The following list summarizes the system clock and clock generation on this device:

• Lock status cont inuously monitored by lock detect circuitry

• Loss-of-clo ck (LOC) de tecti on fo r reference and feedback clocks

• On-chip loop filter (for improved electromagnetic interference performance and fewer external components required)

• Programmabl e outpu t clock divider of system clock (1, 2, 4, 8)

• FlexPWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock

(with max frequency 120 MHz)

• On-chip crystal oscillator with automatic level control

• Dedicated internal 16 MHz internal RC oscillator for rapid start-up

— Supports automated frequency trimming by hardware during device startup and by user application

• Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and SWG)

1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL)

Each device has two FMPLLs.

Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock.

Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor,

output clock divider ratio are all software configurable. The FMPLLs have the following maj or features:

• Input frequency: 4–40 MHz continuous range (limit ed by the cry sta l oscill ator)

• Voltage controlled oscillator (VCO) range: 256–512 MHz

• Frequency modulation via software control to reduce and control emission peaks

— Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register

— Modulation frequency: triangular modulation with 25 kHz nominal rate

• Option to switch modulation on and off via software interface

• Out put divider (ODF) for reduced frequency operation without re-lock

• 3 modes of operation

— Bypass mode

— Normal FMPLL mode with crystal reference (default)

— Normal FMPLL mode with external reference

• Lock monitor circuitry with lock status

• Loss-of-l ock detection for reference and feedback clocks

• Self-clocked mode (SCM) operation

• On-chip loop filter

• Aux ili ary FMPLL

— Used for FlexRay due to precise symbol rate requirem e nt by th e prot ocol

— Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies

of operation for PWM and timers and jitter-free control

— Option to enable/disable modulati on to avoid protocol violation on jitter and/or potential unadjusted error in

electric motor control loop

— Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than

the system to ensure higher resolution

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 13

1.5.15 Main oscillator

The main oscillator provides these features:

• Input frequ e ncy rang e 4–40 MHz

• Crystal input mode

• External reference clock (3.3 V) input mode

• FMPLL reference

1.5.16 Internal Reference Clock (RC) oscillator

The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap

reference voltage. The RC oscillator is the device safe clock.

The RC oscillator provides these features:

• Nominal frequency 16 MHz

• ±5% variati on over volt age and temperature after process trim

• Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the

FMPLL

• RC oscillator is used as the default system clock during startup and can be used as back-up input source of FMPLL(s)

in case XOSC fails

1.5.17 Clock, reset, power, mode and test control modules (MC_CGM,

MC_RGM, MC_PCU, and MC_ME)

These modules provide the following:

• Clock gating and clock distribution contro l

• Halt , stop mode control

• Flexible configurable system and auxiliary clock dividers

• Various execution modes

— HALT and STOP mode as reduced activity low power mode

— Reset, Idle, Test, Safe

— Various RUN modes with software selectable powered modules

— No stand-by mode implemented (no internal switchable power domains)

1.5.18 Periodic Interrupt Timer Module (PIT)

The PIT module implements the following features:

• 4 general purpose interrupt ti mers

• 32-bit counter resolution

• Can be used for so ftware tick or DMA trigger operation

1.5.19 System Timer Module (STM)

The STM implements the following features:

• Up-coun ter wi th 4 output compare registers

• OS task prot ectio n and hardware tick implementation per AUTOSAR1 requirement

1.Automotive Open System Architecture

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor14

The STM is replicated for each processor.

1.5.20 Soft ware Watchdog Timer (SWT)

This module implement s the following features:

• Fault tolerant output

• Safe internal RC oscillator as reference clock

• Windowed watchdog

• Program flow control monitor with 16-bit pseudorandom key generation

• All ows a high level of safety (SIL3 monitor)

The SWT module is replicated for each processor.

1.5.21 Fault Collection and Control Unit (FCCU)

The FCCU module has the following features:

• Redundant collection of hardware checker results

• Redun dant collection of error information and la tch of faults from critical modules on the device

• Col lection of self-test results

• Con figurable and graded fault control

— Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered)

— External reaction (failure is reported to the external/surrounding system via configurable output pins)

1.5.22 System Integration Unit Lite (SIUL)

The SIUL controls MCU reset configuration, pad configuration, external interrupt , general purpose I/O (GPIO), internal

peripheral multiplexing, and system reset operation. The reset configuration block contains the external pin boot configuration

logic. The pad configuration block contro ls the static electrical characteristics of I/O pins. The GPIO block provides uniform

and discrete input/output cont rol of the I/O pins of the MCU.

The SIU provides the following features:

• Centralized pad control on a per-pin basis

— Pin function selection

— Configurable weak pull-up/down

— Configurable slew rate cont rol (slow/medium/fast)

— Hysteresis on GPIO pins

— Configurable automatic safe mode pad control

• Input filtering for external interrupts

1.5.23 Non-Maskable Interrupt (NMI)

The non-maskable interrupt with de-glit chin g filter supports high-priority core exceptions.

1.5.24 Boot Assist Module (BAM)

The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode

is selected via boot configuration pins.

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 15

The BAM provides the following features:

• Enables boo ting via serial mode (FlexCAN or LINFlex-UART)

• Supports programmable 64-bit password protection for serial boot mode

• Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code

• Aut om atic switch to serial boot mode if internal flash me mory is blank or invalid

1.5.25 System Status and Configuration Module (SSCM)

The SSCM on this device features the following:

• System configuration and status

• Debu g port st atus and debug port enable

• Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half

Word

• Sets up the MMU to allow user boot code to execute as either Power Architecture code (default) or as Freescale VLE

code out of flash memory

• Triggering of device self-tests during reset phase of device boot

1.5.26 FlexCAN

The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version

2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of

this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required

bandwidth.

The FlexCAN module provides the following features:

• Full im plementation of the CAN protocol specification, version 2.0B

— Standard data and remote frames

— Extended data and remote frames

— 0 to 8 bytes data length

— Programmable bit rate as fast as 1Mbit/s

• 32 me ssage buffers of 0 to 8 bytes data length

• Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages

• Programmable loop-back mode supporting self-test operation

• 3 programmable mask registers

• Programmable transmit-first scheme: lowest ID or lowest buffer number

• Time stamp based on 16-bit free-running timer

• Glo bal network time, synchronized by a specific message

• Maskable interrupts

• Independent of the transmission medium (an external transceiver is assumed)

• High immunity to EMI

• Short latency time due to an arbitration schem e for high-priority messages

• Transmit features

— Supports configuration of mul tiple mailboxes to form message queu es of scalable depth

— Arbitration scheme according to message ID or message buffer number

— Internal arbitration to guarantee no inner or outer priority inversion

— Transmit abort procedure and notification

• Receive features

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor16

— Individ ual programmable filters for each mailbox

— 8 mailboxes configurable as a 6-entry receive FIFO

— 8 programmable acceptance filters for receive FIFO

• Programmable clock source

— System clock

— Direct oscillator clock to avoid FMPLL jitter

1.5.27 FlexRay

The FlexRay module provides the following features:

• Full im plementation of FlexRay Protocol Specification 2.1 Rev. A

• 64 config urable message buffers can be handled

• Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate

• Message buffers configurable as transmit or receive

• Message buffer size configurable

• Messag e filterin g for all message buffers based on Frame ID, cycle count, and message ID

• Programmable acceptance filters for receive FIFO

• Message buffer header, status, and payload data stored in system memory (SRAM)

• Internal FlexRay memories have error detection and correction

1.5.28 Serial communication interface module (LINFlexD)

The LINFlexD module (LINFlex with DMA support) on this device features the following:

• Suppo rts LIN Master mode, LIN Slave mode and UART mode

• LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications

• Manages LIN frame transmission and reception without CPU intervention

• LIN features

— Autonomous LIN frame handling

— Message buffer to store as many as 8 data bytes

— Supports messages as long as 64 bytes

— Detection and flagging of LIN errors (Sync field, delimiter , ID parity, bit framing, checksum and T ime-out errors)

— Classic or extended checksum calculation

— Configurable break durati on of up to 50-bit times

— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

— Diagnostic features (Loop back, LIN bus stuck dominant detection)

— Interrupt driven operation with 16 interrupt sources

• LIN slave mode features

— Autonomous LIN header handling

— Autonomous LIN response handling

• UART mode

— Full-duplex operation

— Standard non return-to-zero (NRZ) mark/space format

— Data buffers with 4-byte receive, 4-byte transmit

— Configurable word lengt h (8-bit , 9-bit, 16-bit, or 17-bit words)

— Configurable parity scheme: none, odd, even, always 0

— Speed as fast as 2 Mbit/s

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 17

— Error detection and flagging (Parity, Noise and Framing errors)

— Interrupt driven operation with four interrupt sources

— Separate transmitter and receiver CPU interrupt sources

— 16-bit programmable baud-rate modulus counter and 16-bit fractional

— Two receiver wake-up methods

• Su pport for DMA enabled transfers

1.5.29 Deserial Serial Peripheral Interface (DSPI)

The DSPI modules provide a synchronous serial interface for communication between the MPC564 3L and external devices.

A DSPI module provides these features:

• Full du plex, synchronous transfers

• Master or slave operation

• Programmabl e master bi t rates

• Programmabl e clock pol arit y and phase

• End-of-transmi ssion interrupt flag

• Programmable transfer baud rate

• Programmable data frames from 4 to 16 bits

• As many as 8 chip select lines available, depending on package and pin multiplex ing

• 4 clock and transfer attributes registers

• Chip select strobe available as alternate function on one of the chip select pins for de-glitching

• FIFOs for buffering as many as 5 transfers on the transmit and receive side

• Queu eing operation possible through use of the eDMA

• General purpose I/O function alit y on pin s wh en not used for SPI

1.5.30 FlexPWM

The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single

half-bridge power stage. T wo modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is

present. Additionally, four fault input channels are provided per FlexPWM module.

This PWM is capable of controlling most motor types, including:

• AC inducti on motors (ACIM)

• Permanent Magn et AC motors (PMAC)

• Brushless (BLDC) and brush DC motors (BDC)

• Switched (SRM) and variable reluctance motors (VRM)

• Stepper motors

A FlexPWM module implements the following features:

• 16 bi ts of resol ution for center, edge aligned, and asymmetrical PWMs

• Maximum operating frequency as high as 120 MHz

— Clock source not modulated and independent from system clock (generated via secondary FMPLL)

• Fine gran ularity control for enhanced resolution of the PWM period

• PWM outp uts can operat e as compleme ntary pairs or independent channels

• Ability to accept signed numbers for PWM generation

• Independent control of both edges of each PWM output

• Synchronization to external hardware or other PWM supported

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor18

• Double buffered PWM registers

— Integral reload rates from 1 to 16

— Half cycle reload capability

• Mul tipl e ADC trigger events can be generated per PWM cycle via hardware

• Fault inputs can be assigned to control multiple PW M outputs

• Programmable filters for fault inputs

• Independently pr og rammable PWM outp ut polarity

• Independent top and bottom deadtime insertion

• Each complementary pair can operate with its own PWM frequency and deadtime values

• Individual software control for each PWM output

• All outputs can be forced to a value simultaneously

• PWMX pin can optionally output a third signal from each channel

• Chann els not used fo r PWM generation can be used for buffered output compare functions

• Chann els not used fo r PWM ge nerat ion can be used for input capture functions

• Enhanced dual edge capture functionality

• Option to supply the source for each complementary PWM signal pair from any of the following:

— External digital pin

— Internal timer channel

— External ADC input, taking in to account values set in ADC high- and low-limit registers

• DMA support

1.5.31 eTimer module

The MPC5643L provides three eTimer modules (on the LQFP package eTimer_2 is available internally only without any

external I/O access). Six 16-bit general purpose up/down timer/counters per module are implemented with the following

features:

• Maxim um clock frequency of 120 MHz

• Individual channel capability

— Input capture trigger

— Output compare

— Double buffer (to capture rising edge and falling edge)

— Separate prescaler for each counter

— Selectable clock source

— 0–100% pulse measurement

— Rotation direction flag (Quad decoder mode)

• Maxim um count rate

— Equals peripheral clock divided by 2 for external event count ing

— Equals peripheral clock for internal clock counting

• Cascadeable counters

• Programmable count modulo

• Quadrature decode capabilities

• Counters can share available input pi ns

• Cou nt once or repeatedly

• Preloadable coun ters

• Pins availab le as GPIO when tim er functionality not in use

• DMA support

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 19

1.5.32 Sine Wave Generator (SWG)

A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).

1.5.33 Analog-to-Digital Converter module (ADC)

The ADC module features include:

Analog part:

• 2 on-chip ADCs

— 12-bit resolution SAR architecture

— Same digital interface as in the MPC5604P family

— A/D Channels: 9 external , 3 internal and 4 shared with other A/ D (total 16 channels)

— One channel dedicated to each T-sensor to enable temperature reading during application

— Separated reference for each ADC

— Shared analog supply voltage fo r both ADCs

— One sample and hold unit per ADC

— Adjustable sampling and conversion tim e

Digital part:

• 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in

the appropriate ADC result location

• 2 modes of operation: CPU Mode or CTU Mode

• CPU mode features

— Register based interface with the CPU: one result register per channel

— ADC state machine managi ng three request flows: regular command, hardware injected command, software

injected command

— Selectable priority between software and hardware injected commands

— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)

— DMA compatible interface

• CTU mode features

— Triggered mode only

— 4 independent result queues (1 16 entries, 2 8 entries, 1 4 entries)

— Result alignment circuitry (left justified; right justified)

— 32-bit read mode allows to have channel ID on one of the 16-bit parts

— DMA compatible interfaces

• Built-in self-test features triggered by software

1.5.34 Cross Triggering Unit (CTU)

The ADC cross triggering unit allows automatic generation of ADC con versio n requests on user selected conditions with out

CPU load during the PWM period and with minimized CPU load for dynamic configuration.

The CTU implements the following features:

• Cro ss triggering between ADC, FlexPWM, eTimer, and external pins

• Dou ble buffered trigger generation unit with as many as 8 indep endent trig gers generated from external triggers

• Maxim um operating frequency less than or equal to 120 MHz

• Trigger generation unit configurable in sequential mode or in triggered mode

• Trigger delay unit to compensate the delay of external low pass filter

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor20

• Dou ble buffered global trigger unit allowing eTimer synchronization and/or ADC command gen e rati on

• Dou ble buffered ADC command list point ers to mi nimize ADC-trigger unit update

• Double buffered ADC conversion command list with as many as 24 ADC commands

• Each trigger capable of gen erating consecutive commands

• ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling,

independent result queue selection

• DMA support with safety features

1.5.35 Cyclic Redundancy Checker (CRC) Unit

The CRC module is a configurable multiple data flow unit to com pute CRC signatures on data written to its input register.

The CRC unit has the following features:

• 3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable

polynomial and seed

• Com putes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores resu lt in internal register.

The following standard CRC polynomials are implemented:

—x

8+x4+x3+x2+ 1 [8-bit CRC]

—x

16 +x

12 +x

5+ 1 [16-bit CRC-CCITT]

—x32 +x26 +x23 +x22 +x16 +x12 +x11 +x10 +x8+x7+x5+x4+x2+x+1

[32-bit CRC-ethernet(32)]

• Key engine to be coupled with communication periphery where CRC application is added to allow implementation of

safe communication protocol

• Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic

procedures

• CRC unit connected as peripheral bus on internal peripheral bus

• DMA support

1.5.36 Redundancy Control and Checker Unit (RCCU)

The RCCU checks all outputs of the sphere of replication (addre sses, data, control signals). It has the following features:

• Dup licated module to guarantee highest po ssible diagnostic coverage (check of checker)

• Multiple times replicated IPs are used as checkers on the SoR outputs

1.5.37 Junction temperature sensor

The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device

junction temperature.

The key parameters of the junction temp erature sensor include:

• Nominal temperature range from –40 to 150 °C

• Software temperature alarm via analog ADC comparator possible

1.5.38 Nexus Port Controller (NPC)

The NPC module provides real-time developm ent support capabilities for this device in compliance with the IEEE-ISTO

5001-2003. This developm ent support is supplied for MCUs without requiring ext e rnal address and data pins for internal

visibility.

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 21

The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO

5001-2003 Class 3+, including selected features from Class 4 standard.

The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the

MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also

supports a JTAG only mode using only the JTAG pins. The following features are implemented:

• Full and reduced port modes

• MCKO (message clock out) pin

• 4 or 12 MDO (message data out) pins1

•2 MSEO (message start/end out) pins

•EVTO

(event out) pin

— Auxiliary input po rt

•EVTI

(event in) pin

• 5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)

— Supports JTAG mode

• Host processor (e200) development support features

— Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool

to trace reads or writes, or both, to selected internal memory resources.

— Ownership trace via ownership trace messaging (OTM). OTM facilitates owne rship trace by providing visibility

of which process ID or operating system task is activated. An ownership trace message is transmitted when a

new process/task is activated, allowing development tools to trace ownership flow.

— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities

(direct branches, indirect branches, exceptions, etc.), allowing the development tool to in terpolate what

transpires between the discontinuities. Thus, static code may be traced.

— Watchpoint messaging (WPM) via the auxiliary port

— Watchpoint trigger enable of program and/or data trace messaging

— Data tracing of instruction fetches via private opcodes

1.5.39 IEEE 1149.1 JTAG Controller (JTAGC)

The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic

when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block

is compliant with the IEEE standard.

The JTAG controller provides the following features:

• IEEE Test Access Port (TAP) interface with 5 pins:

—TDI

—TMS

—TCK

—TDO

—JCOMP

• Selectabl e modes of operation include JTAGC/debug or normal system operation

• 5-bit in struction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

— IDCODE

1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor22

—EXTEST

—SAMPLE

— SAMPLE/PRELOAD

• 3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the

boundary scan register is parameterized to support a variety of boundary scan chain lengths.

• TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

1.5.40 Voltage regulator / Power Management Unit (PMU)

The on-chip voltage regulator module provides the follo wing features:

• Single external rail required

• Singl e high supp ly required: nominal 3.3 V both for packaged and Known Good Die op tio n

— Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but

can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower

frequency of operation)

— Known Good Die option uses embedded bal last tran sistor as dissipation capacity is increased to reduce system

cost

• All I/Os are at same voltage as external supply (3.3 V nominal)

• Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal

operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing

feature)

1.5.41 Built-In Self-Test (BIST) capability

This device includes the following pro tecti on against latent faults:

• Boot-time Memory Built-In Self-Test (MBIST)

• Boot-time scan-based Logic Built-In Self-Test (LBIST)

• Run -time ADC Built-In Self-Test (BIST)

• Run -ti me Bui lt-In Self Test of LVDs

Package pinouts and signal descriptions

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 23

2 Package pinouts and signal descriptions

2.1 Package pinouts

Figure 2 shows the MPC5643L in the 144 LQFP package.

Figure 2. MPC5643L 144 LQFP pinout (top view)

Figure 3 shows the MPC5643L in the 257 MAPBGA package.

108

107

106

105

104

103

102

101

100

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

A[4]

VPP_TEST

F[12]

D[14]

G[3]

C[14]

G[2]

C[13]

G[4]

D[12]

G[6]

VDD_HV_FLA

VSS_HV_FLA

VDD_HV_REG_1

VSS_LV_COR

VDD_LV_COR

A[3]

VDD_HV_IO

VSS_HV_IO

B[4]

TCK

TMS

B[5]

G[5]

A[2]

G[7]

C[12]

G[8]

C[11]

G[9]

D[11]

G[10]

D[10]

G[11]

A[1]

A[0]

D[7]

FCCU_F[0]

VDD_LV_COR

VSS_LV_COR

C[1]

E[4]

B[7]

E[5]

C[2]

E[6]

B[8]

E[7]

E[2]

VDD_HV_ADR0

VSS_HV_ADR0

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADR1

VSS_HV_ADR1

VDD_HV_ADV

VSS_HV_ADV

B[13]

E[9]

B[15]

E[10]

B[14]

E[11]

C[0]

E[12]

E[0]

BCTRL

VDD_LV_COR

VSS_LV_COR

VDD_HV_PMU

A[15]

A[14]

C[6]

FCCU_F[1]

D[2]

F[3]

B[6]

VSS_LV_COR

A[13]

VDD_LV_COR

A[9]

F[0]

VSS_LV_COR

VDD_LV_COR

VDD_HV_REG_2

D[4]

D[3]

VSS_HV_IO

VDD_HV_IO

D[0]

C[15]

JCOMP

A[12]

E[15]

A[11]

E[14]

A[10]

E[13]

B[3]

F[14]

B[2]

F[15]

F[13]

C[10]

B[1]

B[0]

144 LQFP package

NMI

A[6]

D[1]

F[4]

F[5]

VDD_HV_IO

VSS_HV_IO

F[6]

MDO0

A[7]

C[4]

A[8]

C[5]

A[5]

C[7]

VDD_HV_REG_0

VSS_LV_COR

VDD_LV_COR

F[7]

F[8]

VDD_HV_IO

VSS_HV_IO

F[9]

F[10]

F[11]

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]

VSS_LV_PLL0_PLL1

VDD_LV_PLL0_PLL1

MPC5643L Microcontroller Data Sheet, Rev. 9

Package pinouts and signal descriptions

Freescale Semiconductor24

Figure 3. MPC5643L 257 MAPBGA pinout (top view)

Table 3 and Table 4 prov ide the pin function summaries for the 144-pin and 257-pin packages, respectively, listing all the

signals multiplexed to each pin.

1234567891011121314151617

SS_HV

_IO

SS_HV

_IO

DD_HV

_IO

H[2] H[0] G[14] D[3] C[15] V

DD_HV

_IO

A[12] H[10] H[14] A[10] B[2] C[10] V

SS_HV

_IO

SS_HV

_IO

SS_HV

_IO

SS_HV

_IO

B[6] A[14] F[3] A[9] D[4] D[0] V

SS_HV

_IO

H[12] E[15] E[14] B[3] F[13] B[0] V

DD_HV

_IO

SS_HV

_IO

DD_HV

_IO

1NC = Not connected (the pin is physical ly not connected to anything on the device)

SS_HV

_IO

FCCU_

F[1] D[2] A[13] V

DD_HV

_REG_2

DD_HV

_REG_2

I[0] JCOMP H[11] I[1] F[14] B[1] V

SS_HV

_IO

A[4] F[12]

F[5] F[4] A[15] C[6] V

SS_LV_

COR

DD_LV_

COR

F[0] V

DD_HV

_IO

SS_HV

_IO

NC A[11] E[13] F[15] V

DD_HV

_IO

_TEST

D[14] G[3]

MDO0 F[6] D[1] NMI NC C[14] G[2] I[3]

H[1] G[12] A[7] A[8] V

DD_LV_

COR

DD_LV_

COR

DD_LV_

COR

DD_LV_

COR

DD_LV_

COR

DD_LV_

COR

DD_LV_

COR

NC C[13] I[2] G[4]

H[3] V

DD_HV

_IO

C[5] A[6] V

DD_LV_

COR

SS_LV_

COR

SS_LV_

COR

SS_LV_

COR

SS_LV_

COR

SS_LV_

COR

DD_LV_

COR

D[12] H[13] H[9] G[6]

G[13] V

SS_HV

_IO

C[4] A[5] V

DD_LV

SS_LV

DD_LV

SS_LV

DD_HV

_REG_1

DD_HV

_FLA

H[6]

F[7] G[15] V

DD_HV

_REG_0

DD_HV

_REG_0

DD_LV

SS_LV

DD_LV

DD_HV

_REG_1

SS_HV

_FLA

H[15]

F[9] F[8] C[7] V

DD_LV

SS_LV

DD_LV

NC H[8] H[7] A[3]

F[10] F[11] D[9] NC V

DD_LV

SS_LV

DD_LV

NC TCK H[4] B[4]

DD_HV

_OSC

DD_HV

_IO

D[8] NC V

DD_LV

C[11] B[5] TMS H[5]

XTAL V

SS_HV

_IO

D[5] V

SS_LV_

PLL

NC C[12] A[2] G[5]

SS_HV

_OSC

RESET D[6] V

DD_LV_

PLL

DD_LV_

COR

SS_LV_

COR

B[8] NC V

SS_HV

_IO

DD_HV

_IO

B[14] V

DD_LV_

COR

SS_LV_

COR

DD_HV

_IO

G[10] G[8] G[7]

EXTAL FCCU

_F[0] V

SS_HV

_IO

D[7] B[7] E[6] V

DD_HV

_ADR0

B[10] V

DD_HV

_ADR1

B[13] B[15] C[0] BCTRL A[1] V

SS_HV

_IO

D[11] G[9]

SS_HV

_IO

DD_HV

_IO

NC C[1] E[5] E[7] V

SS_HV

_ADR0

B[11] V

SS_HV

_ADR1

E[9] E[10] E[12] E[0] A[0] D[10] V

DD_HV

_IO

SS_HV

_IO

SS_HV

_IO

SS_HV

_IO

NC E[4] C[2] E[2] B[9] B[12] V

DD_HV

_ADV

SS_HV

_ADV

E[11] NC NC V

DD_HV

_PMU

G[11] V

SS_HV

_IO

SS_HV

_IO

1234567891011121314151617

Package pinouts and signal descriptions

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 25

Table 3. 144 LQFP pin function summary

Pin # Port/function Peripheral Output function Input function

1NMI —

2 A[6] SIUL GPIO[6] GPIO[6]

DSPI_1 SCK SCK

SIUL — EIRQ[6]

3 D[1] SIUL GPIO[49] GPIO[49]

eTimer_1 ETC[2] ETC[2]

CTU_0 EXT_TGR —

FlexRay — CA_RX

4 F[4] SIUL GPIO[84] GPIO[84]

NPC MDO[3] —

5 F[5] SIUL GPIO[85] GPIO[85]

NPC MDO[2] —

DD_HV_IO —

SS_HV_IO —

8 F[6] SIUL GPIO[86] GPIO[86]

NPC MDO[1] —

9MDO0 —

10 A[7] SIUL GPIO[7] GPIO[7]

DSPI_1 SOUT —

SIUL — EIRQ[7]

11 C[4] SIUL GPIO[36] GPIO[36]

DSPI_0 CS0 CS0

FlexPWM_0 X[1] X[1]

SSCM DEBUG[4] —

SIUL — EIRQ[22]

12 A[8] SIUL GPIO[8] GPIO[8]

DSPI_1 — SIN

SIUL — EIRQ[8]

13 C[5] SIUL GPIO[37] GPIO[37]

DSPI_0 SCK SCK

SSCM DEBUG[5] —

FlexPWM_0 — FAULT[3]

SIUL — EIRQ[23]

MPC5643L Microcontroller Data Sheet, Rev. 9

Package pinouts and signal descriptions

Freescale Semiconductor26

14 A[5] SIUL GPIO[5] GPIO[5]

DSPI_1 CS0 CS0

eTimer_1 ETC[5] ETC[5]

DSPI_0 CS7 —

SIUL — EIRQ[5]

15 C[7] SIUL GPIO[39] GPIO[39]

FlexPWM_0 A[1] A[1]

SSCM DEBUG[7] —

DSPI_0 — SIN

16 VDD_HV_REG_0 —

17 VSS_LV_COR —

18 VDD_LV_COR —

19 F[7] SIUL GPIO[87] GPIO[87]

NPC MCKO —

20 F[8] SIUL GPIO[88] GPIO[88]

NPC MSEO[1] —

21 VDD_HV_IO —

22 VSS_HV_IO —

23 F[9] SIUL GPIO[89] GPIO[89]

NPC MSEO[0] —

24 F[10] SIUL GPIO[90] GPIO[90]

NPC EVTO —

25 F[11] SIUL GPIO[91] GPIO[91]

NPC — EVTI

26 D[9] SIUL GPIO[57] GPIO[57]

FlexPWM_0 X[0] X[0]

LINFlexD_1 TXD —

27 VDD_HV_OSC —

28 VSS_HV_OSC —

29 XTAL —

30 EXTAL —

31 RESET —

Table 3. 144 LQFP pin function summary (continued)

Pin # Port/function Peripheral Output function Input function