NMOS linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. The scanning
circuit is made up of N-channel MOS transistors, operates at low power consumption and is easy to handle. Each photodiode has a large active
area, high UV sensitivity yet very low noise, delivering a high S/N even at low light levels. NMOS linear image sensors also offer excellent output
linearity and wide dynamic range.
S3921/S3924 series have a current-integration readout circuit utilizing the video line and an impedance conversion circuit. The output is available
in boxcar waveform allowing signal readout with a simple external circuit.
The photodiodes of S3921 series have a height of 2.5 mm and are arrayed in a row at a spacing of 50 µm. The photodiodes of S3924 series also
have a height of 2.5 mm but are arrayed at a spacing of 25 µm. The photodiodes are available in 3 different pixel quantities for each series, 128
(S3921-128Q), 256 (S3921-256Q, S3924-256Q) and 512 (S3921-512Q, S3924-512Q) and 1024 (S3924-1024Q). Quartz glass is the standard
window material.
Features
l
Built-in current-integration readout circuit utilizing
video line capacitance and impedance conversion
circuit (boxcar waveform output)
l
Wide active area
Pixel pitch: 50 µm (S3921 series)
25 µm (S3924 series)
Pixel height: 2.5 mm
l
High UV sensitivity with good stability
l
Low dark current and high saturation charge allow a long
integration time and a wide dynamic range at room temperature
l
Excellent output linearity and sensitivity spatial uniformity
l
Low voltage, single power supply operation
l
Start pulse, clock pulse and video line reset pulse are
CMOS logic compatible
Applications
l
Multichannel spectrophotometry
l
Image readout system
IMAGE SENSOR
NMOS linear image sensor
Voltage output type with current-integration readout circuit and impedance conversion circuit
S3921/S3924 series
b
a
2.5 mm
1.0 µm1.0 µm
400 µm
Oxidation silicon
P type silicon
N type silicon
S3921 series: a=50 µm, b=45 µm
S3924 series: a=25 µm, b=20 µm
■ Equivalent circuit
Vss
Start st
Clock
Clock 1
2
Address
switch
Address
switch
Active
photodiode
Dummy diode
Reset switch
Reset Reset V
Active video
Vdd
End of scan
Source follower circuit
Digital shift register
(MOS shift register)
Saturation
control gate
Saturation
control drain
Dummy video
■ Active area structure
■ Absolute maximum ratings
Parameter Symbol Value Unit
Supply voltage Vdd 15 V
Input pulse (φ1, φ2, φst) voltage Vφ 15 V
Power consumption*1 P 10 mW
Operating temperature*2 Topr -40 to +65 °C
Storage temperature Tstg -40 to +85 °C
*1: Vdd=5 V, Vr=2.5 V
*2: No condensation
KMPDC0019EA
KMPDA0067EA
1
NMOS linear image sensor
S3921/S3924 series
■
Shape specifications
Parameter S3921-
128Q
S3921-
256Q
S3921-
512Q
S3924-
256Q
S3924-
512Q
S3924-
1024Q Unit
Number of pixels 128 256 512 256 512 1024 -
Package length 31.75 40.6 31.75 40.6 mm
Number of pin 22 22 -
Window material*
3
Quartz Quartz -
W eight
3.0 3.5 3.0 3.5 g
*3: Fiber optic plate is available (excluding the S3921-128Q, S3924-256Q).
■ Specifications (Ta=25 °C)
S3921 series S3924 series
Parameter Symbol Min. Typ. Max. Min. Typ. Max. Unit
Pixel pitch - - 50 - - 25 -
µ
m
Pixel height - - 2.5 - - 2.5 - mm
Spectral response range (10% of peak)
λ
200 to 1000 200 to 1000 nm
Peak sensitivity wavelength
λ
p
- 600 - - 600 - nm
Photodiode dark current*
4
I
D
- 0.2 0.6 - 0.1 0.3 pA
Photodiode capacitance*
4
Cph - 20 - - 10 - pF
Saturation exposure*
4
*
5
Esat - 220 - - 220 - m
lx
· s
Saturation charge*
4
Qsat - 50 - - 25 - pC
-
1350 (-128Q)
- -
1050 (-256Q)
- mV
-
1300 (-256Q)
- -
820 (-512Q)
- mV
Saturation output voltage*
4
Vsat
-
1100 (-512Q)
- -
570 (-1024Q)
- mV
Photo response non-uniformity*
6
PRNU
- - ±3 - - ±3 %
*4: Reset V=2.5 V, Vdd=5.0 V, V
φ
=5.0 V
*5: 2856 K, tungsten lamp
*6: 50% of saturation, excluding the start pixel and last pixel
■
Electrical characteristics (Ta=25 °C)
S3921 series S3924 series
Parameter Symbol Condition Min. Typ. Max. Min. Typ. Max. Unit
High V
φ
1, V
φ
2 (H) - 4.5 5 10 4.5 5 10 V
Clock pulse (
φ
1,
φ
2)
voltage Low V
φ
1, V
φ
2 (L) - 0 - 0.4 0 - 0.4 V
High V
φ
s (H) - 4.5 V
φ
10 4.5 V
φ
10 V
Start pulse (
φ
st) voltage*
7
Low V
φ
s (L) - 0 - 0.4 0 - 0.4 V
High Vr
φ
(H) - 4.5
V
φ
10 4.5 V
φ
10 V
Reset pulse (Reset
φ
)
Voltage*
7
Low Vr
φ
(L) - 0 - 0.4 0 - 0.4 V
Source follower circuit drain voltage*
7
Vdd - 4.5 Vφ 10 4.5 Vφ 10 V
Reset voltage (Reset V)*
8
Vr
- 2.0
V
φ
- 2.5 V
φ
- 2.0 2.0 V
φ
- 2.5 V
φ
- 2.0 V
Saturation control gate voltage
Vscg
- - 0 - - 0 - V
Saturation control drain voltage*
8
Vscd
- - Vr - - Vr - V
Clock pulse (
φ
1,
φ
2) rise / fall time
trφ1, trφ2
tfφ1, tfφ2
- - 20 - - 20 - ns
Clock pulse (
φ
1,
φ
2) pulse width
tpwφ1, tpwφ2
- 200 - - 200 - - ns
Start pulse (
φ
st) rise / fall time
trφs, tfφs
- - 20 - - 20 - ns
Start pulse (
φ
st) pulse width
tpwφs
- 200 - - 200 - - ns
Reset pulse rise / fall time
trrφ, tfrφ
- - 20 - - 20 - ns
Start pulse (
φ
st) and clock pulse
(
φ
2) overlap
tφov
- 200 - - 200 - - ns
Clock pulse (
φ
2) and reset
pulse (Reset
φ
) overlap
tφovr
- 660 - - 660 - - ns
Clock pulse (
φ
2) and reset
pulse (Reset
φ
) delay time
tdφr-2
- 50 - - 50 - - ns
Clock pulse (
φ
1,
φ
2) space*
9
X1, X2
- trf - 20 - - trf - 20 - - ns
Clock pulse (
φ
2, Reset
φ
) space*
9
tsφr-2
- 0 - - 0 - - ns
Data rate*
10
f
- 0.1 - 500 0.1 - 500 kHz
-
100 (-128 Q)
- -
100 (-256 Q)
- ns
-
150 (-256 Q)
- -
150 (-512 Q)
- ns
Video delay time
tvd
50% of
saturation
*
10
-
200 (-512 Q)
- -
200 (-1024 Q)
- ns
-
21 (-128 Q)
- -
27 (-256 Q)
- pF
-
36 (-256 Q)
- -
50 (-512 Q)
- pF
Clock pulse (
φ
1,
φ
2)
line capacitance
Cφ
5 V bias
-
67 (-512 Q)
- -
100 (-1024 Q)
- pF
Reset pulse (Reset
φ
)
line capacitance
Cr
5 V bias
- 6 - - 6
- pF
-
12 (-128 Q)
- -
14 (-256 Q)
- pF
-
20 (-256 Q)
- -
24 (-512 Q)
- pF
Saturation control gate (Vscg)
line capacitance
Cscg
5 V bias
-
35 (-512 Q)
- -
45 (-1024 Q)
- pF
Output impedance
Zo
Vdd=5 V
Vr=2.5 V
- 200 - - 200
-
Ω
*7: V
φ
is input pulse voltage (refer to “
■
Reset V voltage margin”)
*8: Terminal pin 7 is used for both Reset V and saturation control drain voltage
*9: trf is the clock pulse rise or fall time. A clock pulse space of
“rise time/fall tim e - 20
” ns (nanoseconds) or more
should be input if the clock pulse rise or fall time is longer than 20
ns. (refer to “
■
Timing chart for driver circuit”)
*10: Reset V=2.5 V, Vdd=5.0 V, V
φ
=5.0 V
2
NMOS linear image sensor
S3921/S3924 series
■ Dimensional outlines (unit: mm)
S3921-128Q, S3924-256Q S3921-256Q, S3924-512Q
0.51 ± 0.05
25.4 ± 0.13
2.54 ± 0.13
3.0 ± 0.3
31.75 ± 0.3
10.4 ± 0.25
5.2 ± 0.2
3.2 ± 0.3
0.25
10.16 ± 0.25
1.3 ± 0.2*
1
5.0 ± 0.5
Chip surface
Active area
6.4 × 2.5
1 ch
Direction of scan
*1: Distance from upper surface of quartz
window to chip surface
*2: Distance from chip surface
to bottom of package
*3: Window thickness
1.4 ± 0.2*
2
0.5 ± 0.05*
3
0.51 ± 0.05
25.4 ± 0.13
2.54 ± 0.13
3.0 ± 0.3
Active area
12.8 × 2.5 6.4 ± 0.3
31.75 ± 0.3
Direction of scan
10.4 ± 0.25
5.2 ± 0.2
0.25
10.16 ± 0.25
1.3 ± 0.2*
1
*1: Distance from upper surface of quartz
window to chip surface
*2: Distance from chip surface
to bottom of package
*3: Window thickness
1.4 ± 0.2*
2
0.5 ± 0.05*
3
5.0 ± 0.5
1 ch
Chip surface
S3921-512Q, S3924-1024Q
0.51 ± 0.05
25.4 ± 0.13
3.0 ± 0.3
40.6 ± 0.3
10.4 ± 0.25
5.2 ± 0.2
12.8 ± 0.3
Active area
25.6 × 2.5
0.25
10.16 ± 0.25
1.3 ± 0.2*
1
2.54 ± 0.13
1 ch
5.0 ± 0.5
Direction of scan
*1: Distance from upper surface of quartz
window to chip surface
*2: Distance from chip surface
to bottom of package
*3: Window thickness
1.4 ± 0.2*
2
0.5 ± 0.05*
3
Chip surface
2
1
st
Vss
Vscg
Reset
Reset V (Vscd)
Vss
Active video
Dummy video
Vsub
NC
NC
NC
NC
NC
NC
NC
NC
NC
End of scan
Vdd
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
Vss, Vsub and NC should be grounded.
■ Pin connection
KMPDC0025EA
KMPDA0060ED KMPDA0061ED
KMPDA0062ED
3
NMOS linear image sensor
S3921/S3924 series
Terminal Input or output Description
φ1, φ2Input
(CMOS logic compatible)
Pulses for operating the MOS shift register. The video data rate is equal
to the clock pulse frequency since the video output signal is obtained
synchronously with the rise of φ2 pulse.
φst Input
(CMOS logic compatible)
Pulse for starting the MOS shift register operation. The time interval
between start pulses is equal to the signal accumulation time.
Vss - Connected to the anode of each photodiode. This should be grounded.
Vscg Input Used for restricting blooming. This should be grounded.
Reset φInput
(CMOS logic compatible) With Reset φ at high level, the video line is reset at the Reset V voltage.
Reset V Input
The Reset V terminal connects to each photodiode cathode via the video
line when the address turns on. A positive voltage should be applied to
the Reset V terminal to use each photodiode at a reverse bias. Setting
the Reset V voltage to 2.5 V is recommended when the amplitude of φ1,
φ2 and Reset φ is 5 V. Terminal pin 7 is used for both Reset V and Vscd.
Vscd Input Used for restricting blooming. This should be biased at a voltage equal
to “Reset V”.
Active video Output Low-impedance video output signal after internal current-voltage
conversion. Negative-going output including DC offset.
Dummy video Output
This has the same structure as the active video, but is not connected to
photodiodes, so only DC offset is output. Leave this terminal open when
not used.
Vsub -Connected to the silicon substrate. This should be grounded.
Vdd Input Supply voltage to the internal impedance conversion circuit. A voltage
equal to the amplitude of each clock should be applied to this terminal.
End of scan Output
(CMOS logic compatible)
This should be pulled up at 5 V by using a 10 kΩ resistor. This is a
negative going pulse that appears synchronously with the φ2 timing
right after the last photodiode is addressed.
NC - Should be grounded.
■ Construction of image sensor
The NMOS image sensor consists of a scanning circuit made
up of MOS transistors, a photodiode array, and a switching
transistor array that addresses each photodiode, all integrated
onto a monolithic silicon chip. “■Equivalent circuit” shows
the circuit of a NMOS linear image sensor.
The MOS scanning circuit operates at low power consump-
tion and generates a scanning pulse train by using a start
pulse and 2-phase clock pulses in order to turn on each ad-
dress sequentially. Each address switch is comprised of an
NMOS transistor using the photodiode as the source, the
video line as the drain and the scanning pulse input section
as the gate.
The photodiode array operates in charge integration mode
so that the output is proportional to the amount of light expo-
sure (light intensity × integration time).
Each cell consists of an active photodiode and a dummy
diode, which are respectively connected to the active video
line and the dummy video line via a switching transistor . Each
of the active photodiodes is also connected to the saturation
control drain via the saturation control gate, so that the photo-
diode blooming can be suppressed by grounding the satura-
tion control gate. Applying a pulse signal to the saturation
control gate triggers all reset. (See “■Auxiliary functions”.)
10
-5
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-4
10
-3
10
-2
10
-1
10
0
Output voltage (V)
Exposure (lx · s)
(Typ. Reset V=2.5 V, Vdd=5.0 V, V =5 V, light source: 2856 K)
Saturation exposure
S3921-512Q
S3921-128Q
S3921-256Q
Saturation voltage
0.3
0.2
0.1
0200 400 600 800 1000 1200
Wavelength (nm)
Photo sensitivity (A/W)
(Ta=25 ˚C)
10
-5
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-4
10
-3
10
-2
10
-1
10
0
Output voltage (V)
Exposure (lx · s)
S3924-1024Q
S3924-256Q
Saturation voltage
(Typ. Reset V=2.5 V, Vdd=5.0 V, V =5 V, light source: 2856 K)
S3924-512Q
Saturation exposure
KMPDB0149EA KMPDB0118EA KMPDB0119EA
■
Spectral response (typical example)
■
Output voltage vs. exposure
4
NMOS linear image sensor
S3921/S3924 series
“■Active area structure” shows the schematic diagram of the
photodiode active area. This active area has a PN junction
consisting of an N-type diffusion layer formed on a P-type
silicon substrate.
A signal charge generated by light input accumulates as a
capacitive charge in this PN junction. The N-type diffusion
layer provides high UV sensitivity but low dark current.
■ Driver circuit
A start pulse φst and 2-phase clock pulses φ1, φ2 are needed
to dri ve the shift register. These star t and clock pulses are
positive going pulses and CMOS logic compatible.
The 2-phase clock pulses φ1, φ2 can be either completely
separated or complementary. However, both pulses must not
be “High” at the same time.
A clock pulse space (X1 and X2 in “■Timing chart for driver
circuit”) of a “rise time/fall time - 20” ns or more should be
input if the rise and fall times of φ1, φ2 are longer than 20 ns.
The φ1 and φ2 clock pulses must be held at “High” at least
200 ns. Since the photodiode signal is obtained at the rise of
each φ2 pulse, the clock pulse frequency will equal the video
data rate.
The amplitude of start pulse φst is the same as the φ1 and φ2
pulses. The shift register star ts the scanning at the “High”
level of φst, so the start pulse interval is equal to signal accu-
mulation time. The φst pulse must be held “High” at least 200
ns and overlap with φ2 at least for 200 ns . To operate the shift
register correctly, φ2 must change from the “High” level to the
“Low” level only once during “High” level of φst. The timing
chart for each pulse is shown in “■Timing chart for driver
circuit”.
■ End of scan
The end of scan (EOS) signal appears in synchronization
with the φ2 timing right after the last photodiode is addressed,
and the EOS terminal should be pulled up at 5 V using a 10
kΩ resistor.
tvd
tpw
1
tpw
2
tf
s
tr
1 tf
1
X1 X2
t
ov ts
r-2
tf
2
Reset Vr
(H)
Vr
(L)
td
r-2t
ovr
tfr trr
st V
s (H)
V
s (L)
V
1 (H)
V
1 (L)
V
2 (H)
V
2 (L)
1
2
End of scan
Active video output
tpw
s
tr
s
st
1
2
Reset
■ Timing chart for driv er circuit
■ Signal readout circuit
S3921/S3924 series include a current integration circuit uti-
lizing the video line capacitance and an impedance conver-
sion circuit. This allows signal readout with a simple exter nal
circuit. However, a positive bias must be applied to the video
line because the photodiode anode of NMOS linear image
sensors is at 0 V (Vss). This is done by adding an appropriate
pulse to the reset φ terminal. The amplitude of the reset pulse
should be equal to φ1, φ2 and φst.
When the reset pulse is at the high level, the video line is set
at the Reset V voltage. “■Reset V v oltage margin” shows the
Reset V voltage margin. A higher clock pulse amplitude al-
lows higher Reset V v oltage and saturation charge. Con versely,
if the Reset V voltage is set at a low level with a higher clock
pulse amplitude, the rise and fall times of video output wave-
f orm can be shortened. Setting the Reset V voltage to 2.5 V is
recommended when the amplitude of φ1, φ2, φst and Reset φ
is 5 V.
To obtain a stable output, an overlap between the reset pulse
(Reset φ) and φ2 must be settled. (Reset φ must rise while φ2
is at the high level.) Furthermore, Reset φ must fall while φ2 is
at the low level.
S3921/S3924 series provide output signals with negative-
going boxcar waveform which include a DC offset of approxi-
mately 1 V when Reset V is 2.5 V. If y ou want to remo ve the DC
offset to obtain the positive-going output, the signal readout
circuit and pulse timing shown in “■Readout circuit example”
and “■Timing chart” are recommended. In this circuit, Rs must
be larger than 10 kΩ. Also , the gain is determined by the ratio
of Rf to Rs, so choose the Rf value that suits your application.
■ Reset V voltage margin
4
0
6
8
10
12
45678 10
Clock pulse amplitude (V)
Reset V voltage (V)
2
9
Min.
Reset V voltage range
Max.
Recommended reset
V voltage
KMPDC0026EA
KMPDB0047EA
5
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8
France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1 int. 6, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
Information furnished by HAMAMATSU is believed to be reliable. Howev er, no responsibility is assumed for possible inaccuracies or omissions.
Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein.
Type numbers of products listed inthe specification sheets or supplied as samples may have a suffix "(X)" which means tentativ e specifications or a suffix "(Z)"
which means dev elopmental specifications. ©2010 Hamamatsu Photonics K.K.
NMOS linear image sensor
S3921/S3924 series
Cat. No. KMPD1044E02
Jul. 2010 DN
Vscg
Vss
Vsub
NC
EOS EOS
10 kΩ
+5 V
+5 V
+
–
OPEN
Dummy
video
Active
video
Reset
+2.5 V Reset V
(Vscd) +
+
+15 V
Rs 10 kΩ
Rf
Vdd
st
2
1
st
2
1
Reset
Reset
st
2
1
■ Anti-blooming function
If the incident light intensity is higher than the saturation charge level, even partially, a signal charge in excess of the saturation
charge cannot accumulate in the photodiode. This excessive charge flows out into the video line degrading the signal pur ity. To
avoid this problem and maintain the signal purity, applying the same voltage as the Reset V v oltage to the saturation control drain
and grounding the saturation control gate are effective. If the incident light intensity is extremely high, a positive bias should be
applied to the saturation control gate. The larger the voltage applied to the saturation control gate, the higher the function for
suppressing the excessive saturation charge will be. However, this voltage also lowers the amount of saturation charge, so an
optimum bias voltage should be selected.
■ Auxiliary functions
1) All reset
In normal operation, the accumulated charge in each photodiode is reset when the signal is read out. Besides this method that
uses the readout line, S3921/S3924 series can reset the photodiode charge by applying a pulse to the saturation control gate.
The amplitude of this pulse should be equal to the φ1, φ2, φst, Reset φ pulses and the pulse width should be longer than 5 µs.
When the saturation control gate is set at the “High” level, all photodiodes are reset to the saturation control drain potential.
Conversely, when the saturation control gate is set at the “Low” level (0 V), the signal charge accumulates in each photodiode
without being reset.
2) Dummy video
S3921/S3924 ser ies have a dummy video line. Positive-polarity video signals with the DC offset remove can be obtained by
differential amplification of the active video line and dummy video line outputs. When not needed, leave this unconnected.
■ Precautions for using NMOS linear image sensors
1) Electrostatic countermeasures
NMOS linear image sensors are designed to resist static electrical charges. However, take sufficient cautions and countermea-
sures to prevent damage from static charges when handling the sensors.
2) Window
If dust or grime sticks to the surface of the light input window, it appears as a black blemish or smear on the image. Before u sing
the image sensor, the window surface should be cleaned. Wipe off the window surface with a soft cloth, cleaning paper or
cotton swab slightly moistened with organic solvent such as alcohol, and then lightly blow away with compressed air. Do not
rub the window with dry cloth or cotton swab as this may generate static electr icity.
KMPDC0027EA
KMPDC0028EA
Product name Type No. Content Feature
C7885 Low cost driver circuit
Driver circuit C7885G C7885 + C8225-02
Low price
Single power supply (+15 V) operation
Boxcar waveform output
Pulse generator C8225-02 C7885 series
Cable A8226 C7883 to C7885 series BNC, length 1 m
■ Readout circuit example
Hamamatsu provides the following driver circuits and related products (sold separately).
6
■ Timing chart
