DATA SH EET
Product specification
Supersedes data of 2003 May 07 2003 Sep 04
INTEGRATED CIRCUITS
74LVC00A
Quad 2-input NAND gate
2003 Sep 04 2
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
FEATURES
•5 V tolerant inputs for interfacing with 5 V logic
•Wide supply voltage range from 1.2 to 3.6 V
•CMOS low power consumption
•Direct interface with TTL levels
•Inputs accept voltages up to 5.5 V
•Complies with JEDEC standard no. 8-1A
•ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74LVC00A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
The 74LVC00A provides the 2-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay nA, nB to nY CL= 50 pF; VCC = 3.3 V 2.1 ns
CIinput capacitance 4.0 pF
CPD power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 15 pF
INPUT OUTPUT
nA nB nY
LLH
LHH
HLH
HHL
2003 Sep 04 3
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
ORDERING INFORMATION
PINNING
TYPE NUMBER PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74LVC00AD −40 to +125 °C 14 SO14 plastic SOT108-1
74LVC00ADB −40 to +125 °C 14 SSOP14 plastic SOT337-1
74LVC00APW −40 to +125 °C 14 TSSOP14 plastic SOT402-1
74LVC00ABQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1
PIN SYMBOL DESCRIPTION
1 1A data input
2 1B data input
3 1Y data output
4 2A data input
5 2B data input
6 2Y data output
7 GND ground (0 V)
8 3Y data output
9 3A data input
10 3B data input
11 4Y data output
12 4A data input
13 4B data input
14 VCC supply voltage
2003 Sep 04 4
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
handbook, halfpage
00
MNA210
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
Fig.1 Pin configuration SO14 and (T)SSOP14.
handbook, halfpage
114
1A VCC
7
2
3
4
5
6
1B
1Y
2A
2B
2Y
13
12
11
10
9
4B
4A
4Y
3B
3A
8
GND 3Y
MNA950
GND
(1)
Top view
Fig.2 Pin configuration DHVQFN14.
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
handbook, halfpage
MNA212
1Y
1A 3
1B
1
2
2Y
2A 6
2B
4
5
3Y
3A 8
3B
9
10
4Y
4A 11
4B
12
13
Fig.3 Logic symbol.
handbook, halfpage
MNA246
3
&
&
&
&
2
1
6
5
4
8
10
9
11
13
12
Fig.4 Logic symbol (IEEE/IEC).
2003 Sep 04 5
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
handbook, halfpage
MNA211
A
B
Y
Fig.5 Logic diagram (one gate).
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage for maximum speed performance 2.7 3.6 V
for low-voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage 0 VCC V
Tamb operating ambient temperature −40 +125 °C
tr,t
finput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI<0 −−50 mA
VIinput voltage note 1 −0.5 +6.5 V
IOK output diode current VO>V
CC or VO<0 −±50 mA
VOoutput voltage note 1 −0.5 VCC + 0.5 V
IOoutput source or sink current VO=0toV
CC −±50 mA
ICC, IGND VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation Tamb =−40 to +125 °C; note 2 −500 mW
2003 Sep 04 6
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb =−40 to +85 °C
VIH HIGH-level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.2 −−V
I
O
=−12 mA 2.7 VCC −0.5 −−V
I
O
=−18 mA 3.0 VCC −0.6 −−V
I
O
=−24 mA 3.0 VCC −0.8 −−V
V
OL LOW-level output voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.2 V
IO=12mA 2.7 −−0.4 V
IO=24mA 3.0 −−0.55 V
ILI input leakage current VI= 5.5 Vor GND 3.6 −±0.1 ±5µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 3.6 −0.1 10 µA
∆ICC additional quiescent supply
current per input pin VI=V
CC −0.6 V; IO= 0 2.7 to 3.6 −5 500 µA
2003 Sep 04 7
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
Note
1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.
Tamb =−40 to +125 °C
VIH HIGH-level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.3 −−V
I
O
=−12 mA 2.7 VCC −0.65 −−V
I
O
=−18 mA 3.0 VCC −0.75 −−V
I
O
=−24 mA 3.0 VCC −1−−V
V
OL LOW-level output voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.3 V
IO=12mA 2.7 −−0.6 V
IO=24mA 3.0 −−0.8 V
ILI input leakage current VI= 5.5 Vor GND 3.6 −−±20 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 3.6 −−40 µA
∆ICC additional quiescent supply
current per input pin VI=V
CC −0.6 V; IO= 0 2.7 to 3.6 −−5000 µA
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
2003 Sep 04 8
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
AC CHARACTERISTICS
GND = 0 V; tr=t
f≤2.5 ns.
Notes
1. Typical value is measured at VCC = 3.3 V.
2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
AC WAVEFORMS
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =−40 to +85 °C
tPHL/tPLH propagation delay
nA, nB to nY see Figs 6 and 7 VCC = 1.2 −12 −ns
VCC = 2.7 1.0 2.4 5.1 ns
VCC = 3.0 to 3.6 1.0 2.1(1) 4.3 ns
tsk(0) skew note 2 VCC = 3.0 to 3.6 −−1.0 ns
Tamb =−40 to +125 °C
tPHL/tPLH propagation delay
nA, nB to nY see Figs 6 and 7 VCC = 1.2 −−−ns
VCC = 2.7 1.0 −6.5 ns
VCC = 3.0 to 3.6 1.0 −5.5 ns
tsk(0) skew note 2 VCC = 3.0 to 3.6 −−1.5 ns
handbook, halfpage
MNA218
tPHL
tTHL tTLH
tPLH
VM
VM
nA, nB input
nY output
GND
VI
VOH
VOL
Fig.6 The input nA, nB to output nY propagation delays.
VM= 1.5 V at VCC ≥2.7 V;
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
2003 Sep 04 9
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
handbook, full pagewidth
open
GND
50 pF
2 × VCC
VCC
VIVO
MNA368
D.U.T.
CL
RT
RL
500 Ω
RL
500 Ω
PULSE
GENERATOR
S1
Fig.7 Load circuitry for switching times.
VCC VItPLH/tPHL
1.2 V VCC open
2.7 V 2.7 V open
3.0 to 3.6 V 2.7 V open
Definitions for test circuit:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
2003 Sep 04 10
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
PACKAGE OUTLINES
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
2003 Sep 04 11
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
w
M
b
p
D
H
E
E
Z
e
c
v
M
A
X
A
y
17
14 8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
2003 Sep 04 12
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
2003 Sep 04 13
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
2003 Sep 04 14
Philips Semiconductors Product specification
Quad 2-input NAND gate 74LVC00A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese oratanyotherconditionsabovethosegiven inthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusing orsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands R20/05/pp15 Date of release: 2003 Sep 04 Document order number: 9397 750 11929
