M68EML05P6AUM/D Rev. 1.0 M68EML05P6A EMULATION MODULE USER'S MANUAL A G R E E M E N T Emulation Module User's Manual N O N - D I S C L O S U R E R E Q U I R E D M68EML05P6A R E Q U I R E D A G R E E M E N T N O N - D I S C L O S U R E Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc., 1996; All Rights Reserved 4 MOTOROLA Revision History Revision History Revision History This table summarizes differences between this revision and the previous revision of this emulation module user's manual. Previous Revision None Current Revision 1.0 Date 10/96 Changes Redesign EM to support low-voltage emulation. Update manual to reflect these changes. Location Throughout M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA Revision History 5 Revision History M68EML05P6AUM/D -- Rev. 1.0 6 Revision History MOTOROLA Table of Contents General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Emulation Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Emulation Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Target Cable Assemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Connector Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Target Cable Connector Pin Assignments . . . . . . . . . . . . . . . . . . 14 Logic Analyzer Connector Pin Assignments . . . . . . . . . . . . . . . . .16 MMDS/MMEVS Configuration and Operation Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Setting M68EML05P6A Jumper Headers . . . . . . . . . . . . . . . . . . . . . .21 A/D Converter Voltage Reference Header - W1 . . . . . . . . . . . . . .23 External Clock Source Select Header - W2 . . . . . . . . . . . . . . . . .24 IRQ Level Control Header - W3 . . . . . . . . . . . . . . . . . . . . . . . . . . .25 IRQ Source Control Header - W4 . . . . . . . . . . . . . . . . . . . . . . . . .25 MMDS ID Control Switch - SW1 . . . . . . . . . . . . . . . . . . . . . . . . . .26 Port A Interrupt Mask Option Control Switch - SW2. . . . . . . . . . . 26 Remaining System Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Personality Files Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Emulation Specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Mask Option Register (MOR) Control . . . . . . . . . . . . . . . . . . . . . .27 COP Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Port A Pullups/Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Port C Sharing with the A/D Subsystem . . . . . . . . . . . . . . . . . . . .29 Pullup on IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA Table of Contents 7 Table of Contents IRQ/VPP Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MC68HC05P1A Location $1F00. . . . . . . . . . . . . . . . . . . . . . . . . . 30 Installing Other MCU Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Schematics Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 M68EML05P6A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 M68EML05P6A Schematics (Sheet 1 of 7). . . . . . . . . . . . . . . . . . .35 M68EML05P6A Schematics (Sheet 2 of 7). . . . . . . . . . . . . . . . . . .37 M68EML05P6A Schematics (Sheet 3 of 7). . . . . . . . . . . . . . . . . . .39 M68EML05P6A Schematics (Sheet 4 of 7). . . . . . . . . . . . . . . . . . .41 M68EML05P6A Schematics (Sheet 5 of 7). . . . . . . . . . . . . . . . . . .43 M68EML05P6A Schematics (Sheet 6 of 7). . . . . . . . . . . . . . . . . . .45 M68EML05P6A Schematics (Sheet 7 of 7). . . . . . . . . . . . . . . . . . .47 M68EML05P6AUM/D -- Rev. 1.0 8 Table of Contents MOTOROLA General Description Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Emulation Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Emulation Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Target Cable Assemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Connector Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Target Cable Connector Pin Assignments . . . . . . . . . . . . . . . . . . 14 Logic Analyzer Connector Pin Assignments . . . . . . . . . . . . . . . . . 16 Introduction The M68EML05P6A gives your Motorola development tool the ability to emulate target systems based on MC68HC705P6A, MC68HC05P1A, MC68HC05P4A, and MC68HC05P9A microcontroller units (MCUs). The M68EML05P6A is designed to be a low-voltage emulator, operating in the 3.0 Vdc to 5.0 Vdc range at maximum rated frequencies per the general release specification. By substituting a different emulation module (EM), the Motorola development tool can be enabled to emulate other MCUs. Refer to Motorola's Development Tool Selector Guide, order number SG173/D, for a complete list of available EMs. M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA General Description 9 General Description This hardware user's manual explains connection, configuration, and operation information specific to the M68EML05P6A emulation module. The module can be installed in two Motorola development systems. To configure your M68EML05P6A for either an MMDS or an MMEVS, follow the instructions given in MMDS/MMEVS Configuration and Operation on page 19. Emulation Components Motorola's complete emulation system consists of the emulation module described in this manual as well as other separately purchased options described in the following paragraphs. The following items are included with the M68EML05P6A emulation module: * An M68EML05P6A emulation module (EM) -- The printed circuit board that enables system functionality for MC68HC(7)05PxA MCUs. The female connectors, on the bottom of the module, mate with male connectors on a development system platform board. The EM also has connectors for the target cable assembly. * Configuration software -- 3 1/2-inch diskette containing personality files for this module. Separately purchased Motorola modular development tool options include: * An MMEVS platform board (M68MMPFB0508) -- The MMEVS is an economical development tool that provides real-time in-circuit emulation. The unit's integrated design environment includes an editor, an assembler, a user interface, and a source-level debugging program. M68EML05P6AUM/D -- Rev. 1.0 10 General Description MOTOROLA General Description Emulation Module Layout * An MMDS0508 modular development system (M68MMDS0508) -- The MMDS is a high-performance development tool that has all the capabilities of the MMEVS. In addition, it also has a bus state analyzer and real-time memory windows. * Flex cable target assembly -- See Target Cable Assemblies on page 12 for more information. User supplied components include: * Host computer -- See the appropriate development tool user's manual for minimum requirements. * Power supply -- +5 Vdc is required for the MMEVS. Emulation Module Layout Figure 1 shows the layout of the M68EML05P6A. Jumper header W1 controls the voltage reference input for the A/D subsystem. Jumper header W2 selects the MCU clock source. Jumper headers W3 and W4 are part of the IRQ pin voltage control circuit. Connector J1 is used as a connection to a logic analyzer. DIN connectors P1 and P2 connect the emulation module (EM) and a development system platform board. Target connector J2 is the interface to a target system and uses a separately purchased target cable assembly. When the M68EML05P6A is installed on the MMDS, the target cable passes through the slit in the station module enclosure. The resident MC68HC705P6A MCU is at location U4. Switch SW2 enables or disables port A mask options. Switch SW1 controls which MCU is being emulated. M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA General Description 11 General Description U4 W1 P2 P1 J2 SW1 J1 SW2 W3 W2 W4 Figure 1. M68EML05P6A Emulation Module Target Cable Assemblies To connect your M68EML05P6A to a target system, you need a separately purchased target cable assembly. Cable assemblies are available for two MCU packages: dual in-line plastic (DIP) package and small outline integrated circuit (SOIC) package. The target cable connects to the emulator via connector J2 on the M68EML05P6A emulation module. Pin assignments and signal descriptions for connector J2 can be found in Target Cable Connector Pin Assignments on page 14. Figure 2 represents a target cable assembly. An assembly for 28-pin DIP packages consists of a flex cable and a target head adapter. The assembly for 28-pin SOIC packages requires an additional SOIC adapter. One end of the flex cable plugs onto M68EML05P6A connector J2 with orientation shown in Figure 2. The other end of the flex cable plugs into the target head adapter. The target head adapter then inserts into either a DIP footprint in a target system or into the SOIC adapter. M68EML05P6AUM/D -- Rev. 1.0 12 General Description MOTOROLA General Description Target Cable Assemblies TO EMULATION MODULE FLEX CABLE TO TARGET HEAD ADAPTER TARGET HEAD ADAPTER TO TARGET SYSTEM DIP MCU SOCKET OR SOIC ADAPTER EMULATION MODULE DIP TO SOIC ADAPTER (OPTIONAL) TO TARGET SYSTEM SOIC MCU FOOTPRINT 28-PIN DIP FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05P9P28 28-PIN SOIC FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05P9P28 DIP TO SOIC ADAPTER: M68DIP28SOIC Figure 2. Target Cable Assembly The MCU package in the target system determines the target cable assembly components required: * For a 28-pin DIP package, use flex cable M68CBL05A and target head adapter M68TA05P9P28. * For a 28-pin SOIC package, use the flex cable assembly for the 28-pin DIP in conjunction with SOIC adapter M68DIP28SOIC. M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA General Description 13 General Description Connector Information The connectors on the M68EML05P6A module provide access to the user mode emulation signals (J2) as well as select internal signals (J1). Connector J2 is used as a cable interface to a user's target system, while connector J1 is used to connect a logic analyzer. Target Cable Connector Pin Assignments Figure 3 shows the pin assignments for connector J2. Table 1 lists signal descriptions for connector J2. J2 EVDD TGT-OSC 1 2 T_RST 3 4 T_IRQ OSC2 5 6 PA7 PD7/TCAP 7 8 PA6 TCMP 9 10 PA5 PD5 11 12 PA4 PC0 13 14 PA3 PC1 15 16 PA2 PC2 17 18 PA1 PC3/AD3 19 20 PA0 PC4/AD2 21 22 PB5/SDO PC5/AD1 23 24 PB6/SDI PC6/AD0 25 26 PB7/SCK PC7/VREFH 27 28 GND GND 29 30 GND GND 31 32 GND GND 33 34 GND GND 35 36 GND GND 37 38 GND GND 39 40 GND Figure 3. Target Connector Pin Assignment M68EML05P6AUM/D -- Rev. 1.0 14 General Description MOTOROLA General Description Connector Information Table 1. Connector J2 Signal Descriptions Pin Mnemonic Signal 1 EVDD EXTERNAL VOLTAGE DETECT -- VDD input signal from target used by the emulator to detect target system voltage 2 T_RST TARGET RESET -- Active-low input signal that starts a system reset 3 TGT-OSC 4 T_IRQ TARGET INTERRUPT REQUEST -- Active-low input signal from the target that asynchronously applies an MCU interrupt 5 OSC2 OSCILLATOR 2 -- Output clock signal at two times the internal bus frequency 6, 8, 10, 12, 14, 16, 18, 20 PA7-PA0 PORT A (bits 7-0) -- General-purpose I/O lines controlled by software via data direction and data registers 7 PD7/TCAP PORT D (bit 7) -- General-purpose input-only line TIMER CAPTURE -- Input signal used by the input capture feature of the MCU programmable timer system 9 TCMP 11 PD5 PORT D (bit 5) -- General-purpose I/O line controlled by software via data direction and data registers 13, 15, 17 PC0-PC2 PORT C (bits 0-2) -- General-purpose I/O lines controlled by software via data direction and data registers 22, 24, 26 PB5-PB7 / SDO, SDI, SCK PORT B (bits 5-7) -- General-purpose I/O lines controlled by software via data direction and data registers SIOP SIGNALS -- If the serial I/O port (SIOP) is enabled, these pins are the serial communications pins. Pin 22 is the serial data output (SDO), Pin 24 is the serial data input (SDI) and pin 26 is the serial clock (SCK). 19, 21, 23, 25, 27 PC3-PC7 / AD3-AD0, VREFH PORT C (bits 3-7) -- General-purpose I/O lines controlled by software via data direction and data registers A/D INPUTS -- If the analog-to-digital (A/D) subsystem is enabled, then the pins become A/D inputs. Pins 19, 21, 23, and 25 become A/D channel 3, 2, 1, and 0, respectively. Pin 27 is voltage reference high (VREFH). Use of the VREFH input is controlled by jumper header W1. 28-40 GND TARGET OSCILLATOR 1 -- A possible clock source input for the M68EML05P6A board; system bus frequency is OSC1 / 2; signal use is controlled by jumper header W2 TIMER COMPARE -- Output signal used by the output compare feature of the MCU programmable timer system GROUND M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA General Description 15 General Description Logic Analyzer Connector Pin Assignments Figure 4 shows the pin assignments for logic analyzer connector J1. This connector provides the emulator easy access to many of the signals used internally. Table 2 lists signal descriptions for this connector. J1 NC 1 2 GND NC 3 4 NC LA11 5 6 GND LA10 7 8 LA12 LA9 9 10 LA13 LA8 11 12 NC LA7 13 14 NC LA6 15 16 AD7 LA5 17 18 AD6 LA4 19 20 AD5 LA3 21 22 AD4 LA2 23 24 AD3 LA1 25 26 AD2 LA0 27 28 AD1 LR/W 29 30 AD0 NC 31 32 LIR NC 33 34 NC NC 35 36 NC VCC RESET 37 38 ACLK 39 40 NC Figure 4. Connector J1 Pin Assignments M68EML05P6AUM/D -- Rev. 1.0 16 General Description MOTOROLA General Description Connector Information Table 2. Logic Analyzer Connector J1 Signal Descriptions Pin Mnemonic Signal 1, 3, 4, 10, 12, 14, 31, 33, 34, 35, 36 NC 2, 6 GND 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27 LA11-LA0 LATCHED ADDRESSES (bits 11-0) -- MCU latched output address bus 8 LA12 LATCHED ADDRESSES (bits 13-12) -- MCU latched output address bus 16, 18, 20, 22, 24, 26, 28, 30 AD7-AD0 ADDRESS/DATA BUS (bits 7-0) -- MCU multiplexed address/data bus 29 LR/W LATCHED READ/WRITE -- The MCU's write signal is latched and used on the platform board to control emulator memory accesses. 32 LIR LOAD INSTRUCTION REGISTER -- Active-low signal indicating an opcode fetch cycle is in process 37 VCC +5 Vdc POWER -- Connection to the system voltage VCC 38 ACLK 39 RESET 40 TEST No connection GROUND ANALYZER CLOCK -- The latched addresses are valid on the latched address bus at the rising edge of ACLK. Also, data is valid on the AD bus at ACLK's rising edge. RESET -- Active-low signal will be asserted during internally or externally caused resets. TEST -- Used for factory test M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA General Description 17 General Description M68EML05P6AUM/D -- Rev. 1.0 18 General Description MOTOROLA MMDS/MMEVS Configuration and Operation Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Setting M68EML05P6A Jumper Headers . . . . . . . . . . . . . . . . . . . . . .21 A/D Converter Voltage Reference Header - W1 . . . . . . . . . . . . . 23 External Clock Source Select Header - W2 . . . . . . . . . . . . . . . . . 24 IRQ Level Control Header - W3 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 IRQ Source Control Header - W4. . . . . . . . . . . . . . . . . . . . . . . . . 25 MMDS ID Control Switch - SW1. . . . . . . . . . . . . . . . . . . . . . . . . . 26 Port A Interrupt Mask Option Control Switch - SW2 . . . . . . . . . . .26 Remaining System Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Personality Files Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Emulation Specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Mask Option Register (MOR) Control . . . . . . . . . . . . . . . . . . . . . .29 COP Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Port A Pullups/Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Port C Sharing with the A/D Subsystem . . . . . . . . . . . . . . . . . . . . 31 Pullup on IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IRQ/VPP Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MC68HC05P1A Location $1F00. . . . . . . . . . . . . . . . . . . . . . . . . . 32 Installing Other MCU Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA MMDS/MMEVS Configuration and Operation 19 MMDS/MMEVS Configuration and Operation Introduction The following paragraphs explain how to configure and use your M68EML05P6A as part of an MMDS or MMEVS system. For other parts of system installation and configuration, see either the MMDS0508 Operations Manual (MMDS0508OM/D) or MMEVS05/MMEVS08 Operations Manual (MMEVS0508OM/D). The topics covered in this chapter are: * Setting M68EML05P6A Jumper Headers on page 21 explains how to set the M68EML05P6A jumper headers. * Remaining System Installation on page 27 covers the final steps to system installation. * Personality Files Usage on page 28 discusses the personality file used on the M68EML05P6A board. * Emulation Specifics on page 29 explains special considerations for emulating with this module. * Installing Other MCU Devices on page 32 details possibilities for installing other MC68HC05PxA devices as the resident MCU. NOTE: You can configure an M68EML05P6A already installed in the system platform board. To do so, remove system power and then follow the guidance of this chapter. CAUTION: Be sure to switch off power before you reconfigure an installed EM. Reconfiguring EM jumper headers with the power on can damage emulation circuits. M68EML05P6AUM/D -- Rev. 1.0 20 MMDS/MMEVS Configuration and Operation MOTOROLA MMDS/MMEVS Configuration and Operation Setting M68EML05P6A Jumper Headers Setting M68EML05P6A Jumper Headers Your M68EML05P6A has four jumper headers - W1 through W4 and two sets of DIP switches. Table 3 provides a quick reference for configuration options. Refer to the paragraphs that follow for a more detailed explanation. Table 3. Jumper Header and Switch Positions Jumper Header A/D Converter Voltage Reference Header, W1 Position EM TGT Factory Setting Tie VREFH to the LVDD power plane on the EM X Tie VREFH pins to its input pin on connector J2 EM TGT Clock Source Select, W2 Description Y1 CAN MMDS TGT-OSC C C C C Y1 CAN MMDS TGT-OSC C C C C Select the crystal oscillator circuit located on the EM board at Y1. Requires populating the EM with components Y1, R8, R9, C21, and C22 Select the 4-MHz canned oscillator located on the EM board at XY2. Y1 CAN MMDS TGT-OSC C C C C Select the clock originating from the platform board. The frequency, set to 2 MHz on power up, is controlled by the OSC command. Y1 CAN MMDS TGT-OSC C C C C Select a user supplied clock source. The clock is input to the TGT-OSC pin on connector J2 through a target cable assembly. X M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA MMDS/MMEVS Configuration and Operation 21 MMDS/MMEVS Configuration and Operation Table 3. Jumper Header and Switch Positions (Continued) Jumper Header Position 2XHOLD NORMAL Description Factory Setting After reset, drop high voltage on IRQ to operating voltage when not asserting IRQ low. X IRQ Level Select, W3 2XHOLD NORMAL Hold high voltage on IRQ when not asserting IRQ low. For factory test only. NORMAL VIN Use the voltage input to P3 as the high-voltage source for the IRQ pin control. For factory test only. IRQ Source Select, W4 NORMAL VIN Use the EM's chargepump (~12 V) as the high-voltage source for the IRQ pin control. X Switch setting determines which MCU device is emulated. Switch setting is read at start of debugger software. Emulation MCU Control, SW1 ON = 0 MMDSID (01C-01F) Switch left right Device Emulated EM Id no. up up up down down up HC05P9A $01C HC705P6A $01D HC05P4A $01E down down HC05P1A $01F X M68EML05P6AUM/D -- Rev. 1.0 22 MMDS/MMEVS Configuration and Operation MOTOROLA MMDS/MMEVS Configuration and Operation Setting M68EML05P6A Jumper Headers Table 3. Jumper Header and Switch Positions (Continued) Jumper Header PA0 Port A Interrupt Mask Option Control, SW2 PA7 Factory Setting Each port A bit is individually configurable. In the left position, the option is not selected. X ON PORT A MASK OPTION PULLUPS PA0 PA7 TARGET ON PORT A MASK OPTION PULLUPS A/D Converter Voltage Reference Header - W1 Description Position In the right position, the option is selected. The A/D voltage reference header controls the input to the voltage reference high (VREFH) pin of the MCU. The factory configured position applies the MCU's operating voltage to the VREFH pin. FABRICATED JUMPERS VREFH EM TGT W1 Alternatively, you may supply the reference voltage through the target cable connected to connector J2 of the M68EML05P6A emulation module. To do so, reposition the W1 jumper to the TGT position. M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA MMDS/MMEVS Configuration and Operation 23 MMDS/MMEVS Configuration and Operation External Clock Source Select Header - W2 Jumper header W2 determines the source of the external clock signal. The diagram here illustrates the jumper header where the pins marked C indicate common pins. The default configuration selects the 4-MHz canned oscillator clock source at board location XY2. The external clock has three other possible sources. One source, from the platform board, requires repositioning the W2 jumper between pins MMDS and C and then using the system's OSC command to select a frequency. For a user supplied clock source coming through a target cable connected to J2, reposition the W2 jumper between pins TGT_OSC and C. NOTE: The user supplied source through the target cable should be a CMOS-level square wave. The fourth possible external clock source is a user supplied crystal oscillator circuit. The M68EML05P6A has been designed with an unpopulated crystal circuit. For this source, reposition the W2 jumper between pins Y1 and C and supply the components for the Y1 crystal circuit. The IC device at location U14 is an 74HCU04 inverter and provides the inverter for a standard single inverter oscillator. The user supplies the appropriate crystal, resistors, and capacitors for operating the external clock at a particular frequency. See M68EML05P6A Schematics (Sheet 5 of 7) on page 43 for schematic details of the crystal circuit. Y1 C CAN C MMDS C TGT-OSC C FABRICATED JUMPER CLK SRC W2 M68EML05P6AUM/D -- Rev. 1.0 24 MMDS/MMEVS Configuration and Operation MOTOROLA MMDS/MMEVS Configuration and Operation Setting M68EML05P6A Jumper Headers IRQ Level Control Header - W3 When the MC68HC705P6A is in reset, the IRQ voltage level is at the voltage determined by IRQ source control header W4. The IRQ level control header W3 controls the voltage level on the IRQ pin during routine operation, when the external IRQ is not asserted and the part is not in reset. If jumper header W3 is in the NORMAL position, the IRQ level will drop to the MCU operating voltage once the part comes out of reset. If the jumper header is in the 2XHOLD position, the IRQ level will be held at the voltage determined by IRQ source control header W4. NOTE: The only time the W3 jumper header should be in the 2XHOLD position is for factory testing. W3 2XHOLD IRQ Source Control Header - W4 NORMAL FABRICATED JUMPER IRQ LVL Jumper header W4 determines the source for high voltage applied to the IRQ pin. In the NORMAL position, the voltage is supplied from the development systems chargepump (~12 V). In the VPP position, the voltage is supplied from the user through lever terminal connector P3. NOTE: The W4 jumper header should be in the VPP position only for factory testing. W4 IRQ SRC NORMAL VIN FABRICATED JUMPER M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA MMDS/MMEVS Configuration and Operation 25 MMDS/MMEVS Configuration and Operation MMDS ID Control Switch - SW1 The development system software uses specific personality files to emulate the MCUs supported on the M68EML05P6A emulation module. When entering the debugger software, the set ID for the module is read and the appropriate personality file is loaded. The two positions of switch SW1, representing the two low bits of a 10-bit ID, allow multiple IDs to be read by the host software. See Personality Files Usage on page 28 for proper switch position. Port A Interrupt Mask Option Control Switch - SW2 The eight positions of switch SW2 enable or disable the port A interrupt mask options. Each position controls one port A line. A switch in the left position, OFF, disables the option; a switch in the right position, ON, enables the option. If a mask option is enabled (switched ON) and the corresponding bit of the port A data direction register is configured as an input, a low on the port A pin generates an interrupt. The diagram below shows a possible setting: interrupt masks are disabled for port A lines 0 through 3 and enabled for port A lines 4 through 7. SW2 PA0 PA7 ON PORT A MASK OPTION PULLUPS The default setting for all eight positions of SW2 is OFF. M68EML05P6AUM/D -- Rev. 1.0 26 MMDS/MMEVS Configuration and Operation MOTOROLA MMDS/MMEVS Configuration and Operation Remaining System Installation Remaining System Installation When headers W1-W4 have been configured and switches SW1 and SW2 have been set, M68EML05P6A configuration is complete. * Ensure that the power to the development tool is off. * If installing the M68EML05P6A in an MMDS station module, remove the panel from the station module top. * Fit together EM connectors P1 and P2 on the bottom of the board and platform board DIN connectors. Snap the corners of the EM onto the plastic standoffs. * Connect the target cable, if appropriate. * If installing in an MMDS, replace the panel. At this point, the remaining cable connections can be made, as necessary, and power restored. For instructions, consult either the MMEVS05/MMEVS08 Operations Manual (MMEVS0508OM/D) or MMDS0508 Operations Manual (MMDS0508OM/D). M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA MMDS/MMEVS Configuration and Operation 27 MMDS/MMEVS Configuration and Operation Personality Files Usage The development system uses specific personality files to emulate the MCUs supported on the M68EML05P6A board. The debugger software loads a personality file upon power up. Switch SW1 enables the module to emulate the four MCUs supported. The diagram below shows the 2-position DIP switch that controls which MCU is emulated. The personality files needed for this module are on an individual disk included with the EM board. NOTE: Note that personality file names follow the pattern 00ZZZVxx.MEM, where ZZZ is the EM identifier or MCU name and xx is the version of the file. Table 4. SW1 Switch Settings MCU Emulated SW1-1 SW1-2 Associated .MEM Personality File MC68HC05P9A Up Up 0001CVxx.MEM MC68HC705P6A Up Down 0001DVxx.MEM MC68HC05P4A Down Up 0001EVxx.MEM MC68HC05P1A Down Down 0001FVxx.MEM SW1 ON = 0 MMDSID (01C-01F) M68EML05P6AUM/D -- Rev. 1.0 28 MMDS/MMEVS Configuration and Operation MOTOROLA MMDS/MMEVS Configuration and Operation Emulation Specifics Emulation Specifics The following paragraphs detail differences between the performance of an MC68HC705P6A MCU run in single-chip operation and the way certain features will perform during emulation. Mask Option Register (MOR) Control In single-chip mode operation: The MCU mask options will be determined by which options have been programmed in the MOR EPROM locations ($1EFF-$1F00) of the resident MC68HC705P6A MCU. These registers must be programmed using a dedicated programmer. In emulation: The eight mask option bits controlling the port A pullup/interrupt feature (location $1EFF) are rebuilt externally to the MCU and are enabled through setting the 8-position DIP switch SW2. The initial settings for the other 8-mask option bits will be determined by what has been programmed in the MOR EPROM location ($1F00). Alternatively, the mask options can be controlled via software and allow mask option changes during a debug session. Option changes can be accomplished by command entry (for instance, the MM command) or by execution of user code (for instance, STA instruction). The procedure for changing $1F00 mask option register options during an emulation session requires manipulation of the programming register at location $001C and the MOR location $1F00. First set bit 7 of register $001C (write a $80 to location $001C). If you use the memory modify (MM) command, a "write did not verify" message should be ignored. The mask options can then be set by writing the desired mask option register byte value to the MOR location ($1F00). The selected mask options will return to the default options programmed in the MOR EPROM location if the MCU takes any reset. See COP Emulation on page 30 for further steps required to enable the computer operating properly (COP) feature. M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA MMDS/MMEVS Configuration and Operation 29 MMDS/MMEVS Configuration and Operation COP Emulation In single-chip mode operation: The computer operating properly (COP) feature is enabled if the COP bit of the mask option register (MOR) has been programmed. The MOR register must be programmed using a dedicated programmer. In emulation: The COP bit in the MOR can be set by two methods. The bit can be programmed by using a dedicated programmer prior to using the MCU in the emulator. Alternatively, the option can be set during a debug session using the method outlined in Mask Option Register (MOR) Control on page 29. Only setting the COP bit does not enable the mask option. In addition, a value of #$04 must be written to the reserved register $001F. If you use the memory modify (MM) command, a "write did not verify" message should be ignored. Note that any type of MCU reset will disable the COP, and the steps required to enable the COP must be repeated. Port A Pullups/Interrupts In single-chip mode: The simple port A I/O feature and the associated interrupt/pullup mask options are implemented through the port A pins of the MC68HC(7)05PxA MCU. With this implementation, an interrupt service routine could poll the external IRQ pin using BIL and BIH statements and determine if the source of an interrupt was the external IRQ pin or one of the enabled port A interrupts. In emulation: The port A I/O function is rebuilt off-chip and the enabled interrupt/pullup options will generate interrupts through the external IRQ pin. An interrupt service routine using BIL and BIH instructions could not determine if an interrupt was generated via an external IRQ pin or one of the enabled port A interrupts. The proper way to differentiate between a port interrupt and an external interrupt is to have the interrupt service routine poll possible port A interrupts. If none are low, then the interrupt was driven by an external IRQ. M68EML05P6AUM/D -- Rev. 1.0 30 MMDS/MMEVS Configuration and Operation MOTOROLA MMDS/MMEVS Configuration and Operation Emulation Specifics Port C Sharing with the A/D Subsystem In single-chip mode operation: Port C's bit 7-3 pins are shared with the A/D subsystem. When the A/D is enabled, the pins become the A/D inputs. The external port C bits are not available to the CPU. Port C data and data direction bits are still accessible from the CPU, although they have no effect on the external port C pins. If the A/D subsystem is disabled, port C functionality will be restored to the external pin, and the last conditions stored in the port C registers will determine data and direction for the simple I/O. In emulation: Port C is rebuilt external to the MCU while the A/D inputs continue to be at the MCU pin. To prevent the port C source from affecting the A/D function, associated port C bits should be made an input (by clearing the DDRC bit) before enabling the A/D. Pullup on IRQ In single-chip mode operation: There is no pullup on the IRQ pin. Your application must pull the IRQ pin to VDD level to prevent interrupts due to a floating input. In emulation: The IRQ pin is pulled up on the module. Be aware that an application without the IRQ pin pulled high will emulate correctly but will fail in the application because of a floating IRQ line. The IRQ pin pulled high on the module causes these results. IRQ/VPP Input Pin In single-chip mode operation: The IRQ/VPP pin drives the asynchronous IRQ interrupt function of the CPU. The pin also is used for programming voltage when programming the user EPROM or the MOR. M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA MMDS/MMEVS Configuration and Operation 31 MMDS/MMEVS Configuration and Operation In emulation: The IRQ/VPP signal supplied to connector J2 through a target cable only drives the asynchronous IRQ interrupt function. A VPP voltage should not be supplied to the IRQ/VPP pin in a target application while the emulator is connected. MC68HC05P1A Location $1F00 In single-chip mode operation: The MC68HC05P1A ROM location $1F00 is the first byte of the upper block of user ROM. In emulation: The MC68HC05P1A is emulated with an MC68HC705P6A installed as the resident MCU. Because the MC68HC705P6A has the mask option register at this location, $1F00 cannot be emulated as user ROM. Installing Other MCU Devices With an MC68HC705P6A MCU installed as the resident MCU (location U5), the M68EM05EMP6A module will emulate the MC68HC705P6A, MC68HC05P1A, MC68HC05P4A, and MC68HC05P9A MCUs. Thus, the module is shipped with an MC68HC705P6A device installed. Installing one of these other supported devices as the resident MCU is possible. This allows use of other MCU devices. To install another device: * Ensure that development system power is off. * Replace the resident MC68HC705P6A MCU at location U5 with the new MCU device. NOTE: Be aware that when ROM MCUs are the resident MCU, the mask options are determined by what has been masked on the resident device. M68EML05P6AUM/D -- Rev. 1.0 32 MMDS/MMEVS Configuration and Operation MOTOROLA Schematics Contents M68EML05P6A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Sheet 1 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Sheet 2 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Sheet 3 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Sheet 4 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Sheet 5 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Sheet 6 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Sheet 7 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 M68EML05P6A Schematics Refer to the following pages for the seven sheets of schematics for the M68EML05P6A emulation module. M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA Schematics 33 Schematics M68EML05P6AUM/D -- Rev. 1.0 34 Schematics MOTOROLA M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6A Schematics (Sheet 1 of 7) NOTES, 1. M68EML05P6A EMULATION MODULE UNLESS OTHERWISE SPECIFIED VCC PIN LOCATIONS : VCC IS APPLIED TO PIN 8 OF ALL 8-PIN IC's, PIN 14 OF ALL 14-PIN IC's, PIN 16 OF ALL 16-PIN IC's, PIN 20 OF ALL 20-PIN IC's, ETC. 2. GROUND PIN LOCATIONS : GROUND IS APPLIED TO PIN 4 OF ALL 8-PIN IC's, PIN 7 OF ALL 14-PIN IC's, PIN 8 OF ALL 16-PIN IC's, PIN 10 OF ALL 20-PIN IC's, ETC. 3. ECN # PCB REV SCH REV 125 O 2 126 A 3 R E V I S I O N S DESCRIPTION Test mode timing is on E and not PH2 DATE as expected. Change clock for early signals to PH2*. Cut LOCKOUT from U6 SETDFF pin. Cut LVDD from the U2 SETDFF pin. Diode on WR_DDRD signal to ensure write of 0 to DDRD7. Redo RESET circuit for LV Bidi. Implement modifications from ECO 125 in new rev of PWB. Decouple Caps for ICs as labeled. All caps are 0.1 uF @ 50 V DEVICE TYPE, PIN NUMBERS, AND REFERENCE DESIGNATOR OF GATES ARE SHOWN AS FOLLOWS : VCC-1 10/21/96 10/22/96 GROUND PLANE ----> GND-1 SPLIT POWER PLANE ----> VCC-1 & LVDD-1 U1A 1 2 C23 C24 C17 C19 C5 C7 C25 C15 7407 7407 1 AND 2 U1A GND-1 = DEVICE TYPE = PIN NUMBERS = REFERENCE DESIGNATORS VCC-1 C16 Schematics 4. RESISTANCE VALUES ARE IN OHMS. 5. RESISTORS ARE 1/4 WATT, 5%. 6. CAPACITANCE VALUES ARE IN MICROFARADS. C13 C11 C14 C18 C26 C20 GND-1 LVDD-1 TP1 3 TEST POINT FOR LVDD ADJUST 2 1 C6 C4 C27 C28 C8 4.7UF_RT_16V HDR103 VOLTAGE REGULATOR GND-1 3 LVDD VOUT C10 C12 C9 C2 0.1UF 1 GND-1 CHRGPMP U1 VIN 2 ADJUST LM317T SH 3 LVDD-1 SH 2,4,5,6,7 R1 240 C3 0.1UF C1 4.7UF_RT_16V GND-1 Spare Gates VCC U14F 13 VR1 1K_POT GND-1 GND-1 12 U10A 1 74HCU04 U14E 3 2 GND-1 11 74HC32 10 U8C U10B 4 74HCU04 U14D 5 6 6 2 3 4 5 5 9 8 74HC04 74HC32 5 6 GND GND 74HCU04 GND ORCAD IV FLAT FILES |LINK |LP6AR3S2.SCH |LP6AR3S3.SCH |LP6AR3S4.SCH |LP6AR3S5.SCH |LP6AR3S6.SCH |LP6AR3S7.SCH CSIC DEVELOPMENT TOOLS Title COMPUTER GENERATED DRAWING : DO NOT REVISE MANUALLY M68EML05P6A EMULATION MODULE Size Document Number B 63BSE90895W Date: October 22, 1996 Sheet 1 of REV 3 7 35 Schematics M68EML05P6A Schematics RN3A RN3B RN3C RN3D RES_BUS9I_L_10K 74HCU04 U14C Schematics 36 Schematics M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6A Schematics (Sheet 2 of 7) SH 3 SH 3 LIR/A10 LV-LIR* LIR/A10 LV-LIR* GND MCU15 MCU16 MCU17 MCU18 MCU19 MCU13 MCU12 MCU11 28 XU4 VDD 14 VSS 15 16 17 18 19 VREFH/PC7 AN0/PC6 AN1/PC5 AN2/PC4 AN3/PC3 13 12 11 1 2 25 MCU-RESET* IRQ* TCAP Schematics SH 4 SH 3 IRQ* TCAP SH 5 SH 5 LV-EMCU EMCU MCU15 MCU16 MCU17 MCU18 MCU19 MCU13 MCU12 MCU11 IRQ* TCAP LV-OSC1 MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 TCMP PC1 PC2 PD5 PC0 24 21 20 23 22 TCMP/A12 RW/A11 LIR/A10 A8/A9 LV-EMCU 28 XU5 VDD 14 VSS 15 16 17 18 19 VREFH/PC7 AN0/PC6 AN1/PC5 AN2/PC4 AN3/PC3 1 2 25 SCK/PB7 SDI/PB6 SDO/PB5 19 LE 10 SETDFF 11 12 D0 D1 15 CLK 13 OUT 14 18 PRE-RW 17 IN 16 LV-OSC1 R4 10K PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 3 4 5 6 7 8 9 10 TCMP PC1 PC2 PD5 PC0 24 21 20 23 22 MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 TCMP/A12 RW/A11 LIR/A10 A8/A9 LV-EMCU RESET IRQ PD7/TCAP 27 26 GND-1 U2 LVDD 1 LVDD-1 TCMP/A12 RW/A11 LIR/A10 A8/A9 A8 PRE-LIR PRE-RW GND 1 0 EMCU 12 11 D P R CLK C L PH2* Q 27 26 25 24 23 22 21 20 Q0 Q1 18 17 IN 16 19 LE 10 SETDFF 11 12 D0 D1 15 CLK 13 OUT 9 14 1 3 LV-OSC1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A0 A1 A2 A3 A4 A5 A6 A7 U9B Q 28 2 3 4 5 6 7 8 9 VCC LV-LIR* VDD 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND SH 5,7 SH 3,4 VCC GND-1 AD[0..7] LA12 SH 3,5,6 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 LIR* ACLK TST-RNG SH 4 HDR220 LA12 LA11 LA10 LA9 LA8 LIR* LRW LV-TCMP LIR* LRW LV-TCMP COP-RESET* COP-RESET* A8 SH 3 SH 3,4,5 SH 3 SH 5 U8E PH2* 10 11 SCLK SH 3 74HC04 GND LV_LATCH 8 E-EM SH 3 J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 VCC-1 35 37 39 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 LRW LV-TCMP 27 26 LA[0..14] LOGIC ANALYZER CONNECTOR LATCHES Q0 Q1 MCUAD[0..7] LA[0..14] GND LV_LATCH GND MCU-SOIC 13 12 11 PH2* RESET IRQ PD7/TCAP OSC1 OSC2 MC68HC705P6ADW SH 7 3 4 5 6 7 8 9 10 OSC1 OSC2 MC68HC705P6AP LVDD GND SCK/PB7 SDI/PB6 SDO/PB5 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 MCU[1..28] MCUAD[0..7] LSByte Address/Data Bus U6 1 LVDD VDD 28 VCC LA7 2 A0 Y0 27 LA6 3 A1 Y1 26 LA5 4 A2 25 Y2 24 LA4 5 A3 Y3 23 LA3 6 A4 Y4 LA2 7 A5 22 Y5 LA1 8 A6 21 Y6 LA0 9 A7 Y7 20 LVDD-1 MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 MCU-DIP LVDD SH 5 MCU[1..28] Direct Target Connector Bus U10D 12 74HC74 11 8 VCC 13 U8D 74HC04 SCLK* SH 3 74HC32 VCC U9A 4 LV-OSC1 2 3 D P R CLK C L 1 GND U10C Q 5 9 8 9 10 6 Q 74HC74 74HC32 PH2 PH2 SH 3,4 E-EM SH 5 OSC2 OSC2 SH 5 OSC1 OSC1 E-EM OSC2 SH 4 CSIC DEVELOPMENT TOOLS Title M68EML05P6A EMULATION MODULE Size Document Number B 63BSE90895W Date: October 22, 1996 Sheet 2 of REV 3 7 37 Schematics M68EML05P6A Schematics VCC Schematics 38 Schematics M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6A Schematics (Sheet 3 of 7) U8F DAUGHTER BOARD CONNECTOR #2 13 VCC-1 GND-1 GND-1 P2C PFB PRU NOT USED USE THE ADPRU CHIP ON EM GND-1 43 SW1 SW_DIP2 12 Schematics MCU EMULATED PE0 P9A P6A P1A ID9 ID8 ID7 GND-1 ID6 ID5 ID4 ID3 GND-1 ID2 ID1 ID0 SET SW VCC-1 GND-1 MMDSID 00 01 10 11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 CON_DIN96 P2A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 CON_DIN96 12 LOCKOUT LOCKOUT* 74HC04 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 LOCKOUT* B12 T-RST* B13 (RESET-IN) B14 (PORTS*) B15 B16 MMDS-RESET* B17 COP-RESET* B18 (PRU-D*) B19 B20 B21 B22 B23 B24 B25 B26 B27 (VPRU) B28 B29 EVDD B30 B31 VCC-1 B32 CON_DIN96 GND-1 5 LOCKOUT* GND-1 3 10K 4 TCAP PD7/TCAP LV-TCMP TGT-PD5 LV-OSC2 TOSC1 EVDD 1 3 TOSC1 5 LV-OSC2 PD7/TCAP 7 9 LV-TCMP TGT-PD5 11 TGT-PC0 13 TGT-PC1 15 TGT-PC2 17 TGT-PC3 19 TGT-PC4 21 TGT-PC5 23 TGT-PC6 25 TGT-PC7 27 29 31 33 35 37 39 GND-1 MCU16 MCU17 MCU18 MCU19 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 T-RESET* TGT-PA[0..7] TGT-PA[0..7] P1B P1C SH 2 SH 2 SH 2 SH 2 LIR* 3 1 INTERNAL* INTERNAL* INTERNAL* SH 4 SWITCH SWITCH SWITCH (WE*) (U/M) (OE*) VCC-1 SH 2 GND-1 CON_DIN96 LVDD-1 HDR103 GND-1 TGT-PC[0..7] MCU[1..28] SH 6,7 SH 2 P1A 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 (LA14) (LA13) LA12 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 LVDD 1 3 5 7 9 11 14 GND U7 VCC GND A0 A1 A2 A3 A4 A5 Y0 Y1 Y2 Y3 Y4 Y5 8 GND 2 4 6 10 12 15 LV_74HC4049 PH2 LA[0..14] MMDSIRQ* CHRGPMP (ABT) SCLK-30 MMDSOSC LV-SCLK30* LV-LIR* LV-SCLK* PH2 LIR/A10 SH 7 SH 2 SH 7 SH 2 SH 2 LA[0..14] SH 2 MMDSIRQ* CHRGPMP SH 6 SH 1,4 MMDSOSC SH 5 CSIC DEVELOPMENT TOOLS VCC-1 CON_DIN96 CON_DIN96 GND-1 GND-1 DAUGHTER BOARD CONNECTOR #1 GND Title M68EML05P6A EMULATION MODULE Size Document Number B 63BSE90895W Date: October 22, 1996 Sheet 3 of REV 3 7 39 Schematics M68EML05P6A Schematics SH 4 SH 5,7 W1 MCU[1..28] 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SH 5 SH 6 2 TGT-PC[0..7] B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 SH 5 SH 5 VOLTAGE REF MCU15 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 LIR* LRW SCLK SCLK* LV-OSC2 TGT-OSC T-RESET* T-IRQ* T-IRQ* TGT-PA7 TGT-PA6 TGT-PA5 TGT-PA4 TGT-PA3 TGT-PA2 TGT-PA1 TGT-PA0 MCU11 (PB5) MCU12 (PB6) MCU13 (PB7) AD[0..7] LRW SCLK SCLK* SH 7 SH 2 SH 7 J2 COP-RESET* MMDS-RESET* T-RST* AD[0..7] PD7/TCAP LV-TCMP TGT-PD5 TARGET CONNECTOR VCC-1 GND-1 SH 6 SH 2,5,6 SH 2 U15B 74HC4066 $01C $01D $01E $01F COP-RESET* MMDS-RESET* SH 2,4,6 R7 HDR220 SH 5 SH 5 SH 4,7 VCC-1 P2B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Schematics 40 Schematics M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6A Schematics (Sheet 4 of 7) Q9 2N4403 7 RN4D RES_ISO5I_10K LVDD-1 8 VCC-1 9 P3 1 RN5C RES_ISO5I_1K V-IN PWRTERM2 GND-1 IRQ VOLTAGE CONTROL RN4E RES_ISO5I_10K 5 2 CR2 1N5817 1 0 6 Q10 2N4401 7 Q6 2N4403 IRQ SRC RN5D RES_ISO5I_1K W4 8 (VIN) 1 (NORMAL) 3 2 GND-1 SH 3 SH 3 CHRGPMP LOCKOUT GND-1 3 RN4B 4 1 RN5A RES_ISO5I_1K RES_ISO5I_10K HDR103 9 RN5E RES_ISO5I_1K IRQ W3LEVEL (NORMAL) 1 (2xVDD) 3 1 2 VCC 2 1 0 RN4A 2 IRQ* SH 2 Q8 2N4401 RES_ISO5I_10K HDR103 Schematics SH 6 GND-1 RN4C 5 6 EM-IRQ Q7 2N4401 RES_ISO5I_10K GND-1 LA[0..14] SH 7 BUF-LA[0..2] VCC SH SH SH SH SH 3 6 6 7 3 SH 2 SH 2 SH 7 INTERNAL* WR-DDRA* WR-DDRC* WR-DDRD* SWITCH LRW PH2 ADPRU-CS LA[0..14] SH 2 TST-RNG SH 2 DECODE BUF-LA[0..2] BUF-LA0 BUF-LA1 BUF-LA2 INTERNAL* WR-DDRA* WR-DDRC* WR-DDRD* SWITCH LA0 LRW PH2 ADPRU-CS XU12 VDD VDD 44 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 IO31 IO0 IO1 IO30 IO2 IO29 IO28 IO3 IO4 IO27 IO26 IO5 IO6 IO25 IO24 IO7 I0 CLK1/I5 I1 I4 I3 CLK0/I2 IO8 IO23 IO22 IO9 IO10 IO21 IO20 IO11 IO12 IO19 IO13 IO18 IO17 IO14 IO15 IO16 43 42 41 40 39 38 37 36 35 33 32 31 30 29 28 27 26 25 24 1 12 VSS VSS VSS VSS MACH110-20JC 23 34 DECODE TABLE INTERNAL* SWITCH TEST RANGE WR-DDRA WR-DDRC WR-DDRD* ADPRU-CS DATAOUT-EN* TST-RNG LA3 LA7 LA8 LA9 LA10 LA11 LA2 LA1 LA6 E-EM LA12 LA4 LA5 LOCKOUT* DATAOUT-EN* DATAIN-EN* DATAIN-EN* BUF-LA0 BUF-LA1 BUF-LA2 $0000-$001F $0050 $0080-$00FF $0004*/LRW*/PH2*/E $0006*/LRW*/PH2*/E $0007*/LRW*/PH2*/E $00,02,03,04,06,07 LOCKOUT*(/INTERNAL + ((/PH2*/LRW)+PH2)) LOCKOUT*(/PH2*LRW* /INTERNAL LA0 LA1 LA2 E-EM SH 2 LOCKOUT* DATAOUT-EN* DATAIN-EN* SH 3 SH 5 SH 5 GND CSIC DEVELOPMENT TOOLS Title M68EML05P6A EMULATION MODULE Size Document Number B 63BSE90895W Date: October 22, 1996 Sheet 4 of REV 3 7 41 Schematics M68EML05P6A Schematics GND VCC 22 Schematics 42 Schematics M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6A Schematics (Sheet 5 of 7) MCUAD[0..7] MCUAD[0..7] SH 2 SH 4 DATAIN-EN* DATAIN-EN* SH 4 DATAOUT-EN* DATAOUT-EN* ADDRESS/DATA BUS LEVEL CONVERSION AD[0..7] EM RESET CIRCUIT LVDD-1 MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 COP-RESET* SH 2,3 VCC-1 LVDD-1 R5 4.7K MCU-RESET* SH 2 5 RN1C RES_ISO5I_10K 1 2 3 4 5 6 7 8 9 A0 A1 A2 A3 A4 A5 A6 A7 R2 B_OE NC 12 OUT0 IN0 18 13 IN1 OUT1 17 IN-OSC 15 IN2 OUT2 16 LV-EMCU GND-1 Schematics 14 U14A 1 U14B 2 4 3 27 26 25 24 23 22 21 20 A_OE Q1 2N4401 MMDS-RESET* B0 B1 B2 B3 B4 B5 B6 B7 11 10K SH 3 28 19 74HC04 RES_ISO5I_10K VDD 10 2 6 Q5 2N4401 U3 LVDD U8A VCC-1 RN1D 7 8 1 AD[0..7] OSC2 EMCU OSC1 GND U8B 3 Y1 4 OSC2 74HC04 VCC XY2 1 NC VCC 7 GNDOUT 4MHZ_FS SH 2 EMCU SH 2 OSC2 SH 2,3 LV-EMCU R3 USER_DEFINED_XTL R9 OSC1 GND LV_BUFFER R10 74HCU04 USER_DEFINED_RES 74HCU04 SH 2,3,6 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 14 SH 2 LV-OSC2 LV-OSC2 SH 3 MACH-PA[0..7] SH 6 100 USER_DEFINED_RES C21 USER_DEFINED_CAP SH 3 SH 3 GND-1 MMDSOSC TGT-OSC C22 USER_DEFINED_CAP GND-1 CLK SRC 8 W2 1 3 5 7 GND 2 4 6 8 PORT A CONVERSION 1 -----> U16 LVDD VDD 28 2 3 4 5 6 7 8 9 A0 A1 A2 A3 A4 A5 A6 A7 27 26 25 24 23 22 21 20 HDR204 LVDD-1 TGT-PA[0..7] PULL-PA0 PULL-PA1 PULL-PA2 PULL-PA3 PULL-PA4 PULL-PA5 PULL-PA6 PULL-PA7 TGT-PA[0..7] SH 3,7 PORT A MASK OPTION PULLUPS/INTS LVDD-1 1 2 3 4 5 6 7 8 A_OE 19 B_OE 11 NC 16 15 14 13 12 11 10 9 2 3 4 5 6 7 8 9 10 12 OUT0 PRU-PC1 13 IN1 OUT1 17 MACH-PC1 PRU-PC0 15 IN2 OUT2 16 MACH-PC0* 14 GND LV_BUFFER GND SW_DIP8 SH 6,7 PRU-PC[0..1] PRU-PC[0..1] RN6 RES_BUS9_220K GND IN0 18 LV-LRW LRW SH 2 MACH-PC1 SH 6 MACH-PC0* SH 6 LV-LRW SH 7 CSIC DEVELOPMENT TOOLS Title M68EML05P6A EMULATION MODULE Size Document Number B 63BSE90895W Date: October 22, 1996 Sheet 5 of REV 3 7 43 Schematics M68EML05P6A Schematics TGT-PA0 TGT-PA1 TGT-PA2 TGT-PA3 TGT-PA4 TGT-PA5 TGT-PA6 TGT-PA7 LRW 10 VCC 1 SW2 B0 B1 B2 B3 B4 B5 B6 B7 MACH-PA[0..7] VCC MACH-PA0 MACH-PA1 MACH-PA2 MACH-PA3 MACH-PA4 MACH-PA5 MACH-PA6 MACH-PA7 Schematics 44 Schematics M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6A Schematics (Sheet 6 of 7) LVDD-1 VCC-1 3 9 RN1B RES_ISO5I_10K 1 RN1A RES_ISO5I_10K RN1E RES_ISO5I_10K 4 2 SH 3 SH 3 SH 3 SH 4 T-IRQ* AD[0..7] MACH-PA[0..7] MMDSIRQ* LOCKOUT* WR-DDRC* LVDD 9 PC0:1 HIGH CURRENT SINK AND SOURCE Schematics TGT-PC[0..7] AD[0..7] Q3 2N4401 HI-PC0 SH 3 PORT A INTERRUPT LOGIC 1 0 LVDD U15C 1 0 6 U15D 12 HI-PC1 74HC4066 8 1 1 R8 100 74HC4066 22 VCC TGT-PC0 2 HI-PC0 3 HV-TIRQ* 4 MMDSIRQ* 5 MACH-PA7 6 DDRC0 7 8 9 LOCKOUT* 10 AD0 11 WR-DDRC* 13 14 15 16 DDRC1 17 18 HI-PC1 19 EM-IRQ 20 TGT-PC1 21 TGT-PC[0..7] 1 12 R6 100 XU13 VDD VDD 44 IO31 IO0 IO30 IO1 IO29 IO2 IO3 IO28 IO27 IO4 IO26 IO5 IO25 IO6 IO24 IO7 CLK1/I5 I0 I4 I1 I3 CLK0/I2 IO8 IO23 IO22 IO9 IO10 IO21 IO20 IO11 IO12 IO19 IO18 IO13 IO14 IO17 IO15 IO16 43 42 41 40 39 38 37 36 35 33 32 31 30 29 28 27 26 25 24 VSS VSS VSS VSS MACH210-20JC 23 34 GND SH 2,3,5 MACH-PA[0..7] SH 5 WR-DDRA* MACH-PC1 MACH-PC0* SH 4 SH 5 SH 5 EM-IRQ SH 4 VCC MACH-PA0 MACH-PA1 MACH-PA2 MACH-PA3 MACH-PA4 MACH-PA5 MACH-PA6 WR-DDRA* AD2 AD1 MACH-PC1 MACH-PC0* AD7 AD6 AD5 AD4 AD3 GND TGT-PC1 TGT-PC0 TGT-RESET LEVEL CONVERSION VCC-1 LVDD-1 VCC-1 9 RN2E RES_ISO5I_10K 5 7 RN2C RES_ISO5I_10K RN2D RES_ISO5I_10K SH 3 T-RST* RN2A RES_ISO5I_10K 3 Q2 6 TO/FROM MMDS 1 1 0 CR1 1N5817 2 8 Q4 2N4401 RN2B RES_ISO5I_10K 4 2N4401 T-RST* 12 13 Y0 Y1 5 3 Z0 Z1 TO/FROM TARGET T-RESET* X 14 Y 15 PRU-PC0 Z 4 PRU-PC1 PRU-PC[0..1] INH A B 7 C VEE 74HC4053 PRU-PC[0..1] SH 3 SH 5,7 CSIC DEVELOPMENT TOOLS Title GND-1 M68EML05P6A EMULATION MODULE Size Document Number B 63BSE90895W Date: October 22, 1996 Sheet 6 of REV 3 7 45 Schematics M68EML05P6A Schematics 2 1 6 11 DDRC0 10 DDRC1 9 GND-1 U11 X0 X1 Schematics 46 Schematics M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA M68EML05P6A Schematics (Sheet 7 of 7) A/D PORT REPLACEMENT SH 4 BUF-LA[0..2] BUF-LA[0..2] LVDD XU17 SH 2,5 BUF-LA0 BUF-LA1 BUF-LA2 GND MCUAD[0..7] MCUAD[0..7] 5 6 7 8 9 AB0 AB1 AB2 AB3 AB4 63 64 65 66 67 68 1 2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 13 10 14 15 RW XCLK T12 T12_DELAY U15A 74HC4066 MCUAD7 SH 4 WR-DDRD* WR-DDRD* 1 MCUAD0 MCUAD1 MCUAD2 MCUAD3 MCUAD4 MCUAD5 MCUAD6 2 1 3 CR3 1N5817 Schematics SH 7 LV-LRW LV-LRW SH 2 LV-OSC1 LV-OSC1 SH 3 LV-SCLK* LV-SCLK* SH 3 LV-SCLK30* LV-SCLK30* SH 3 LOCKOUT LOCKOUT SH 4 ADPRU-CS ADPRU-CS PA0/ATD0 PA1/ATD1 PA2/ATD2 PA3/ATD3 PA4/ATD4 PA5/ATD5 PA6/ATD6 PA7/ATD7 20 21 22 23 24 25 26 27 PB0/ATD8 PB1/ATD9 PB2/ATD10 PB3/ATD11 PB4/ATD12 PB5/ATD13 PB6/ATD14 PB7/ATD15 28 29 30 31 32 33 34 35 PC0/ATD16 PC1/ATD17 PC2/ATD18 PC3/ATD19 PC4/ATD20 PC5/ATD21 PC6/ATD22 PC7/ATD23 44 45 46 47 48 49 50 51 PD0/ATD24 PD1/ATD25 PD2/ATD26 PD3 PD4 PD5 PD6 PD7 53 54 55 56 57 58 59 60 TGT-PA[0..7] TGT-PA[0..7] SH 3,5 PRU-PC[0..1] PRU-PC[0..1] SH 5,6 TGT-PC[0..7] TGT-PC[0..7] SH 3,6 TGT-PA0 TGT-PA1 TGT-PA2 TGT-PA3 TGT-PA4 TGT-PA5 TGT-PA6 TGT-PA7 GND-1 PRU-PC0 PRU-PC1 TGT-PC2 TGT-PC3 TGT-PC4 TGT-PC5 TGT-PC6 TGT-PC7 62 61 TEST RST 11 12 CS1 CS2 4 3 41 IIREQCPU IIREQDMA CLRFLGEN 16 17 STOP WAIT 52 ADSIGI 36 VREFH VDDA VDDAREF 39 38 LVDD LVDD GND-1 37 VREFL 40 18 42 43 VSSA VSS GND NC NC MC68HC08ADRUFN68 GND GND VDD 19 LVDD-1 4 RN5B RES_ISO5I_1K 3 6 7 8 9 1 0 RN3E RN3F RN3G RN3H RN3I RES_BUS9I_L_10K TGT-PD5 PD7/TCAP TGT-PD5 PD7/TCAP SH 3 SH 3 M68EML05P6A EMULATION MODULE Size Document Number B 63BSE90895W Date: October 22, 1996 Sheet 7 of REV 3 7 47 Schematics M68EML05P6A Schematics CSIC DEVELOPMENT TOOLS Title Schematics 48 Schematics M68EML05P6AUM/D -- Rev. 1.0 MOTOROLA Motorola reserves the right to make changes without further notice to any products herein. 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