M68EML05P6A
EMULATION MODULE
USER’S MANUAL
M68EML05P6AUM/D
Rev. 1.0
NON-DISCLOSURE AGREEMENT REQUIRED
M68EML05P6A
Emulation Module
User’s Manual
NON-DISCLOSURE AGREEMENT REQUIRED
© Motorola, Inc., 1996; All Rights Reserved
4 MOTOROLA
Motorola reserves the right to make changes without further notice to any products
herein to improve reliability, function, or design. Motorola does not assume any liability
arising out of the application or use of any product or circuit described herein; neither
does it convey any license under its patent rights nor the rights of others. Motorola
products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the
design or manufacture of the part.
Motorola and the Motorola logo are registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Revision History
Revision History
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Revision History 5
Revision History
This table summarizes differences between this revision and the
previous revision of this emulation module user’s manual.
Previous
Revision None
Current
Revision 1.0
Date 10/96
Changes Redesign EM to support low-voltage emulation. Update manual to
reflect these changes.
Location Throughout
M68EML05P6AUM/D — Rev. 1.0
6 Revision History MOTOROLA
Revision History
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Table of Contents 7
Table of Contents
General
Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Emulation Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Emulation Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Target Cable Assemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Connector Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Target Cable Connector Pin Assignments . . . . . . . . . . . . . . . . . . 14
Logic Analyzer Connector Pin Assignments . . . . . . . . . . . . . . . . .16
MMDS/MMEVS
Configuration
and Operation
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Setting M68EML05P6A Jumper Headers . . . . . . . . . . . . . . . . . . . . . .21
A/D Converter Voltage Reference Header – W1 . . . . . . . . . . . . . .23
External Clock Source Select Header – W2 . . . . . . . . . . . . . . . . .24
IRQ Level Control Header – W3 . . . . . . . . . . . . . . . . . . . . . . . . . . .25
IRQ Source Control Header – W4 . . . . . . . . . . . . . . . . . . . . . . . . .25
MMDS ID Control Switch – SW1 . . . . . . . . . . . . . . . . . . . . . . . . . .26
Port A Interrupt Mask Option Control Switch – SW2. . . . . . . . . . . 26
Remaining System Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Personality Files Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Emulation Specifics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Mask Option Register (MOR) Control . . . . . . . . . . . . . . . . . . . . . .27
COP Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Port A Pullups/Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Port C Sharing with the A/D Subsystem . . . . . . . . . . . . . . . . . . . .29
Pullup on IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
M68EML05P6AUM/D — Rev. 1.0
8 Table of Contents MOTOROLA
Table of Contents
IRQ/VPP Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MC68HC05P1A Location $1F00. . . . . . . . . . . . . . . . . . . . . . . . . . 30
Installing Other MCU Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Schematics Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
M68EML05P6A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
M68EML05P6A Schematics (Sheet 1 of 7). . . . . . . . . . . . . . . . . . .35
M68EML05P6A Schematics (Sheet 2 of 7). . . . . . . . . . . . . . . . . . .37
M68EML05P6A Schematics (Sheet 3 of 7). . . . . . . . . . . . . . . . . . .39
M68EML05P6A Schematics (Sheet 4 of 7). . . . . . . . . . . . . . . . . . .41
M68EML05P6A Schematics (Sheet 5 of 7). . . . . . . . . . . . . . . . . . .43
M68EML05P6A Schematics (Sheet 6 of 7). . . . . . . . . . . . . . . . . . .45
M68EML05P6A Schematics (Sheet 7 of 7). . . . . . . . . . . . . . . . . . .47
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA General Description 9
General Description
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Emulation Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Emulation Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Target Cable Assemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Connector Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Target Cable Connector Pin Assignments . . . . . . . . . . . . . . . . . . 14
Logic Analyzer Connector Pin Assignments. . . . . . . . . . . . . . . . . 16
Introduction
The M68EML05P6A gives your Motorola development tool the ability to
emulate target systems based on MC68HC705P6A, MC68HC05P1A,
MC68HC05P4A, and MC68HC05P9A microcontroller units (MCUs).
The M68EML05P6A is designed to be a low-voltage emulator, operating
in the 3.0 Vdc to 5.0 Vdc range at maximum rated frequencies per the
general release specification.
By substituting a different emulation module (EM), the Motorola
development tool can be enabled to emulate other MCUs. Refer to
Motorola’s Development Tool Selector Guide
, order number SG173/D,
for a complete list of available EMs.
M68EML05P6AUM/D — Rev. 1.0
10 General Description MOTOROLA
General Description
This hardware user's manual explains connection, configuration, and
operation information specific to the M68EML05P6A emulation module.
The module can be installed in two Motorola development systems. To
configure your M68EML05P6A for either an MMDS or an MMEVS, follow
the instructions given in MMDS/MMEVS Configuration and Operation
on page 19.
Emulation Components
Motorola’s complete emulation system consists of the emulation module
described in this manual as well as other separately purchased options
described in the following paragraphs.
The following items are included with the M68EML05P6A emulation
module:
•An M68EML05P6A emulation module (EM) — The printed
circuit board that enables system functionality for
MC68HC(7)05PxA MCUs. The female connectors, on the bottom
of the module, mate with male connectors on a development
system platform board. The EM also has connectors for the target
cable assembly.
•Configuration software — 3 1/2-inch diskette containing
personality files for this module.
Separately purchased Motorola modular development tool options
include:
•An MMEVS platform board (M68MMPFB0508) — The MMEVS
is an economical development tool that provides real-time
in-circuit emulation. The unit's integrated design environment
includes an editor, an assembler, a user interface, and a
source-level debugging program.
General Description
Emulation Module Layout
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA General Description 11
•An MMDS0508 modular development system
(M68MMDS0508) — The MMDS is a high-performance
development tool that has all the capabilities of the MMEVS. In
addition, it also has a bus state analyzer and real-time memory
windows.
•Flex cable target assembly — See Target Cable Assemblies
on page 12 for more information.
User supplied components include:
•Host computer — See the appropriate development tool user’s
manual for minimum requirements.
•Power supply — +5 Vdc is required for the MMEVS.
Emulation Module Layout
Figure 1 shows the layout of the M68EML05P6A. Jumper header W1
controls the voltage reference input for the A/D subsystem. Jumper
header W2 selects the MCU clock source. Jumper headers W3 and W4
are part of the IRQ pin voltage control circuit.
Connector J1 is used as a connection to a logic analyzer. DIN
connectors P1 and P2 connect the emulation module (EM) and a
development system platform board.
Target connector J2 is the interface to a target system and uses a
separately purchased target cable assembly. When the M68EML05P6A
is installed on the MMDS, the target cable passes through the slit in the
station module enclosure.
The resident MC68HC705P6A MCU is at location U4. Switch SW2
enables or disables port A mask options. Switch SW1 controls which
MCU is being emulated.
M68EML05P6AUM/D — Rev. 1.0
12 General Description MOTOROLA
General Description
Figure 1. M68EML05P6A Emulation Module
Target Cable Assemblies
To connect your M68EML05P6A to a target system, you need a
separately purchased target cable assembly. Cable assemblies are
available for two MCU packages: dual in-line plastic (DIP) package and
small outline integrated circuit (SOIC) package.
The target cable connects to the emulator via connector J2 on the
M68EML05P6A emulation module. Pin assignments and signal
descriptions for connector J2 can be found in Target Cable Connector
Pin Assignments on page 14.
Figure 2 represents a target cable assembly. An assembly for 28-pin
DIP packages consists of a flex cable and a target head adapter. The
assembly for 28-pin SOIC packages requires an additional SOIC
adapter. One end of the flex cable plugs onto M68EML05P6A connector
J2 with orientation shown in Figure 2. The other end of the flex cable
plugs into the target head adapter. The target head adapter then inserts
into either a DIP footprint in a target system or into the SOIC adapter.
J1
P1 P2 J2
U4 W1
SW1
W3
SW2
W4
W2
General Description
Target Cable Assemblies
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA General Description 13
Figure 2. Target Cable Assembly
The MCU package in the target system determines the target cable
assembly components required:
• For a 28-pin DIP package, use flex cable M68CBL05A and target
head adapter M68TA05P9P28.
• For a 28-pin SOIC package, use the flex cable assembly for the
28-pin DIP in conjunction with SOIC adapter M68DIP28SOIC.
28-PIN DIP
FLEX CABLE:
M68CBL05A
TARGET HEAD ADAPTER:
M68TA05P9P28
TARGET
HEAD
ADAPTER
TO
TARGET
HEAD
ADAPTER
TO TARGET SYSTEM
DIP MCU SOCKET OR
SOIC ADAPTER
EMULATION
MODULE
FLEX
CABLE
TO
EMULATION
MODULE
28-PIN SOIC
FLEX CABLE:
M68CBL05A
TARGET HEAD ADAPTER:
M68TA05P9P28
DIP TO SOIC ADAPTER:
M68DIP28SOIC
TO TARGET SYSTEM
SOIC MCU FOOTPRINT
DIP TO SOIC
ADAPTER
(OPTIONAL)
M68EML05P6AUM/D — Rev. 1.0
14 General Description MOTOROLA
General Description
Connector Information
The connectors on the M68EML05P6A module provide access to the
user mode emulation signals (J2) as well as select internal signals (J1).
Connector J2 is used as a cable interface to a user’s target system, while
connector J1 is used to connect a logic analyzer.
Target Cable
Connector Pin
Assignments
Figure 3 shows the pin assignments for connector J2. Table 1 lists
signal descriptions for connector J2.
Figure 3. Target Connector Pin Assignment
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
T_RST
T_IRQ
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB5/SDO
PB6/SDI
PB7/SCK
GND
GND
GND
GND
GND
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
EVDD
TGT-OSC
OSC2
PD7/TCAP
TCMP
PD5
PC0
PC1
PC2
PC3/AD3
PC4/AD2
PC5/AD1
PC6/AD0
PC7/VREFH
GND
GND
GND
GND
GND
GND
J2
General Description
Connector Information
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA General Description 15
Table 1. Connector J2 Signal Descriptions
Pin Mnemonic Signal
1EV
DD EXTERNAL VOLTAGE DETECT — VDD input signal from target used by the
emulator to detect target system voltage
2 T_RST TARGET RESET — Active-low input signal that starts a system reset
3 TGT–OSC TARGET OSCILLATOR 1 — A possible clock source input for the
M68EML05P6A board; system bus frequency is OSC1 ÷2; signal use
is controlled by jumper header W2
4 T_IRQ TARGET INTERRUPT REQUEST — Active-low input signal from the
target that asynchronously applies an MCU interrupt
5 OSC2 OSCILLATOR 2 — Output clock signal at two times the internal bus
frequency
6, 8, 10,
12, 14, 16,
18, 20 PA7–PA0 PORT A (bits 7–0) — General-purpose I/O lines controlled by software
via data direction and data registers
7 PD7/TCAP PORT D (bit 7) — General-purpose input-only line
TIMER CAPTURE — Input signal used by the input capture feature of
the MCU programmable timer system
9 TCMP TIMER COMPARE — Output signal used by the output compare feature
of the MCU programmable timer system
11 PD5 PORT D (bit 5) — General-purpose I/O line controlled by software via
data direction and data registers
13, 15, 17 PC0–PC2 PORT C (bits 0–2) — General-purpose I/O lines controlled by software
via data direction and data registers
22, 24, 26 PB5–PB7
/
SDO, SDI, SCK
PORT B (bits 5–7) — General-purpose I/O lines controlled by software
via data direction and data registers
SIOP SIGNALS — If the serial I/O port (SIOP) is enab led, these pins are
the serial communications pins. Pin 22 is the serial data output (SDO),
Pin 24 is the serial data input (SDI) and pin 26 is the serial cloc k (SCK).
19, 21, 23,
25, 27
PC3–PC7
/
AD3–AD0, VREFH
PORT C (bits 3–7) — General-purpose I/O lines controlled by software
via data direction and data registers
A/D INPUTS — If the analog-to-digital (A/D) subsystem is enabled, then
the pins become A/D inputs. Pins 19, 21, 23, and 25 become A/D
channel 3, 2, 1, and 0, respectively. Pin 27 is voltage reference high
(VREFH). Use of the VREFH input is controlled by jumper header W1.
28–40 GND GROUND
M68EML05P6AUM/D — Rev. 1.0
16 General Description MOTOROLA
General Description
Logic Analyzer
Connector Pin
Assignments
Figure 4 shows the pin assignments for logic analyzer connector J1.
This connector provides the emulator easy access to many of the signals
used internally. Table 2 lists signal descriptions for this connector.
Figure 4. Connector J1 Pin Assignments
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
NC
GND
LA12
LA13
NC
NC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
LIR
NC
NC
ACLK
NC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
NC
NC
LA11
LA10
LA9
LA8
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
LR/W
NC
NC
NC
VCC
RESET
J1
General Description
Connector Information
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA General Description 17
Table 2. Logic Analyzer Connector J1 Signal Descriptions
Pin Mnemonic Signal
1, 3, 4, 10, 12, 14,
31, 33, 34, 35, 36 NC No connection
2, 6 GND GROUND
5, 7, 9, 11, 13, 15,
17, 19, 21, 23, 25, 27 LA11–LA0 LATCHED ADDRESSES (bits 11–0) — MCU latched output address
bus
8 LA12 LATCHED ADDRESSES (bits 13–12) — MCU latched output address
bus
16, 18, 20, 22,
24, 26, 28, 30 AD7–AD0 ADDRESS/DATA BUS (bits 7–0) — MCU multiplexed address/data bus
29 LR/W LATCHED READ/WRITE — The MCU’s write signal is latched and
used on the platform board to control emulator memory accesses.
32 LIR LOAD INSTRUCTION REGISTER — Active-low signal indicating an
opcode fetch cycle is in process
37 VCC +5 Vdc POWER — Connection to the system voltage VCC
38 ACLK ANALYZER CLOCK — The latched addresses are valid on the latched
address bus at the rising edge of ACLK. Also, data is valid on the AD
bus at ACLK’s rising edge.
39 RESET RESET — Active-low signal will be asserted during internally or
externally caused resets.
40 TEST TEST — Used for factory test
M68EML05P6AUM/D — Rev. 1.0
18 General Description MOTOROLA
General Description
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA MMDS/MMEVS Configuration and Operation 19
MMDS/MMEVS Configuration and Operation
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Setting M68EML05P6A Jumper Headers . . . . . . . . . . . . . . . . . . . . . .21
A/D Converter Voltage Reference Header – W1 . . . . . . . . . . . . . 23
External Clock Source Select Header – W2 . . . . . . . . . . . . . . . . . 24
IRQ Level Control Header – W3 . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IRQ Source Control Header – W4. . . . . . . . . . . . . . . . . . . . . . . . . 25
MMDS ID Control Switch – SW1. . . . . . . . . . . . . . . . . . . . . . . . . . 26
Port A Interrupt Mask Option Control Switch – SW2 . . . . . . . . . . .26
Remaining System Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Personality Files Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Emulation Specifics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Mask Option Register (MOR) Control . . . . . . . . . . . . . . . . . . . . . .29
COP Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Port A Pullups/Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Port C Sharing with the A/D Subsystem . . . . . . . . . . . . . . . . . . . . 31
Pullup on IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IRQ/VPP Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MC68HC05P1A Location $1F00. . . . . . . . . . . . . . . . . . . . . . . . . . 32
Installing Other MCU Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
M68EML05P6AUM/D — Rev. 1.0
20 MMDS/MMEVS Configuration and Operation MOTOROLA
MMDS/MMEVS Configuration and Operation
Introduction
The following paragraphs explain how to configure and use your
M68EML05P6A as part of an MMDS or MMEVS system. For other parts
of system installation and configuration, see either the
MMDS0508
Operations Manual
(MMDS0508OM/D) or
MMEVS05/MMEVS08
Operations Manual
(MMEVS0508OM/D).
The topics covered in this chapter are:
•Setting M68EML05P6A Jumper Headers on page 21 explains
how to set the M68EML05P6A jumper headers.
•Remaining System Installation on page 27 covers the final
steps to system installation.
•Personality Files Usage on page 28 discusses the personality
file used on the M68EML05P6A board.
•Emulation Specifics on page 29 explains special considerations
for emulating with this module.
•Installing Other MCU Devices on page 32details possibilities for
installing other MC68HC05PxA devices as the resident MCU.
NOTE:
You can configure an M68EML05P6A already installed in the
system platform board. To do so, remove system power and
then follow the guidance of this chapter.
CAUTION:
Be sure to switch off power before you reconfigure an
installed EM. Reconfiguring EM jumper headers with the
power on can damage emulation circuits.
MMDS/MMEVS Configuration and Operation
Setting M68EML05P6A Jumper Headers
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA MMDS/MMEVS Configuration and Operation 21
Setting M68EML05P6A Jumper Headers
Your M68EML05P6A has four jumper headers – W1 through W4 and
two sets of DIP switches. Table 3 provides a quick reference for
configuration options. Refer to the paragraphs that follow for a more
detailed explanation.
Table 3. Jumper Header and Switch Positions
Jumper
Header Position Description Factory
Setting
A/D
Converter
Voltage
Reference
Header, W1
Tie VREFH to the LVDD power
plane on the EM X
Tie VREFH pins to its input pin on
connector J2
Clock
Source
Select, W2
Select the crystal oscillator circuit
located on the EM board at Y1.
Requires populating the EM
with components Y1, R8,
R9, C21, and C22
Select the 4-MHz canned
oscillator located on the EM
board at XY2. X
Select the clock originating
from the platform board. The
frequency, set to 2 MHz
on power up, is controlled
by the OSC command.
Select a user supplied clock
source. The clock is input to the
TGT-OSC pin on connector J2
through a target cable assembly.
EM
TGT
EM
TGT
C
C
C
C
Y1
CAN
MMDS
TGT-OSC
C
C
C
C
Y1
CAN
MMDS
TGT-OSC
C
C
C
C
Y1
CAN
MMDS
TGT-OSC
C
C
C
C
Y1
CAN
MMDS
TGT-OSC
M68EML05P6AUM/D — Rev. 1.0
22 MMDS/MMEVS Configuration and Operation MOTOROLA
MMDS/MMEVS Configuration and Operation
IRQ Level
Select, W3
After reset, drop high voltage
on IRQ to operating voltage
when not asserting IRQ low. X
Hold high voltage on IRQ
when not asserting IRQ low.
For factory test only.
IRQ Source
Select, W4
Use the voltage input to P3 as the
high-voltage source for the IRQ
pin control. For factory test only.
Use the EM’s chargepump
(~12 V) as the high-voltage
source for the IRQ pin control. X
Emulation
MCU
Control,
SW1
Switch setting determines
which MCU device is emulated.
Switch setting is read at start
of debugger software.
X
Table 3. Jumper Header and Switch Positions (Continued)
Jumper
Header Position Description Factory
Setting
2XHOLD
NORMAL
2XHOLD
NORMAL
NORMAL
VIN
NORMAL
VIN
ON = 0
MMDSID
(01C-01F)
Switch
up down
Device
down
up
up up
down down
HC05P9A
HC05P1A
HC05P4A
HC705P6A
left right Emulated EM
Id no.
$01C
$01F
$01E
$01D
MMDS/MMEVS Configuration and Operation
Setting M68EML05P6A Jumper Headers
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA MMDS/MMEVS Configuration and Operation 23
A/D Converter
Voltage
Reference
Header – W1
The A/D voltage reference header controls the input to the voltage
reference high (VREFH) pin of the MCU. The factory configured position
applies the MCU’s operating voltage to the VREFH pin.
Alternatively, you may supply the reference voltage through the target
cable connected to connector J2 of the M68EML05P6A emulation
module. To do so, reposition the W1 jumper to the TGT position.
Port A
Interrupt
Mask Option
Control,
SW2
Each port A bit is individually
configurable. In the left position,
the option is not selected. X
In the right position,
the option is selected.
Table 3. Jumper Header and Switch Positions (Continued)
Jumper
Header Position Description Factory
Setting
PA0
PA7
ON
PORT A MASK
OPTION PULLUPS
TARGET
PA0
PA7
ON
PORT A MASK
OPTION PULLUPS
FABRICATED
JUMPERS
EM
TGT
W1
VREFH
M68EML05P6AUM/D — Rev. 1.0
24 MMDS/MMEVS Configuration and Operation MOTOROLA
MMDS/MMEVS Configuration and Operation
External Clock
Source Select
Header – W2
Jumper header W2 determines the source of the external clock signal.
The diagram here illustrates the jumper header where the pins marked
C indicate common pins. The default configuration selects the 4-MHz
canned oscillator clock source at board location XY2.
The external clock has three other possible sources. One source, from
the platform board, requires repositioning the W2 jumper between pins
MMDS and C and then using the system’s OSC command to select a
frequency.
For a user supplied clock source coming through a target cable
connected to J2, reposition the W2 jumper between pins TGT_OSC
and C.
NOTE:
The user supplied source through the target cable should be
a CMOS-level square wave.
The fourth possible external clock source is a user supplied crystal
oscillator circuit. The M68EML05P6A has been designed with an
unpopulated crystal circuit. For this source, reposition the W2 jumper
between pins Y1 and C and supply the components for the Y1 crystal
circuit. The IC device at location U14 is an 74HCU04 inverter and
provides the inverter for a standard single inverter oscillator. The user
supplies the appropriate crystal, resistors, and capacitors for operating
the external clock at a particular frequency. See M68EML05P6A
Schematics (Sheet 5 of 7) on page 43 for schematic details of the
crystal circuit.
C
C
C
C
FABRICATED
JUMPER
CLK SRC
W2
Y1
CAN
MMDS
TGT-OSC
MMDS/MMEVS Configuration and Operation
Setting M68EML05P6A Jumper Headers
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA MMDS/MMEVS Configuration and Operation 25
IRQ Level Control
Header – W3 When the MC68HC705P6A is in reset, the IRQ voltage level is at the
voltage determined by IRQ source control header W4. The IRQ level
control header W3 controls the voltage level on the IRQ pin during
routine operation, when the external IRQ is not asserted and the part is
not in reset.
If jumper header W3 is in the NORMAL position, the IRQ level will drop
to the MCU operating voltage once the part comes out of reset.
If the jumper header is in the 2XHOLD position, theIRQ level will be held
at the voltage determined by IRQ source control header W4.
NOTE:
The only time the W3 jumper header should be in the
2XHOLD position is for factory testing.
IRQ Source Control
Header – W4 Jumper header W4 determines the source for high voltage applied to the
IRQ pin. In the NORMAL position, the voltage is supplied from the
development systems chargepump (~12 V). In the VPP position, the
voltage is supplied from the user through lever terminal connector P3.
NOTE:
The W4 jumper header should be in the V
PP
position only for
factory testing.
FABRICATED
JUMPER
2XHOLD
NORMAL
W3 IRQ LVL
NORMAL
VIN
FABRICATED
JUMPER
W4 IRQ SRC
M68EML05P6AUM/D — Rev. 1.0
26 MMDS/MMEVS Configuration and Operation MOTOROLA
MMDS/MMEVS Configuration and Operation
MMDS ID Control
Switch – SW1 The development system software uses specific personality files to
emulate the MCUs supported on the M68EML05P6A emulation module.
When entering the debugger software, the set ID for the module is read
and the appropriate personality file is loaded. The two positions of switch
SW1, representing the two low bits of a 10-bit ID, allow multiple IDs to
be read by the host software. See Personality Files Usage on page 28
for proper switch position.
Port A Interrupt
Mask Option
Control
Switch – SW2
The eight positions of switch SW2 enable or disable the port A interrupt
mask options. Each position controls one port A line. A switch in the left
position, OFF, disables the option; a switch in the right position, ON,
enables the option.
If a mask option is enabled (switched ON) and the corresponding bit of
the port A data direction register is configured as an input, a low on the
port A pin generates an interrupt. The diagram below shows a possible
setting: interrupt masks are disabled for port A lines 0 through 3 and
enabled for port A lines 4 through 7.
The default setting for all eight positions of SW2 is OFF.
PA0
PA7
ON
PORT A MASK
OPTION PULLUPS
SW2
MMDS/MMEVS Configuration and Operation
Remaining System Installation
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA MMDS/MMEVS Configuration and Operation 27
Remaining System Installation
When headers W1–W4 have been configured and switches SW1 and
SW2 have been set, M68EML05P6A configuration is complete.
• Ensure that the power to the development tool is off.
• If installing the M68EML05P6A in an MMDS station module,
remove the panel from the station module top.
• Fit together EM connectors P1 and P2 on the bottom of the board
and platform board DIN connectors. Snap the corners of the EM
onto the plastic standoffs.
• Connect the target cable, if appropriate.
• If installing in an MMDS, replace the panel.
At this point, the remaining cable connections can be made, as
necessary, and power restored.
For instructions, consult either the
MMEVS05/MMEVS08 Operations
Manual
(MMEVS0508OM/D) or
MMDS0508 Operations Manual
(MMDS0508OM/D).
M68EML05P6AUM/D — Rev. 1.0
28 MMDS/MMEVS Configuration and Operation MOTOROLA
MMDS/MMEVS Configuration and Operation
Personality Files Usage
The development system uses specific personality files to emulate the
MCUs supported on the M68EML05P6A board. The debugger software
loads a personality file upon power up. Switch SW1 enables the module
to emulate the four MCUs supported. The diagram below shows the
2-position DIP switch that controls which MCU is emulated. The
personality files needed for this module are on an individual disk
included with the EM board.
NOTE:
Note that personality file names follow the pattern
00ZZZVxx.MEM, where ZZZ is the EM identifier or MCU name
and xx is the version of the file.
Table 4. SW1 Switch Settings
MCU Emulated SW1–1 SW1–2 Associated .MEM
Personality File
MC68HC05P9A Up Up 0001CVxx.MEM
MC68HC705P6A Up Down 0001DVxx.MEM
MC68HC05P4A Down Up 0001EVxx.MEM
MC68HC05P1A Down Down 0001FVxx.MEM
ON = 0
MMDSID
(01C-01F)
SW1
MMDS/MMEVS Configuration and Operation
Emulation Specifics
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA MMDS/MMEVS Configuration and Operation 29
Emulation Specifics
The following paragraphs detail differences between the performance of
an MC68HC705P6A MCU run in single-chip operation and the way
certain features will perform during emulation.
Mask Option
Register (MOR)
Control
In single-chip mode operation:
The MCU mask options will be determined by which options have
been programmed in the MOR EPROM locations ($1EFF–$1F00) of
the resident MC68HC705P6A MCU. These registers must be
programmed using a dedicated programmer.
In emulation:
The eight mask option bits controlling the port A pullup/interrupt
feature (location $1EFF) are rebuilt externally to the MCU and are
enabled through setting the 8-position DIP switch SW2.
The initial settings for the other 8-mask option bits will be determined
by what has been programmed in the MOR EPROM location ($1F00).
Alternatively, the mask options can be controlled via software and
allow mask option changes during a debug session. Option changes
can be accomplished by command entry (for instance, the MM
command) or by execution of user code (for instance, STA
instruction).
The procedure for changing $1F00 mask option register options
during an emulation session requires manipulation of the
programming register at location $001C and the MOR location $1F00.
First set bit 7 of register $001C (write a $80 to location $001C). If you
use the memory modify (MM) command, a "write did not verify"
message should be ignored. The mask options can then be set by
writing the desired mask option register byte value to the MOR
location ($1F00).
The selected mask options will return to the default options
programmed in the MOR EPROM location if the MCU takes any reset.
See COP Emulation on page 30 for further steps required to enable
the computer operating properly (COP) feature.
M68EML05P6AUM/D — Rev. 1.0
30 MMDS/MMEVS Configuration and Operation MOTOROLA
MMDS/MMEVS Configuration and Operation
COP Emulation In single-chip mode operation:
The computer operating properly (COP) feature is enabled if the COP
bit of the mask option register (MOR) has been programmed. The
MOR register must be programmed using a dedicated programmer.
In emulation:
The COP bit in the MOR can be set by two methods. The bit can be
programmed by using a dedicated programmer prior to using the
MCU in the emulator. Alternatively, the option can be set during a
debug session using the method outlined in Mask Option Register
(MOR) Control on page 29.
Only setting the COP bit does not enable the mask option. In addition,
a value of #$04 must be written to the reserved register $001F. If you
use the memory modify (MM) command, a "write did not verify"
message should be ignored.
Note that any type of MCU reset will disable the COP, and the steps
required to enable the COP must be repeated.
Port A
Pullups/Interrupts In single-chip mode:
The simple port A I/O feature and the associated interrupt/pullup
mask options are implemented through the port A pins of the
MC68HC(7)05PxA MCU. With this implementation, an interrupt
service routine could poll the external IRQ pin using BIL and BIH
statements and determine if the source of an interrupt was the
external IRQ pin or one of the enabled port A interrupts.
In emulation:
The port A I/O function is rebuilt off-chip and the enabled
interrupt/pullup options will generate interrupts through the external
IRQ pin. An interrupt service routine using BIL and BIH instructions
could not determine if an interrupt was generated via an external IRQ
pin or one of the enabled port A interrupts. The proper way to
differentiate between a port interrupt and an external interrupt is to
have the interrupt service routine poll possible port A interrupts. If
none are low, then the interrupt was driven by an external IRQ.
MMDS/MMEVS Configuration and Operation
Emulation Specifics
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA MMDS/MMEVS Configuration and Operation 31
Port C Sharing
with the A/D
Subsystem
In single-chip mode operation:
Port C’s bit 7–3 pins are shared with the A/D subsystem. When the
A/D is enabled, the pins become the A/D inputs. The external port C
bits are not available to the CPU. Port C data and data direction bits
are still accessible from the CPU, although they have no effect on the
external port C pins. If the A/D subsystem is disabled, port C
functionality will be restored to the external pin, and the last conditions
stored in the port C registers will determine data and direction for the
simple I/O.
In emulation:
Port C is rebuilt external to the MCU while the A/D inputs continue to
be at the MCU pin. To prevent the port C source from affecting the
A/D function, associated port C bits should be made an input (by
clearing the DDRC bit) before enabling the A/D.
Pullup on IRQ In single-chip mode operation:
There is no pullup on the IRQ pin. Your application must pull the IRQ
pin to VDD level to prevent interrupts due to a floating input.
In emulation:
The IRQ pin is pulled up on the module. Be aware that an application
without the IRQ pin pulled high will emulate correctly but will fail in the
application because of a floating IRQ line. The IRQ pin pulled high on
the module causes these results.
IRQ/VPP Input Pin In single-chip mode operation:
The IRQ/VPP pin drives the asynchronous IRQ interrupt function of
the CPU. The pin also is used for programming voltage when
programming the user EPROM or the MOR.
M68EML05P6AUM/D — Rev. 1.0
32 MMDS/MMEVS Configuration and Operation MOTOROLA
MMDS/MMEVS Configuration and Operation
In emulation:
The IRQ/VPP signal supplied to connector J2 through a target cable
only drives the asynchronous IRQ interrupt function.
A VPP voltage should not be supplied to the IRQ/VPP pin in a target
application while the emulator is connected.
MC68HC05P1A
Location $1F00 In single-chip mode operation:
The MC68HC05P1A ROM location $1F00 is the first byte of the upper
block of user ROM.
In emulation:
The MC68HC05P1A is emulated with an MC68HC705P6A installed
as the resident MCU. Because the MC68HC705P6A has the mask
option register at this location, $1F00 cannot be emulated as user
ROM.
Installing Other MCU Devices
With an MC68HC705P6A MCU installed as the resident MCU (location
U5), the M68EM05EMP6A module will emulate the MC68HC705P6A,
MC68HC05P1A, MC68HC05P4A, and MC68HC05P9A MCUs. Thus,
the module is shipped with an MC68HC705P6A device installed.
Installing one of these other supported devices as the resident MCU is
possible. This allows use of other MCU devices.
To install another device:
• Ensure that development system power is off.
• Replace the resident MC68HC705P6A MCU at location U5 with
the new MCU device.
NOTE:
Be aware that when ROM MCUs are the resident MCU, the
mask options are determined by what has been masked on
the resident device.
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Schematics 33
Schematics
Contents
M68EML05P6A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Sheet 1 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Sheet 2 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Sheet 3 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Sheet 4 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Sheet 5 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Sheet 6 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Sheet 7 of 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
M68EML05P6A Schematics
Refer to the following pages for the seven sheets of schematics for the
M68EML05P6A emulation module.
M68EML05P6AUM/D — Rev. 1.0
34 Schematics MOTOROLA
Schematics
Schematics
M68EML05P6A Schematics
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Schematics 35
Date: October 22, 1996 Sheet 1 of 7
Size Document Number REV
B 63BSE90895W 3
Title M68EML05P6A EMULATION MODULE
CSIC DEVELOPMENT TOOLS
DATE
GROUND PLANE ----> GND-1
SPLIT POWER PLANE ----> VCC-1 & LVDD-1
10/21/96
10/22/96
R E V I S I O N S
DESCRIPTION
ECN
#PCB
REV SCH
REV
VCC-1
Test mode timing is on E and not PH2 as
expected. Change clock for early signals
to PH2*. Cut LOCKOUT from U6 SETDFF pin.
Cut LVDD from the U2 SETDFF pin. Diode on
WR_DDRD signal to ensure write of 0 to
DDRD7. Redo RESET circuit for LV Bidi.
2O125
126 A 3 Implement modifications from ECO 125
in new rev of PWB.
All caps are 0.1 uF @ 50 V
Decouple Caps for ICs as labeled.
EMULATION MODULE
M68EML05P6A
NOTES, UNLESS OTHERWISE SPECIFIED
VCC IS APPLIED TO PIN 8 OF ALL 8-PIN IC’s,
PIN 14 OF ALL 14-PIN IC’s, PIN 16 OF ALL
16-PIN IC’s, PIN 20 OF ALL 20-PIN IC’s, ETC.
GROUND IS APPLIED TO PIN 4 OF ALL 8-PIN IC’s,
PIN 7 OF ALL 14-PIN IC’s, PIN 8 OF ALL 16-PIN
IC’s, PIN 10 OF ALL 20-PIN IC’s, ETC.
DESIGNATOR OF GATES ARE SHOWN AS FOLLOWS :
DEVICE TYPE, PIN NUMBERS, AND REFERENCE3.
GROUND PIN LOCATIONS :2.
VCC PIN LOCATIONS :1.
7407
21
U1A
7407
1 AND 2
U1A
= DEVICE TYPE
= PIN NUMBERS
= REFERENCE DESIGNATORS
4. RESISTANCE VALUES ARE IN OHMS.
5. RESISTORS ARE 1/4 WATT, 5%.
6. CAPACITANCE VALUES ARE IN MICROFARADS.
C6 1
2 3
TP1
HDR103
C13
C23 C24
C16
TEST POINT FOR
LVDD ADJUST C4
C5 C15
C11
C19 C25C7
C27
C20C18 C26
C17
C28
C14
VOLTAGE REGULATOR
VCC-1
GND-1
GND-1
GND-1
C8
4.7UF_RT_16V
LVDD-1
LVDD
CHRGPMP SH 3
VIN
3
ADJUST
1
VOUT 2
U1
LM317T
SH 2,4,5,6,7
R1
240 C3
0.1UF C1
4.7UF_RT_16V
GND-1 GND-1
LVDD-1
VR1
1K_POT
C9C12
1
2 3
U10A
74HC32
4
5 6
U10B
74HC32
C2
0.1UF
GND-1
GND-1
GND-1
Spare Gates
C10
13 12
U14F
74HCU04
11 10
U14E
74HCU04 5 6
U8C
74HC04
VCC
COMPUTER GENERATED DRAWING : DO NOT REVISE MANUALLY
|LINK
ORCAD IV FLAT FILES GND
|LP6AR3S2.SCH
|LP6AR3S3.SCH
|LP6AR3S4.SCH
|LP6AR3S5.SCH
|LP6AR3S6.SCH
|LP6AR3S7.SCH
9 8
U14D
74HCU04
5 6
U14C
74HCU04
GND GND
2
RN3A
3
RN3B
4
RN3C
RES_BUS9I_L_10K
5
RN3D
M68EML05P6A Schematics (Sheet 1 of 7)
M68EML05P6AUM/D — Rev. 1.0
36 Schematics MOTOROLA
Schematics
Schematics
M68EML05P6A Schematics
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Schematics 37
Date: October 22, 1996 Sheet 2 of 7
Size Document Number REV
B 63BSE90895W 3
Title M68EML05P6A EMULATION MODULE
CSIC DEVELOPMENT TOOLS
LA[0..14]
LA12
SH 3
MCU[1..28]
MCUAD[0..7]
AD[0..7]
SH 5,7
SH 3,4
SH 3,5,6
GND-1
LOGIC ANALYZER
CONNECTOR
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
LA[0..14]
LA11
LA10
LA9
MCU[1..28]
MCUAD[0..7]
VCC
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J1
HDR220
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
14
Y0 27
Y1 26
Y2 25
Y3 24
Y4 23
Y5 22
Y6 21
Y7 20
LVDD
1 VDD 28
LE
19
SETDFF
10
D0
11
D1
12 Q0 18
Q1 17
CLK
15
OUT
13 IN 16
U6
LV_LATCH
LATCHES
PRE-RW
LSByte Address/Data Bus
Direct Target Connector Bus
MCUAD7
MCUAD6
MCUAD5
MCUAD4
MCUAD3
MCUAD2
MCUAD1
MCUAD0
MCUAD7
MCUAD6
MCUAD5
MCUAD4
MCUAD3
MCUAD2
MCUAD1
MCUAD0
LVDD-1
MCU16
MCU15
MCU17
MCU18
MCU19
VDD
28
VSS
14
VREFH/PC7
15
AN0/PC6
16
AN1/PC5
17
AN2/PC4
18
AN3/PC3
19
SCK/PB7
13
SDI/PB6
12
SDO/PB5
11
PA7 3
PA6 4
PA5 5
PA4 6
PA3 7
PA2 8
PA1 9
PA0 10
TCMP 24
PC1 21
PC2 20
PD5 23
PC0 22
OSC1 27
OSC2 26
RESET
1
IRQ
2
PD7/TCAP
25
XU4
MC68HC705P6AP
MCU-DIP
LIR/A10
LIR/A10
SH 3 LV-LIR*
SH 3 LV-LIR*
GND
LVDD
MCU13
MCU12
IRQ*
MCU-RESET*
MCU11
LV-EMCU
EMCU
TCAP
SH 5
SH 4
SH 3
SH 5
SH 5
MCUAD7
IRQ*
TCAP
VDD
28
VSS
14
VREFH/PC7
15
AN0/PC6
16
AN1/PC5
17
AN2/PC4
18
AN3/PC3
19
SCK/PB7
13
SDI/PB6
12
SDO/PB5
11
PA7 3
PA6 4
PA5 5
PA4 6
PA3 7
PA2 8
PA1 9
PA0 10
TCMP 24
PC1 21
PC2 20
PD5 23
PC0 22
OSC1 27
OSC2 26
RESET
1
IRQ
2
PD7/TCAP
25
XU5
MC68HC705P6ADW
MCU-SOIC
GND
LVDD
LV-OSC1
LIR/A10
TCMP/A12
A8/A9
RW/A11
A8/A9
LIR/A10
GND
LV-EMCU
TCMP/A12
RW/A11
A8
PRE-LIR
PRE-RW
PH2*
R4
10K
GND-1
LVDD-1
LA12
LA11
LA10
LA8
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
LA8
LA9
VCC
LV-TCMP
LRW
LRW
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
14
Y0 27
Y1 26
Y2 25
Y3 24
Y4 23
Y5 22
Y6 21
Y7 20
LVDD
1 VDD 28
LE
19
SETDFF
10
D0
11
D1
12 Q0 18
Q1 17
CLK
15
OUT
13 IN 16
U2
LV_LATCH
LIR*
VCC-1
LIR*
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ACLK
TST-RNG SH 4
LRW SH 3
LIR*
SH 3
SCLK
SCLK* SH 3
COP-RESET* SH 5
GND
LV-TCMP SH 3
SH 3,4,5
12
13 11
U10D
74HC32
11 10
U8E
74HC04
PH2*
COP-RESET*
A8
LV-TCMP
9
10 8
U10C
74HC32
D
2
CLK
3
Q 5
Q 6
P
R
4
C
L
1
U9A
74HC74
9
8
U8D
74HC04
VCC
E-EM
LV-OSC1
EMCU D
12
CLK
11
Q 9
Q 8
P
R
1
0
C
L
1
3
U9B
74HC74
LV-LIR*
VCC
VCC
GND
GND
PH2*
MCU16
MCU15
MCU17
MCU18
MCU19
MCU13
MCU12
MCU11
MCUAD6
MCUAD5
MCUAD4
MCUAD3
MCUAD2
MCUAD1
MCUAD0
LIR/A10
TCMP/A12
A8/A9
RW/A11
LV-EMCU
LV-OSC1
IRQ*
TCAP
LV-OSC1
SH 7
OSC1
OSC2
SH 5
SH 5 OSC1
OSC2
PH2
E-EM
OSC2
VCC
PH2
SH 4
E-EM
SH 3,4
M68EML05P6A Schematics (Sheet 2 of 7)
M68EML05P6AUM/D — Rev. 1.0
38 Schematics MOTOROLA
Schematics
Schematics
M68EML05P6A Schematics
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Schematics 39
M68EML05P6A Schematics (Sheet 3 of 7)
Date: October 22, 1996 Sheet 3 of 7
Size Document Number REV
B 63BSE90895W 3
Title M68EML05P6A EMULATION MODULE
CSIC DEVELOPMENT TOOLS
LOCKOUT* LOCKOUT*
LOCKOUT
SH 5
TCAP
PD7/TCAP
LV-OSC2
LV-OSC2
PD7/TCAP
LV-TCMP
LV-TCMP
TGT-PD5 TGT-PD5
SH 2,4,6
SH 2
SH 7
SH 2
SH 7
SH 4,7
R7
10K
GND-1
TARGET CONNECTOR
13 12
U8F
74HC04
4 3
5
U15B
74HC4066
CONNECTOR #2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
DAUGHTER BOARD
MMDS-RESET*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P2A
CON_DIN96
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P2B
CON_DIN96
(RESET-IN)
LOCKOUT*
T-RST*
(PORTS*)
VCC-1GND-1
VCC-1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
P2C
CON_DIN96
PFB PRU NOT USED
USE THE ADPRU CHIP ON EM
VCC-1 GND-1
GND-1
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
MMDSID
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
MCU EMULATED SET
SW
00
01
10
11 $01FP1A
P6A
P9A
PE0 $01C
$01D
$01E
12
43
SW1
SW_DIP2
VCC-1
GND-1
GND-1
GND-1
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
EVDD
COP-RESET*
(PRU-D*)
(VPRU)
VCC-1
GND-1
GND-1
EVDD
(PB6)
(PB7)
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J2
HDR220
MCU13
(PB5)
TGT-PC3
TGT-PC2
TGT-PC1
TGT-PC0
TGT-PC4
TGT-PC5
TGT-PC6
TGT-PC7
TGT-PA5
TGT-PA4
TGT-PA3
TGT-PA0
TGT-PA1
TGT-PA2
TGT-PA6
MCU11
MCU12
TGT-PA7
TGT-PD5
PD7/TCAP
TOSC1
MCU16
MCU17
MCU18
MCU19
LV-OSC2 T-IRQ*
LV-TCMP
SH 6
TOSC1 TGT-OSC SH 5
T-RESET* T-RESET* SH 5
TGT-PA[0..7]
TGT-PA[0..7]
MCU15
SH 5,7
T-IRQ*
VOLTAGE REF
1
2 3
W1
HDR103
TGT-PC[0..7]
TGT-PC[0..7]
MCU[1..28] MCU[1..28] SH 2
SH 6,7
PH2 PH2
LV-SCLK*
GND
SH 7
SH 2
LV-SCLK30* SH 7
VCC
1
A0
3
A1
5
A2
7
A3
9
A4
11
A5
14
Y0 2
Y1 4
Y2 6
Y3 10
Y4 12
Y5 15
GND 8
U7
LV_74HC4049
LIR/A10
LV-LIR* SH 2
SH 2
LVDD-1
LA1
LA2
LA3
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
C1
C2
C3
C4
C5
C6
C7
C8
C9
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
LA4
C10
C11
C12
C13
C14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P1A
CON_DIN96
(LA14)
(LA13)
GND
GND
GND-1 GND-1
LVDD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD[0..7]
LIR*
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
SCLK
SCLK*
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P1B
CON_DIN96
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
P1C
CON_DIN96
MMDS-RESET*
COP-RESET*
LRW
SH 2
SH 2
SH 2
SH 2
LIR*
AD[0..7]
SCLK
SCLK*
SH 5 MMDS-RESET*
COP-RESET*
SH 5
T-RST*
SH 6
LRW
SH 2,5,6
INTERNAL*
SWITCH
INTERNAL*
SWITCH
SH 4
SH 4
SH 2
CONNECTOR #1
DAUGHTER BOARD
INTERNAL*
SWITCH
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
(U/M)
(WE*)
(OE*)
VCC-1
GND-1
LA0 LA[0..14]
CHRGPMP
MMDSIRQ*
MMDSOSC
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
(ABT)
SCLK-30
VCC-1
GND-1
GND-1
SH 5
LA[0..14]
CHRGPMP
MMDSOSC
MMDSIRQ* SH 6
SH 2
SH 1,4
M68EML05P6AUM/D — Rev. 1.0
40 Schematics MOTOROLA
Schematics
Schematics
M68EML05P6A Schematics
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Schematics 41
Date: October 22, 1996 Sheet 4 of 7
Size Document Number REV
B 63BSE90895W 3
Title M68EML05P6A EMULATION MODULE
CSIC DEVELOPMENT TOOLS
1
2
RN5A
RES_ISO5I_1K
CR2
1N5817
LVDD-1
Q6
2N4403
IRQ SRC
(NORMAL)
(VIN) 3 4
RN4B
RES_ISO5I_10K
IRQ VOLTAGE CONTROL
1 2
3
W4
HDR103
9
1
0
RN4E
RES_ISO5I_10K
7
8
RN4D
RES_ISO5I_10K
Q9
2N4403
7
8
RN5D
RES_ISO5I_1K
5
6
RN5C
RES_ISO5I_1K
Q10
2N4401
VCC-1
GND-1 GND-1
CHRGPMP
SH 3
1
2
P3
PWRTERM2
GND-1
V-IN
SH 3 LOCKOUT
EM-IRQ
SH 6
Q8
2N4401
9
1
0
RN5E
RES_ISO5I_1K
IRQ LEVEL
(NORMAL) 1 2
RN4A
RES_ISO5I_10K
(2xVDD)
VCC
1 2
3
W3
HDR103
SH 2
IRQ*
5 6
RN4C
RES_ISO5I_10K
Q7
2N4401
GND-1
GND-1
LA[0..14]
LA[0..14]
DECODE TABLE
SH 2
TST-RNG SH 2
WR-DDRA $0004*/LRW*/PH2*/E
WR-DDRC $0006*/LRW*/PH2*/E
WR-DDRD* $0007*/LRW*/PH2*/E
ADPRU-CS $00,02,03,04,06,07
((/PH2*/LRW)+PH2))
LOCKOUT*(/INTERNAL +DATAOUT-EN*
DATAIN-EN* /INTERNAL
LOCKOUT*(/PH2*LRW*
$0000-$001F
$0050
$0080-$00FF
INTERNAL*
SWITCH
TEST RANGE
LA0
LA1
LA2
LA3
LA6
LA7
LA8
LA9
LA10
LA11
VCCVCC
PH2
TST-RNG
DECODE
LRW
VDD
22
IO0
2
IO1
3
IO2
4
IO3
5
IO4
6
IO5
7
IO6
8
IO7
9
I0
10
I1
11
CLK0/I2
13
IO8
14
IO9
15
IO10
16
IO11
17
IO12
18
IO13
19
IO14
20
IO15
21
VSS
1
VSS
12
VDD 44
IO31 43
IO30 42
IO29 41
IO28 40
IO27 39
IO26 38
IO25 37
IO24 36
CLK1/I5 35
I4 33
I3 32
IO23 31
IO22 30
IO21 29
IO20 28
IO19 27
IO18 26
IO17 25
IO16 24
VSS 23
VSS 34
XU12
MACH110-20JC
INTERNAL*
SWITCH
BUF-LA0
BUF-LA1
BUF-LA2
ADPRU-CS
WR-DDRD*
WR-DDRA*
WR-DDRC*
SWITCH
INTERNAL*
SH 3
SH 2
SH 3
PH2
SH 2 LRW
BUF-LA[0..2] BUF-LA[0..2]
ADPRU-CS
WR-DDRD*
SH 7
SH 6
SH 6
SH 7
WR-DDRA*
WR-DDRC*
SH 7
LA4
LA5
LA12
LOCKOUT*
GND GND
DATAOUT-EN*
DATAIN-EN*
E-EM
LOCKOUT* SH 3
SH 2
E-EM
DATAOUT-EN*
DATAIN-EN* SH 5
SH 5
BUF-LA0 LA0
BUF-LA1 LA1
BUF-LA2 LA2
M68EML05P6A Schematics (Sheet 4 of 7)
M68EML05P6AUM/D — Rev. 1.0
42 Schematics MOTOROLA
Schematics
Schematics
M68EML05P6A Schematics
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Schematics 43
Date: October 22, 1996 Sheet 5 of 7
Size Document Number REV
B 63BSE90895W 3
Title M68EML05P6A EMULATION MODULE
CSIC DEVELOPMENT TOOLS
AD[0..7]
AD[0..7] SH 2,3,6
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VCC
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
14
B0 27
B1 26
B2 25
B3 24
B4 23
B5 22
B6 21
B7 20
LVDD
1 VDD 28
A_OE
10
B_OE
19
NC
11
IN0 18
OUT0
12
IN1
13 OUT1 17
OUT2 16
IN2
15
U3
LV_BUFFER
LVDD-1
MCUAD[0..7]
MCUAD7
MCUAD6
MCUAD5
MCUAD4
MCUAD3
MCUAD2
MCUAD1
MCUAD0
ADDRESS/DATA BUS LEVEL CONVERSION
R5
4.7K
VCC-1
MCUAD[0..7]
COP-RESET*
MCU-RESET*
SH 2,3
SH 2
SH 2
DATAOUT-EN*
DATAIN-EN*
DATAOUT-EN*
SH 4
SH 4
5
6
RN1C
RES_ISO5I_10K
EM RESET CIRCUIT
DATAIN-EN*
LVDD-1
MMDS-RESET*
SH 3
R10
USER_DEFINED_RES
Y1
USER_DEFINED_XTL
1 2
U14A
74HCU04
3 4
U14B
74HCU04
VCC-1
7 8
RN1D
RES_ISO5I_10K
Q5
2N4401
LV-EMCU
1 2
U8A
74HC04
Q1
2N4401
GND-1
R2
10K
GND
EMCU
OSC1
OSC2
3 4
U8B
74HC04
IN-OSC
LV-EMCU
EMCU
OSC2 OSC2
SH 2
OSC1 SH 2
SH 2,3
MACH-PA[0..7]
LV-OSC2
LV-OSC2
SH 2
SH 3
SH 6
R3
100
VCC
MACH-PA0
MACH-PA1
MACH-PA2
MACH-PA3
MACH-PA[0..7]----->
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
14
B0 27
B1 26
B2 25
B3 24
B4 23
B5 22
B6 21
B7 20
LVDD
1 VDD 28
A_OE
10
B_OE
19
NC
11
IN0 18
OUT0
12
IN1
13 OUT1 17
OUT2 16
IN2
15
U16
LV_BUFFER
PORT A CONVERSION
LVDD-1
VCC
GND
CLK SRC
PULL-PA0
PULL-PA1
PULL-PA2
PULL-PA3
NC
1 VCC 14
OUT 8
GND
7
XY2
4MHZ_FS 1 2
3 4
5 6
7 8
W2
HDR204
MMDSOSC
SH 3 TGT-OSC
SH 3
C21
USER_DEFINED_CAP C22
USER_DEFINED_CAP
R9
USER_DEFINED_RES
GND-1 GND-1
TGT-PA[0..7]
TGT-PA0
TGT-PA1
TGT-PA2
TGT-PA3
TGT-PA4
TGT-PA5
TGT-PA6
TGT-PA7
TGT-PA[0..7]
PRU-PC[0..1]
SH 3,7
PRU-PC[0..1]
SH 6,7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SW2
SW_DIP8
PORT A
MASK OPTION
PULLUPS/INTS
PRU-PC1
PRU-PC0
PULL-PA4
PULL-PA5
PULL-PA6
PULL-PA7
GND
VCC
GND
LVDD-1
2
3
4
5
6
7
8
9
10
1
RN6
RES_BUS9_220K
MACH-PC1
MACH-PC0*
MACH-PA4
MACH-PA5
MACH-PA6
MACH-PA7
MACH-PC1
MACH-PC0*
LRW LRW
LV-LRW
LV-LRW
SH 2
SH 6
SH 6
SH 7
M68EML05P6A Schematics (Sheet 5 of 7)
M68EML05P6AUM/D — Rev. 1.0
44 Schematics MOTOROLA
Schematics
Schematics
M68EML05P6A Schematics
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Schematics 45
Date: October 22, 1996 Sheet 6 of 7
Size Document Number REV
B 63BSE90895W 3
Title M68EML05P6A EMULATION MODULE
CSIC DEVELOPMENT TOOLS
SH 5
AD[0..7]
MACH-PA[0..7]
MACH-PA[0..7]
SH 2,3,5
AD[0..7]
VCCVCC
MACH-PA0
MACH-PA1
MACH-PA2
MACH-PA3
VDD
22
IO0
2
IO1
3
IO2
4
IO3
5
IO4
6
IO5
7
IO6
8
IO7
9
I0
10
I1
11
CLK0/I2
13
IO8
14
IO9
15
IO10
16
IO11
17
IO12
18
IO13
19
IO14
20
IO15
21
VSS
1
VSS
12
VDD 44
IO31 43
IO30 42
IO29 41
IO28 40
IO27 39
IO26 38
IO25 37
IO24 36
CLK1/I5 35
I4 33
I3 32
IO23 31
IO22 30
IO21 29
IO20 28
IO19 27
IO18 26
IO17 25
IO16 24
VSS 23
VSS 34
XU13
MACH210-20JC
PORT A INTERRUPT LOGIC
HI-PC0
TGT-PC0
HI-PC0
MACH-PA7
MMDSIRQ*
HV-TIRQ*
9
1
0
RN1E
RES_ISO5I_10K
VCC-1
MMDSIRQ*
SH 3
SH 3 LOCKOUT*
SH 3
SH 4
T-IRQ* Q3
2N4401
1
2
RN1A
RES_ISO5I_10K
3
4
RN1B
RES_ISO5I_10K
LVDD-1
LVDD
WR-DDRC*
CURRENT SINK
PC0:1 HIGH
AND SOURCE
TGT-PC[0..7] TGT-PC[0..7]
8
9
6
U15C
74HC4066
R8
100
SH 3
AD0
TGT-PC0
TGT-PC1
DDRC0
DDRC1
TGT-PC1
HI-PC1
HI-PC1
EM-IRQ
LOCKOUT*
1
1
1
0
12
U15D
74HC4066
R6
100
LVDD
WR-DDRC* AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND GND
MACH-PC1
MACH-PA4
MACH-PA5
MACH-PA6
MACH-PC0*
WR-DDRA*
SH 4
EM-IRQ
MACH-PC0*
MACH-PC1 SH 5SH 5
SH 5
SH 4
WR-DDRA*
CR1
1N5817
3
4
RN2B
RES_ISO5I_10K
LVDD-1
1
2
RN2A
RES_ISO5I_10K
TGT-RESET LEVEL CONVERSION
7
8
RN2D
RES_ISO5I_10K
9
1
0
RN2E
RES_ISO5I_10K
VCC-1
VCC-1
5
6
RN2C
RES_ISO5I_10K
T-RST*
TO/FROM MMDS
T-RST*
SH 3
Q4
2N4401
DDRC1
DDRC0
X0
12
X1
13
Y0
2
Y1
1
Z0
5
Z1
3
INH
6
A
11
B
10
C
9
X14
Y15
Z 4
VEE 7
U11
74HC4053
Q2
2N4401
PRU-PC1
PRU-PC0
GND-1 GND-1
T-RESET* SH 3
TO/FROM TARGET
PRU-PC[0..1]
PRU-PC[0..1] SH 5,7
M68EML05P6A Schematics (Sheet 6 of 7)
M68EML05P6AUM/D — Rev. 1.0
46 Schematics MOTOROLA
Schematics
Schematics
M68EML05P6A Schematics
M68EML05P6AUM/D — Rev. 1.0
MOTOROLA Schematics 47
Date: October 22, 1996 Sheet 7 of 7
Size Document Number REV
B 63BSE90895W 3
Title M68EML05P6A EMULATION MODULE
CSIC DEVELOPMENT TOOLS
TGT-PA[0..7] SH 3,5
TGT-PA0
TGT-PA1
TGT-PA2
TGT-PA3
TGT-PA4
TGT-PA5
TGT-PA[0..7]
LVDD
MCUAD0
BUF-LA0
BUF-LA1
BUF-LA2
AB0
5
AB1
6
AB2
7
AB3
8
AB4
9
DB0
63
DB1
64
DB2
65
DB3
66
DB4
67
DB5
68
DB6
1
DB7
2
RW
13
XCLK
10
T12
14
T12_DELAY
15
TEST
62
RST
61
CS1
11
CS2
12
IIREQCPU
4
IIREQDMA
3
STOP
16
WAIT
17
ADSIGI
52
VREFH
36
VREFL
37
VDD 19
PA0/ATD0 20
PA1/ATD1 21
PA2/ATD2 22
PA3/ATD3 23
PA4/ATD4 24
PA5/ATD5 25
PA6/ATD6 26
PA7/ATD7 27
PB0/ATD8 28
PB1/ATD9 29
PB2/ATD10 30
PB3/ATD11 31
PB4/ATD12 32
PB5/ATD13 33
PB6/ATD14 34
PB7/ATD15 35
PC0/ATD16 44
PC1/ATD17 45
PC2/ATD18 46
PC3/ATD19 47
PC4/ATD20 48
PC5/ATD21 49
PC6/ATD22 50
PC7/ATD23 51
PD0/ATD24 53
PD1/ATD25 54
PD2/ATD26 55
PD3 56
PD4 57
PD5 58
PD6 59
PD7 60
VDDA 39
VDDAREF 38
VSSA 40
VSS 18
NC
42
NC
43
CLRFLGEN
41
XU17
MC68HC08ADRUFN68
A/D PORT REPLACEMENT
GND
MCUAD7
MCUAD[0..7]
MCUAD[0..7]
BUF-LA[0..2] BUF-LA[0..2]
SH 4
SH 2,5
1 2
1
3
U15A
74HC4066
LV-LRW LV-LRW
WR-DDRD*
WR-DDRD*
ADPRU-CS
ADPRU-CS
SH 4
SH 7
LOCKOUT
LOCKOUT
SH 3
LV-SCLK*
LV-SCLK30*
LV-SCLK*
LV-SCLK30*
SH 3
SH 3
LV-OSC1
LV-OSC1
SH 2
CR3
1N5817
MCUAD1
MCUAD2
MCUAD3
MCUAD4
MCUAD5
MCUAD6
GND
TGT-PA6
TGT-PA7
TGT-PC2
TGT-PC3
TGT-PC4
TGT-PC5
TGT-PC6
TGT-PC7
PRU-PC0
PRU-PC1
TGT-PC[0..7]
PRU-PC[0..1]
3
4RN5B
RES_ISO5I_1K
GND-1
LVDD-1
TGT-PC[0..7]
PRU-PC[0..1] SH 5,6
SH 3,6
PD7/TCAP
TGT-PD5 SH 3
SH 3
1
0
RN3I
GND
TGT-PD5
PD7/TCAP
6
RN3E
RES_BUS9I_L_10K
9
RN3H
8
RN3G
7
RN3F
LVDD
GND
GND-1
LVDD
SH 4
M68EML05P6A Schematics (Sheet 7 of 7)
M68EML05P6AUM/D — Rev. 1.0
48 Schematics MOTOROLA
Schematics
M68EML05P6AUM/D
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