R5F35M66KFB - Renesas Electronics

M16C/5M Group, M16C/57 Group

RENESAS MCU R01DS0019EJ0110

Rev.1.10

Sep 01, 2011

Datasheet

R01DS0019EJ0110 Rev.1.10 Page 1 of 156

Sep 01, 2011

1. Overview

1.1 Features

The M16C/5M and M16C/57 Group’s microcomputers (MCUs) are single-chip control units that utilize

high-performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5M

Group and M16C/57 Group are available in 64-pin, 80-pin, and 100-pin plastic molded LQFP packages.

The MCUs employ sophisticated instructions for a high level of efficiency and they are capable of

executing instructions at high speed.

The MCUs have th e CAN module (M16 C/5M Group) and L IN module, which makes th em suitable for

automotive control and factory automation LAN systems. In addition, the CPU core boast s a multiplier and

DMAC for high-speed operation processing which makes it adequate for controlling office equipment,

home appliances, and industrial equipment.

The M16C/5M and M16C/57 Group’s MCUs are a high-end microcontroller series in the M1 6C/5L and

M16C/56 Group, featuring a single architecture as well as compatible pin assignments and peripheral

functions. They have an on-chip E2PRO M emulation data flash (E2dataFlash) which is a data flash with

serial E2PROM.

1.1.1 Applications

Automotive, car audio, factory automation LAN system, etc.

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Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

1.2 Specifications

Table 1.1 to Table 1.6 list specifications of the M16C/5M Group, M16C/57 Group.

Table 1.1 Specifications (100-pin Package) (1/2)

Item Function Specification

CPU Central processing unit

M16C/60 Series CPU Core (Multiplier: 16 × 16  32 bits, Multiply-accumulate

unit: 16 × 16 + 32  32 bits ))

•Basic instructions: 91

•Minimum instruction execution time:

•Operating mode: Single-chip mode

Memory ROM, RAM, data flash,

E2dataFlash See Table 1.7 to Table 1. 10 .

Voltage

Detection Voltage detector •2 voltage detect points

Clock Clock generator

•5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz on-

chip oscillator, 40 MHz on-chip oscillator)

•Oscillation stop detector: Main clock oscillator stop/restart detection

•Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable

•Low-power consumption modes: Wait mode, stop mode

•Real-time clock

I/O Ports Programmable I/O

ports •70 CMOS inputs/outputs, a pull-up resistor selectable

•N-channel open drain ports: 1

Interrupts •Interrupt vectors: 70

•External interrupt inputs: 13 (NMI, INT × 8, key input × 4)

•Interrupt priority levels: 7

Watchdog Timer •15 bits × 1 (with prescale r)

•Automatic reset start function selectable

•Dedicated 125 kHz on-chip oscillator for the watchdog timer contained

DMA DMAC •4 channels, Cycle-steal transfer mode

•Trigger sources: 50

•Transfer modes: 2 (single transfer, repeat transfer)

Timers

Timer A

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width

modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (two-phase

encoder input) × 3

Programmable output mode × 3

Timer B 16-bit timer × 6

Timer mode, event counter mode, pulse fre quency measurement mode,

pulse-width measurement mode

T imer function for three-

phase motor control Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)

On-chip dead time timer

Timer S (Input capture/

output compare) •16-bit timer × 1 (base timer)

•I/O: 8 channels

Task monitoring timer 16-bit timer × 1 channel

Real-time clock Count: seconds, minutes, hours, weeks

Serial

Interface UART0 to UART4 4 channels (UART, clock synchronous serial interfa c e)

1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)

Multi-master I2C-bus Interface 1 channel

A/D Converter 10-bit resolution × 26 channels

D/A Converter 8-bit resolution × 1 chann el

R01DS0019EJ0110 Rev.1.10 Page 3 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Note:

1. Refer to Table 1. 7 “ M1 6 C/5 M Gro u p Pro d uc t Lis t (J- Ver sio n)” to Table 1.10 “M16 C/ 57 Gr ou p Pr od u ct

List (K-Version) for Operating Temperature, CAN Module, and E2dataFlash.

Table 1.2 Specifications (100-pin Package) (2/2)

Item Function Specification

CRC Calculator •1 circuit

•CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant

•MSB/LSB selectable

Serial Bus Interface

1 channel

•Clock synchronous serial communication mode

•4-wire bus communication mode

•Programmable character length: 8 to 16 bits

LIN Module 1 channel

CAN Module 32-slot message buffer × 2 channels or 1 channel (M16C/5M Group) (1)

Flash Memor y •Programming and erasure supply voltage: 3.0 to 5.5 V

•Programming and erasure endurance: 1,000 times (program ROM 1,

program ROM 2) /1 0,000 times (data fla sh)

•Program security: ROM code protect, ID code check

E2dataFlash Programming and erasure endurance: 100,000 (1)

Debug Functions On-board flash rewrite function, address match × 4

Operating Frequency/Power Supply

Voltage 32 MHz / 3.0 to 5.5 V

Current Consumption Described in 31. “Electrical Characteristics”

Operating Temperature -40°C to 85°C

-40°C to 125°C (1)

Package 100-pin plastic mold LQFP: PLQP0100KB-A (Previous package code:

100P6Q-A)

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Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Table 1.3 Specifications (80-pin Package) (1/2)

Item Function Specification

CPU Central processing unit

M16C/60 Series CPU Core (Multiplier: 16 × 16  32 bits, Multiply-accumulate

unit: 16 × 16 + 32  32 bits ))

•Basic instructions: 91

•Minimum instruction execution time:

•Operating mode: Single-chip mode

Memory ROM, RAM, data flash,

E2dataFlash See Table 1.7 to Table 1.10.

Voltage

Detection Voltage detector •2 voltage detect points

Clock Clock generator

•5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz on-

chip oscillator, 40 MHz on-chip oscillator)

•Oscillation stop detector: Main clock oscillator stop/restart detection

•Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable

•Low-power consumption modes: Wait mode, stop mode

•Real-time clock

I/O Ports Programmable I/O

ports •70 CMOS inputs/outputs, a pull-up resistor selectable

•N-channel open drain ports: 1

Interrupts •Interrupt vectors: 70

•External interrupt inputs: 11 (NMI, INT × 6, key input × 4)

•Interrupt priority levels: 7

Watchdog Timer •15 bits × 1 (with prescale r)

•Automatic reset start function selectable

•Dedicated 125 kHz on-chip oscillator for the watchdog timer contained

DMA DMAC •4 channels, Cycle-steal transfer mode

•Trigger sources: 43

•Transfer modes: 2 (single transfer, repeat transfer)

Timers

Timer A

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width

modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (two-phase

encoder input) × 3

Programmable output mode × 3

Timer B 16-bit timer × 3

Timer mode, event counter mode, pulse fre quency measurement mode,

pulse-width measurement mode

T imer function for three-

phase motor control Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)

On-chip dead time timer

Timer S (Input capture/

output compare) •16-bit timer × 1 (base timer)

•I/O: 8 channels

Task monitoring timer 16-bit timer × 1 channel

Real-time clock Count: seconds, minutes, hours, weeks

Serial

Interface UART0 to UART4 4 channels (UART, clock synchronous serial interfa c e)

1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)

Multi-master I2C-bus Interface 1 channel

A/D Converter 10-bit resolution × 27 channels

D/A Converter 8-bit resolution × 1 chann el

R01DS0019EJ0110 Rev.1.10 Page 5 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Note:

1. Refer to Table 1. 7 “ M1 6 C/5 M Gro u p Pro d uc t Lis t (J- Ver sio n)” to Table 1.10 “M16 C/ 57 Gr ou p Pr od u ct

List (K-Version) for Operating Temperature, CAN Module, and E2dataFlash.

Table 1.4 Specifications (80-pin Package) (2/2)

Item Function Specification

CRC Calculator •1 circuit

•CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant

•MSB/LSB selectable

Serial Bus Interface

1 channel

•Clock synchronous serial communication mode

•4-wire bus communication mode

•Programmable character length: 8 to 16 bits

LIN Module 1 channel

CAN Module 32-slot message buffer × 2 channels or 1 channel (M16C/5M Group) (1)

Flash Memor y •Programming and erasure supply voltage: 3.0 to 5.5 V

•Programming and erasure endurance: 1,000 times (program ROM 1,

program ROM 2) /1 0,000 times (data fla sh)

•Program security: ROM code protect, ID code check

E2dataFlash Programming and erasure endurance: 100,000 (1)

Debug Functions On-board flash rewrite function, address match × 4

Operating Frequency/Power Supply

Voltage 32 MHz / 3.0 to 5.5 V

Current Consumption Described in 31. “Electrical Characteristics”

Operating Temperature -40°C to 85°C

-40°C to 125°C (1)

Package 80-pin plastic mold LQFP: PLQP0080KB-A (Previous package code: 80P6Q-A)

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Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Table 1.5 Specifications (64-pin Package) (1/2)

Item Function Specification

CPU Central processing unit

M16C/60 Series CPU Core (Multiplier: 16 × 16  32 bits, Multiply-accumulate

unit: 16 × 16 + 32  32 bits ))

•Basic instructions: 91

•Minimum instruction execution time:

•Operating mode: Single-chip mode

Memory ROM, RAM, data flash,

E2dataFlash See Table 1.7 to Table 1.10.

Voltage

Detection Voltage detector •2 voltage detect points

Clock Clock generator

•5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz on-

chip oscillator, 40 MHz on-chip oscillator)

•Oscillation stop detector: Main clock oscillator stop/restart detection

•Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable

•Low-power consumption modes: Wait mode, stop mode

•Real-time clock

I/O Ports Programmable I/O

ports •54 CMOS inputs/outputs, a pull-up resistor selectable

•N-channel open drain ports: 1

Interrupts •Interrupt vectors: 70

•External interrupt inputs: 11 (NMI, INT × 6, key input × 4)

•Interrupt priority levels: 7

Watchdog Timer •15 bits × 1 (with prescale r)

•Automatic reset start function selectable

•Dedicated 125 kHz on-chip oscillator for the watchdog timer contained

DMA DMAC •4 channels, Cycle-steal transfer mode

•Trigger sources: 41

•Transfer modes: 2 (single transfer, repeat transfer)

Timers

Timer A

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width

modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (two-phase

encoder input) × 3

Programmable output mode × 3

Timer B 16-bit timer × 3

Timer mode, event counter mode, pulse fre quency measurement mode,

pulse-width measurement mode

T imer function for three-

phase motor control Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)

On-chip dead time timer

Timer S (Input capture/

output compare) •16-bit timer × 1 (base timer)

•I/O: 8 channels

Task monitoring timer 16-bit timer × 1 channel

Real-time clock Count: seconds, minutes, hours, weeks

Serial

Interface UART0 to UART3 3 channels (UART, clock synchronous serial interfa c e)

1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)

Multi-master I2C-bus Interface 1 channel

A/D Converter 10-bit resolution × 16 channels

D/A Converter 8-bit resolution × 1 chann el

R01DS0019EJ0110 Rev.1.10 Page 7 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Note:

1. Refer to Table 1. 7 “ M1 6 C/5 M Gro u p Pro d uc t Lis t (J- Ver sio n)” to Table 1.10 “M16 C/ 57 Gr ou p Pr od u ct

List (K-Version) for Operating Temperature, CAN Module, and E2dataFlash.

Table 1.6 Specifications (64-pin Package) (2/2)

Item Function Specification

CRC Calculator •1 circuit

•CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant

•MSB/LSB selectable

Serial Bus Interface

1 channel

•Clock synchronous serial communication mode

•4-wire bus communication mode

•Programmable character length: 8 to 16 bits

LIN Module 1 channel

CAN Module 32-slot message buffer × 2 channels or 1 channel (M16C/5M Group) (1)

Flash Memor y •Programming and erasure supply voltage: 3.0 to 5.5 V

•Programming and erasure endurance: 1,000 times (program ROM 1,

program ROM 2) /1 0,000 times (data fla sh)

•Program security: ROM code protect, ID code check

E2dataFlash Programming and erasure endurance: 100,000 (1)

Debug Functions On-board flash rewrite function, address match × 4

Operating Frequency/Power Supply

Voltage 32 MHz / 3.0 to 5.5 V

Current Consumption Described in 31. “Electrical Characteristics”

Operating Temperature -40°C to 85°C

-40°C to 125°C (1)

Package 64-pin plastic mold LQFP: PLQP0064KB-A (Previous package code: 64P6Q-A)

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Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

1.3 Product List

Table 1.7 to Table 1.8 list pr oduct informations. Figure 1.1 shows part numbers, memo ry sizes, and

packages. Figure 1.2 shows marking drawing (top view).

Table 1.7 M16C/5M Group Product List (J-Version) As of September 2011

Part Number ROM Capacity RAM

Capacity CAN Package Name Remarks

Program

ROM 1 Program

ROM 2 Data flash E2dataFlash

R5F35M23JFE

96 KB 16 KB 4 KB

× 2 blocks

4 KB 8 KB

1 channel

PLQP0080KB-A

Operating

Temperature

-40°C to 85°C

R5F35M33JFF PLQP0064KB-A

R5F35M73JFE —– PLQP0080KB-A

R5F35M83JFF PLQP0064KB-A

R5F35M16JFB

128 KB 16 KB 4 KB

× 2 blocks

4 KB

12 KB

PLQP0100KB-A

R5F35M26JFE PLQP0080KB-A

R5F35M36JFF PLQP0064KB-A

R5F35M66JFB —– PLQP0100KB-A

R5F35M76JFE PLQP0080KB-A

R5F35M86JFF PLQP0064KB-A

R5F35M1EJFB

256 KB 16 KB 4 KB

× 2 blocks

4 KB

20 KB

PLQP0100KB-A

R5F35M2EJFE PLQP0080KB-A

R5F35M3EJFF PLQP0064KB-A

R5F35M6EJFB —– PLQP0100KB-A

R5F35M7EJFE PLQP0080KB-A

R5F35M8EJFF PLQP0064KB-A

R5F35MB3JFE

96 KB 16 KB 4 KB

× 2 blocks

4 KB 8 KB

2 channels

PLQP0080KB-A

R5F35MC3JFF PLQP0064KB-A

R5F35ME3JFE —– PLQP0080KB-A

R5F35MF3JFF PLQP0064KB-A

R5F35MA6JFB

128 KB 16 KB 4 KB

× 2 blocks

4 KB

12 KB

PLQP0100KB-A

R5F35MB6JFE PLQP0080KB-A

R5F35MC6JFF PLQP0064KB-A

R5F35MD6JFB —– PLQP0100KB-A

R5F35ME6JFE PLQP0080KB-A

R5F35MF6JFF PLQP0064KB-A

R5F35MAEJFB

256 KB 16 KB 4 KB

× 2 blocks

4 KB

20 KB

PLQP0100KB-A

R5F35MBEJFE PLQP0080KB-A

R5F35MCEJFF PLQP0064KB-A

R5F35MDEJFB —– PLQP0100KB-A

R5F35MEEJFE PLQP0080KB-A

R5F35MFEJFF PLQP0064KB-A

(D): Under development

(P): Under planning

The old package names are as follows:

PLQP00100KB-A: 100P6Q-A

PLQP0080KB-A: 80P6Q-A

PLQP0064KB-A: 64P6Q-A

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M16C/5M Group, M16C/57 Group 1. Overview

Table 1.8 M16C/5M Group Product List (K-Version) As of September 2011

Part Number ROM Capacity RAM

Capacity CAN Package Name Remarks

Program

ROM 1 Program

ROM 2 Data flash E2dataFlash

R5F35M23KFE

96 KB 16 KB 4 KB

× 2 blocks

4 KB 8 KB

1 channel

PLQP0080KB-A

Operating

Temperature

-40°C to 125°C

R5F35M33KFF PLQP0064KB-A

R5F35M73KFE —– PLQP0080KB-A

R5F35M83KFF PLQP0064KB-A

R5F35M16KFB

128 KB 16 KB 4 KB

× 2 blocks

4 KB

12 KB

PLQP0100KB-A

R5F35M26KFE PLQP0080KB-A

R5F35M36KFF PLQP0064KB-A

R5F35M66KFB —– PLQP0100KB-A

R5F35M76KFE PLQP0080KB-A

R5F35M86KFF PLQP0064KB-A

R5F35M1EKFB

256 KB 16 KB 4 KB

× 2 blocks

4 KB

20 KB

PLQP0100KB-A

R5F35M2EKFE PLQP0080KB-A

R5F35M3EKFF PLQP0064KB-A

R5F35M6EKFB —– PLQP0100KB-A

R5F35M7EKFE PLQP0080KB-A

R5F35M8EKFF PLQP0064KB-A

R5F35MB3KFE

96 KB 16 KB 4 KB

× 2 blocks

4 KB 8 KB

2 channels

PLQP0080KB-A

R5F35MC3KFF PLQP0064KB-A

R5F35ME3KFE —– PLQP0080KB-A

R5F35MF3KFF PLQP0064KB-A

R5F35MA6KFB

128 KB 16 KB 4 KB

× 2 blocks

4 KB

12 KB

PLQP0100KB-A

R5F35MB6KFE PLQP0080KB-A

R5F35MC6KFF PLQP0064KB-A

R5F35MD6KFB —– PLQP0100KB-A

R5F35ME6KFE PLQP0080KB-A

R5F35MF6KFF PLQP0064KB-A

R5F35MAEKFB

256 KB 16 KB 4 KB

× 2 blocks

4 KB

20 KB

PLQP0100KB-A

R5F35MBEKFE PLQP0080KB-A

R5F35MCEKFF PLQP0064KB-A

R5F35MDEKFB —– PLQP0100KB-A

R5F35MEEKFE PLQP0080KB-A

R5F35MFEKFF PLQP0064KB-A

(D): Under development

(P): Under planning

The old package names are as follows:

PLQP00100KB-A: 100P6Q-A

PLQP0080KB-A: 80P6Q-A

PLQP0064KB-A: 64P6Q-A

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M16C/5M Group, M16C/57 Group 1. Overview

Table 1.9 M16C/57 Group Product List (J-Version) As of September 2011

Part Number ROM Capacity RAM

Capacity CAN Package Name Remarks

Program

ROM 1 Program

ROM 2 Data flash E2dataFlash

R5F35723JFE

96 KB 16 KB 4 KB

× 2 blocks

4 KB 8 KB

N/A

PLQP0080KB-A

Operating

Temperature

-40°C to 85°C

R5F35733JFF PLQP0064KB-A

R5F35773JFE —– PLQP0080KB-A

R5F35783JFF PLQP0064KB-A

R5F35716JFB

128 KB 16 KB 4 KB

× 2 blocks

4 KB

12 KB

PLQP0100KB-A

R5F35726JFE PLQP0080KB-A

R5F35736JFF PLQP0064KB-A

R5F35766JFB —– PLQP0100KB-A

R5F35776JFE PLQP0080KB-A

R5F35786JFF PLQP0064KB-A

R5F3571EJFB

256 KB 16 KB 4 KB

× 2 blocks

4 KB

20 KB

PLQP0100KB-A

R5F3572EJFE PLQP0080KB-A

R5F3573EJFF PLQP0064KB-A

R5F3576EJFB —– PLQP0100KB-A

R5F3577EJFE PLQP0080KB-A

R5F3578EJFF PLQP0064KB-A

(D): Under development

(P): Under planning

The old package names are as follows:

PLQP00100KB-A: 100P6Q-A

PLQP0080KB-A: 80P6Q-A

PLQP0064KB-A: 64P6Q-A

Table 1.10 M16C/57 Group Product List (K-Version) As of September 2011

Part Number ROM Capacity RAM

Capacity CAN Package Name Remarks

Program

ROM 1 Program

ROM 2 Data flash E2dataFlash

R5F35723KFE

96 KB 16 KB 4 KB

× 2 blocks

4 KB 8 KB

N/A

PLQP0080KB-A

Operating

Temperature

-40°C to 125°C

R5F35733KFF PLQP0064KB-A

R5F35773KFE —– PLQP0080KB-A

R5F35783KFF PLQP0064KB-A

R5F35716KFB

128 KB 16 KB 4 KB

× 2 blocks

4 KB

12 KB

PLQP0100KB-A

R5F35726KFE PLQP0080KB-A

R5F35736KFF PLQP0064KB-A

R5F35766KFB —– PLQP0100KB-A

R5F35776KFE PLQP0080KB-A

R5F35786KFF PLQP0064KB-A

R5F3571EKFB

256 KB 16 KB 4 KB

× 2 blocks

4 KB

20 KB

PLQP0100KB-A

R5F3572EKFE PLQP0080KB-A

R5F3573EKFF PLQP0064KB-A

R5F3576EKFB —– PLQP0100KB-A

R5F3577EKFE PLQP0080KB-A

R5F3578EKFF PLQP0064KB-A

(D): Under development

(P): Under planning

The old package names are as follows:

PLQP00100KB-A: 100P6Q-A

PLQP0080KB-A: 80P6Q-A

PLQP0064KB-A: 64P6Q-A

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M16C/5M Group, M16C/57 Group 1. Overview

Figure 1.1 Part Number, Memory Size, and Package

Figure 1.2 Marking Diagram of Flash Memory Version (Top View)

MCU Part No. R 5 F 3 5M 2 E J FE Package type

FB: PLQP0100KB-A (100P6Q-A)

FE: PLQP0080KB-A (80P6Q-A)

FF: PLQP0064KB-A (64P6Q-A)

Property code

J: Operating tempera ture -40°C to 85°C

K: Operatin g temperature -40°C to 125°C

Memory type

F: Flash memory

Group Name

5M: M16C/5M Group,

57: M16C/57 Group

16-bit MCU

Pin / CAN module / E2 data flash capacity

1: 100 pins / 1 channel / 4 KB

2: 80 pins / 1 channel / 4 KB

3: 64 pins / 1 channel / 4 KB

6: 100 pins / 1 channel / —

7: 80 pins / 1 channel / —

8: 64 pins / 1 channel / —

A: 100 pins / 2 channels / 4 KB

B: 80 pins / 2 channels / 4 KB

C: 64 pins / 2 channels / 4 KB

D: 100 pins / 2 channels / —

E: 80 pins / 2 channels / —

F: 64 pins / 2 channels / —

Memory capacity

Program ROM 1/RAM

3: 96 KB/8 KB

6: 128 KB/12 KB

E: 256 KB/20 KB

Renesas MCU

Renesas semiconductor

M16C/57 Group has

no CAN Module

Part number

Seven digit date code

M 1 6 C

R 5 F 3 5 M 2 E J F E

X X X X X X X

Part number

Seven digit date code

M 1 6 C

R 5 F 3 5 M 2 E J F E

X X X X X X X

(See Figure 1.1 “Part Number, Memory Size, and Package”.)

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M16C/5M Group, M16C/57 Group 1. Overview

1.4 Block Diagrams

Figure 1.3 to Figure 1.5 show a block diag ram of M16C/5M Group and M16C/57 Group.

Figure 1.3 100-Pin Block Diagram

Port P0 Port P1 Port P2 Port P3

8 8 8 8

Port P6 Port P 8 Port P9 Port P10

8 8 8 8

Peripherals

Timer (16 bits)

Output (timer A): 5

Input (timer B): 6

Three-phase motor con tro l circuit

Timer S

(Input capture/output compare)

Time measurement: 8 channels

Waveform generating: 8 channels

A/D converter

(10 bits x 26 channels)

UART/clock synchronous serial

interface (5 channels)

Multi-master I2C-bus (1 channel)

Clock generator

XIN-XOUT

XCIN-XCOUT

40 MHz on-chip oscillator

125 kHz on-chip oscillator

PLL frequency synthesizer

CAN module

(32-slot message buffer,

2 or 1 channel)

(M16C/5M Group only) (1)

Watchdog timer (15 bi ts,

with the dedicated 125 kHz on-chip

oscillator for the watchdog timer)

CRC calculator

(CCITT, CRC-16)

DMAC (4 channels)

M16C/60 Series CPU core

INTB

USP

ISP

FLG

R0H R0L

R1H R1L

Memory

ROM (1)

RAM (1)

Multiplier

Note:

1. The ROM size, RAM size, number of channels for the CAN module, and whether the E2dataFlash is provided or not

depend on the MCU type.

Port P7

I/O ports

Task monitoring timer (1 channel)

Real-time clock

LIN module (1 channel)

E2dataFlash (1)

D/A converter (8 bits x 1 circuit)

Serial bus interface

(1 channel)

Port P4 Por t P5

8 8

Power-on reset

Voltage detector

On-chip debugger

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M16C/5M Group, M16C/57 Group 1. Overview

Figure 1.4 80-Pin Block Diagram

Port P0 Port P1 Port P2 Port P3

8 8 8 8

Port P6 Port P8 Port P9 Port P10

8 8 7 8

Peripherals

Timer (16 bits)

Output (timer A): 5

Input (timer B): 3

Three-phase motor con tro l circuit

Timer S

(Input capture/output compare)

Time measurement: 8 channels

Waveform generating: 8 channels

A/D converter

(10 bits x 27 channels)

UART/clock synchronous serial

interface (5 channels)

Multi-master I2C-bus (1 channel)

Clock generator

XIN-XOUT

XCIN-XCOUT

40 MHz on-chip oscillator

125 kHz on-chip oscillator

PLL frequency synthesizer

CAN module

(32-slot message buffer,

2 or 1 channel)

(M16C/5M Group only) (1)

Watchdog timer (15 bits,

with the dedicated 125 kHz on-chip

oscillator for the watchdog timer)

CRC calculator

(CCITT, CRC-16)

DMAC (4 channels)

M16C/60 Series CPU core

INTB

USP

ISP

FLG

R0H R0L

R1H R1L

Memory

ROM (1)

RAM (1)

Multiplier

Port P7

I/O ports

Task monitoring timer (1 channel)

Real-time clock

LIN module (1 channel)

E2dataFlash (1)

D/A converter (8 bits x 1 circuit)

Serial bus interface

(1 channel)

Power-on reset

Voltage detector

On-chip debugger

Note:

1. The ROM size, RAM size, number of channels for the CAN module, and whether the E2dataFlash is provided or not

depend on the MCU type.

R01DS0019EJ0110 Rev.1.10 Page 14 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Figure 1.5 64-Pin Block Diagram

Port P0 Port P1 Port P2 Port P3

4 3 8 4

Port P6 Port P8 Port P9 Port P10

8 8 4 8

Peripherals

Timer (16 bits)

Output (timer A) : 5

Input (timer B): 3

Three-phase motor control circuit

Timer S

(Input capture/output compare)

Time measurement: 8 channels

Waveform generating: 8 channels

A/D converter

(10 bits x 16 channels)

UART/clock synchronous serial

interface (4 channels)

Multi-master I2C-bus (1 channel)

Clock generator

XIN-XOUT

XCIN-XCOUT

40 MHz on-chip oscillator

125 kHz on-chip oscillator

PLL frequency synthesizer

CAN module

(32-slot message buffer,

2 or 1 channel)

(M16C/5M Group only) (1)

Watchdog timer (15 bits,

the dedicated 125 kHz on-chip

oscillator for the watchdog timer)

CRC calculator

(CCITT, CRC-16)

DMAC(4 channels)

M16C/60 Series CPU core

INTB

USP

ISP

FLG

R0H R0L

R1H R1L

Memory

ROM (1)

RAM (1)

Multiplier

Port P7

I/O ports

Task monitoring timer (1 channel)

Real-time clock

Serial bus interface

(1 channel)

LIN module (1 channel)

E2dataFlash (1)

D/A converter (8 bits x 1 circuit)

Power- on reset

Voltage detector

On-chip debugger

Note:

1. The ROM size, RAM size, number of channels for the CAN module, and whether the E2dataFlash is provided or not

depend on the MCU type.

R01DS0019EJ0110 Rev.1.10 Page 15 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

1.5 Pin Assignments

Figure 1.6 shows the pin assignments for the 100-pin package, Figure 1.7 shows the pin assignments for

the 80-pin package, and Figure 1.8 shows the pin assignments for the 64-pin package.

Figure 1.6 Pin Assignments for 100-Pin Package (Top View)

Set bits PACR2 to PACR0 in the PACR register to 100 b before signals are input or ou tput to individual

pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.

100

P0_0 / AN0_0

P0_1 / AN0_1

P0_2 / AN0_2

P0_3 / AN0_3

P0_4 / AN0_4

P0_5 / AN0_5

P0_6 / AN0_6

P0_7 / AN0_7

P1_0 / AN2_0

P1_1 / AN2_1

P1_2 / AN2_2

VREF

AVSS

AVCC

P10_0 / AN_0

P10_1 / AN_1

P10_2 / AN_2

P10_3 / AN_3

P9_5 / CLK4 / CRX0 (1) / AN2_5

P9_ 6 / T X D 4 / C T X 0 (1) / AN2_6

P9_7 / RX D 4 / AN 2 _7

P10_7 / AN_7 / KI3

P10_6 / AN_6 / KI2

P10_5 / AN_5 / KI1

P10_4 / AN_4 / KI0

P1_3 / AN2_3

P1_4

P3_ 1 / RXD3 / SSI0

P3_2 / TXD3 / SSO0

P3_3 / CTS3 / RTS3 / SCS0

P3_4

P3_5

P3_6

P3_7

P4_0

P4_1

VCC

VSS

P4_2

P4_3

P5_6

P5_5

P5_4

P5_3

P5_2

P5_7

P6_3 / TXD0

P6_5 / CLK1

P6_6 / RXD1

P6_7 / TXD1

P6_1 / CLK0

P6_2 / RXD0

P6_0 / RTCOU T / CTS0 / RTS0

P6_4 / CT S1 / RTS1

P5_0

P5_1

P7_2 / C LK 2 / T A 1 OUT / V / RXD 1

P7_1 / RXD2 / SCL2 / CLK1 / TA0IN / TB5IN

P7_0 / TXD2 / SDA2 / CTS1 / RTS1 / TA0OUT

VCC

XIN

XOUT

VSS

RESET

CNVSS

P8_7 / XCIN

P8_6 / XCOUT

P7_4 / TA2OUT / W / LIN0OUT

P9_3/DA0/TB3IN

P9_4 / TB4IN

P9_1 / TB1IN / AN3_1

P9_2 / TB2IN / AN3_2

P8_2 / INT0

P8_3 / INT1

P8_5 / NMI / SD

P9_0 / TB0IN / CLKOUT / AN3_0

P8_4 / INT2 / ZP

P7_5 / TA2IN / W / LIN0IN

P7_3 / CTS2 / RTS2 / TA1IN / V /TXD1

P7_6 / TA3OUT / CTX1 (1)

P7_7 / TA3IN / CRX1 (1)

P8_0 / TA4OUT / U / TSUDA

P8_1 / TA4IN / U / TSUDB

P4_5

P4_4

P3_0 / CLK3 / SSCK0

P2_0 / OUTC1_0 / INPC1_0 / SDAMM

P2_1 / OUTC1_1 / INPC1_1 / SCLMM

P2_2 / OUTC1_2 / INPC1_2

P2_3 / / OUTC1_3 / INPC1_3

P2_4 / INT6 / OUTC1_ 4 / INP C1_ 4

P2_5 / INT7 / OUTC1_ 5 / INP C1_ 5

P2_6 / OUTC1_6 / INPC1_6

P2_7 / OUTC1_7 / INPC1_7

P1_5 / INT3 / IDV / ADTRG

P1_ 6 / INT 4 / IDW

P1_7 / INT5 / IDU / INPC 1 _7

P4_6

P4_7

Note:

1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.

PLQP0100KB-A

(100P6Q-A)

(Top view)

M16C/5M Group

M16C/57 Group

R01DS0019EJ0110 Rev.1.10 Page 16 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Note:

1. There are pins CTX1 and CRX1 only in the M16C/5M Group.

Table 1.11 Pin Names, 100-Pin Package(1/2)

No. Control

Pin Port Interrupt

Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial

Bus Interface Pin

Multi-

master

I2C-bus Pin Analog Pin

1 P9_4 TB4IN

2 P9_3 TB3IN DA0

3 P9_2 TB2IN AN3_2

4 P9_1 TB1IN AN3_1

5 CLKOUT P9_0 TB0IN AN3_0

6NC

7CNVSS

8 XCIN P8_7

9 XCOUT P8_6

10 RESET

11 XOUT

12 VSS

13 XIN

14 VCC

15 P8_5 NMI SD

16 P8_4 INT2 ZP

17 P8_3 INT1

18 P8_2 INT0

19 P8_1 TA4IN/UTSUDB

20 P8_0 TA4OUT/U TSUDA

21 P7_7 TA3IN CRX1(1)

22 P7_6 TA3OUT CTX1 (1)

23 P7_5 TA2IN/WLIN0IN

24 P7_4 TA2OUT/W LIN0OUT

25 P7_3 TA1IN/VCTS2/RTS2/TXD1

26 P7_2 TA1OUT/V CLK2/RXD1

27 P7_1 TA0IN/TB5IN RXD2/SCL2/CLK1

28 P7_0 TA0OUT TXD2/SDA2/CTS1/RTS1

29 P6_7 TXD1

30 P6_6 RXD1

31 P6_5 CLK1

32 P6_4 CTS1/RTS1

33 P6_3 TXD0

34 P6_2 RXD0

35 P6_1 CLK0

36 P6_0 RTCOUT CTS0/RTS0

37 P5_7

38 P5_6

39 P5_5

40 P5_4

41 P5_3

42 P5_2

43 P5_1

44 P5_0

45 P4_7

46 P4_6

47 P4_5

48 P4_4

49 P4_3

50 P4_2

R01DS0019EJ0110 Rev.1.10 Page 17 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Note:

1. Pins CTX0 and CRX0 are only available in the M16C/5M Group.

Table 1.12 Pin Names, 100-Pin Package(2/2)

No. Control

Pin Port Interrupt

Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial

Bus Interface Pin

Multi-

master I2C-

bus Pin Analog Pin

51 P4_1

52 P4_0

53 P3_7

54 P3_6

55 P3_5

56 P3_4

57 P3_3 CTS3/RTS3/SCS0

58 P3_2 TXD3/SSO0

59 P3_1 RXD3/SSI0

60 VCC

61 P3_0 CLK3/SSCK0

62 VSS

63 P2_7 OUTC1_7/INPC1_7

64 P2_6 OUTC1_6/INPC1_6

65 P2_5 INT7 OUTC1_5/INPC1_5

66 P2_4 INT6 OUTC1_4/INPC1_4

67 P2_3 OUTC1_3/INPC1_3

68 P2_2 OUTC1_2/INPC1_2

69 P2_1 OUTC1_1/INPC1_1 SCLMM

70 P2_0 OUTC1_0/INPC1_0 SDAMM

71 P1_7 INT5 IDU INPC1_7

72 P1_6 INT4 IDW

73 P1_5 INT3 IDV ADTRG

74 P1_4

75 P1_3 AN2_3

76 P1_2 AN2_2

77 P1_1 AN2_1

78 P1_0 AN2_0

79 P0_7 AN0_7

80 P0_6 AN0_6

81 P0_5 AN0_5

82 P0_4 AN0_4

83 P0_3 AN0_3

84 P0_2 AN0_2

85 P0_1 AN0_1

86 P0_0 AN0_0

87 P10_7 KI3 AN_7

88 P10_6 KI2 AN_6

89 P10_5 KI1 AN_5

90 P10_4 KI0 AN_4

91 P10_3 AN_3

92 P10_2 AN_2

93 P10_1 AN_1

94 AVSS

95 P10_0 AN_0

96 VREF

97 AVCC

98 P9_7 RXD4 AN2_7

99 P9_6 TXD4/CTX0 (1) AN2_6

100 P9_5 CLK4/CRX0 (1) AN2_5

R01DS0019EJ0110 Rev.1.10 Page 18 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Figure 1.7 Pin Assignment for 80-Pin Package (Top View)

Set bits PACR2 to PACR0 in the PACR register to 011b before signa ls are input or output to individual

pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.

P9_6 / AN2_6 / TXD4 P7_6 / TA3OUT / CTX1 (1)

P7_5 / TA2IN / W / LIN0INP9_7 / AN2_7 / RXD4

AVCC

VREF

P10_0 / AN_0

AVSS

P10_1 / AN_1

P10_2 / AN_2

P10_3 / AN_3

P10_4 / AN_4 / KI0

P10_5 / AN_5 / KI1

P10_6 / AN_6 / KI2

P10_7 / AN_7 / KI3

P0_0 / AN0_0

P0_1 / AN0_1

P0_2 / AN0_2

P0_3 / AN0_3

P0_4 / AN0_4

P0_5 / AN0_5

P0_6 / AN0_6

P7_4 / TA2OUT / W / LIN0OUT

P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1

P7_2 / CLK2 / TA1OUT / V / RXD1

P7_1 / RXD2 / SCL2 / TA0IN / CLK1

P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1

P6_7 / TXD1

P6_6 / RXD1

P6_5 / CLK1

P6_4 / CTS1 / RTS1

P3_7

P3_6

P3_5

P3_4

P3_3 / CTS3 / RTS3 / SCS0

P3_2 / TXD3 / SSO0

P3_1 / RXD3 / SSI0

P3_0 / CLK3 / SSCK0

P6_3 / TXD0

P9_5 / AN 2_5/ CLK4

P9_3 / AN2_4 /CTX0 (1)

P9_2 / AN3_2 / TB2IN / CRX0 (1)

P9_0 / AN3_0 / TB0IN / CLKOUT

CNVSS

P8_7 / XCIN

P8_6 / XCOUT

RESET

XOUT

VSS

P8_4 / INT2 / ZP

P8_3 / INT1

P8_2 / INT0

P8_1 / TA4IN / U/ TSUDB

P8_0 / TA4OUT / U/ TSUDA

P7_7 / TA3IN / CRX1 (1)

P9_1 / AN3_1 / TB1IN / DA0

XIN

VCC

P8_5 / NMI / SD

P0_7 / AN0_7

P1_0 / AN2_0

P1_1 / AN2_1

P1_2 / AN2_2

P1_3 / AN2_3

P1_4

P1_5 / INT3 / ADTRG / IDV

P2_6 / OUTC1_6 / INPC1_6

P6_0 / RTCOUT / CTS0 / RTS0

P6_1 / CLK0

P6_2 / RXD0

P1_6 / INT4 / IDW

P2_7 / OUTC1_7 / INPC1_7

P1_7 / INT5 / INPC1_7 / IDU

P2_0 / OUTC1_0 / INPC1_0 / SDAMM

P2_1 / OUTC1_1 / IN PC1_1 / SCLMM

P2_2 / OUTC1_2 / INPC1_2

P2_3 / OUTC1_3 / INPC1_3

P2_4 / OUTC1_4 / INPC1_4

P2_5 / OUTC1_5 / INPC1_5

1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.

Note:

PLQP0080KB-A

(80P6Q-A)

(Top view)

M16C/5M Group

M16C/57 Group

R01DS0019EJ0110 Rev.1.10 Page 19 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Note:

1. Pins CTX0, CRX0, CTX1 and CRX1 are only available in the M16C/5M Group.

Table 1.13 Pin Names, 80-Pin Package (1/2)

No. Control

pin Port Interrupt

Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial

Bus Interface Pin

Multi-

master

I2C-bus

Analog Pin

1 P9_5 CLK4 AN2_5

2P9_3 CTX0 (1) AN2_4

3P9_2 TB2IN CRX0 (1) AN3_2

4P9_1 TB1IN AN3_1/

DA0

5 CLKOUT P9_0 TB0IN AN3_0

6CNVSS

7 XCIN P8_7

8 XCOUT P8_6

9RESET

10 XOUT

11 VSS

12 XIN

13 VCC

14 P8_5 NMI SD

15 P8_4 INT2 ZP

16 P8_3 INT1

17 P8_2 INT0

18 P8_1 TA4IN/UTSUDB

19 P8_0 TA4OUT/U TSUDA

20 P7_7 TA3IN CRX1 (1)

21 P7_6 TA3OUT CTX1 (1)

22 P7_5 TA2IN/WLIN0IN

23 P7_4 TA2OUT/W LIN0OUT

24 P7_3 TA1IN/VCTS2/RTS2/TXD1

25 P7_2 TA1OUT/V CLK2/RXD1

26 P7_1 TA0IN RXD2/SCL2/CLK1

27 P7_0 TA0OUT TXD2/SDA2/CTS1/RTS1

28 P6_7 TXD1

29 P6_6 RXD1

30 P6_5 CLK1

31 P6_4 CTS1/RTS1

32 P3_7

33 P3_6

34 P3_5

35 P3_4

36 P3_3 CTS3/RTS3/SCS0

37 P3_2 TXD3/SSO0

38 P3_1 RXD3/SSI0

39 P3_0 CLK3/SSCK0

40 P6_3 TXD0

R01DS0019EJ0110 Rev.1.10 Page 20 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Table 1.14 Pin Names, 80-Pin Package (2/2)

No. Control

pin Port Interrupt

Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial

Bus Interface Pin

Multi-

master

I2C-bus

Analog Pin

41 P6_2 RXD0

42 P6_1 CLK0

43 P6_0 RTCOUT CTS0/RTS0

44 P2_7 OUTC1_7/INPC1_7

45 P2_6 OUTC1_6/INPC1_6

46 P2_5 OUTC1_5/INPC1_5

47 P2_4 OUTC1_4/INPC1_4

48 P2_3 OUTC1_3/INPC1_3

49 P2_2 OUTC1_2/INPC1_2

50 P2_1 OUTC1_1/INPC1_1 SCLMM

51 P2_0 OUTC1_0/INPC1_0 SDAMM

52 P1_7 INT5 IDU INPC1_7

53 P1_6 INT4 IDW

54 P1_5 INT3 IDV ADTRG

55 P1_4

56 P1_3 AN2_3

57 P1_2 AN2_2

58 P1_1 AN2_1

59 P1_0 AN2_0

60 P0_7 AN0_7

61 P0_6 AN0_6

62 P0_5 AN0_5

63 P0_4 AN0_4

64 P0_3 AN0_3

65 P0_2 AN0_2

66 P0_1 AN0_1

67 P0_0 AN0_0

68 P10_7 KI3 AN_7

69 P10_6 KI2 AN_6

70 P10_5 KI1 AN_5

71 P10_4 KI0 AN_4

72 P10_3 AN_3

73 P10_2 AN_2

74 P10_1 AN_1

75 AVSS

76 P10_0 AN_0

77 VREF

78 AVCC

79 P9_7 RXD4 AN2_7

80 P9_6 TXD4 AN2_6

R01DS0019EJ0110 Rev.1.10 Page 21 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Figure 1.8 Pin Assignments for 64-Pin Package (Top View)

Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual

pins afte r reset. When the PACR register is not set, signals are not input or output for some of the pins.

P9_2 / AN3_2 / TB2IN / CRX0 (1) P7_7 / TA3IN / CRX1 (1)

P7_6 / TA3OUT / CTX1 (1)

P9_3 / AN2_4 /C TX0 (1)

AVCC

VREF

P10_0 / AN_0

AVSS

P10_1 / AN_1

P10_2 / AN_2

P10_3 / AN_3

P10_4 / AN_4 / KI0

P10_5 / AN_5 / KI1

P10_6 / AN_6 / KI2

P10_7 / AN_7 / KI3

P0_0 / AN0_0

P0_1 / AN0_1

P0_2 / AN0_2

P7_5 / TA2IN / W / LIN0IN

P7_4 / TA2OUT / W / LIN0OUT

P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1

P7_2 / CLK2 / TA1OUT / V / RXD1

P7_1 / RXD2 / SCL2 / TA0IN / CLK1

P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1

P6_7 / TXD1

P6_6 / RXD1

P6_5 / CLK1

P6_4 / RTS1 / CTS1

P3_3 / CTS3 / RTS3 / SCS0

P3_2 / TXD3 / SSO0

P3_1 / RXD3 / SSI0

P3_0 / CLK3 / SSCK0

P9_1 / AN3_1 / TB1IN / DA0

P9_0 / AN3_0 / TB0IN / CLKOUT

CNVSS

P8_6 / XCOUT

RESET

XOUT

VSS

XIN

VCC

P8_5 / NMI / SD

P8_1 / TA4IN / U / TSUDB

P8_0 / TA4OUT / U / TSUDA

P8_7 / XCIN

P8_4 / I NT2 / ZP

P8_3 / INT1

P8_2 / INT0

P0_3 / AN0_3

P1_5 / I NT3 / ADTRG / IDV

P1_6 / I NT4 / IDW

P1_7 / I NT5 / INPC1 _ 7 / IDU

P2_0 / OUTC1_0 / INPC1_0 / SDAMM

P2_1 / OUTC1_1 / INPC1_1 / SCLMM

P2_2 / OUTC1_2 / INPC1_2

P6_3 / TXD0

P2_3 / OUTC1_3 / INPC1_3

P2_4 / OUTC1_4 / INPC1_4

P2_5 / OUTC1_5 / INPC1_5

P2_6 / OUTC1_6 / INPC1_6

P2_7 / OUTC1_7 / INPC1_7

P6_0 / RTCOUT / CTS0 / RTS0

P6_1 / CLK0

P6_2 / RXD0

Note:

1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.

PLQP0064KB-A

(64P6Q-A)

(Top view)

M16C/5M Group

M16C/57 Group

R01DS0019EJ0110 Rev.1.10 Page 22 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Note:

1. Pins CTX1 and CRX1 are only available in the M16C/5M Group.

Table 1.15 Pin Names, 64-Pin Package (1/2)

No. Control

pin Port Interrupt

Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial

Bus Interface Pin

Multi-

master

I2C-bus

Analog Pin

1P9_1 TB1IN AN3_1/

DA0

2 CLKOUT P9_0 TB0IN AN3_0

3CNVSS

4 XCIN P8_7

5 XCOUT P8_6

6RESET

7XOUT

8 VSS

9XIN

10 VCC

11 P8_5 NMI SD

12 P8_4 INT2 ZP

13 P8_3 INT1

14 P8_2 INT0

15 P8_1 TA4IN/UTSUDB

16 P8_0 TA4OUT/U TSUDA

17 P7_7 TA3IN CRX1 (1)

18 P7_6 TA3OUT CTX1 (1)

19 P7_5 TA2IN/WLIN0IN

20 P7_4 TA2OUT/W LIN0OUT

21 P7_3 TA1IN/VCTS2/RTS2/TXD1

22 P7_2 TA1OUT/V CLK2/RXD1

23 P7_1 TA0IN RXD2/SCL2/CLK1

24 P7_0 TA0OUT TXD2/SDA2/CTS1/RTS1

25 P6_7 TXD1

26 P6_6 RXD1

27 P6_5 CLK1

28 P6_4 CTS1/RTS1

29 P3_3 CTS3/RTS3 / SCS0

30 P3_2 TXD3 / SSO0

R01DS0019EJ0110 Rev.1.10 Page 23 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 1. Overview

Note:

1. Pins CTX0 and CRX0 are only available in the M16C/5M Group.

Table 1.16 Pin Names, 64-Pin Package (2/2)

No. Control

pin Port Interrupt

Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial

Bus Interface Pin

Multi-

master

I2C-bus

Analog Pin

31 P3_1 RXD3 / SSI0

32 P3_0 CLK3 / SSCK0

33 P6_3 TXD0

34 P6_2 RXD0

35 P6_1 CLK0

36 P6_0 RTCOUT CTS0/RTS0

37 P2_7 OUTC1_7/INPC1_7

38 P2_6 OUTC1_6/INPC1_6

39 P2_5 OUTC1_5/INPC1_5

40 P2_4 OUTC1_4/INPC1_4

41 P2_3 OUTC1_3/INPC1_3

42 P2_2 OUTC1_2/INPC1_2

43 P2_1 OUTC1_1/INPC1_1 SCLMM

44 P2_0 OUTC1_0/INPC1_0 SDAMM

45 P1_7 INT5 IDU INPC1_7

46 P1_6 INT4 IDW

47 P1_5 INT3 IDV ADTRG

48 P0_3 AN0_3

49 P0_2 AN0_2

50 P0_1 AN0_1

51 P0_0 AN0_0

52 P10_7 KI3 AN_7

53 P10_6 KI2 AN_6

54 P10_5 KI1 AN_5

55 P10_4 KI0 AN_4

56 P10_3 AN_3

57 P10_2 AN_2

58 P10_1 AN_1

59 AVSS

60 P10_0 AN_0

61 VREF

62 AVCC

63 P9_3 CTX0 (1) AN2_4

64 P9_2 TB2IN CRX0 (1) AN3_2

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M16C/5M Group, M16C/57 Group 1. Overview

1.6 Pin Functions

Note:

1. Please contact the manufacturer of crystal/ceramic resonator for oscillation characteristic.

Table 1.17 Pin Functions (64-Pin, 80-Pin, and 100-Pin Packages)

Signal Name Pin Name I/O Description

Power supply VCC, VSS I Apply 3.0 to 5.5 V to the VCC pin and 0 V to the VSS pin.

Analog powe r

supply AVCC,

AVSS IPower supply for the A/D converter and D/A converter. Pins

AVCC and AVSS should be connected to VCC and VSS,

respectively.

Reset input RESET I Driving this pin low resets the MCU.

CNVSS CNVSS I Connect to VSS via a resistor.

Main clock input XIN IInput/output for the main clock oscillator. Connect a ceramic

resonator or crystal oscillator between XIN and XOUT. (1)

To apply an external clock, connect it to XIN and leave XOUT

open. When XIN is not used, connect XIN to VCC pin and leave

XOUT open.

Main clock output XOUT O

Sub clock input XCIN I Input/output for the sub clock oscillator. Connect a crystal

oscillator between XCIN and XCOUT. (1)

Sub clock output XCOUT O

Clock output CLKOUT O This pin outputs the clock having the same frequency as f1, f8 ,

f32, or fC.

INT interrupt input INT0 to INT5 I Input for INT interrupt

NMI input NMI I Input for NMI

Key input interrupt KI0 to KI3 I Input for the key input interrupt

Timer A

TA0OUT to

TA4OUT I/O Timers A0 to A4 input/output

TA0IN to TA4IN I Timers A0 to A4 input

ZP I Input for Z-phase

Timer B TB0IN to TB2IN I Timers B0 to B2 input

Three-phase motor

control timer U,U,V,V,W,WO Output for three-phase motor control timer

IDU, IDW, IDV, SD I Input for three-phase motor control timer

Real-time clock RTCOUT O Output for real-time clock

Serial interface

UART0 to UART 3

CTS0 to CTS3 I Input to control data transmission

RTS0 to RTS3 O Output to control data reception

CLK0 to CLK3 I/O Transfer clock input/output

RXD0 to RXD3 I Serial data input

TXD0 to TXD3 O Serial data output

UART2

I2C mode SDA2 I/O Serial data input/output

SCL2 I/O Transfer clock input/output

Multi-master

I2C-bus SDAMM I/O Serial data input/output

SCLMM Transfer clock input/output

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M16C/5M Group, M16C/57 Group 1. Overview

Note:

1. The CAN module is only in the M16C/5M Group.

Table 1.18 Pin Functions (64-Pin, 80-Pin, and 100-Pin Packages)

Signal Name Pin Name I/O Description

Reference voltage

input VREF I Reference voltage input for the A/D converter and D/A converter.

A/D converter

AN_0 to AN_7

AN0_0 to AN0_3

AN3_0 to AN3_2 I Analog input

ADTRG I Input for an external trigger

Timer S INPC1_0 to INPC1_7 I Input for time measurement function

OUTC1_0 to OUTC1_7 O Output for waveform generating function

TSUDA, TSUDB I Two-phase pulse input

CAN Module (1) CRX0, CRX1 I Receive data input for CAN communication

CTX0, CTX1 O Transmit data output for CAN communication

D/A converter DA0 O Output for the D/A converter

LIN module LIN0OUT O Transmit data output for LIN communication

LIN0IN I Receive data input for LIN communication

Serial bus interface

SSO0 O Serial data output

SSI0 I Serial data input

SSCK0 I/O Input/output for transmit/receive clock

SCS0 I Input to control the serial interface

I/O port

P0_0 to P0_3

P1_5 to P1_7

P2_0 to P2_7

P3_0 to P3_3

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_7

P9_0 to P9_3

P10_0 to P10_7

I/O

CMOS I/O ports. Each port has a corresponding direction

input ports, pull-up resistor is selectable for every unit of 4 bits.

However, P8_5 output is N-channel open drain output and does

not have a pull-up resistor.

Port P8_5 shares the pin with NMI, so that the NMI input level

can be read from the P8 register P8_5 bit.

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M16C/5M Group, M16C/57 Group 1. Overview

Table 1.19 Pin Functions (100-Pin Package Only)

Signal Name Pin Name I/O Description

INT interrupt input INT6 and INT7 I Input for INT interrupt

Timer B TB3IN to TB5IN ITimers B3 to B5 input

I/O port P4_0 to P4_7

P5_0 to P5_7

P9_4 I/O CMOS I/O ports. Each port has a corres ponding direction

input ports, pull-up resistor is selectable for every unit of 4 bits.

Table 1.20 Pin Functions (80-Pin and 64-Pin Package Only)

Signal Name Pin Name I/O Description

A/D converter AN2_4 IAnalog inp ut

Table 1.21 Pin Functions (100-Pin and 80-Pin Package Only)

Signal Name Pin Name I/O Description

Serial Interface

UART4

CLK4 I/O Transfer clock input/output

RXD4 ISerial dat a in p ut

TXD4 OSerial data output

A/D converter AN0_4 to AN0_7

AN2_0 to AN2_3

AN2_5 to AN2_7 IAnalog input

I/O port

P0_4 to P0_7

P1_0 to P1_4

P3_4 to P3_7

P9_5 to P9_7

I/O CMOS I/O ports. Each port has a corres ponding direction

input ports, Pull-up resistor is selectable for every unit of 4 bits.

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M16C/5M Group, M16C/57 Group 2. Central Processing Unit (CPU)

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. Seve n register s (R0, R1 , R2, R3, A0, A1, and F B) out of 13 compose a

Figure 2.1 CPU Registers

R0H (upper bits of R0)

b15 b8b7 b0

INTBH

USP

ISP

Note: 1. These registers compose a register bank. There are two register banks.

CDZSBOIU

IPL

b31

b19

INTBL

b15 b0

INTBH is the 4 upper bits of the INTB register and INTBL

is the 16 lower bits.

b19 b0

b15 b0

FLG

b15 b0

b7b8

Data registers (1)

Address registers (1)

Frame base registers (1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

R1H (upper bits of R1)

R0L (lower bits of R0)

R1L (lower bits of R1)

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M16C/5M Group, M16C/57 Group 2. Central Processing Unit (CPU)

2.1 Data Registers (R0, R1, R2, and R3)

R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can

be split into upper (R0H/ R 1H ) an d lower (R0L/R1L ) bits to be used separately as 8- bit data registers.

R0 can be combined with R2, and R3 can b e combined with R1 and be used as 32-bit data registers

R2R0 and R3R1, respectively.

2.2 Address Registers (A0 and A1)

A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and

logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register that is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.

2.5 Program Counter (PC)

The PC is 20 bits wide and in dicates the address of the next instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The USP and ISP stack pointe rs (SP) are each comprised of 16 bit s. The U flag is used to switch between

USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register used for SB relative addressing.

2.8 Flag Register (FLG)

FLG is an 11-bit register that indicates the CPU state.

2.8.1 Carry Flag (C Flag)

The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

The D flag is for debugging only. Set it to 0.

2.8.3 Zero Flag (Z Flag)

The Z flag becomes 1 when an ar ithmetic operation results in 0. Otherwise, it becomes 0.

2.8.4 Sign Flag (S Flag)

The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes

2.8.5 Register Bank Select Flag (B Flag)

2.8.6 Overflow Flag (O Flag)

The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.

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M16C/5M Group, M16C/57 Group 2. Central Processing Unit (CPU)

2.8.7 Interrupt Enable Flag (I Flag)

The I flag enables maskable interrup ts.

Maskable interrup ts are disabled when the I flag is 0, a nd enabled when it is 1. The I flag becomes 0

when an interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is 0. USP is selected when the U flag is 1.

The U flag becomes 0 when a har dware interrupt re quest is accepted, or the INT instruction of software

interrupt number 0 to 31 is executed.

2.8.9 P rocessor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7.

If a requested interrupt ha s higher priority than IPL, the interrupt request is enabled.

2.8.10 Reserved Areas

Only set these bits to 0. The read value is undefined.

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M16C/5M Group, M16C/57 Group 3. Memory

3. Memory

Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to

0D7FFh. Peripheral function control registers are located here. All blank spaces within SFRs are reserved,

so do not access any blank spaces.

The internal RAM is allocated from addre ss 0040 0h to supe rior direction. For examp le, a 8 KB intern al RAM

is addressed from 00400h to 023FFh. The internal RAM is used not only for data storage but also for stack

area when subroutines are called or when interrupt request are acknowledged.

The internal ROM is flash memory. Four internal ROM areas are available: E2dataFlash, data flash,

program ROM 1, and program ROM 2.

The data flash is ad dressed from 0 E000h to 0FFFFh . Th is dat a fla sh sp ace is used n ot only for dat a storage

but also for program storage.

Program ROM 2 is assigned addresses 10000h to 13FFFh. Program ROM 1 is assigned addresses

FFFFFh to inferior direction. For example, the 64 KB program ROM 1 space has addresses F0000h to

FFFFFh.

The E2dataFlash is not shown in the memory map because the E2FA register value is used as an address.

The E2dat aFlash cannot be used for progr am storage. Whethe r the E2da taFla sh is provided or not de pends

on the produc t.

The special page vectors are assigned addresses FFE00h to FFFD7h. They are used for the JMPS

instruction and JSRS instruction. Refer to the M16C/60, M1 6C/20, M16C/Tiny Series Software Manual for

details.

The fixed vector table for interrupts, ID code write address, OFS1 address and OSF2 address are assigned

addresses FFFDBh to FFFFFh.

The 256 bytes beginning with the start ad dress set in the INTB re gister compose the relo catabl e vector table

for interrupts.

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M16C/5M Group, M16C/57 Group 3. Memory

Figure 3.1 Memory Map

Notes:

1. Do not access these reserved areas.

2. Do not change the data from FFh.

00000h

XXXXXh

0D000h

00400h

0D800h

0E000h

10000h

14000h

YYYYYh

FFFFFh FFFFFh

FFFDBh

FFFD8h

FFE00h

256 bytes beginning with t he start

address set in the INTB register

13FFFh

13FF0h

13000h

Reserved (1)

Internal ROM

(Data flash)

Internal ROM

(Program ROM 2)

SFRs

Internal RAM

Reserved (1)

Internal ROM

(Program ROM 1)

On-chip debugger

monitor area

User boot code area

Relocatable vector table

Special page vector

table

Reserved (2)

Fixed vector table

ID code write address

OFS1 address

OSF2 address

Internal RAM

Capacity XXXXXh

8 KB 023FFh

12 KB 033FFh

20 KB 053FFh

Internal ROM

Capacity YYYYYh

96 KB E8000h

128 KB E0000h

256 KB C0000h

The above assumes the following:

-The PM10 bit in the PM1 register is set to 1 (addresses from 0E000h to 0FFFFh are used as data flash)

-The PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled)

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

4. Special Function Registers (SFRs)

4.1 SFRs

An SFR is a control register for a pe ripheral function.

Notes:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

2. Software reset, watchdog timer reset, oscillator stop detect reset, and voltage monitor 2 reset do not affect the

following registers: registers VCR1 and VCR2.

3. Oscillator stop detect reset does not affect bits CM20, CM21, and CM27.

4. The state of bits in the RSTFR register depends on the reset type.

5. This is the reset value when the LVDAS bit of the OFS1 address is 1 during hardware reset.

6. This is the reset value after voltage monitor 0 reset, power-on reset, or when the LVDAS bit of the OFS1 address is 0

during hardware reset.

Tab le 4. 1 SFR Inform at io n (1) (1)

Address Re g ister Symbo l Reset Value

0000h

0001h

0002h

0003h

0004h Processor Mode Register 0 PM0 00h

0005h Processor Mode Register 1 PM1 0000 1000b

0006h System Clock Control Register 0 CM0 0100 1000b

0007h System Clock Control Register 1 CM1 0010 0000b

0008h

0009h

000Ah Protect Register PRCR 00h

000Bh

000Ch Oscillation Stop Detection Register CM2 0X00 0010b

(3)

000Dh

000Eh

000Fh

0010h Program 2 Area Control Register PRG2C XXXX XX00b

0011h

0012h Peripheral Clock Select Register PCLKR 0000 0011b

0013h

0014h

0015h Clock Prescaler Reset Flag CPSRF 0XXX XXXXb

0016h

0017h

0018h Reset Source Determine Register RSTFR XX0X 001Xb

(hardware reset)

(4)

0019h Voltage Detector 2 Flag Register VCR1 0000 1000b

(2)

001Ah Voltage Detector Operation Enable Register VCR2 000X 0000b

(2, 5)

001X 0000b

(2, 6)

001Bh

001Ch PLL Control Register 0 PLC0 0X01 X010b

001Dh

001Eh Processor Mode Register 2 PM2 XX00 0X01b

001Fh X: Undefined

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Notes:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

2. Hardware reset, power-on reset, voltage monitor 0 reset, or voltage monitor 2 reset.

3. Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 0 reset, and voltage monitor 2 reset

do not affect the following registers or bit: the VW0C register, and bits VW2C2 and VW2C3 in the VW2C register.

4. This is the reset value when the LVDAS bit of the OFS1 address is 1 during hardware reset

5. This is the reset value after voltage monitor 0 reset, power-on reset, or when the LVDAS bit of the OFS1 address is 0

during hardware reset.

6. This is the reset value after hardware reset, power-on reset, or voltage monitor 0 reset

Tab le 4. 2 SFR Inform at io n (2) (1)

Address Register Symbol Reset Value

0020h

0021h

0022h 40 MHz On-Chip Oscillator Control Register 0 FRA0 XXXX XX00b

0023h

0024h 40 MHz On-Chip Oscillator Control Register 2 FRA2 0XX0 X000b

0025h

0026h Voltage Monitor Function Select Register VWCE 00h

0027h

0028h Voltage Detector 2 Level Select Register VD2LS 0000 0100b

(2)

0029h

002Ah Voltage Monitor 0 Control Register VW0C 1100 1X10b

(3, 4)

11 00 1X11b

(3, 5)

002Bh

002Ch Voltage Monitor 2 Cont rol Register VW2C 1000 0X10b

(3, 6)

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh X: Undefined

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 3 SFR Inform at io n (3) (1)

Address Register Symbol Reset Value

0040h

0041h E2dataFlash Interrupt Control Register E2FIC XXXX X000b

0042h INT7 Interrupt Control Register

Serial Bus Interface 0 Inte rrupt Control Register INT7IC

SS0IC XX00 X000b

0043h INT6 Interrupt Control Register

LIN0 Interrupt Control Register INT6IC

LIN0IC XX00 X000b

0044h INT3 Interrupt Control Register INT3IC XX00 X000b

0045h Timer B5 Interrupt Control Register TB5IC XXXX X000b

0046h Timer B4 Interrupt Control Register TB4IC XXXX X000b

0047h Timer B3 Interrupt Control Register TB3IC XXXX X000b

0048h INT5 Interrupt Control Register INT5IC XX00 X000b

0049h INT4 Interrupt Control Register INT4IC XX00 X000b

004Ah UART2 Bus Collis ion Detection Interrupt Control Register

Task Monitoring Timer Interrupt Control Register BCNIC

TMOSIC XXXX X000b

004Bh DMA0 Interrupt Control Register DM0IC XXXX X000b

004Ch DMA1 Interrupt Control Register DM1IC XXXX X000b

004Dh Key Input Interrupt Control Register KUPIC XXXX X000b

004Eh A /D Conversion Interrupt Control Register ADIC XXXX X000b

004Fh UART2 Transmit Interrupt Control Register S2TIC XXXX X000b

0050h UART2 Receive Interrupt Control Register S2RIC XXXX X000b

0051h UART0 Transmit Interrupt Control Register

LIN0 Low Detection Interru pt Control Register S0TIC

L0WIC XXXX X000b

0052h UART0 Receive Interrupt Control Register S0RIC XXXX X000b

0053h UART1 Transmit Interrupt Control Register S1TIC XXXX X000b

0054h UART1 Receive Interrupt Control Register S1RIC XXXX X000b

0055h Timer A0 Interrupt Control Register TA0IC XXXX X000b

0056h Timer A1 Interrupt Control Register TA1IC XXXX X000b

0057h Timer A2 Interrupt Control Register TA2IC XXXX X000b

0058h Timer A3 Interrupt Control Register TA3IC XXXX X000b

0059h Timer A4 Interrupt Control Register TA4IC XXXX X000b

005Ah Timer B0 Interrupt Control Register TB0IC XXXX X000b

005Bh Timer B1 Interrupt Control Register TB1IC XXXX X000b

005Ch Timer B2 Interrupt Control Register TB2IC XXXX X000b

005Dh INT0 Interrupt Control Register INT0IC XX00 X000b

005Eh INT1 Interrupt Control Register INT1IC XX00 X000b

005Fh INT2 Interrupt Control Register INT2IC XX00 X000b

X: Undefined

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 4 SFR Inform at io n (4) (1)

Address Register Symbol Reset Value

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h DMA2 Interrupt Control Register DM2IC XXXX X000b

006Ah DMA3 Interrupt Control Register DM3IC XXXX X000b

006Bh CAN 1 Reception Complete Interrupt Control Register C1RIC XXXX X000b

006Ch CAN 1 Transmission Complete Interrupt Control Register C1TIC XXXX X000b

006Dh CAN 1 Receive FIFO Interrupt Control Register C1FRIC XXXX X000b

006Eh CAN 1 Transmit FIFO Interrupt Control Register C1FTIC XXXX X000b

006Fh UART4 Transmit Interrupt Control Register

Real-Time Clock Compare Interrupt Control Register S4TIC

RTCCIC XXXX X000b

0070h UART4 Receive Interrupt Control Register S4RIC XXXX X000b

0071h CAN0 Wake-up Interrupt Control Register C0WIC XXXX X000b

0072h UART3 Transmit Interrupt Control Register

CAN0 Error Interrupt Control Register S3TIC

C0EIC XXXX X000b

0073h UART3 Receive Interrupt Control Register

CAN 1 Wake-up Interrupt Control Register S3RIC

C1WIC XXXX X000b

0074h Real-Time Clock Cycle Interrupt Control Register

CAN 1 Error Interrupt Control Regist er RTCTIC

C1EIC XXXX X000b

0075h CAN0 Reception Complete Interrupt Control Register C0RIC XXXX X000b

0076h CAN0 Transmission Complete Interrupt Control Register C0TIC XXXX X000b

0077h CAN0 Receive FIFO Interrupt Control Register C0FRIC XXXX X000b

0078h CAN0 Transmit FIFO Interrupt Cont rol Register C0FTIC XXXX X000b

0079h IC/OC Interrupt 0 Control Register ICOC0IC XXXX X000b

007Ah IC/OC Channel 0 Interrupt Control Register ICOCH0IC XXXX X000b

007Bh IC/OC Interrupt 1 Control Register

I2C-bus Interface Interrupt Control Register ICOC1IC

IICIC XXXX X000b

007Ch IC/OC Channel 1 Interrupt Control Register

SCL/SDA Interrupt Control Register ICOCH1IC

SCLDAIC XXXX X000b

007Dh IC/OC Channel 2 Interrupt Control Register ICOCH2IC XXXX X000b

007Eh IC/OC Channel 3 Interrupt Control Register ICOCH3IC XXXX X000b

007Fh IC/OC Base Timer Interrupt Control Register BTIC XXXX X000b

X: Undefined

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 5 SFR Inform at io n (5) (1)

Address Register Symbol Reset Value

0080h

E2dataFlash Address Register E2FA

00h

0081h 00h

0082h XXh

0083h XXh

0084h

0085h

0086h

0087h

0088h E2dataFlash Command Register E2FI 00h

0089h XXh

008Ah

008Bh

008Ch E2dataFlash Data Register E2FD XXh

008Dh XXh

008Eh

008Fh

0090h E2dataFlash Mode Register E2FM 00h

0091h

0092h E2dataFlash Control Register E2FC XXXX XXX0b

0093h

0094h E2dataFlash Status Register 1 E2FS1 XXXX XXX0b

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h

00A1h E2data Flash Status Register 0 E2FS0 0X00 XXXXb

00A2h

00A3h

00A4h

00A5h

00A6h

00A7h

00A8h

00A9h

00AAh

00ABh

00ACh

00ADh

00AEh

00AFh

00B0h to

015Fh X: Undefined

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 6 SFR Inform at io n (6) (1)

Address Register Symbol Reset Value

0160h

0161h LIN Wake-up Baud Rate Select Register LWBR 00h

0162h LIN Baud Rate Prescaler 0 Register LBRP0 00h

0163h LIN Baud Rate Prescaler 1 Register LBRP1 00h

0164h LIN Self-test Control Register LSTC 00h

0165h LIN Port Clock Control Register LPC 00h

0166h

0167h

0168h LIN0 Mode Register L0MD 00h

0169h LIN0 Break Field Setting Register L0BRK 00h

016Ah LIN0 Space Width Setting Register L0SPC 00h

016Bh LIN0 Wake-up Setting Register L0WUP 00h

016Ch LIN0 Interrupt Enable Register L0IE 00h

016Dh LIN0 Error Detection Enable Register L0EDE 00h

016Eh LIN0 Control Register L0C 00h

016Fh

0170h LIN0 Transmit Control Register L0TC 00h

0171h LIN0 Mode Status Register L0MST 00h

0172h LIN0 Status Register L0ST 00h

0173h LIN0 Error Status Register L0EST 00h

0174h LIN0 Response Field Setting Register L0RFC 00h

0175h LIN0 ID Buffer Register L0IDB XXh

0176h LIN0 Checksum Buffer Register L0CB XXh

0177h

0178h LIN0 Data 1 Buffer Register L0DB1 XXh

0179h LIN0 Data 2 Buffer Register L0DB2 XXh

017Ah LIN0 Data 3 Buffer Register L0DB3 XXh

017Bh LIN0 Data 4 Buffer Register L0DB4 XXh

017Ch LIN0 Data 5 Buffer Register L0DB5 XXh

017Dh LIN0 Data 6 Buffer Register L0DB6 XXh

017Eh LIN0 Data 7 Buffer Register L0DB7 XXh

017Fh LIN0 Data 8 Buffer Register L0DB8 XXh

X: Undefined

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 7 SFR Inform at io n (7) (1)

Address Register Symbol Reset Value

0180h DMA0 Source Pointer SAR0 XXh

0181h XXh

0182h 0Xh

0183h

0184h DMA0 Destination Pointer DAR0 XXh

0185h XXh

0186h 0Xh

0187h

0188h DMA0 Transfer Counter TCR0 XXh

0189h XXh

018Ah

018Bh

018Ch DMA0 Control Register DM0CON 0000 0X00b

018Dh

018Eh

018Fh

0190h DMA1 Source Pointer SAR1 XXh

0191h XXh

0192h 0Xh

0193h

0194h DMA1 Destination Pointer DAR1 XXh

0195h XXh

0196h 0Xh

0197h

0198h DMA1 Transfer Counter TCR1 XXh

0199h XXh

019Ah

019Bh

019Ch DMA1 Control Register DM1CON 0000 0X00b

019Dh

019Eh

019Fh

01A0h DMA2 Source Pointer SAR2 XXh

01A1h XXh

01A2h 0Xh

01A3h

01A4h DMA2 Destination Pointer DAR2 XXh

01A5h XXh

01A6h 0Xh

01A7h

01A8h DMA2 Transfer Counter TCR2 XXh

01A9h XXh

01AAh

01ABh

01ACh DMA2 Control Register DM2CON 0000 0X00b

01ADh

01AEh

01AFh X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 39 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 8 SFR Inform at io n (8) (1)

Address Register Symbol Reset Value

01B0h DMA3 Source Pointer SAR3 XXh

01B1h XXh

01B2h 0Xh

01B3h

01B4h DMA3 Destination Pointer DAR3 XXh

01B5h XXh

01B6h 0Xh

01B7h

01B8h DMA3 Transfer Counter TCR3 XXh

01B9h XXh

01BAh

01BBh

01BCh DMA3 Control Register DM3CON 0000 0X00b

01BDh

01BEh

01BFh

01C0h Timer B0-1 Register TB01 XXh

01C1h XXh

01C2h Timer B1-1 Register TB11 XXh

01C3h XXh

01C4h Timer B2-1 Register TB21 XXh

01C5h XXh

01C6h Pulse Period/Pulse Width Measurement Mode Function Select

01C7h

01C8h Timer B Count Source Select Register 0 TBCS0 00h

01C9h Timer B Count Source Select Register 1 TBCS1 X0h

01CAh

01CBh Timer AB Division Control Register 0 TCKDIVC0 0000 X000b

01CCh

01CDh

01CEh

01CFh

01D0h Timer A Count Source Select Register 0 TACS0 00h

01D1h Timer A Count Source Select Register 1 TACS1 00h

01D2h Timer A Count Source Select Register 2 TACS2 X0h

01D3h

01D4h 16-bit Pulse Width Modulation Mode Function Select Register PWMFS 0XX0 X00Xb

01D5h Timer A Waveform Output Function Select Register TAPOFS XXX0 0000b

01D6h

01D7h

01D8h Timer A Output Waveform Change Enable Register TAOW XXX0 X00Xb

01D9h

01DAh Three-Phase Protect Control Register TPRC 00h

01DBh

01DCh

01DDh

01DEh

01DFh X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 40 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 9 SFR Inform at io n (9) (1)

Address Register Symbol Reset Value

01E0h Timer B3-1 Register TB31 XXh

01E1h XXh

01E2h Timer B4-1 Register TB41 XXh

01E3h XXh

01E4h Timer B5-1 Register TB51 XXh

01E5h XXh

01E6h Pulse Period/Pulse Wid th Measureme nt Mode Func tion Select Reg-

ister 2 PPWFS2 XXXX X000b

01E7h

01E8h Timer B Count Source Select Register 2 TBCS2 00h

01E9h Timer B Count Source Select Register 3 TBCS3 X0h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h Task Monitor Timer Register TMOS XXh

01F1h XXh

01F2h Task Monitor T imer Count Start Flag TMOSSR XXXX XXX0b

01F3h Task Monitor Timer Count Source Select Register TMOSCS XXXX 0000b

01F4h Task Monitor Timer Protect Register TMOSPR 00h

01F5h

01F6h

01F7h

01F8h

01F9h

01FAh

01FBh

01FCh

01FDh

01FEh

01FFh

0200h

0201h

0202h

0203h

0204h Interrupt Source Select Register 4 IFSR4A 00h

0205h Interrupt Source Select Register 3 IFSR3A 00h

0206h Interrupt Source Select Register 2 IFSR2A 00h

0207h Interrupt Source Select Register IFSR 00h

0208h

0209h

020Ah

020Bh

020Ch

020Dh

020Eh Address Match Interrupt Enable Register AIER XXXX XX00b

020Fh Address Match Interrupt Enable Register 2 AIER2 XXXX XX00b

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 41 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 10 SFR Inform ation (10) (1)

Address Register Symbol Reset Value

0210h Address Match Interrupt Register 0 RMAD0 00h

0211h 00h

0212h X0h

0213h

0214h Address Match Interrupt Register 1 RMAD1 00h

0215h 00h

0216h X0h

0217h

0218h Address Match Interrupt Register 2 RMAD2 00h

0219h 00h

021Ah X0h

021Bh

021Ch Address Match Interrupt Register 3 RMAD3 00h

021Dh 00h

021Eh X0h

021Fh

0220h Flash Memory Control Register 0 FMR0

0000 0001b

(Other than user boot mode)

0010 0001b

(User boot mode)

0221h Flash Memory Control Register 1 FMR1 00X0 XX0Xb

0222h Flash Memory Control Register 2 FMR2 XXXX 0000b

0223h Flash Memory Control Register 3 FMR3 XXXX 0000b

0224h

0225h

0226h

0227h

0228h

0229h

022Ah

022Bh

022Ch

022Dh

022Eh

022Fh

0230h Flash Memory Control Register 6 FMR6 XX0X XX00b

0231h

0232h

0233h

0234h

0235h

0236h

0237h

0238h

0239h

023Ah

023Bh

023Ch

023Dh

023Eh

023Fh X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 42 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 11 SFR Information (11) (1)

Address Register Symbol Reset Value

0240h

0241h

0242h

0243h

0244h

0245h

0246h

0247h

0248h UART0 Transmit/Receive Mode Register U0MR 00h

0249h UART0 Bit Rate Register U0BRG XXh

024Ah UART0 Transmit Buffer Register U0TB XXh

024Bh XXh

024Ch UART0 Transmit/Receive Control Register 0 U0C0 0000 1000b

024Dh UART0 Transmit/Receive Control Register 1 U0C1 0000 0010b

024Eh UART0 Receive Buffer Register U0RB XXh

024Fh XXh

0250h

0251h

0252h UART Clock Select Re gister UCLKSEL0 X0h

0253h

0254h

0255h

0256h

0257h

0258h UART1 Transmit/Receive Mode Register U1MR 00h

0259h UART1 Bit Rate Register U1BRG XXh

025Ah UART1 Transmit Buffer Register U1TB XXh

025Bh XXh

025Ch UART1 Transmit/Receive Control Register 0 U1C0 0000 1000b

025Dh UART1 Transmit/Receive Control Register 1 U1C1 0000 0010b

025Eh UART1 Receive Buffer Register U1RB XXh

025Fh XXh

0260h

0261h

0262h

0263h

0264h UART2 Special Mode Register 4 U2SMR4 00h

0265h UART2 Special Mode Register 3 U2SMR3 000X 0X0Xb

0266h UART2 Special Mode Register 2 U2SMR2 X000 0000b

0267h UART2 Special Mode Register U2SMR X000 0000b

0268h UART2 Transmit/Receive Mode Register U2MR 00h

0269h UART2 Bit Rate Register U2BRG XXh

026Ah UART2 Transmit Buffer Register U2TB XXh

026Bh XXh

026Ch UART2 Transmit/Receive Control Register 0 U2C0 0000 1000b

026Dh UART2 Transmit/Receive Control Register 1 U2C1 0000 0010b

026Eh UART2 Receive Buffer Register U2RB XXh

026Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 43 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 12 SFR Inform ation (12) (1)

Address Register Symbol Reset Value

0270h

0271h

0272h

0273h

0274h

0275h

0276h

0277h

0278h

0279h

027Ah

027Bh

027Ch

027Dh

027Eh

027Fh

0280h

0281h

0282h

0283h

0284h

0285h

0286h

0287h

0288h

0289h

028Ah

028Bh

028Ch

028Dh

028Eh

028Fh

0290h

0291h

0292h

0293h

0294h

0295h

0296h

0297h

0298h UART4 Transmit/Receive Mode Register U4MR 00h

0299h UART4 Bit Rate Register U4BRG XXh

029Ah UART4 Transmit Buffer Register U4TB XXh

029Bh XXh

029Ch UART4 Transmit/Receive Control Register 0 U4C0 0000 1000b

029Dh UART4 Transmit/Receive Control Register 1 U4C1 0000 0010b

029Eh UART4 Receive Buffer Register U4RB XXh

029Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 44 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 13 SFR Inform ation (13) (1)

Address Register Symbol Reset Value

02A0h

02A1h

02A2h

02A3h

02A4h

02A5h

02A6h

02A7h

02A8h UART3 Transmit/Receive Mode Register U3MR 00h

02A9h UART3 Bit Rate Register U3BRG XXh

02AAh UART3 Transmit Buffer Register U3TB XXh

02ABh XXh

02ACh UART3 Transmit/Receive Control Register 0 U3C0 0000 1000b

02ADh UART3 Transmit/Receive Control Register 1 U3C1 0000 0010b

02AEh UART3 Receive Buffer Register U3RB XXh

02AFh XXh

02B0h I2C0 Data Shift Register S00 XXh

02B1h

02B2h I2C0 Address Register 0 S0D0 0000 000Xb

02B3h I2C0 Control Register 0 S1D0 00h

02B4h I2C0 Clock Control Register S20 00h

02B5h I2C0 Start/Stop Condition Control Register S2D0 0001 1010b

02B6h I2C0 Control Register 1 S3D0 0011 0000b

02B7h I2C0 Control Register 2 S4D0 00h

02B8h I2C0 Status Register 0 S10 0001 000Xb

02B9h I2C0 Status Register 1 S11 XXXX X000b

02BAh I2C0 Address Register 1 S0D1 0000 000Xb

02BBh I2C0 Address Register 2 S0D2 0000 000Xb

02BCh

02BDh

02BEh

02BFh

02C0h Time Measurement Register 0

Waveform Generation Register 0 G1TM0

G1PO0 XXh

02C1h XXh

02C2h Time Measurement Register 1

Waveform Generation Register 1 G1TM1

G1PO1 XXh

02C3h XXh

02C4h Time Measurement Register 2

Waveform Generation Register 2 G1TM2

G1PO2 XXh

02C5h XXh

02C6h Time Measurement Register 3

Waveform Generation Register 3 G1TM3

G1PO3 XXh

02C7h XXh

02C8h Time Measurement Register 4

Waveform Generation Register 4 G1TM4

G1PO4 XXh

02C9h XXh

02CAh Time Measurement Register 5

Waveform Generation Register 5 G1TM5

G1PO5 XXh

02CBh XXh

02CCh Time Measurement Register 6

Waveform Generation Register 6 G1TM6

G1PO6 XXh

02CDh XXh

02CEh Time Measurement Register 7

Waveform Generation Register 7 G1TM7

G1PO7 XXh

02CFh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 45 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 14 SFR Inform ation (14) (1)

Address Register Symbol Reset Value

02D0h Waveform Generation Control Register 0 G1POCR0 0X00 XX00b

02D1h Waveform Generation Control Register 1 G1POCR1 0X00 XX00b

02D2h Waveform Generation Control Register 2 G1POCR2 0X00 XX00b

02D3h Waveform Generation Control Register 3 G1POCR3 0X00 XX00b

02D4h Waveform Generation Control Register 4 G1POCR4 0X00 XX00b

02D5h Waveform Generation Control Register 5 G1POCR5 0X00 XX00b

02D6h Waveform Generation Control Register 6 G1POCR6 0X00 XX00b

02D7h Waveform Generation Control Register 7 G1POCR7 0X00 XX00b

02D8h Time Measurement Control Register 0 G1TMCR0 00h

02D9h Time Measurement Control Register 1 G1TMCR1 00h

02DAh Time Measurement Control Register 2 G1TMCR2 00h

02DBh Time Measurement Control Register 3 G1TMCR3 00h

02DCh Time Measurement Control Register 4 G1TMCR4 00h

02DDh Time Measur ement Control Register 5 G1TMCR5 00h

02DEh Time Measurement Control Register 6 G1TMCR6 00h

02DFh Time Measurement Control Regi ster 7 G1TMCR7 00h

02E0h Base Timer Register G1BT XXh

02E1h XXh

02E2h Base Timer Control Register 0 G1BCR0 00h

02E3h Base Timer Control Register 1 G1BCR1 00h

02E4h Time Measurement Prescaler Register 6 G1TPR6 00h

02E5h Time Measurement Prescaler Register 7 G1TPR7 00h

02E6h Function Enable Register G1FE 00h

02E7h Function Select Register G1FS 00h

02E8h Base Timer Reset Register G1BTRR XXh

02E9h XXh

02EAh Count Source Divide Register G1DV 00h

02EBh

02ECh Waveform Output Master Enable Register G1OER 00h

02EDh

02EEh Timer S I/O Control Regi ster 0 G1IOR0 00h

02EFh Timer S I/O Control Register 1 G1IOR1 00h

02F0h Interrupt Request Register G1IR XXh

02F1h Interrupt Enable Register 0 G1IE0 00h

02F2h Interrupt Enable Register 1 G1IE1 00h

02F3h

02F4h

02F5h

02F6h

02F7h

02F8h

02F9h

02FAh

02FBh

02FCh

02FDh

02FEh NMI Digital Debounce Register NDDR FFh

02FFh P1_7 Digital Debounce Register P17D DR FFh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 46 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 15 SFR Inform ation (15) (1)

Address Register Symbol Reset Value

0300h Timer B3/B4/B5 Count Start Flag TBSR 000X XXXXb

0301h

0302h Timer A1-1 Register TA11 XXh

0303h XXh

0304h Timer A2-1 Register TA21 XXh

0305h XXh

0306h Timer A4-1 Register TA41 XXh

0307h XXh

0308h Three-Phase PWM Control Regi ster 0 INVC0 00h

0309h Three-Phase PWM Control Regi ster 1 INVC1 00h

030Ah T hree-Phase Output Buffer Register 0 IDB0 XX11 1111b

030Bh T hree-Phase Output Buffer Register 1 IDB1 XX11 1111b

030Ch Dead Time Timer DTT XXh

030Dh Timer B2 Interrupt Generation Frequency Set Counter ICTB2 XXh

030Eh Position-Data-Retain Function Control Register PDRF XXXX 0000b

030Fh

0310h Timer B3 Register TB3 XXh

0311h XXh

0312h Timer B4 Register TB4 XXh

0313h XXh

0314h Timer B5 Register TB5 XXh

0315h XXh

0316h

0317h

0318h Port Function Control Register PFCR 0011 1111b

0319h

031Ah

031Bh Timer B3 Mode Register TB3MR 00XX 0000b

031Ch Timer B4 Mode Register TB4MR 00XX 0000b

031Dh Timer B5 Mode Register TB5MR 00XX 0000b

031Eh

031Fh

0320h Count Start Flag TABSR 00h

0321h

0322h One-Shot Start Flag ONSF 00h

0323h Trigger Select Register TRGSR 00h

0324h Increment/Decrement Flag UDF 00h

0325h

0326h Timer A0 Register TA0 XXh

0327h XXh

0328h Timer A1 Register TA1 XXh

0329h XXh

032Ah Timer A2 Register TA2 XXh

032Bh XXh

032Ch Timer A3 Register TA3 XXh

032Dh XXh

032Eh Timer A4 Register TA4 XXh

032Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 47 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 16 SFR Inform ation (16) (1)

Address Register Symbol Reset Value

0330h Timer B0 Register TB0 XXh

0331h XXh

0332h Timer B1 Register TB1 XXh

0333h XXh

0334h Timer B2 Register TB2 XXh

0335h XXh

0336h Timer A0 Mode Register TA 0MR 00h

0337h Timer A1 Mode Register TA 1MR 00h

0338h Timer A2 Mode Register TA 2MR 00h

0339h Timer A3 Mode Register TA 3MR 00h

033Ah Timer A4 Mode Register TA4MR 00h

033Bh Timer B0 Mode Register TB0MR 00XX 0000b

033Ch Timer B1 Mode Register TB1MR 00XX 0000b

033Dh Timer B2 Mode Register TB2MR 00XX 0000b

033Eh Timer B2 Special Mode Register TB2SC X000 0000b

033Fh

0340h Real-Time Clock Second Data Register RTCSEC 00h

0341h Real-Time Clock Minute Data Register RTCMIN X000 0000b

0342h Real-Time Clock Hour Data Register RTCHR XX00 0000b

0343h Real-Time Clock Day Data Register RTCWK XXXX X000b

0344h Real-Time Clock Control Regi ster 1 RTCCR1 0000 X00Xb

0345h Real-Time Clock Control Register 2 RTCCR2 X000 0000b

0346h Real-Time Clock Count Source Select Register RTCCSR XXX0 0000b

0347h

0348h Real-Time Clock Second Compare Data Register RTCCSEC X000 0000b

0349h Real-Time Clock Minute Compare Data Register RTCCMIN X000 0000b

034Ah R eal-Time Clock Hour Compare Data Register RTCCHR X000 0000b

034Bh

034Ch

034Dh

034Eh

034Fh

0350h

0351h

0352h

0353h SS0 Bit Counter Register SS0BR 1111 1000b

0354h SS0 Transmit Data Register SS0TDR FFh

0355h FFh

0356h SS0 Receive Data Register SS0RDR FFh

0357h FFh

0358h SS0 Control Register H SS0CRH 00h

0359h SS0 Control Register L SS0CRL 0111 1101b

035Ah SS0 Mode Register SS0MR 0001 0000b

035Bh S S0 Enable Register SS0ER 00h

035Ch SS0 Status Register SS0SR 00h

035Dh SS0 Mode Register 2 SS0MR2 00h

035Eh

035Fh X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 48 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Notes:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

2. When the CSPROINI bit in the OFS1 address is 0, the reset value is 1000 0000b.

Tab le 4. 17 SFR Inform ation (17) (1)

Address Register Symbol Reset Value

0360h Pull-Up Control Register 0 PUR0 00h

0361h Pull-Up Control Register 1 PUR1 00h

0362h Pull-Up Control Register 2 PUR2 00h

0363h

0364h

0365h

0366h Port Control Register PCR 0XX0 0XX0b

0367h

0368h

0369h

036Ah

036Bh

036Ch Input Threshold Select Register 0 VLT0 00h

036Dh Input Threshold Select Register 1 VLT1 00h

036Eh Input Threshold Select Regi ster 2 VLT2 XX00 0000b

036Fh

0370h Pin Assignment Control Register PA CR 0XXX X000b

0371h

0372h

0373h

0374h

0375h

0376h

0377h

0378h

0379h

037Ah

037Bh

037Ch Count Source Protection Mode Register CSPR 00h

(2)

037Dh Watchdog Timer Refresh Register WDTR XXh

037Eh Watchdog Timer Start Register WDTS XXh

037Fh Watchdog Timer Control Register WDC 00XX XXXXb

0380h

0381h

0382h

0383h

0384h

0385h

0386h

0387h

0388h

0389h

038Ah

038Bh

038Ch

038Dh

038Eh

038Fh X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 49 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 18 SFR Inform ation (18) (1)

Address Register Symbol Reset Value

0390h DMA2 Source Select Register DM2SL 00h

0391h

0392h DMA3 Source Select Register DM3SL 00h

0393h

0394h

0395h

0396h

0397h

0398h DMA0 Source Select Register DM0SL 00h

0399h

039Ah DMA1 Source Select Register DM1SL 00h

039Bh

039Ch

039Dh

039Eh

039Fh

03A0h

03A1h

03A2h O pen-Circuit Detection Assist Function Register AINRST XX00 XXXXb

03A3h

03A4h

03A5h

03A6h

03A7h

03A8h

03A9h

03AAh

03ABh

03ACh

03ADh

03AEh

03AFh

03B0h

03B1h

03B2h

03B3h

03B4h SFR Snoop Address Register CRCSAR XXXX XXXXb

03B5h 00XX XXXXb

03B6h CRC Mode Register CRCMR 0XXX XXX0b

03B7h

03B8h

03B9h

03BAh

03BBh

03BCh CRC Data Register CRCD XXh

03BDh XXh

03BEh CRC Input Register CRCIN XXh

03BFh X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 50 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 19 SFR Inform ation (19) (1)

Address Register Symbol Reset Value

03C0h A/D Register 0 AD0 XXXX XXXXb

03C1h 0000 00XXb

03C2h A/D Register 1 AD1 XXXX XXXXb

03C3h 0000 00XXb

03C4h A/D Register 2 AD2 XXXX XXXXb

03C5h 0000 00XXb

03C6h A/D Register 3 AD3 XXXX XXXXb

03C7h 0000 00XXb

03C8h A/D Register 4 AD4 XXXX XXXXb

03C9h 0000 00XXb

03CAh A/D Register 5 AD5 XXXX XXXXb

03CBh 0000 00XXb

03CCh A/D Register 6 AD6 XXXX XXXXb

03CDh 0000 00XXb

03CEh A/D Register 7 AD7 XXXX XXXXb

03CFh 0000 00XXb

03D0h

03D1h

03D2h

03D3h

03D4h A/D Control Register 2 ADCON2 0000 X00Xb

03D5h

03D6h A/D Control Register 0 ADCON0 0000 0XXXb

03D7h A/D Control Register 1 ADCON1 0000 X000b

03D8h D/A0 Register DA0 00h

03D9h

03DAh

03DBh

03DCh D/A Control Register DACON 00h

03DDh

03DEh

03DFh

03E0h Port P0 Register P0 XXh

03E1h Port P1 Register P1 XXh

03E2h Port P0 Direction Register PD0 00h

03E3h Port P1 Direction Register PD1 00h

03E4h Port P2 Register P2 XXh

03E5h Port P3 Register P3 XXh

03E6h Port P2 Direction Register PD2 00h

03E7h Port P3 Direction Register PD3 00h

03E8h Port P4 Register P4 XXh

03E9h Port P5 Register P5 XXh

03EAh Port P4 Direction Register PD4 00h

03EBh Port P5 Direction Register PD5 00h

03ECh Port P6 Register P6 XXh

03EDh Port P7 Register P7 XXh

03EEh Port P6 Direction Register PD6 00h

03EFh Port P7 Direction Register PD7 00h

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 51 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 20 SFR Inform ation (20) (1)

Address Register Symbol Reset Value

03F0h Port P8 Register P8 XXh

03F1h Port P9 Register P9 XXh

03F2h Port P8 Direction Register PD8 00h

03F3h Port P9 Direction Register PD9 00h

03F4h Port P10 Register P10 XXh

03F5h

03F6h Port P10 Direction Register PD10 00h

03F7h

03F8h

03F9h

03FAh

03FBh

03FCh

03FDh

03FEh

03FFh X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 52 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 21 SFR Inform ation (21) (1)

Address Register Symbol Reset Value

D1F0h

D1F1h

D1F2h

D1F3h

D1F4h

D1F5h

D1F6h

D1F7h

D1F8h

D1F9h

D1FAh

D1FBh

D1FCh

D1FDh

D1FEh

D1FFh

D200h

CAN1 Mailbox 0: Message Identifier

C1MB0

XXh

D201h XXh

D202h XXh

D203h XXh

D204h

D205h CAN1 Mailbox 0: Data Length XXh

D206h

CAN1 Mailbox 0: Data Field

XXh

D207h XXh

D208h XXh

D209h XXh

D20Ah XXh

D20Bh XXh

D20Ch XXh

D20Dh XXh

D20Eh CAN1 Mailbox 0: Time Stamp XXh

D20Fh XXh

D210h

CAN1 Message Identifier

C1MB1

XXh

D211h XXh

D212h XXh

D213h XXh

D214h

D215h CAN1 Mailbox 1: Data Length XXh

D216h

CAN1 Mailbox 1: Data Field

XXh

D217h XXh

D218h XXh

D219h XXh

D21Ah XXh

D21Bh XXh

D21Ch XXh

D21Dh XXh

D21Eh CAN1 Mailbox 1: Time Stamp XXh

D21Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 53 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 22 SFR Inform ation (22) (1)

Address Register Symbol Reset Value

D220h

CAN1 Mailbox 2: Message Identifier

C1MB2

XXh

D221h XXh

D222h XXh

D223h XXh

D224h

D225h CAN1 Mailbox 2: Data Length XXh

D226h

CAN1 Mailbox 2: Data Field

XXh

D227h XXh

D228h XXh

D229h XXh

D22Ah XXh

D22Bh XXh

D22Ch XXh

D22Dh XXh

D22Eh CAN1 Mailbox 2: Time Stamp XXh

D22Fh XXh

D230h

CAN1 Mailbox 3: Message Identifier

C1MB3

XXh

D231h XXh

D232h XXh

D233h XXh

D234h

D235h CAN1 Mailbox 3: Data Length XXh

D236h

CAN1 Mailbox 3: Data Field

XXh

D237h XXh

D238h XXh

D239h XXh

D23Ah XXh

D23Bh XXh

D23Ch XXh

D23Dh XXh

D23Eh CAN1 Mailbox 3: Time Stamp XXh

D23Fh XXh

D240h

CAN1 Mailbox 4: Message Identifier

C1MB4

XXh

D241h XXh

D242h XXh

D243h XXh

D244h

D245h CAN1 Mailbox 4: Data Length XXh

D246h

CAN1 Mailbox 4: Data Field

XXh

D247h XXh

D248h XXh

D249h XXh

D24Ah XXh

D24Bh XXh

D24Ch XXh

D24Dh XXh

D24Eh CAN1 Mailbox 4: Time Stamp XXh

D24Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 54 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 23 SFR Inform ation (23) (1)

Address Register Symbol Reset Value

D250h

CAN1 Mailbox 5: Message Identifier

C1MB5

XXh

D251h XXh

D252h XXh

D253h XXh

D254h

D255h CAN1 Mailbox 5: Data Length XXh

D256h

CAN1 Mailbox 5: Data Field

XXh

D257h XXh

D258h XXh

D259h XXh

D25Ah XXh

D25Bh XXh

D25Ch XXh

D25Dh XXh

D25Eh CAN1 Mailbox 5: Time Stamp XXh

D25Fh XXh

D260h

CAN1 Mailbox 6: Message Identifier

C1MB6

XXh

D261h XXh

D262h XXh

D263h XXh

D264h

D265h CAN1 Mailbox 6: Data Length XXh

D266h

CAN1 Mailbox 6: Data Field

XXh

D267h XXh

D268h XXh

D269h XXh

D26Ah XXh

D26Bh XXh

D26Ch XXh

D26Dh XXh

D26Eh CAN1 Mailbox 6: Time Stamp XXh

D26Fh XXh

D270h

CAN1 Mailbox 7: Message Identifier

C1MB7

XXh

D271h XXh

D272h XXh

D273h XXh

D274h

D275h CAN1 Mailbox 7: Data Length XXh

D276h

CAN1 Mailbox 7: Data Field

XXh

D277h XXh

D278h XXh

D279h XXh

D27Ah XXh

D27Bh XXh

D27Ch XXh

D27Dh XXh

D27Eh CAN1 Mailbox 7: Time Stamp XXh

D27Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 55 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 24 SFR Inform ation (24) (1)

Address Register Symbol Reset Value

D280h

CAN1 Mailbox 8: Message Identifier

C1MB8

XXh

D281h XXh

D282h XXh

D283h XXh

D284h

D285h CAN1 Mailbox 8: Data Length XXh

D286h

CAN1 Mailbox 8: Data Field

XXh

D287h XXh

D288h XXh

D289h XXh

D28Ah XXh

D28Bh XXh

D28Ch XXh

D28Dh XXh

D28Eh CAN1 Mailbox 8: Time Stamp XXh

D28Fh XXh

D290h

CAN1 Mailbox 9: Message Identifier

C1MB9

XXh

D291h XXh

D292h XXh

D293h XXh

D294h

D295h CAN1 Mailbox 9: Data Length XXh

D296h

CAN1 Mailbox 9: Data Field

XXh

D297h XXh

D298h XXh

D299h XXh

D29Ah XXh

D29Bh XXh

D29Ch XXh

D29Dh XXh

D29Eh CAN1 Mailbox 9: Time Stamp XXh

D29Fh XXh

D2A0h

CAN1 Mailbox 10: Messag e Identifier

C1MB10

XXh

D2A1h XXh

D2A2h XXh

D2A3h XXh

D2A4h

D2A5h CAN1 Mailbox 10: Data Length XXh

D2A6h

CAN1 Mailbox 10: Da ta Field

XXh

D2A7h XXh

D2A8h XXh

D2A9h XXh

D2AAh XXh

D2ABh XXh

D2ACh XXh

D2ADh XXh

D2AEh CAN1 Mailbox 10: Time Stamp XXh

D2AFh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 56 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 25 SFR Inform ation (25) (1)

Address Register Symbol Reset Value

D2B0h

CAN1 Mailbox 11: Message Identifier

C1MB11

XXh

D2B1h XXh

D2B2h XXh

D2B3h XXh

D2B4h

D2B5h CAN1 Mailbox 11: Data Length XXh

D2B6h

CAN1 Mailbox 11: Data Field

XXh

D2B7h XXh

D2B8h XXh

D2B9h XXh

D2BAh XXh

D2BBh XXh

D2BCh XXh

D2BDh XXh

D2BEh CAN1 Mailbox 11: Time Stamp XXh

D2BFh XXh

D2C0h

CAN1 Mailbox 12: Messag e Identifier

C1MB12

XXh

D2C1h XXh

D2C2h XXh

D2C3h XXh

D2C4h

D2C5h CAN1 Mailbox 12: Data Length XXh

D2C6h

CAN1 Mailbox 12: Da ta Field

XXh

D2C7h XXh

D2C8h XXh

D2C9h XXh

D2CAh XXh

D2CBh XXh

D2CCh XXh

D2CDh XXh

D2CEh CAN1 Mailbox 12: Time Stamp XXh

D2CFh XXh

D2D0h

CAN1 Mailbox 13: Messag e Identifier

C1MB13

XXh

D2D1h XXh

D2D2h XXh

D2D3h XXh

D2D4h

D2D5h CAN1 Mailbox 13: Data Length XXh

D2D6h

CAN1 Mailbox 13: Da ta Field

XXh

D2D7h XXh

D2D8h XXh

D2D9h XXh

D2DAh XXh

D2DBh XXh

D2DCh XXh

D2DDh XXh

D2DEh CAN1 Mailbox 13: Time Stamp XXh

D2DFh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 57 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 26 SFR Inform ation (26) (1)

Address Register Symbol Reset Value

D2E0h

CAN1 Mailbox 14: Messag e Identifier

C1MB14

XXh

D2E1h XXh

D2E2h XXh

D2E3h XXh

D2E4h

D2E5h CAN1 Mailbox 14: Data Length XXh

D2E6h

CAN1 Mailbox 14: Da ta Field

XXh

D2E7h XXh

D2E8h XXh

D2E9h XXh

D2EAh XXh

D2EBh XXh

D2ECh XXh

D2EDh XXh

D2EEh CAN1 Mailbox 14: Time Stamp XXh

D2EFh XXh

D2F0h

CAN1 Mailbox 15: Messag e Identifier

C1MB15

XXh

D2F1h XXh

D2F2h XXh

D2F3h XXh

D2F4h

D2F5h CAN1 Mailbox 15: Data Length XXh

D2F6h

CAN1 Mailbox 15: Da ta Field

XXh

D2F7h XXh

D2F8h XXh

D2F9h XXh

D2FAh XXh

D2FBh XXh

D2FCh XXh

D2FDh XXh

D2FEh CAN1 Mailbox 15: Time Stamp XXh

D2FFh XXh

D300h

CAN1 Mailbox16: Message Identifier

C1MB16

XXh

D301h XXh

D302h XXh

D303h XXh

D304h

D305h CAN1 Mailbox 16: Data Length XXh

D306h

CAN1 Mailbox 16: Da ta Field

XXh

D307h XXh

D308h XXh

D309h XXh

D30Ah XXh

D30Bh XXh

D30Ch XXh

D30Dh XXh

D30Eh CAN1 Mailbox 16: Time Stamp XXh

D30Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 58 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 27 SFR Inform ation (27) (1)

Address Register Symbol Reset Value

D310h

CAN1 Mailbox 17: Messag e Identifier

C1MB17

XXh

D311h XXh

D312h XXh

D313h XXh

D314h

D315h CAN1 Mailbox 17: Data Length XXh

D316h

CAN1 Mailbox 17: Da ta Field

XXh

D317h XXh

D318h XXh

D319h XXh

D31Ah XXh

D31Bh XXh

D31Ch XXh

D31Dh XXh

D31Eh CAN1 Mailbox 17: Time Stamp XXh

D31Fh XXh

D320h

CAN1 Mailbox 18: Messag e Identifier

C1MB18

XXh

D321h XXh

D322h XXh

D323h XXh

D324h

D325h CAN1 Mailbox 18: Data Length XXh

D326h

CAN1 Mailbox 18: Da ta Field

XXh

D327h XXh

D328h XXh

D329h XXh

D32Ah XXh

D32Bh XXh

D32Ch XXh

D32Dh XXh

D32Eh CAN1 Mailbox 18: Time Stamp XXh

D32Fh XXh

D330h

CAN1 Mailbox 19: Messag e Identifier

C1MB19

XXh

D331h XXh

D332h XXh

D333h XXh

D334h

D335h CAN1 Mailbox 19: Data Length XXh

D336h

CAN1 Mailbox 19: Da ta Field

XXh

D337h XXh

D338h XXh

D339h XXh

D33Ah XXh

D33Bh XXh

D33Ch XXh

D33Dh XXh

D33Eh CAN1 Mailbox 19: Time Stamp XXh

D33Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 59 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 28 SFR Inform ation (28) (1)

Address Register Symbol Reset Value

D340h

CAN1 Mailbox 20: Messag e Identifier

C1MB20

XXh

D341h XXh

D342h XXh

D343h XXh

D344h

D345h CAN1 Mailbox 20: Data Length XXh

D346h

CAN1 Mailbox 20: Da ta Field

XXh

D347h XXh

D348h XXh

D349h XXh

D34Ah XXh

D34Bh XXh

D34Ch XXh

D34Dh XXh

D34Eh CAN1 Mailbox 20: Time Stamp XXh

D34Fh XXh

D350h

CAN1 Mailbox 21: Messag e Identifier

C1MB21

XXh

D351h XXh

D352h XXh

D353h XXh

D354h

D355h CAN1 Mailbox 21: Data Length XXh

D356h

CAN1 Mailbox 21: Da ta Field

XXh

D357h XXh

D358h XXh

D359h XXh

D35Ah XXh

D35Bh XXh

D35Ch XXh

D35Dh XXh

D35Eh CAN1 Mailbox 21: Time Stamp XXh

D35Fh XXh

D360h

CAN1 Mailbox 22: Messag e Identifier

C1MB22

XXh

D361h XXh

D362h XXh

D363h XXh

D364h

D365h CAN1 Mailbox 22: Data Length XXh

D366h

CAN1 Mailbox 22: Da ta Field

XXh

D367h XXh

D368h XXh

D369h XXh

D36Ah XXh

D36Bh XXh

D36Ch XXh

D36Dh XXh

D36Eh CAN1 Mailbox 22: Time Stamp XXh

D36Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 60 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 29 SFR Inform ation (29) (1)

Address Register Symbol Reset Value

D370h

CAN1 Mailbox 23: Messag e Identifier

C1MB23

XXh

D371h XXh

D372h XXh

D373h XXh

D374h

D375h CAN1 Mailbox 23: Data Length XXh

D376h

CAN1 Mailbox 23: Da ta Field

XXh

D377h XXh

D378h XXh

D379h XXh

D37Ah XXh

D37Bh XXh

D37Ch XXh

D37Dh XXh

D37Eh CAN1 Mailbox 23: Time Stamp XXh

D37Fh XXh

D380h

CAN1 Mailbox 24: Messag e Identifier

C1MB24

XXh

D381h XXh

D382h XXh

D383h XXh

D384h

D385h CAN1 Mailbox 24: Data Length XXh

D386h

CAN1 Mailbox 24: Da ta Field

XXh

D387h XXh

D388h XXh

D389h XXh

D38Ah XXh

D38Bh XXh

D38Ch XXh

D38Dh XXh

D38Eh CAN1 Mailbox 24: Time Stamp XXh

D38Fh XXh

D390h

CAN1 Mailbox 25: Messag e Identifier

C1MB25

XXh

D391h XXh

D392h XXh

D393h XXh

D394h

D395h CAN1 Mailbox 25: Data Length XXh

D396h

CAN1 Mailbox 25: Da ta Field

XXh

D397h XXh

D398h XXh

D399h XXh

D39Ah XXh

D39Bh XXh

D39Ch XXh

D39Dh XXh

D39Eh CAN1 Mailbox 25: Time Stamp XXh

D39Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 61 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 30 SFR Inform ation (30) (1)

Address Register Symbol Reset Value

D3A0h

CAN1 Mailbox 26: Messag e Identifier

C1MB26

XXh

D3A1h XXh

D3A2h XXh

D3A3h XXh

D3A4h

D3A5h CAN1 Mailbox 26: Data Length XXh

D3A6h

CAN1 Mailbox 26: Da ta Field

XXh

D3A7h XXh

D3A8h XXh

D3A9h XXh

D3AAh XXh

D3ABh XXh

D3ACh XXh

D3ADh XXh

D3AEh CAN1 Mailbox 26: Time Stamp XXh

D3AFh XXh

D3B0h

CAN1 Mailbox 27: Messag e Identifier

C1MB27

XXh

D3B1h XXh

D3B2h XXh

D3B3h XXh

D3B4h

D3B5h CAN1 Mailbox 27: Data Length XXh

D3B6h

CAN1 Mailbox 27: Da ta Field

XXh

D3B7h XXh

D3B8h XXh

D3B9h XXh

D3BAh XXh

D3BBh XXh

D3BCh XXh

D3BDh XXh

D3BEh CAN1 Mailbox 27: Time Stamp XXh

D3BFh XXh

D3C0h

CAN1 Mailbox 28: Messag e Identifier

C1MB28

XXh

D3C1h XXh

D3C2h XXh

D3C3h XXh

D3C4h

D3C5h CAN1 Mailbox 28: Data Length XXh

D3C6h

CAN1 Mailbox 28: Da ta Field

XXh

D3C7h XXh

D3C8h XXh

D3C9h XXh

D3CAh XXh

D3CBh XXh

D3CCh XXh

D3CDh XXh

D3CEh CAN1 Mailbox 28: Time Stamp XXh

D3CFh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 62 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 31 SFR Inform ation (31) (1)

Address Register Symbol Reset Value

D3D0h

CAN1 Mailbox 29: Messag e Identifier

C1MB29

XXh

D3D1h XXh

D3D2h XXh

D3D3h XXh

D3D4h

D3D5h CAN1 Mailbox 29: Data Length XXh

D3D6h

CAN1 Mailbox 29: Da ta Field

XXh

D3D7h XXh

D3D8h XXh

D3D9h XXh

D3DAh XXh

D3DBh XXh

D3DCh XXh

D3DDh XXh

D3DEh CAN1 Mailbox 29: Time Stamp XXh

D3DFh XXh

D3E0h

CAN1 Mailbox 30: Messag e Identifier

C1MB30

XXh

D3E1h XXh

D3E2h XXh

D3E3h XXh

D3E4h

D3E5h CAN1 Mailbox 30: Data Length XXh

D3E6h

CAN1 Mailbox 30: Da ta Field

XXh

D3E7h XXh

D3E8h XXh

D3E9h XXh

D3EAh XXh

D3EBh XXh

D3ECh XXh

D3EDh XXh

D3EEh CAN1 Mailbox 30: Time Stamp XXh

D3EFh XXh

D3F0h

CAN1 Mailbox 31: Messag e Identifier

C1MB31

XXh

D3F1h XXh

D3F2h XXh

D3F3h XXh

D3F4h

D3F5h CAN1 Mailbox 31: Data Length XXh

D3F6h

CAN1 Mailbox 31: Da ta Field

XXh

D3F7h XXh

D3F8h XXh

D3F9h XXh

D3FAh XXh

D3FBh XXh

D3FCh XXh

D3FDh XXh

D3FEh CAN1 Mailbox 31: Time Stamp XXh

D3FFh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 63 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 32 SFR Inform ation (32) (1)

Address Register Symbol Reset Value

D400h

CAN1 Mask Register 0 C1MKR0

XXh

D401h XXh

D402h XXh

D403h XXh

D404h

CAN1 Mask Register 1 C1MKR1

XXh

D405h XXh

D406h XXh

D407h XXh

D408h

CAN1 Mask Register 2 C1MKR2

XXh

D409h XXh

D40Ah XXh

D40Bh XXh

D40Ch

CAN1 Mask Register 3 C1MKR3

XXh

D40Dh XXh

D40Eh XXh

D40Fh XXh

D410h

CAN1 Mask Register 4 C1MKR4

XXh

D411h XXh

D412h XXh

D413h XXh

D414h

CAN1 Mask Register 5 C1MKR5

XXh

D415h XXh

D416h XXh

D417h XXh

D418h

CAN1 Mask Register 6 C1MKR6

XXh

D419h XXh

D41Ah XXh

D41Bh XXh

D41Ch

CAN1 Mask Register 7 C1MKR7

XXh

D41Dh XXh

D41Eh XXh

D41Fh XXh

D420h

CAN1FIFO Receive ID Compare Register 0 C1FIDCR0

XXh

D421h XXh

D422h XXh

D423h XXh

D424h

CAN1FIFO Receive ID Compare Register 1 C1FIDCR1

XXh

D425h XXh

D426h XXh

D427h XXh

D428h

CAN1 Mask Invalid Register C1MKIVLR

XXh

D429h XXh

D42Ah XXh

D42Bh XXh

D42Ch

CAN1 Mailbox Interrupt Enable Register C1MIER

XXh

D42Dh XXh

D42Eh XXh

D42Fh XXh

D430h to

D49Fh X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 64 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 33 SFR Inform ation (33) (1)

Address Register Symbol Reset Value

D4A0h CAN1 Message Control Register 0 C1MCTL0 00h

D4A1h CAN1 Message Control Register 1 C1MCTL1 00h

D4A2h CAN1 Message Control Register 2 C1MCTL2 00h

D4A3h CAN1 Message Control Register 3 C1MCTL3 00h

D4A4h CAN1 Message Control Register 4 C1MCTL4 00h

D4A5h CAN1 Message Control Register 5 C1MCTL5 00h

D4A6h CAN1 Message Control Register 6 C1MCTL6 00h

D4A7h CAN1 Message Control Register 7 C1MCTL7 00h

D4A8h CAN1 Message Control Register 8 C1MCTL8 00h

D4A9h CAN1 Message Control Register 9 C1MCTL9 00h

D4AAh CAN1 Message Control Register 10 C1MCTL10 00h

D4ABh CAN1 Message Control Register 11 C1MCTL11 00h

D4ACh CAN1 Message Control Register 12 C1MCTL12 00h

D4ADh CAN1 Message Control Register 13 C1MCTL13 00h

D4AEh CAN1 Message Control Register 14 C1MCTL14 00h

D4AFh CAN1 Message Control Register 15 C1MCTL15 00h

D4B0h CAN1 Message Control Register 16 C1MCTL16 00h

D4B1h CAN1 Message Control Register 17 C1MCTL17 00h

D4B2h CAN1 Message Control Register 18 C1MCTL18 00h

D4B3h CAN1 Message Control Register 19 C1MCTL19 00h

D4B4h CAN1 Message Control Register 20 C1MCTL20 00h

D4B5h CAN1 Message Control Register 21 C1MCTL21 00h

D4B6h CAN1 Message Control Register 22 C1MCTL22 00h

D4B7h CAN1 Message Control Register 23 C1MCTL23 00h

D4B8h CAN1 Message Control Register 24 C1MCTL24 00h

D4B9h CAN1 Message Control Register 25 C1MCTL25 00h

D4BAh CAN1 Message Control Register 26 C1MCTL26 00h

D4BBh CAN1 Message Control Register 27 C1MCTL27 00h

D4BCh CAN1 Message Control Register 28 C1MCTL28 00h

D4BDh CAN1 Message Control Register 29 C1MCTL29 00h

D4BEh CAN1 Message Control Register 30 C1MCTL30 00h

D4BFh CAN1 Message Control Register 31 C1MCTL31 00h

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 65 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 34 SFR Inform ation (34) (1)

Address Register Symbol Reset Value

D4C0h CAN1 Control Register C1CTLR 0000 0101b

D4C1h 00h

D4C2h CAN1 Status Register C1STR 0000 0101b

D4C3h 00h

D4C4h CAN1 Bit Configuration Register C1BCR 00h

D4C5h 00h

D4C6h 00h

D4C7h CAN1 Clock Select Register C1CLKR 00h

D4C8h CAN1 Receive FIFO Control Register C1RFCR 10000000b

D4C9h CAN1 Receive FIFO Pointer Control Register C1RFPCR XXh

D4CAh CAN1 Transmit FIFO Control Register C1TFCR 1000 0000b

D4CBh CAN1 Transmit FIFO Pointer Control Register C1TFPCR XXh

D4CCh CAN1 Error Interrupt Enable Register C1EIER 00h

D4CDh CAN1 Error Interrupt Source Judge Register C1EIFR 00h

D4CEh CAN1 Receive Error Count Register C1RECR 00h

D4CFh CAN1 Transmit Error Count Register C1TECR 00h

D4D0h CAN1 Error Code Store Register C1ECSR 00h

D4D1h CAN1 Channel Search Support Register C1CSSR XXh

D4D2h CAN1 Mailbox Search Status Register C1MSSR 1000 0000b

D4D3h CAN1 Mailbox Search Mode Register C1MSMR 0000 0000b

D4D4h CAN1 Time Stamp Register C1TSR 00h

D4D5h 00h

D4D6h CAN1 Acceptance Filter Support Register C1AFSR XXh

D4D7h XXh

D4D8h CAN1 Test Control Register C1TCR 00h

D4D9h

D4DAh

D4DBh

D4DCh

D4DDh

D4DEh

D4DFh

D4E0h to

D4FFh X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 66 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 35 SFR Inform ation (35) (1)

Address Register Symbol Reset Value

D500h

CAN0 Mailbox 0: Message Identifier

C0MB0

XXh

D501h XXh

D502h XXh

D503h XXh

D504h

D505h CAN0 Mailbox 0: Data Length XXh

D506h

CAN0 Mailbox 0: Data Field

XXh

D507h XXh

D508h XXh

D509h XXh

D50Ah XXh

D50Bh XXh

D50Ch XXh

D50Dh XXh

D50Eh CAN0 Mailbox 0: Time Stamp XXh

D50Fh XXh

D510h

CAN0 Mailbox 1: Message Identifier

C0MB1

XXh

D511h XXh

D512h XXh

D513h XXh

D514h

D515h CAN0 Mailbox 1: Data Length XXh

D516h

CAN0 Mailbox 1: Data Field

XXh

D517h XXh

D518h XXh

D519h XXh

D51Ah XXh

D51Bh XXh

D51Ch XXh

D51Dh XXh

D51Eh CAN0 Mailbox 1: Time Stamp XXh

D51Fh XXh

D520h

CAN0 Mailbox 2: Message Identifier

C0MB2

XXh

D521h XXh

D522h XXh

D523h XXh

D524h

D525h CAN0 Mailbox 2: Data Length XXh

D526h

CAN0 Mailbox 2: Data Field

XXh

D527h XXh

D528h XXh

D529h XXh

D52Ah XXh

D52Bh XXh

D52Ch XXh

D52Dh XXh

D52Eh CAN0 Mailbox 2: Time Stamp XXh

D52Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 67 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 36 SFR Inform ation (36) (1)

Address Register Symbol Reset Value

D530h

CAN0 Mailbox 3: Message Identifier

C0MB3

XXh

D531h XXh

D532h XXh

D533h XXh

D534h

D535h CAN0 Mailbox 3: Data Length XXh

D536h

CAN0 Mailbox 3: Data Field

XXh

D537h XXh

D538h XXh

D539h XXh

D53Ah XXh

D53Bh XXh

D53Ch XXh

D53Dh XXh

D53Eh CAN0 Mailbox 3: Time Stamp XXh

D53Fh XXh

D540h

CAN0 Mailbox 4: Message Identifier

C0MB4

XXh

D541h XXh

D542h XXh

D543h XXh

D544h

D545h CAN0 Mailbox 4: Data Length XXh

D546h

CAN0 Mailbox 4: Data Field

XXh

D547h XXh

D548h XXh

D549h XXh

D54Ah XXh

D54Bh XXh

D54Ch XXh

D54Dh XXh

D54Eh CAN0 Mailbox 4: Time Stamp XXh

D54Fh XXh

D550h

CAN0 Mailbox 5: Message Identifier

C0MB5

XXh

D551h XXh

D552h XXh

D553h XXh

D554h

D555h CAN0 Mailbox 5: Data Length XXh

D556h

CAN0 Mailbox 5: Data Field

XXh

D557h XXh

D558h XXh

D559h XXh

D55Ah XXh

D55Bh XXh

D55Ch XXh

D55Dh XXh

D55Eh CAN0 Mailbox 5: Time Stamp XXh

D55Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 68 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 37 SFR Inform ation (37) (1)

Address Register Symbol Reset Value

D560h

CAN0 Mailbox 6: Message Identifier

C0MB6

XXh

D561h XXh

D562h XXh

D563h XXh

D564h

D565h CAN0 Mailbox 6: Data Length XXh

D566h

CAN0 Mailbox 6: Data Field

XXh

D567h XXh

D568h XXh

D569h XXh

D56Ah XXh

D56Bh XXh

D56Ch XXh

D56Dh XXh

D56Eh CAN0 Mailbox 6: Time Stamp XXh

D56Fh XXh

D570h

CAN0 Mailbox 7: Message Identifier

C0MB7

XXh

D571h XXh

D572h XXh

D573h XXh

D574h

D575h CAN0 Mailbox 7: Data Length XXh

D576h

CAN0 Mailbox 7: Data Field

XXh

D577h XXh

D578h XXh

D579h XXh

D57Ah XXh

D57Bh XXh

D57Ch XXh

D57Dh XXh

D57Eh CAN0 Mailbox 7: Time Stamp XXh

D57Fh XXh

D580h

CAN0 Mailbox 8: Message Identifier

C0MB8

XXh

D581h XXh

D582h XXh

D583h XXh

D584h

D585h CAN0 Mailbox 8: Data Length XXh

D586h

CAN0 Mailbox 8: Data Field

XXh

D587h XXh

D588h XXh

D589h XXh

D58Ah XXh

D58Bh XXh

D58Ch XXh

D58Dh XXh

D58Eh CAN0 Mailbox 8: Time Stamp XXh

D58Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 69 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 38 SFR Inform ation (38) (1)

Address Register Symbol Reset Value

D590h

CAN0 Mailbox 9: Message Identifier

C0MB9

XXh

D591h XXh

D592h XXh

D593h XXh

D594h

D595h CAN0 Mailbox 9: Data Length XXh

D596h

CAN0 Mailbox 9: Data Field

XXh

D597h XXh

D598h XXh

D599h XXh

D59Ah XXh

D59Bh XXh

D59Ch XXh

D59Dh XXh

D59Eh CAN0 Mailbox 9: Time Stamp XXh

D59Fh XXh

D5A0h

CAN0 Mailbox 10: Messag e Identifier

C0MB10

XXh

D5A1h XXh

D5A2h XXh

D5A3h XXh

D5A4h

D5A5h CAN0 Mailbox 10: Data Length XXh

D5A6h

CAN0 Mailbox 10: Da ta Field

XXh

D5A7h XXh

D5A8h XXh

D5A9h XXh

D5AAh XXh

D5ABh XXh

D5ACh XXh

D5ADh XXh

D5AEh CAN0 Mailbox 10: Time Stamp XXh

D5AFh XXh

D5B0h

CAN0 Mailbox 11: Message Identifier

C0MB11

XXh

D5B1h XXh

D5B2h XXh

D5B3h XXh

D5B4h

D5B5h CAN0 Mailbox 11: Data Length XXh

D5B6h

CAN0 Mailbox 11: Data Field

XXh

D5B7h XXh

D5B8h XXh

D5B9h XXh

D5BAh XXh

D5BBh XXh

D5BCh XXh

D5BDh XXh

D5BEh CAN0 Mailbox 11: Time Stamp XXh

D5BFh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 70 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 39 SFR Inform ation (39) (1)

Address Register Symbol Reset Value

D5C0h

CAN0 Mailbox 12: Messag e Identifier

C0MB12

XXh

D5C1h XXh

D5C2h XXh

D5C3h XXh

D5C4h

D5C5h CAN0 Mailbox 12: Data Length XXh

D5C6h

CAN0 Mailbox 12: Da ta Field

XXh

D5C7h XXh

D5C8h XXh

D5C9h XXh

D5CAh XXh

D5CBh XXh

D5CCh XXh

D5CDh XXh

D5CEh CAN0 Mailbox 12: Time Stamp XXh

D5CFh XXh

D5D0h

CAN0 Mailbox 13: Messag e Identifier

C0MB13

XXh

D5D1h XXh

D5D2h XXh

D5D3h XXh

D5D4h

D5D5h CAN0 Mailbox 13: Data Length XXh

D5D6h

CAN0 Mailbox 13: Da ta Field

XXh

D5D7h XXh

D5D8h XXh

D5D9h XXh

D5DAh XXh

D5DBh XXh

D5DCh XXh

D5DDh XXh

D5DEh CAN0 Mailbox 13: Time Stamp XXh

D5DFh XXh

D5E0h

CAN0 Mailbox 14: Messag e Identifier

C0MB14

XXh

D5E1h XXh

D5E2h XXh

D5E3h XXh

D5E4h

D5E5h CAN0 Mailbox 14: Data Length XXh

D5E6h

CAN0 Mailbox 14: Da ta Field

XXh

D5E7h XXh

D5E8h XXh

D5E9h XXh

D5EAh XXh

D5EBh XXh

D5ECh XXh

D5EDh XXh

D5EEh CAN0 Mailbox 14: Time Stamp XXh

D5EFh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 71 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 40 SFR Inform ation (40) (1)

Address Register Symbol Reset Value

D5F0h

CAN0 Mailbox 15: Messag e Identifier

C0MB15

XXh

D5F1h XXh

D5F2h XXh

D5F3h XXh

D5F4h

D5F5h CAN0 Mailbox 15: Data Length XXh

D5F6h

CAN0 Mailbox 15: Da ta Field

XXh

D5F7h XXh

D5F8h XXh

D5F9h XXh

D5FAh XXh

D5FBh XXh

D5FCh XXh

D5FDh XXh

D5FEh CAN0 Mailbox 15: Time Stamp XXh

D5FFh XXh

D600h

CAN0 Mailbox 16: Messag e Identifier

C0MB16

XXh

D601h XXh

D602h XXh

D603h XXh

D604h

D605h CAN0 Mailbox 16: Data Length XXh

D606h

CAN0 Mailbox 16: Da ta Field

XXh

D607h XXh

D608h XXh

D609h XXh

D60Ah XXh

D60Bh XXh

D60Ch XXh

D60Dh XXh

D60Eh CAN0 Mailbox 16: Time Stamp XXh

D60Fh XXh

D610h

CAN0 Mailbox 17: Messag e Identifier

C0MB17

XXh

D611h XXh

D612h XXh

D613h XXh

D614h

D615h CAN0 Mailbox 17: Data Length XXh

D616h

CAN0 Mailbox 17: Da ta Field

XXh

D617h XXh

D618h XXh

D619h XXh

D61Ah XXh

D61Bh XXh

D61Ch XXh

D61Dh XXh

D61Eh CAN0 Mailbox 17: Time Stamp XXh

D61Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 72 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 41 SFR Inform ation (41) (1)

Address Register Symbol Reset Value

D620h

CAN0 Mailbox 18: Messag e Identifier

C0MB18

XXh

D621h XXh

D622h XXh

D623h XXh

D624h

D625h CAN0 Mailbox 18: Data Length XXh

D626h

CAN0 Mailbox 18: Da ta Field

XXh

D627h XXh

D628h XXh

D629h XXh

D62Ah XXh

D62Bh XXh

D62Ch XXh

D62Dh XXh

D62Eh CAN0 Mailbox 18: Time Stamp XXh

D62Fh XXh

D630h

CAN0 Mailbox 19: Messag e Identifier

C0MB19

XXh

D631h XXh

D632h XXh

D633h XXh

D634h

D635h CAN0 Mailbox 19: Data Length XXh

D636h

CAN0 Mailbox 19: Da ta Field

XXh

D637h XXh

D638h XXh

D639h XXh

D63Ah XXh

D63Bh XXh

D63Ch XXh

D63Dh XXh

D63Eh CAN0 Mailbox 19: Time Stamp XXh

D63Fh XXh

D640h

CAN0 Mailbox 20: Messag e Identifier

C0MB20

XXh

D641h XXh

D642h XXh

D643h XXh

D644h

D645h CAN0 Mailbox 20: Data Length XXh

D646h

CAN0 Mailbox 20: Da ta Field

XXh

D647h XXh

D648h XXh

D649h XXh

D64Ah XXh

D64Bh XXh

D64Ch XXh

D64Dh XXh

D64Eh CAN0 Mailbox 20: Time Stamp XXh

D64Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 73 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 42 SFR Inform ation (42) (1)

Address Register Symbol Reset Value

D650h

CAN0 Mailbox 21: Messag e Identifier

C0MB21

XXh

D651h XXh

D652h XXh

D653h XXh

D654h

D655h CAN0 Mailbox 21: Data Length XXh

D656h

CAN0 Mailbox 21: Da ta Field

XXh

D657h XXh

D658h XXh

D659h XXh

D65Ah XXh

D65Bh XXh

D65Ch XXh

D65Dh XXh

D65Eh CAN0 Mailbox 21: Time Stamp XXh

D65Fh XXh

D660h

CAN0 Mailbox 22: Messag e Identifier

C0MB22

XXh

D661h XXh

D662h XXh

D663h XXh

D664h

D665h CAN0 Mailbox 22: Data Length XXh

D666h

CAN0 Mailbox 22: Da ta Field

XXh

D667h XXh

D668h XXh

D669h XXh

D66Ah XXh

D66Bh XXh

D66Ch XXh

D66Dh XXh

D66Eh CAN0 Mailbox 22: Time Stamp XXh

D66Fh XXh

D670h

CAN0 Mailbox 23: Messag e Identifier

C0MB23

XXh

D671h XXh

D672h XXh

D673h XXh

D674h

D675h CAN0 Mailbox 23: Data Length XXh

D676h

CAN0 Mailbox 23: Da ta Field

XXh

D677h XXh

D678h XXh

D679h XXh

D67Ah XXh

D67Bh XXh

D67Ch XXh

D67Dh XXh

D67Eh CAN0 Mailbox 23: Time Stamp XXh

D67Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 74 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 43 SFR Inform ation (43) (1)

Address Register Symbol Reset Value

D680h

CAN0 Mailbox 24: Messag e Identifier

C0MB24

XXh

D681h XXh

D682h XXh

D683h XXh

D684h

D685h CAN0 Mailbox 24: Data Length XXh

D686h

CAN0 Mailbox 24: Da ta Field

XXh

D687h XXh

D688h XXh

D689h XXh

D68Ah XXh

D68Bh XXh

D68Ch XXh

D68Dh XXh

D68Eh CAN0 Mailbox 24: Time Stamp XXh

D68Fh XXh

D690h

CAN0 Mailbox 25: Messag e Identifier

C0MB25

XXh

D691h XXh

D692h XXh

D693h XXh

D694h

D695h CAN0 Mailbox 25: Data Length XXh

D696h

CAN0 Mailbox 25: Da ta Field

XXh

D697h XXh

D698h XXh

D699h XXh

D69Ah XXh

D69Bh XXh

D69Ch XXh

D69Dh XXh

D69Eh CAN0 Mailbox 25: Time Stamp XXh

D69Fh XXh

D6A0h

CAN0 Mailbox 26: Messag e Identifier

C0MB26

XXh

D6A1h XXh

D6A2h XXh

D6A3h XXh

D6A4h

D6A5h CAN0 Mailbox 26: Data Length XXh

D6A6h

CAN0 Mailbox 26: Da ta Field

XXh

D6A7h XXh

D6A8h XXh

D6A9h XXh

D6AAh XXh

D6ABh XXh

D6ACh XXh

D6ADh XXh

D6AEh CAN0 Mailbox 26: Time Stamp XXh

D6AFh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 75 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 44 SFR Inform ation (44) (1)

Address Register Symbol Reset Value

D6B0h

CAN0 Mailbox 27: Messag e Identifier

C0MB27

XXh

D6B1h XXh

D6B2h XXh

D6B3h XXh

D6B4h

D6B5h CAN0 Mailbox 27: Data Length XXh

D6B6h

CAN0 Mailbox 27: Da ta Field

XXh

D6B7h XXh

D6B8h XXh

D6B9h XXh

D6BAh XXh

D6BBh XXh

D6BCh XXh

D6BDh XXh

D6BEh CAN0 Mailbox 27: Time Stamp XXh

D6BFh XXh

D6C0h

CAN0 Mailbox 28: Messag e Identifier

C0MB28

XXh

D6C1h XXh

D6C2h XXh

D6C3h XXh

D6C4h

D6C5h CAN0 Mailbox 28: Data Length XXh

D6C6h

CAN0 Mailbox 28: Da ta Field

XXh

D6C7h XXh

D6C8h XXh

D6C9h XXh

D6CAh XXh

D6CBh XXh

D6CCh XXh

D6CDh XXh

D6CEh CAN0 Mailbox 28: Time Stamp XXh

D6CFh XXh

D6D0h

CAN0 Mailbox 29: Messag e Identifier

C0MB29

XXh

D6D1h XXh

D6D2h XXh

D6D3h XXh

D6D4h

D6D5h CAN0 Mailbox 29: Data Length XXh

D6D6h

CAN0 Mailbox 29: Da ta Field

XXh

D6D7h XXh

D6D8h XXh

D6D9h XXh

D6DAh XXh

D6DBh XXh

D6DCh XXh

D6DDh XXh

D6DEh CAN0 Mailbox 29: Time Stamp XXh

D6DFh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 76 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 45 SFR Inform ation (45) (1)

Address Register Symbol Reset Value

D6E0h

CAN0 Mailbox 30: Messag e Identifier

C0MB30

XXh

D6E1h XXh

D6E2h XXh

D6E3h XXh

D6E4h

D6E5h CAN0 Mailbox 30: Data Length XXh

D6E6h

CAN0 Mailbox 30: Da ta Field

XXh

D6E7h XXh

D6E8h XXh

D6E9h XXh

D6EAh XXh

D6EBh XXh

D6ECh XXh

D6EDh XXh

D6EEh CAN0 Mailbox 30: Time Stamp XXh

D6EFh XXh

D6F0h

CAN0 Mailbox 31: Messag e Identifier

C0MB31

XXh

D6F1h XXh

D6F2h XXh

D6F3h XXh

D6F4h

D6F5h CAN0 Mailbox 31: Data Length XXh

D6F6h

CAN0 Mailbox 31: Da ta Field

XXh

D6F7h XXh

D6F8h XXh

D6F9h XXh

D6FAh XXh

D6FBh XXh

D6FCh XXh

D6FDh XXh

D6FEh CAN0 Mailbox 31: Time Stamp XXh

D6FFh XXh

D700h

CAN0 Mask Register 0 C0MKR0

XXh

D701h XXh

D702h XXh

D703h XXh

D704h

CAN0 Mask Register 1 C0MKR1

XXh

D705h XXh

D706h XXh

D707h XXh

D708h

CAN0 Mask Register 2 C0MKR2

XXh

D709h XXh

D70Ah XXh

D70Bh XXh

D70Ch

CAN0 Mask Register 3 C0MKR3

XXh

D70Dh XXh

D70Eh XXh

D70Fh XXh

X: Undefined

R01DS0019EJ0110 Rev.1.10 Page 77 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 46 SFR Inform ation (46) (1)

Address Register Symbol Reset Value

D710h

CAN0 Mask Register 4 C0MKR4

XXh

D711h XXh

D712h XXh

D713h XXh

D714h

CAN0 Mask Register 5 C0MKR5

XXh

D715h XXh

D716h XXh

D717h XXh

D718h

CAN0 Mask Register 6 C0MKR6

XXh

D719h XXh

D71Ah XXh

D71Bh XXh

D71Ch

CAN0 Mask Register 7 C0MKR7

XXh

D71Dh XXh

D71Eh XXh

D71Fh XXh

D720h

CAN0 FIFO Receive ID Compare Register 0 C0FIDCR 0

XXh

D721h XXh

D722h XXh

D723h XXh

D724h

CAN0 FIFO Receive ID Compare Register 1 C0FIDCR 1

XXh

D725h XXh

D726h XXh

D727h XXh

D728h

CAN0 Mask Invalid Register C0MKIVLR

XXh

D729h XXh

D72Ah XXh

D72Bh XXh

D72Ch

CAN0 Mailbox Interrupt Enable Register C0MIER

XXh

D72Dh XXh

D72Eh XXh

D72Fh XXh

D730h to

D79Fh

D7A0h CAN0 Message Control Register 0 C0MCTL0 00h

D7A1h CAN0 Message Control Register 1 C0MCTL1 00h

D7A2h CAN0 Message Control Register 2 C0MCTL2 00h

D7A3h CAN0 Message Control Register 3 C0MCTL3 00h

D7A4h CAN0 Message Control Register 4 C0MCTL4 00h

D7A5h CAN0 Message Control Register 5 C0MCTL5 00h

D7A6h CAN0 Message Control Register 6 C0MCTL6 00h

D7A7h CAN0 Message Control Register 7 C0MCTL7 00h

D7A8h CAN0 Message Control Register 8 C0MCTL8 00h

D7A9h CAN0 Message Control Register 9 C0MCTL9 00h

D7AAh CAN0 Message Control Register 10 C0MCTL10 00h

D7ABh CAN0 Message Control Register 11 C0MCTL11 00h

D7ACh CAN0 Message Control Register 12 C0MCTL12 00h

D7ADh CAN0 Message Control Register 13 C0MCTL13 00h

D7AEh CAN0 Message Control Register 14 C0MCTL14 00h

D7AFh CAN0 Message Control Register 15 C0MCTL15 00h

X: Undefined

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Note:

1. The blank ar ea s are r ese rv e d. No ac c e s s is allowed.

Tab le 4. 47 SFR Inform ation (47) (1)

Address Register Symbol Reset Value

D7B0h CAN0 Message Control Register 16 C0MCTL16 00h

D7B1h CAN0 Message Control Register 17 C0MCTL17 00h

D7B2h CAN0 Message Control Register 18 C0MCTL18 00h

D7B3h CAN0 Message Control Register 19 C0MCTL19 00h

D7B4h CAN0 Message Control Register 20 C0MCTL20 00h

D7B5h CAN0 Message Control Register 21 C0MCTL21 00h

D7B6h CAN0 Message Control Register 22 C0MCTL22 00h

D7B7h CAN0 Message Control Register 23 C0MCTL23 00h

D7B8h CAN0 Message Control Register 24 C0MCTL24 00h

D7B9h CAN0 Message Control Register 25 C0MCTL25 00h

D7BAh CAN0 Message Control Register 26 C0MCTL26 00h

D7BBh CAN0 Message Control Register 27 C0MCTL27 00h

D7BCh CAN0 Message Control Register 28 C0MCTL28 00h

D7BDh CAN0 Message Control Register 29 C0MCTL29 00h

D7BEh CAN0 Message Control Register 30 C0MCTL30 00h

D7BFh CAN0 Message Control Register 31 C0MCTL31 00h

D7C0h CAN0 Control Register C0CTLR 0000 0101b

D7C1h 00h

D7C2h CAN0 Status Register C0STR 0000 0101b

D7C3h 00h

D7C4h CAN0 Bit Configuration Register C0BCR 00h

D7C5h 00h

D7C6h 00h

D7C7h CAN0 Clock Select Register C0CLKR 00h

D7C8h CAN0 Receive FIFO Control Register C0RFCR 1000 0000b

D7C9h CAN0 Receive FIFO Pointer Control Register C0RFPCR XXh

D7CAh CAN0 Transmit FIFO Control Register C0TFCR 1000 0000b

D7CBh CAN0 Transmit FIFO pointer Control Register C0TFPCR XXh

D7CCh CAN0 Error Interrupt Enable Register C0EIER 00h

D7CDh CAN0 Error Interrupt Source Judge Register C0EIFR 00h

D7CEh CAN0 Receive Error Count Register C0RECR 00h

D7CFh CAN0 Transmit Error Count Register C0TECR 00h

D7D0h CAN0 Error Code Store Register C0ECSR 00h

D7D1h CAN0 Channel Search Support Register C0CSSR XXh

D7D2h CAN0 Mailbox Search Status Register C0MSSR 1000 0000b

D7D3h CAN0 Mailbox Search Mode Register C0MSMR 0000 0000b

D7D4h CAN0 Time Stamp Register C0TSR 00h

D7D5h 00h

D7D6h CAN0 Acceptance Filter Support Register C0AFSR XXh

D7D7h XXh

D7D8h CAN0 Test Control Register C0TCR 00h

D7D9h

D7DAh

D7DBh

D7DCh

D7DDh

D7DEh

D7DFh X: Undefined

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

4.2 Notes on SFRs

4.2.1 Register Settings

Table 4.48 lists Register s with W rite-Only Bit s a nd registers whose function dif fers between reading and

writing. Set these registers with immediate values . Do not use read-modify-write instructions. When

establishing the next value by altering the existing value, write the existing value to the RAM as well as

to the register. Transfer the next value to the register after making changes in the RAM.

Read-modify-write instructions can be used when writing to the no register bit s.

Table 4.48 Registers with Write-Only Bits

Address Register Symbol

0249h UART0 Bit Rate Register U0BRG

024Bh to 024Ah UART0 Transmit Buffer Register U0TB

0259h UART1 Bit Rate Register U1BRG

025Bh to 025Ah UART1 Transmit Buffer Register U1TB

0269h UART2 Bit Rate Register U2BRG

026Bh to 026Ah UART2 Transmit Buffer Register U2TB

0299h UART4 Bit Rate Register U4BRG

029Bh to 029Ah UART4 Transmit Buffer Register U4TB

02A9h UART3 Bit Rate Register U3BRG

02ABh to 02AAh UART3 Transmit Buffer Register U3TB

02B6h I2C0 Control Register 1 S3D0

02B8h I2C0 Status Register 0 S10

0303h to 0302h Timer A1-1 Register TA11

0305h to 0304h Timer A2-1 Register TA21

0307h to 0306h Timer A4-1 Register TA41

030Ah Three-Phase Output Buffer Register 0 IDB0

030Bh Three-Phase Output Buffer Register 1 IDB1

030Ch Dead Time Timer DTT

030Dh Timer B2 Interrupt Generation Frequency Set Counter ICTB2

0327h to 0326h Timer A0 Register TA0

0329h to 0328h Timer A1 Register TA1

032Bh to 032Ah Timer A2 Register TA2

032Dh to 032Ch Timer A3 Register TA3

032Fh to 032Eh Ti mer A4 Register TA4

037Dh Watchdog T imer Refresh Register WDTR

037Eh Watchdog Timer Start Reg i st er WDTS

D4C9h CAN1 Receive FIFO Pointer Control Register C1RFPCR

D4CBh CAN1 Transmit FIFO Pointer Control Register C1TFPCR

D7C9h CAN0 Receive FIFO Pointer Control Register C0RFPCR

D7CBh CAN0 Transmit FIFO pointer Control Register C0TFPCR

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M16C/5M Group, M16C/57 Group 4. Special Function Registers (SFRs)

Table 4.49 Read-Modify-Write Instructions

Function Mnemonic

Transfer MOVDir

Bit processing BCLR, BMCnd, BNOT, BSET, BTSTC, and BTSTS

Shifting ROLC, RORC, ROT, SHA, and SHL

Arithmetic operation ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG,

SBB, and SUB

Decimal operation DADC, DADD, DSBB, and DSUB

Logical operation AND, NOT, OR, and XOR

Jump ADJNZ, SBJNZ

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

5. Electrical Characteristics J-Version

5.1 Electrical Characteristics (J-Version, Common to 3 V and 5 V)

5.1.1 Absolute Maximum Rating

Note:

1. Maximum value is 6.5 V.

Table 5.1 Absolute Maximum Ratings

Symbol Characteristic Condition Rated Value Unit

VCC Supply voltage VCC = AVCC -0.3 to 6.5 V

AVCC Analog supply voltage VCC = AVCC -0.3 to 6.5 V

VREF Analog reference voltage −0.3 to VCC + 0.1 (1) V

VIInput voltage

P0_0 to P0_7, P1_0 to

P1_7, P2_0 to P2_7, P3_0

to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to

P6_7, P7_0 to P7_7, P8_0

to P8_7, P9_0 toP9_7,

P10_0 to P10_7

XIN, RESET, CNVSS

-0.3 to VCC + 0.3 V

Output

voltage

P0_0 to P0_7, P1_0 to

P1_7, P2_0 to P2_7, P3_0

to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to

P6_7, P7_0 to P7_7, P8_0

to P8_7, P9_0 to P9_7,

P10_0 to P10_7

XOUT

-0.3 to VCC + 0.3 V

PdPower

consumption -40°C ≤ Topr ≤ 85°C 300 mW

Topr

Operating

temperature

range

While CPU operation -40 to 85

°C

While flash memory

program and erase

operation

Programming area 0 to 60

Data area -40 to 85

Tstg S torage temperature range -65 to 150 °C

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

5.1.2 Recommended Operating Conditions

Notes:

1. The mean output current is the mean value within 100 ms.

2. Refer to Figure 5.1 “Main clock input oscillation frequency, PLL clock oscillation frequency” for the relationship between main

clock oscillation frequency/PLL clock oscillation frequency and supply voltage.

Table 5.2 Operating Conditions (1)

VCC = 3.0 V to 5.5 V, Topr = -40°C to 85°C unless otherwise specified.

Symbol Characteristic Standard Unit

Min. Typ. Max.

VCC Supply voltage 3.0 5.5 V

AVCC Analog supply voltage VCC V

VSS Ground voltage 0V

AVSS Analog ground voltage 0V

VIH High level

input voltage

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7

Input level 0.50 VCC 0.7 VCC VCC V

Input level 0.70 VCC 0.85VCC VCC V

XIN, RESET, CNVSS 0.8 VCC VCC

SDAMM, SCLMM When I2C-bus input level selected 0.7 VCC VCC V

When SMBUS input level selected 2.1 VCC V

VIL Low level input

voltage

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7

Input level 0.50 VCC 00.3 VCC V

Input level 0.70 VCC 00.45VCC V

XIN, RESET, CNVSS 00.2 VCC V

SDAMM, SCLMM When I2C-bus input level selected 00.3 VCC V

When SMBUS input level selected 0 0.8 V

IOH(sum) High peak

output current

Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 -80.0 mA

IOH(peak)

High level

peak output

current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to

P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 -10.0 mA

IOH(avg)

High level

average output

current (1)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to

P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 -5.0 mA

IOL(sum) Low peak

output current

Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 80.0 mA

IOL(peak) Low level peak

output current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to

P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7 10.0 mA

IOL(avg)

Low level

average output

current (1)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to

P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7 5.0 mA

f(XIN) Main clock input oscillation frequency (2) 020MHz

f(XCIN) Sub clock oscillation frequency 32.768 50 kHz

f(PLL) PLL clock oscillation frequency (2) 10 32 MHz

f(BCLK) CPU operation frequency 0 32 MHz

tsu(PLL) Wait time to stabilize PLL frequency synthesizer 1 ms

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

Figure 5.1 Main clock input oscillation frequency, PLL clock oscillation frequency

Note:

1. The device is opera tio nally guaranteed under these operating con d ition s.

Figure 5.2 Ripple Waveform

Table 5.3 Recommended Operating Conditions (2/2) (1)

VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40°C to 85°C unless otherwise specified.

The ripple voltage must not exceed Vr(VCC) and/or dVr(VCC)/dt.

Symbol Parameter Standard Unit

Min. Typ. Max.

Vr(VCC) Allow ab l e ri pp l e voltage VCC = 5.0 V 0.5 Vp-p

VCC = 3.0 V 0.3 Vp-p

dVr(VCC)/dt Ripple voltage falling gradient VCC = 5.0 V 0.3 V/ms

VCC = 3.0 V 0.3 V/ms

maxim um operating fr equency [MHz]

Main clock input oscillation frequency PLL clock oscillation frequency

20.0

10.0

0.0

32.0

10.0

0.0

maximum operatin g freque n cy [MHz]

3.0 5.5

Vcc [V] (main clock: no division) Vcc [V] (PLL clo ck oscillation)

32.0 MHz

20.0 MHz

f(XIN)

Vr ( )

VCC

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

5.1.3 A/D Conversion Characteristics

Notes:

1. Use when AVCC = VCC

2. Flash memory rewrite disabled. Except for the analog input pin , se t the pin s to be me as ured as input

ports and connect them to VSS. See Figure 5.3 “A/D Accuracy Meas ur e Circuit”.

3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.

Figure 5.3 A/D Accuracy Measure Circuit

Table 5.4 A/D Conversion Characteristics (1)

VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40°C to 85°C unle ss othe r wise spe cified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

—– Resolution VREF = VCC 10 Bits

INL Integral non-linearity error VREF = VCC = 5.0 V (2) ±3 LSB

VREF = VCC = 3.3 V (2) ±5 LSB

—– Absolute accuracy VREF = VCC = 5.0 V (2) ±3 LSB

VREF = VCC = 3.3 V (2) ±5 LSB

φAD A/D operating clock frequency

4.0 V ≤ VCC ≤ 5.5 V 225MHz

3.2 V ≤ VCC ≤ 4.0 V 216MHz

3.0 V ≤ VCC ≤ 3.2 V 210MHz

—– Tolerance level impedance 3 kΩ

DNL Differential non-linearity error Se e no te 2 ±1 LSB

—– Offset error See note 2 ±3 LSB

—– Gain error Se e no te 2 ±3 LSB

tCONV 10-bit conversion time VREF = VCC = 5V,

φAD = 25 MHz 1.60 μs

tSAMP Sampling time 0.6 μs

VREF Reference voltage 3.0 VCC V

VIA Analog input voltage (3) 0VREF V

AN Analog input

AN: One of the analog input pin

P0 to P10: I/O pins other than AN

P0 to P10

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

5.1.4 D/A Conversion Characteristics

Notes:

1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.

2. The current consumption of the A/D converter is not included. Also, t he IVREF of the D/A converter will flow even

if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).

Table 5.5 D/A Conversion Characteristics

VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40°C to 85°C unle ss othe r wise spe cified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

- Resolution 8Bits

- Absolut e accuracy 2.5 LSB

tSU Setup time 3μs

ROOutput resistance 568.2k

IVREF Reference power supply input current See Notes 1 and 21.5 mA

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

5.1.5 Flash Memory Electrical Characteristics

Notes:

1. Set the PM17 bit in the PM1 register to 1 (one wait).

2. When the frequency is over this value , set th e FMR17 bit i n the FMR1 regist er to 0 (one wait ) or the PM1 7 bit in

the PM1 register to 1 (one wait)

3. Set the PM17 bit in the PM1 register to 1 (one wait). When using the 125 kHz on-chip oscillator clock or sub

clock as the CPU clock source, a wait is no t necessary.

Table 5.6 CPU Clock When Operating Flash Memory (f(BCLK))

VCC = 3.0 to 5.5 V at Topr = -40°C to 85°C, unless otherwise specified.

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

- CPU rewrite mode 16 (1) MHz

f(SLOW_R) Slow read mod e 5 (3) MHz

- Low current consu mp ti o n read mod e fC 35 kHz

Data flash read 20 (2) MHz

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

Notes:

1. Definition of program and erase cycles:

The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n

(n = 1,000), each block can be erased n time s. Fo r example, if a 64 KB block is erased after writing 2 word data

16,384 times, each to a different address, this counts as one pro gram and erase cycle s. Data cannot be written

to the same address more than on ce without erasing the block (rewrite prohibited).

2. Cycles to guarantee all elect rical characteristics after program and erase. (1 to Min. value can be guaranteed).

3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing

to sequential addresse s in turn so that as much of the block as possib le is used up before performing an erase

operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase

operations to a certain number.

4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the

block erase command at least thre e times until the erase error does not occur.

5. Customers desiring pro gram/erase failure rate information should contact a Renesas Electronics sales office.

6. The data hold time includes time t hat the power supply is off or the clock is not supplied.

7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the

erase seque nce cannot be completed.

Table 5.7 Flash Memory (Program ROM 1, 2) Electrical Characteristics

VCC = 3.0 to 5.5 V at Topr = 0°C to 60°C, unless otherwise specified.

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

-Program/erase cycles (1, 3, 4) VCC = 3.3 V, Topr = 25°C1,000 (2) times

- 2 words program time VCC = 3.3 V, Topr = 25°C150 4000 μs

Lock bit program time VCC = 3.3 V, Topr = 25°C70 3000 μs

- Block erase time VCC = 3.3 V, Topr = 25°C0.2 3.0 s

td(SR-SUS) Time delay from suspend request

until suspend ms

- Interval from erase start/restart

until following suspend request 0μs

-Suspend interval necessary for

auto-erasure to comp lete (7) 20 ms

- Time from suspend until erase

restart μs

- Program, erase voltage 3.0 5.5 V

- Read voltage Topr = -40°C to 85°C3.0 5.5 V

- Program, erase temperature 0 60 °C

tPS Flash memory circuit stabilization wait time 50 μs

-Data hold time (6) Ambient temperature = 55°C 20 year

fBCLK()

----------------+

30 1

fBCLK()

----------------+

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

1. Definition of program and erase cycles

The program and erase cycles refer to the number of per-block erasures.

If the program and erase cycles are n (n = 10,000), each block can be erased n times.

For example, if a 4 KB block is erased after writing 2 word data 1,024 times, each to a different address, this

counts as one program and erase cycles. Data cannot be written to the same address more than once without

erasing the block (rewrite prohibited).

2. Cycles to guarantee all elect rical characteristics after program and erase. (1 to Min. value can be guaranteed).

3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing

to sequential addresse s in turn so that as much of the block as possib le is used up before performing an erase

operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be

minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the

erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain

data on the erasure cycles of each block and limit the number of erase operations to a certain number.

4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the

block erase command at least thre e times until the erase error does not occur.

5. Customers desiring pro gram/erase failure rate information should contact a Renesas Electronics sales office.

6. The data hold time includes time t hat the power supply is off or the clock is not supplied.

7. After an erase start or erase restart, if an interval of at least 2 0 ms is not set before the next suspen d request,

the erase sequence cannot be completed.

Table 5.8 Flash Memory (Data Flash) Electrical Characteristics

VCC = 3.0 to 5.5 V at Topr = -40°C to 85°C, unless otherwise specified.

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

-Program/erase cycles (1, 3, 4) VCC = 3.3 V, Topr = 25°C10,000 (2) times

- 2 words program time VCC = 3.3 V, Topr = 25°C300 4000 μs

- Lo ck bi t pr og ra m tim e VCC = 3.3 V, Topr = 25°C140 3000 μs

- B lo ck erase time VCC = 3.3 V, Topr = 25°C0.2 3.0 s

td(SR-SUS) Time delay from suspend request

until suspend ms

- Interval from erase start/restart until

following suspend request 0μs

-Suspend interval necessary for

auto-erasure to complete (7) 20 ms

- Time from suspend until erase

restart μs

- Program, erase voltage 3.0 5.5 V

- Read voltage 3.0 5.5 V

- Program, erase temperature −40 85 °C

tPS Flash memory circuit stabilization wait time 50 μs

-Data hold time (6) Ambient temperature = 55°C20 year

fBCLK()

----------------+

30 1

fBCLK()

----------------+

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

5.1.6 E2PROM Emulation Data Flash

Notes:

1. Definition of program/erase cycles definition

This value represents the number of erasure per block.

If the flash memory is programmed/erased n times, each block can be erased n times.

i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it

is considered the programming/erasure is performed just once. However a write in the same

address more than once for one erasure is disabled. (overwrite disab l ed).

2. The data hold time includes the periods when the supply voltage is not applied and no clock is

provided.

3. This data hold time includes (7000) hours in Ambient temperature = 85°C.

4. Please contact a Renesas Electronics sales office regarding data retention time other than the

above.

Table 5.9 E2PROM Emulation Data Flash Electrical Characteristics

VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40°C to 85°C unless otherwise specified.

Symbol Characteristic Standard Unit

Min. Typ. Max.

—Program/erase cycles (1) 100000 times

— Word program time (2-byte program) 100 2000 µs

— Read time (2-byte read) 1 µs

— Block erase time (32-byte block) 15 200 ms

tPS Flash memory circuit stabilization wait time

(sleep mode to normal mode) 50 µs

—Data hold time (2) Ambient temperat ure = 55°C (3, 4) 20 years

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

5.1.7 Voltage Detector and Power Supply Circuit Electrical Characteristics

Note:

1. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2

Note:

1. Necessary time until t he voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2

Table 5.10 Voltage Detector 0 Electrical Characteristics

The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 85°C, unless otherwise specified.

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet0 Voltage detection level Vdet0 When VCC is falling. 2.70 2.85 3.00 V

td(E-A) Waiting time until voltage detector operation

starts (1) VCC = 3.0 to 5.0 V 100 μs

Table 5.11 Voltage Detector 2 Electrical Characteristics

The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 85°C, unless otherwise specified.

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet2_0 Voltage detection level Vdet2_0

When VCC is falling

3.21 V

Vdet2_1 Voltage detection level Vdet2_1 3.36 V

Vdet2_2 Voltage detection level Vdet2_2 3.51 V

Vdet2_3 Voltage detection level Vdet2_3 3.66 V

Vdet2_4 Voltage detection level Vdet2_4 3.51 3.81 4.11 V

Vdet2_5 Voltage detection level Vdet2_5 3.96 V

Vdet2_6 Voltage detection level Vdet2_6 4.10 V

Vdet2_7 Voltage detection level Vdet2_7 4.25 V

-Hysteresis width at the rising of VCC in voltage

detector 2 0.15 V

td(E-A) Waiting time until voltage detector operation starts (1) VCC = 3.0 to 5.0 V 100 μs

R01DS0019EJ0110 Rev.1.10 Page 91 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

Note:

1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address

to 0.

Figure 5.4 Power-On Reset Circuit Electrical Characteristics

Note:

1. When VCC = 5 V.

Table 5.12 Power-On Reset Circuit

The measurement condition is Topr = -40°C to 85°C, unless otherwise specified.

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

trth External power VCC rise gradient 2.0 50000 mV/ms

tfth External power VCC fall gradient 50000 mV/ms

Vpor Voltage at which power-on reset enabled (1) 0.1 V

tw(por) Hold time at which power-on reset enabled 1.0 ms

Table 5.13 Power Supply Circuit Timing Characteristics

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

td(P-R) Time for internal power supply stabilization

during powering-on VCC = 3.0 V to 5.5V

5ms

td(R-S) STOP release time 300 μs

td(W-S) Low power mode wait mode release time 300 μs

Vpor

Internal

reset signal

OCO-S

× 128

External Power V

det0 t

rth

w(por)

rth V

det0

OCO-S

× 128

fth

R01DS0019EJ0110 Rev.1.10 Page 92 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version

Figure 5.5 Power Supply Circuit Timing Diagram

5.1.8 Oscillator Electrical Characteristics

Table 5.14 On-Chip Oscillator Electrical Characteristics

VCC = 3.0 to 5.5 V, Topr = −40°C to 85°C, unless otherwise specified

Symbol Characteristic Standard Unit

Min. Typ. Max.

fOCO-S 125 kHz on-chip oscillator oscillation frequency 100 125 150 kHz

fOCO40M 40 MHz on-chip oscillator oscillation frequency 32 40 48 MHz

fWDT Dedicated 125 kHz on-chip oscillator for the watchdog timer oscillation

frequency 100 125 150 kHz

CPU clock

Time to stabilize internal supply

voltage du rin g powering-on

(a) Interrupt to ex it fro m sto p mo de

(b) Interrupt to ex it fro m wa it m ode

CPU clock (a)

(b)

Stop Operate

Recommended

operating

voltage

Voltage detection circuit

d(P-R)

STOP release time

d(R-S)

d(W-S)

Low power consump tion

mode wait mode exit time

Voltage de te ction circuit

operatio n s tart time

d(E-A)

d(P- R)

d(R-S )

td(W-S)

d(E-A)

VCC

VC25, VC27

R01DS0019EJ0110 Rev.1.10 Page 93 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

5.2 Electrical Characteristics (J-Version, VCC = 5 V)

5.2.1 Electrical Characteristics J-Version, VCC = 5 V

Table 5.15 Electrical Characteristics (1)

VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.

Symbol Parameter Measuring Condit ion Standard Unit

Min. Typ. Max.

VOH

HIGH output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7

IOH=−5 mA VCC−2.0 VCC V

VOH

HIGH output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7,P9_0 to P9_7, P10_0 to P10_7

IOH = −200 μAV

CC−−0.3 VCC V

VOH

HIGH output voltage XOUT HIGH POWER IOH = −1 mA VCC−−2.0 VCC V

LOW POWER IOH = −0.5 mA VCC−−2.0 VCC

HIGH output voltage XCOUT HIGH POWER With no load applied 2.5 V

LOW POWER With no load applied 1.6

VOL

LOW output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

IOL = 5 mA 2.0 V

VOL

LOW output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

IOL = 200 μA0.45 V

VOL

LOW output voltage XOUT HIGH POWER IOL = 1 mA 2.0 V

LOW POWER IOL = 0.5 mA 2.0

LOW output voltage XCOUT HIGH POWER With no load applied 0 V

LOW POWER With no load applied 0

VT+-VT- Hysteresis

TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7,

NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2,

CLK0 to CLK4, TA0OU T to TA4 OUT,

KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV,

SD, INPC1_0 to INPC1_7, SSI0, SSCK0 , SCS0,

LIN0IN, CRX0, CRX1

0.2 0.4VCC V

VT+-VT- Hysteresis RESET 0.2 2.5 V

VT+-VT- Hysteresis XIN 0.2 0.8 V

IIH HIGH input current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

XIN, RESET, CNVSS

VI = 5 V 5.0 μA

IIL LOW input current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

XIN, RESET, CNVSS

VI = 0 V −5.0 μA

RPULLUP Pull-up

resistance

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7

VI = 0 V 30 50 170 kΩ

RfXIN Feedback resistance XIN 1.5 MΩ

RfXCIN Feedback resistance XCIN 15 MΩ

VRAM RAM retention vol tage At stop mode 2.0 V

R01DS0019EJ0110 Rev.1.10 Page 94 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Note: 1. This indicates the memo ry in which the progra m to be ex ec uted exists.

Table 5.16 Electrical Characteristics (2)

Topr = −40°C to 85°C unless otherwise specified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

ICC

Power supply

current

= 4.2V to 5.5

In single-chip

mode, the output

pins are open and

other pins are

VSS

High speed mode

f(BCLK) = 32 MHz,

XIN = 8 MHz (square wave), PLL multiply-by-8

125 kHz on-chip oscillator operating 25 45 mA

f(BCLK) = 20 MHz,

XIN = 20 MHz (square wave),

125 kHz on-chip oscillator operating 21 39 mA

f(BCLK) = 16 MHz,

XIN = 16 MHz (square wave),

125 kHz on-chip oscillator operating 17 mA

40 MHz on-chip oscillator

mode

Main clock stopped

40 MHz on-chip oscillator operating

125 kHz on-chip oscillator operating

No division

21 39 mA

Main clock stopped

40 MHz on-chip oscillator operating

125 kHz on-chip oscillator operating

Divide-by-8

6mA

125 kHz on-chip oscillator

mode

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Divide-by-8

FMR22 = FMR23 = 1 (Low-current

consumption read mode)

190 580 μA

Low powe r mo de

f(BCLK) = 32 kHz

On Flash memory (2)

FMR22 = FMR23 = 1 (Low-current

consumption read mode)

200 μA

Wait mode

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 25°C

25 μA

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 85°C

55 μA

Stop mode Topr = 25°C315

μA

Topr = 85°C30 μA

During flash memory

program f(BCLK) = 10 MHz, PM17 = 1 (one wait)

VCC = 5.0 V 20.0 mA

During flash memory

erase f(BCLK) = 10 MHz, PM17 = 1 (one wait)

VCC = 5.0 V 30.0 mA

Idet2 Low voltage detection dissipation current 3

μA

Idet0 Reset area detection dissipation current 6

μA

R01DS0019EJ0110 Rev.1.10 Page 95 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

5.2.2 Timing Requirements (Peripheral Functions and Others)

(VCC = 5 V, VSS = 0 V, at Topr = -40°C to 85°C unless otherwise specifie d)

5.2.2.1 Reset Input (RESET Input)

Figure 5.6 Reset Input (RESET Input)

5.2.2.2 External Clock Input

Note:

1. The condition is VCC = 5.0V.

Figure 5.7 External Clock Input (XIN Input)

Table 5.17 Reset Input (RESET Input)

Symbol Parameter Standard Unit

Min. Max.

tw(RSTL) RESET input low pulse width 10 μs

Table 5.18 External Clock Input (XIN Input) (1)

Symbol Parameter Standard Unit

Min. Max.

tcExternal clock input cycle time 50 ns

tw(H) External clock input high pulse width 20 ns

tw(L) External clock input low pulse width 20 ns

trExternal clock rise time 9ns

tfExternal clock fall time 9ns

RESET input

w(RTSL)

XIN input

w(H)

r t

f t

w(L)

R01DS0019EJ0110 Rev.1.10 Page 96 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.2.2.3 Timer A Input

Figure 5.8 Timer A Input

Table 5.19 Timer A Input (Counter Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 100 ns

tw(TAH) TAiIN input high pulse width 40 ns

tw(TAL) TAiIN input low pulse width 40 ns

Table 5.20 Timer A Input (Gating Input in Timer Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 400 ns

tw(TAH) TAiIN input high pulse width 200 ns

tw(TAL) TAiIN input low pulse width 200 ns

Table 5.21 Timer A Input (External Trigger Input in One-Shot Timer Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 200 ns

tw(TAH) TAiIN input high pulse width 100 ns

tw(TAL) TAiIN input low pulse width 100 ns

Table 5.22 Timer A Input (External Trigger Input in PWM Mode, Programmable Outp ut Mode)

Symbol Parameter Standard Unit

Min. Max.

tw(TAH) TAiIN input high pulse width 100 ns

tw(TAL) TAiIN input low pulse width 100 ns

TAiIN input

TAiOUT input

w(TAH)

c(TA)

w(TAL)

c(UP)

w(UPH)

w(UPL)

R01DS0019EJ0110 Rev.1.10 Page 97 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

Figure 5.9 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Table 5.23 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 800 ns

tsu(TAIN-TAOUT)

TAiOUT input setup time 200 ns

tsu(TAOUT-TAIN)

TAiIN input setup time 200 ns

TAiIN input

Two-phase pulse input in event counter mode

TAiOUT input

c(TA)

su(TAIN-TAOUT) t

su(TAIN-TAOUT)

su(TAOUT-TAIN)

R01DS0019EJ0110 Rev.1.10 Page 98 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.2.2.4 Timer B Input

Figure 5.10 Timer B Input

Table 5.24 Timer B Input (Counter Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time (counted on one edge) 100 ns

tw(TBH) TBiIN input high pulse width (counted on one edge) 40 ns

tw(TBL) TBiIN input low pulse width (counted on one edge) 40 ns

tc(TB) TBiIN input cycle time (counted on both edges) 200 ns

tw(TBH) TBiIN input high pulse width (counted on both edges) 80 ns

tw(TBL) TBiIN Input low pulse width (counted on both edges) 80 ns

Table 5.25 Timer B Input (Pulse Period Measurement Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time 400 ns

tw(TBH) TBiIN input high pulse width 200 ns

tw(TBL) TBiIN input low pulse width 200 ns

Table 5.26 Timer B Input (Pulse Width Measurement Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time 400 ns

tw(TBH) TBiIN input high pulse width 200 ns

tw(TBL) TBiIN input low pulse width 200 ns

TBiIN input

c(TB)

w(TBH)

w(TBL)

R01DS0019EJ0110 Rev.1.10 Page 99 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.2.2.5 Timer S Input

Figure 5.11 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)

Table 5.27 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)

Symbol Parameter Standard Unit

Min. Max.

tw(TSH) TSUDA, TSUDB input high pulse width 2μs

tw(TSL)

TSUDA, TSUDB input low pulse width 2μs

tsu(TSUDA-TSUDB)

TSUDB input setup time 1μs

tsu(TSUDB-TSUDA)

TSUDA input setup time 1μs

TSUDA input

Two-phase pulse input in two-phase pul se signal processing mode

w(TSH)

su(TSUDA-TSUDB)

TSUDB input

w(TSL)

su(TSUDA-TSUDB)

su(TSUDB-TSUDA)

su(TSUDB-TSUDA)t

w(TSL)

w(TSH)

Note:

1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)

are also interchanged.

R01DS0019EJ0110 Rev.1.10 Page 100 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.2.2.6 Serial Interface

Figure 5.12 Serial Interface

5.2.2.7 External Interrupt INTi Input

Figure 5.13 External Interrupt INTi Input

Table 5. 28 Seria l Int e rf ac e

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 200 ns

tw(CKH) CLKi input high pulse width 100 ns

tw(CKL) CLKi input low pulse width 100 ns

td(C-Q) TXDi output delay time 80 ns

th(C-Q) TXDi hold time 0ns

tsu(D-C) RXDi input setup time 70 ns

th(C-D) RXDi input hold time 90 ns

Table 5.29 Ext ern al Interru pt INTi Input

Symbol Parameter Standard Unit

Min. Max.

tw(INH) INTi input high pulse width 250 ns

tw(INL) INTi input low pulse width 250 ns

CLKi

TXDi

RXDi

c(CK)

w(CKH)

w(CKL) t

h(C-Q)

d(C-Q) t

su (D-C) t

h(C-D)

INTi input

w(INL)

w(INH)

R01DS0019EJ0110 Rev.1.10 Page 101 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.2.2.8 Multi-master I2C-bus

Figure 5.14 Multi-master I2C-bus

Table 5. 30 M u lt i-master I2C-bus

Symbol Parameter Standard Clock Mode Fast-mode Unit

Min. Max. Min. Max.

tBUF Bus free time 4.7 1.3 μs

tHD;STA Hold time in start condition 4.0 0.6 μs

tLOW Hold time in SCL clock 0 status 4.7 1.3 μs

tRSCL, SDA signals’ rising time 1000 20 + 0.1 Cb 300 ns

tHD;DAT Data hold time 000.9

μs

tHIGH Hold time in SCL clock 1 status 4.0 0.6 μs

fFSCL, SDA signals’ falling time 300 20 + 0.1 Cb 300 ns

tsu;DAT Data setup time 250 100 ns

tsu;STA Setup time in restart condition 4.7 0.6 μs

tsu;STO Stop condition setup time 4.0 0.6 μs

SDA

SCL p

ps Sr

LOW

HD;STA t

HD;DAT t

HIGH t

su;DAT t

su;STA

R t

HD;STA t

su;STO

BUF

R01DS0019EJ0110 Rev.1.10 Page 102 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.2.2.9 Serial bus interface

Note:

1. 1 tCYC is 1/f1 (s).

Table 5.31 Serial Bus Interface

Symbol Characteristic Measurement

condition Standard Unit

Min. Typ. Max.

tc(SSCK) SSCK clock cycle time 250 ns

tw(SSCKH) SSCK clock high pulse width 0.4 0.6 tc(SSCK)

tw(SSCKL) SSCK clock low pulse width 0.4 0.6 tc(SSCK)

tr(SSCK) SSCK clock ri sing time Master 1 tCYC (1)

Slave 1 μs

tf(SSCK) SSCK clock falling time Master 1 tCYC (1)

Slave 1 μs

tsu(SSIO-SSCK) SSO, SSI data input setup time 100 ns

th(SSCK-SSIO) SSO, SSI data input hold time 1 tCYC (1)

tsu(SCS-SSCK) SCS setup time Slave 1 tCYC + 50 (1) ns

th(SSCK-SCS) SCS hold time Slave 1 tCYC + 50 (1) ns

td(SSCK-SSIO) SSO, SSI data output delay

time Master 1 tCYC (1)

Slave 80 ns

ten(SCS-SSI) SSI output enable time 3.0 V ≤ VCC ≤ 5.5 V 1.5 tCYC + 100 (1) ns

tdis(SCS-SSI) SSI output disable time 3.0 V ≤ VCC ≤ 5.5 V 1.5 tCYC + 100 (1) ns

R01DS0019EJ0110 Rev.1.10 Page 103 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Figure 5.15 I/O Timing of Serial Bus Interface (Master)

VIH or VOH

VIL or VOL

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS = 0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH

VIL or VOL

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS =0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 0

CPHS, CPOS: Bits in the SSMR register

w(SSCKH)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

d(SSCK-SSIO)

f(SSCK) t

r(SSCK)

su(SSIO-SSCK) t

h(SSCK-SSIO)

w(SSCKH) t

f(SSCK) t

r(SSCK)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

d(SSCK-SSIO)

su(SSIO-SSCK) t

h(SSCK-SSIO)

R01DS0019EJ0110 Rev.1.10 Page 104 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Figure 5.16 I/O Timing of Serial Bus Interface (Slave)

VIH or VOH

VIL or VOL

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH

VIL or VOL

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 0

CPHS, CPOS: Bits in the SSMR register

su(SCS-SSCK) t

w(SSCKH) t

f(SSCK) t

r(SSCK)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

su(SSIO -SSC K) t

h(SSCK-SSIO)

en(SCS-SSI) t

d(SSCK-SSIO)

h(SSCK-SCS)

dis(SCS-SSI)

su(SCS-SSCK) t

w(SSCKH) t

f(SSCK) t

r(SSCK) t

h(SSCK-SCS)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

su(SSIO-SSCK) t

h(SSCK-SSIO)

en(SCS-SSI) t

d(SSCK-SSIO) t

dis(SCS-SSI)

R01DS0019EJ0110 Rev.1.10 Page 105 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 5 V

Figure 5.17 I/O Timing of Serial Bus Interface (Synchronous Communication Mode)

Figure 5.18 Switching Characteristic Measurement Circuit

VIH or VOH

SSCK

SSO (output)

SSI (input)

VIL or VOL

w(SSCKL)

w(SSCKH)

c(SSCK)

d(SSCK-SSIO)

su(SSIO-SSCK) t

h(SSCK-SSIO)

30 pF

Pin to be

measured

MCU

R01DS0019EJ0110 Rev.1.10 Page 106 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

5.3 Electrical Characteristics (J-Version, VCC = 3 V)

5.3.1 Electrical Characteristics

J-Version, VCC = 3 V

Table 5.32 Electrical Characteristics (1)

VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = −40°C to 85°C, f(BCLK)= 32 MHz unless otherwise specified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

VOH HIGH

output

voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to P6_7, P7_0 to

P7_7, P8_0 to P8_4, P8_6 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

IOH = −1 mA VCC−0.5 VCC V

VOH

HIGH output voltage XOUT HIGH POWER IOH = −0.1 mA VCC−0.5 VCC V

LOW POWER IOH = −50 μAV

CC−0.5 VCC

HIGH output voltage XCOUT HIGH POWER With no load applied 2.5 V

LOW POWER With no load applied 1.6

VOL LOW output

voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to P6_7, P7_0 to

P7_7, P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7

IOL = 1mA 0.5 V

VOL

LOW output voltage XOUT HIGH POWER IOL = 0.1mA 0.5 V

LOW POWER IOL = 50μA0.5

LOW output voltage XCOUT HIGH POWER With no load applied 0 V

LOW POWER With no load applied 0

VT+-VT- Hysteresis

TA0IN to TA4IN, TB0IN to TB5IN, INT0

to INT7, NMI, ADTRG, CTS0 to CTS3,

SCL2, SDA2, CLK0 to CLK4, TA0OUT

to TA4OUT, KI0 to KI3, RXD0 to RXD4,

ZP, IDU, IDW, IDV, SD, INPC1_0 to

INPC1_7, SSI0, SSCK0, SCS0, LIN0IN,

CRX0, CRX1

0.4VCC V

VT+-VT- Hysteresis RESET 1.8 V

VT+-VT- Hysteresis XIN 0.8 V

IIH HIGH input

current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to P6_7, P7_0 to

P7_7, P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7

XIN, RESET, CNVSS

VI = 3V 4.0 μA

IIL LOW input

current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to P6_7, P7_0 to

P7_7, P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7

XIN, RESET, CNVSS

VI = 0V −4.0 μA

RPULLUP Pull-up

resistance

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to P6_7, P7_0 to

P7_7, P8_0 to P8_4, P8_6 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

VI = 0V 50 100 500 kΩ

RfXIN Feedback resistance XIN 3.0 MΩ

RfXCIN Feedback resistance XCIN 25 MΩ

VRAM RAM retention voltage At stop mode 2.0 V

R01DS0019EJ0110 Rev.1.10 Page 107 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Note: 1. This indicates the memory in which the program to be executed exists.

Table 5.33 Electrical Characteristics (2)

Topr = −40°C to 85°C unless otherwise specified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

ICC

Power supply

current

= 3.0 V to 3.6

In single-chip

mode, the output

pins are open and

other pins are

VSS

High speed mode

f(BCLK) = 32 MHz,

XIN = 8 MHz (square wave), PLL multiply-by-8

125 kHz on-chip oscillator operating 23 43 mA

f(BCLK) = 20 MHz,

XIN = 20 MHz (square wave),

125 kHz on-chip oscillator operating 20 38 mA

f(BCLK) = 16 MHz,

XIN = 16 MHz (square wave),

125 kHz on-chip oscillator operating 16 mA

40 MHz on-chip oscillator

mode

Main clock stopped

40 MHz on-chip oscillator operating

125 kHz on-chip oscillator operating

No division

20 38 mA

Main clock stopped

40 MHz on-chip oscillator operating

125 kHz on-chip oscillator operating

Divide-by-8

6 mA

125 kHz on-chip oscillator

mode

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Divide-by-8

FMR22 = FMR23 = 1 (Low-current

consumption read mode)

190 580 μA

Low powe r mode

f(BCLK) = 32 kHz

On Flash memory (1)

FMR22 = FMR23 = 1 (Low-current

consumption read mode)

200 μA

Wait mode

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 25°C

25 μA

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 85°C

55 μA

Stop mode Topr = 25°C212

μA

Topr = 85°C30 μA

During flash memory

program f(BCLK) = 10 MHz, PM17 = 1 (one wait)

VCC = 3.0 V 20.0 mA

During flash memory

erase f(BCLK) = 10 MHz, PM17 = 1 (one wait)

VCC = 3.0 V 30.0 mA

Idet2 Low voltage detection dissipation current 3

μA

Idet0 Reset area detection dissipation current 6

μA

R01DS0019EJ0110 Rev.1.10 Page 108 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

5.3.2 Timing Requirements (Peripheral Functions and Others)

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.3.2.1 Reset Input (RESET Input)

Figure 5.19 Reset Input (RESET Input)

5.3.2.2 External Clock Input

Note:

1. The condition is VCC = 3.0V.

Figure 5.20 External Clock Input (XIN Input)

Table 5.34 Reset Input (RESET Input)

Symbol Parameter Standard Unit

Min. Max.

tw(RSTL) RESET input low pulse width 10 μs

Table 5.35 External Clock Input (XIN input) (1)

Symbol Parameter Standard Unit

Min. Max.

tcExternal clock input cycle time 50 ns

tw(H) External clock input high pulse width 20 ns

tw(L) External clock input low pulse width 20 ns

trExternal clock rise time 9ns

tfExternal clock fall time 9ns

RESET input

w(RTSL)

XIN input

w(H)

r t

f t

w(L)

R01DS0019EJ0110 Rev.1.10 Page 109 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.3.2.3 Timer A Input

Figure 5.21 Timer A Input

Table 5.36 Timer A Input (Counter Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 150 ns

tw(TAH) TAiIN input high pulse width 60 ns

tw(TAL) TAiIN input low pulse width 60 ns

Table 5.37 Timer A Input (Gating Input in Timer Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 600 ns

tw(TAH) TAiIN input high pulse width 300 ns

tw(TAL) TAiIN input low pulse width 300 ns

Table 5.38 Timer A Input (External Trigger Input in One-Shot Timer Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 300 ns

tw(TAH) TAiIN input high pulse width 150 ns

tw(TAL) TAiIN input low pulse width 150 ns

Table 5.39 Timer A Input (External Trigger Input in PWM Mode, Programmable Outp ut Mode)

Symbol Parameter Standard Unit

Min. Max.

tw(TAH) TAiIN input high pulse width 150 ns

tw(TAL) TAiIN input low pulse width 150 ns

TAiIN input

TAiOUT input

w(TAH)

c(TA)

w(TAL)

c(UP)

w(UPH)

w(UPL)

R01DS0019EJ0110 Rev.1.10 Page 110 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

Figure 5.22 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Table 5.40 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 2μs

tsu(TAIN-TAOUT)

TAiOUT input setup time 500 ns

tsu(TAOUT-TAIN)

TAiIN input setup time 500 ns

TAiIN input

Two-phase pulse input in event counter mode

TAiOUT input

c(TA)

su(TAIN-TAOUT) t

su(TAIN-TAOUT)

su(TAOUT-TAIN)

R01DS0019EJ0110 Rev.1.10 Page 111 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.3.2.4 Timer B Input

Figure 5.23 Timer B Input

Table 5.41 Timer B Input (Counter Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time (counted on one edge) 150 ns

tw(TBH) TBiIN input high pulse width (counted on one edge) 60 ns

tw(TBL) TBiIN input low pulse width (counted on one edge) 60 ns

tc(TB) TBiIN input cycle time (counted on both edges) 300 ns

tw(TBH) TBiIN input high pulse width (counted on both edges) 120 ns

tw(TBL) TBiIN Input low pulse width (counted on both edges) 120 ns

Table 5.42 Timer B Input (Pulse Period Measurement Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time 600 ns

tw(TBH) TBiIN input high pulse width 300 ns

tw(TBL) TBiIN input low pulse width 300 ns

Table 5.43 Timer B Input (Pulse Width Measurement Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time 600 ns

tw(TBH) TBiIN input high pulse width 300 ns

tw(TBL) TBiIN input low pulse width 300 ns

TBiIN input

c(TB)

w(TBH)

w(TBL)

R01DS0019EJ0110 Rev.1.10 Page 112 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.3.2.5 Timer S Input

Figure 5.24 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)

Table 5.44 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)

Symbol Parameter Standard Unit

Min. Max.

tw(TSH) TSUDA, TSUDB input high pulse width 2μs

tw(TSL)

TSUDA, TSUDB input low pulse width 2μs

tsu(TSUDA-TSUDB)

TSUDB input setup time 1μs

tsu(TSUDB-TSUDA)

TSUDA input setup time 1μs

TSUDA input

Two-phase pu lse input in two-phase pulse signal processing mode

w(TSH)

su(TSUDA-TSUDB)

TSUDB input

w(TSL)

su(TSUDA-TSUDB)

su(TSUDB-TSUDA)

su(TSUDB-TSUDA)t

w(TSL)

w(TSH)

Note:

1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)

are also interchanged.

R01DS0019EJ0110 Rev.1.10 Page 113 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.3.2.6 Serial Interface

Figure 5.25 Serial Interface

5.3.2.7 External Interrupt INTi Input

Figure 5.26 External Interrupt INTi Input

Table 5. 45 Seria l Int e rf ac e

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 300 ns

tw(CKH) CLKi input high pulse width 150 ns

tw(CKL) CLKi input low pulse width 150 ns

td(C-Q) TXDi output delay time 160 ns

th(C-Q) TXDi hold time 0ns

tsu(D-C) RXDi input setup time 100 ns

th(C-D) RXDi input hold time 90 ns

Table 5.46 Ext ern al Interru pt INTi Input

Symbol Parameter Standard Unit

Min. Max.

tw(INH) INTi Input HIGH Pulse Width 380 ns

tw(INL) INTi Input LOW Pulse Width 380 ns

CLKi

TXDi

RXDi

c(CK)

w(CKH)

w(CKL) t

h(C-Q)

d(C-Q) t

su (D-C) t

h(C-D)

INTi input

w(INL)

w(INH)

R01DS0019EJ0110 Rev.1.10 Page 114 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.3.2.8 Multi-master I2C-bus

Figure 5.27 Multi-master I2C-bus

Table 5. 47 M u lt i-master I2C-bus

Symbol Parameter Standard Clock Mode Fast-mode Unit

Min. Max. Min. Max.

tBUF Bus free time 4.7 1.3 μs

tHD;STA Hold time in start condition 4.0 0.6 μs

tLOW Hold time in SCL clock 0 status 4.7 1.3 μs

tRSCL, SDA signals’ rising time 1000 20 + 0.1 Cb 300 ns

tHD;DAT Data hold time 000.9

μs

tHIGH Hold time in SCL clock 1 status 4.0 0.6 μs

fFSCL, SDA signals’ falling time 300 20 + 0.1 Cb 300 ns

tsu;DAT Data setup time 250 100 ns

tsu;STA Setup time in restart condition 4.7 0.6 μs

tsu;STO Stop condition setup time 4.0 0.6 μs

SDA

SCL p

ps Sr

LOW

HD;STA t

HD;DAT t

HIGH t

su;DAT t

su;STA

R t

HD;STA t

su;STO

BUF

R01DS0019EJ0110 Rev.1.10 Page 115 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 85°C unless otherwise specified)

5.3.2.9 Serial bus interface

Note:

1. 1 tCYC is 1/f1 (s).

Table 5.48 Serial Bus Interface

Symbol Characteristic Measurement

condition Standard Unit

Min. Typ. Max.

tc(SSCK) SSCK clock cycle time 250 ns

tw(SSCKH) SSCK clock high pulse width 0.4 0.6 tc(SSCK)

tw(SSCKL) SSCK clock low pulse width 0.4 0.6 tc(SSCK)

tr(SSCK) SSCK clock rising time Master 1 tCYC (1)

Slave 1 μs

tf(SSCK) SSCK clock falling time Master 1 tCYC (1)

Slave 1 μs

tsu(SSIO-SSCK) SSO, SSI data input setup time 100 ns

th(SSCK-SSIO) SSO, SSI data input hold time 1 tCYC (1)

tsu(SCS-SSCK) SCS setup time Slave 1 tCYC + 50 (1) ns

th(SSCK-SCS) SCS hold time Slave 1 tCYC + 50 (1) ns

td(SSCK-SSIO) SSO, SSI data output delay

time Master 1 tCYC (1)

Slave 80 ns

ten(SCS-SSI) SSI output enable time 3.0 V ≤ VCC ≤ 5.5 V 1.5 tCYC + 100 (1) ns

tdis(SCS-SSI) SSI output disable time 3.0 V ≤ VCC ≤ 5.5 V 1.5 tCYC + 100 (1) ns

R01DS0019EJ0110 Rev.1.10 Page 116 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Figure 5.28 I/O Timing of Serial Bus Interface (Master)

VIH or VOH

VIL or VOL

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS = 0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH

VIL or VOL

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS =0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 0

CPHS, CPOS: Bits in the SSMR register

w(SSCKH)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

d(SSCK-SSIO)

f(SSCK) t

r(SSCK)

su(SSIO-SSCK) t

h(SSCK-SSIO)

w(SSCKH) t

f(SSCK) t

r(SSCK)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

d(SSCK-SSIO)

su(SSIO-SSCK) t

h(SSCK-SSIO)

R01DS0019EJ0110 Rev.1.10 Page 117 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Figure 5.29 I/O Timing of Serial Bus Interface (Slave)

VIH or VOH

VIL or VOL

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH

VIL or VOL

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 0

CPHS, CPOS: Bits in the SSMR register

su(SCS-SSCK) t

w(SSCKH) t

f(SSCK) t

r(SSCK)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

su(SSIO -SSC K) t

h(SSCK-SSIO)

en(SCS-SSI) t

d(SSCK-SSIO)

h(SSCK-SCS)

dis(SCS-SSI)

su(SCS-SSCK) t

w(SSCKH) t

f(SSCK) t

r(SSCK) t

h(SSCK-SCS)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

su(SSIO-SSCK) t

h(SSCK-SSIO)

en(SCS-SSI) t

d(SSCK-SSIO) t

dis(SCS-SSI)

R01DS0019EJ0110 Rev.1.10 Page 118 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

J-Version, VCC = 3 V

Figure 5.30 I/O Timing of Serial Bus Interface (Synchronous Communication Mode)

Figure 5.31 Switching Characteristic Measurement Circuit

VIH or VOH

SSCK

SSO (output)

SSI (input)

VIL or VOL

w(SSCKL)

w(SSCKH)

c(SSCK)

d(SSCK-SSIO)

su(SSIO-SSCK) t

h(SSCK-SSIO)

30 pF

Pin to be

measured

MCU

R01DS0019EJ0110 Rev.1.10 Page 119 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

5.4 Electrical Characteristics (K-Version, Common to 3 V and 5 V)

5.4.1 Absolute Maximum Rating

Note:

1. Maximum value is 6.5 V.

Table 5.49 Absolute Maximum Ratings

Symbol Characteristic Condition Rated Value Unit

VCC Supply voltage VCC = AVCC -0.3 to 6.5 V

AVCC Analog supply voltage VCC = AVCC -0.3 to 6.5 V

VREF Analog reference voltage −0.3 to VCC + 0.1 (1) V

VIInput volta ge P0_0 to P0_7, P1_0 to

P1_7, P2_0 to P2_7, P3_0

to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to

P6_7, P7_0 to P7_7, P8_0

to P8_7, P9_0 to P9_7,

P10_0 to P10_7

XIN, RESET, CNVSS,

VREF

-0.3 to VCC + 0.3 V

VOOutput

voltage P0_0 to P0_7, P1_0 to

P1_7, P2_0 to P2_7, P3_0

to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to

P6_7, P7_0 to P7_7, P8_0

to P8_7, P9_0 to P9_7,

P10_0 to P10_7

XOUT

-0.3 to VCC + 0.3 V

PdPower consumption -40°C ≤ Topr ≤ 85°C 300 mW

85°C < Topr ≤ 125°C 250 mW

Topr Operating

temperature

range

While CPU operation -40 to 125 °C

While flash memory

program and erase

operation

Programming area 0 to 60

Data area -40 to 125

Tstg S torage temperature range -65 to 150 °C

R01DS0019EJ0110 Rev.1.10 Page 120 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

5.4.2 Recommended Operating Conditions

Notes:

1. The mean output current is the mean value within 100 ms.

2. Refer to “Figure 5.1 “Main clock input oscillation frequency, PLL clock oscillation frequency”” for the relationship between main

clock oscillation frequency/PLL clock oscillation frequency and supply voltage.

Table 5.50 Operating Conditions (1)

VCC = 3.0 V to 5.5 V, Topr = -40°C to 125°C unless otherwise specified.

Symbol Characteristic Standard Unit

Min. Typ. Max.

VCC Supply voltage 3.0 5.5 V

AVCC Analog supply voltage VCC V

VSS Ground voltage 0V

AVSS Analog ground voltage 0V

VIH High level input

voltage

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7

Input level 0.50 VCC 0.7 VCC VCC V

Input level 0.70 VCC 0.85VCC VCC V

XIN, RESET, CNVSS 0.8 VCC VCC

SDAMM, SCLMM When I2C-bus input level selected 0.7 VCC VCC V

When SMBUS input level selected 2.1 VCC V

VIL Low level input

voltage

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7

Input level 0.50 VCC 00.3 VCC V

Input level 0.70 VCC 00.45VCC V

XIN, RESET, CNVSS 0 0.2 VCC V

SDAMM, SCLMM When I2C-bus input level selected 00.3 VCC V

When SMBUS input level selected 0 0.8 V

IOH(sum) High peak

output current

Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 -80.0 mA

IOH(peak) High level peak

output current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to

P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 -10.0 mA

IOH(avg)

High level

average output

current (2)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to

P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 -5.0 mA

IOL(sum) Low peak

output current

Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 80.0 mA

IOL(peak) Low level peak

output current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to

P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7 10.0 mA

IOL(avg)

Low level

average output

current (2)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to

P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7 5.0 mA

f(XIN) Main clock input oscillation frequency (2) 020MHz

f(XCIN) Sub clock oscillation frequency 32.768 50 kHz

f(PLL) PLL clock oscillation frequency (2) 10 32 MHz

f(BCLK) CPU operation frequency 0 32 MHz

tsu(PLL) Wait time to stabilize PLL frequency synthesizer 1 ms

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

Figure 5.32 Main Clock Input Oscillation Frequency, PLL Clock Oscillation Frequency

Note:

1. The device is opera tionally guaranteed under these operating con d itions.

Figure 5.33 Ripple Waveform

Table 5.51 Recommended Operating Conditions (2/2) (1)

VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40°C to 125°C unless otherwise specified.

The ripple voltage must not exceed Vr(VCC) and/or dVr(VCC)/dt.

Symbol Parameter Standard Unit

Min. Typ. Max.

Vr(VCC) Allow ab l e ri pp l e voltage VCC = 5.0 V 0.5 Vp-p

VCC = 3.0 V 0.3 Vp-p

dVr(VCC)/dt Ripple voltage falling gradient VCC = 5.0 V 0.3 V/ms

VCC = 3.0 V 0.3 V/ms

maximum operating frequency [MHz]

Main clock input oscillation frequency PLL clock oscillation frequency

20.0

10.0

0.0

32.0

10.0

0.0

maximum operating frequency [MHz]

3.0 5.5

Vcc [V] (main clock: no division) Vcc [V] (PLL clock oscillation)

32.0 MHz

20.0 MHz

f(XIN)

Vr( )

VCC

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

5.4.3 A/D Conversion Characteristics

Notes:

1. Use when AVCC = VCC

2. Flash memory rewrite disabled. Except for the analog input pin , se t the pin s to be me as ured as input

ports and connect them to VSS. See Figure 5.34 “A/D Accuracy Measure Cir cuit”.

3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.

Figure 5.34 A/D Accuracy Measure Circuit

Table 5.52 A/D Conversion Characteristics (1)

VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40°C to 125°C unless otherwise specified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

—– Resolution VREF = VCC 10 Bits

INL Integral non-linearity error VREF = VCC = 5.0 V (2) ±3 LSB

VREF = VCC = 3.3 V (2) ±5 LSB

—– Absolute accuracy VREF = VCC = 5.0 V (2) ±3 LSB

VREF = VCC = 3.3 V (2) ±5 LSB

φAD A/D operating clock frequency

4.0 V ≤ VCC ≤ 5.5 V 2 25 MHz

3.2 V ≤ VCC ≤ 4.0 V 2 16 MHz

3.0 V ≤ VCC ≤ 3.2 V 2 10 MHz

—– Tolerance level impedance 3 kΩ

DNL Differential non-linearity error See note 2 ±1 LSB

—– Offset error (4) See note 2 ±3 LSB

—– Gain error (4) See note 2 ±3 LSB

tCONV 10-bit conversion time VREF = VCC = 5V,

φAD = 25 MHz 1.60 μs

tsamp Sampling time 0.6 μs

VREF Reference voltage 3.0 VCC V

VIA Analog input voltage (3) 0V

REF V

AN Analog input

AN: One of the analog input pi n

P0 to P10: I/O pins other than AN

P0 to P10

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

5.4.4 D/A Conversion Characteristics

Notes:

1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.

2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even

if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).

Table 5.53 D/A Conversion Characteristics

VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40°C to 125°C unless otherwise specified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

- Resolution 8Bits

- Absolute accuracy 2.5 LSB

tSU Setup time 3μs

ROOutput resistance 568.2k

IVREF Reference power supply input current See Notes 1 and 21.5 mA

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

5.4.5 Flash Memory Electrical Characteristics

Notes:

1. Set the PM17 bit in the PM1 register to 1 (one wait).

2. When the frequency is over this value , set th e FMR17 bit i n th e FMR1 regist er to 0 (one wait ) or the PM1 7 bit in

the PM1 register to 1 (one wait)

3. Set the PM17 bit in the PM1 register to 1 (one wait). No wait states are required if the 125 kHz on-chip oscillat or

clock or sub clock is used as the clock source of the CPU clock.

Table 5.54 CPU Clock When Operating Flash Memory (f(BCLK))

VCC = 3.0 to 5.5 V at Topr = -40°C to 125°C, unless otherwise specified.

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

- CPU rewrite mode 16 (1) MHz

f(SLOW_R) Slow read mod e 5 (3) MHz

- Low current consu mp ti o n read mod e fC 35 kHz

- Data flash read 20 (2) MHz

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

Notes:

1. Definition of program and erase cycles:

The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n

(n = 1,000), each block can be erased n time s. Fo r example, if a 64 KB block is erased after writing 2 word data

16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be written

to the same address more than on ce without erasing the block (rewrite prohibited).

2. Cycles to guarantee all elect rical characteristics afte r program and erase. (1 to Min. value can be guaranteed).

3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing

to sequential addres ses in turn so that as much of the b lock as possible is used up before perf orming an erase

operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase

operations to a certain number.

4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the

block erase command at least thre e times until the erase error does not occur.

5. Customers desiring pro gram/erase failure rate information should contact a Renesas Electronics sales office.

6. The data hold time includes time t hat the power supply is off or the clock is not supplied.

7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the

erase seque nce cannot be completed.

Table 5.55 Flash Memory (Program ROM 1, 2) Electrical Characteristics

VCC = 3.0 to 5.5 V at Topr = 0°C to 60°C, unless otherwise specified.

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

-Program/erase cycles (1, 3, 4) VCC = 3.3 V, Topr = 25°C1,000 (2) times

- 2 words program time VCC = 3.3 V, Topr = 25°C150 4000 μs

Lock bit program time VCC = 3.3 V, Topr = 25°C70 3000 μs

- Block erase time VCC = 3.3 V, Topr = 25°C0.2 3.0 s

td(SR-SUS) Time delay from suspend request

until suspend ms

- Interval from erase start/restart

until following suspend request 0μs

-Suspend interval necessary for

auto-erasure to complete (7) 20 ms

- Time from suspend until erase

restart μs

- Program, erase voltage 3.0 5.5 V

- Read voltage Topr = -40°C to 125°C3.0 5.5 V

- Program, erase temperature 0 60 °C

tPS Flash Memory Circuit St abilization Wait Time 50 μs

-Data hold time (6) Ambient temperature = 55°C 20 year

fBCLK()

----------------+

30 1

fBCLK()

----------------+

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

Notes:

1. Definition of program and erase cycles

The program and erase cycles refer to the number of per-block erasures.

If the program and erase cycles are n (n = 10,000), each block can be erased n times.

For example, if a 4 KB block is erased after writing 2 word data 1,024 times, each to a different address, this

counts as one program and erase cycles. Data cannot be written to the same address more than once without

erasing the block (rewrite prohibited).

2. Cycles to guarantee all elect rical characteristics after program and erase. (1 to Min. value can be guaranteed).

3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing

to sequential addres ses in turn so that as much of the b lock as possible is used up before perf orming an erase

operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be

minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the

erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain

data on the erasure cycles of each block and limit the number of erase operations to a certain numb er.

4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the

block erase command at least thre e times until the erase error does not occur.

5. Customers desiring pro gram/erase failure rate information should contact a Renesas Electronics sales office.

6. The data hold time includes time t hat the power supply is off or the clock is not supplied.

7. After an erase start or erase restart, if an interval of at least 2 0 ms is not set before the next suspen d request,

the erase sequence cannot be completed.

Table 5.56 Flash Memory (Data Flash) Electrical Characterist ics

VCC = 3.0 to 5.5 V at Topr = -40°C to 125°C, unless otherwise specified.

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

-Program/erase cycles (1, 3, 4) VCC = 3.3 V, Topr = 25°C10,000 (2) times

- 2 words program time VCC = 3.3 V, Topr = 25°C300 4000 μs

- Lo ck bi t pr og ra m tim e VCC = 3. 3 V, Topr = 25°C140 3000 μs

- B lo ck er ase time VCC = 3.3 V, Topr = 25°C0.2 3.0 s

td(SR-SUS) Time delay from suspend request

until suspend ms

- Interval from erase start/restart until

following suspend request 0μs

-Suspend interval necessary for

auto-erasure to complete (7) 20 ms

- Time from suspend until erase

restart μs

- Program, erase voltage 3.0 5.5 V

- Read voltage 3.0 5.5 V

- Program, erase temperature −40 125 °C

tPS Flash Memory Circuit Stabilization Wait Time 50 μs

-Data hold time (6) Ambient temperat u r e = 55 °C20 year

fBCLK()

----------------+

30 1

fBCLK()

----------------+

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

5.4.6 E2PROM Emulation Data Flash

Notes:

1. Definition of program/erase cycles definition

This value represents the number of erasure per block.

If the flash memory is programmed/erased n times, each block can be erased n times.

i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it

is considered the programming/erasure is performed just once. However a write in the same

address more than once for one erasure is disabled. (overwrite disabl ed).

2. The data hold time includes the periods when the supply voltage is not applied and no clock is

provided.

3. This data hold time includes (3000) hours in Ambient temperature = 125°C.

4. Please contact a Renesas Electronics sales office regarding data retention time other than the

above.

Table 5.57 E2PROM Emulation Data Flash Electrical Characteristics

VCC = 3.0 to 5.5 V at Topr = -40°C to 125°C, unless otherwise specified.

Symbol Characteristic Standard Unit

Min. Typ. Max.

—Program/erase cycles (1) 100000 times

— Word program time (2-byte program) 100 2000 µ s

— Read time (2-byte read) 1 µs

— Block erase time (32-byte block) 15 200 ms

tPS Flash memory circuit stabilization wait time

(sleep mode to normal mode) 35 50 µs

—Data hold time (2) Ambient temperatur e = 55 ° C (3 , 4) 20 years

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

5.4.7 Voltage Detector and Power Supply Circuit Electrical Characteristics

Note:

1. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2

Note:

1. Necessary time until the voltage detector operates after setting to 1 again after settin g the VC27 bit in the VCR2

Table 5.58 Voltage Detector 0 Electrical Characteristics

The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 125°C, unless otherwise specified.

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet0 Voltage detection level Vdet0 When VCC is falling. 2.70 2.85 3.00 V

td(E-A) Waiting time until voltage detector operation

starts (1) VCC = 3.0 to 5.0 V 100 μs

Table 5.59 Voltage Detector 2 Electrical Characteristics

The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 125°C, unless otherwise specified.

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet2_0 Voltage detection level Vdet2_0

When VCC is falling

3.21 V

Vdet2_1 Voltage detection level Vdet2_1 3.36 V

Vdet2_2 Voltage detection level Vdet2_2 3.51 V

Vdet2_3 Voltage detection level Vdet2_3 3.66 V

Vdet2_4 Voltage detection level Vdet2_4 3.51 3.81 4.11 V

Vdet2_5 Voltage detection level Vdet2_5 3.96 V

Vdet2_6 Voltage detection level Vdet2_6 4.10 V

Vdet2_7 Voltage detection level Vdet2_7 4.25 V

-Hysteresis width at the rising of VCC in voltage

detector 2 0.15 V

td(E-A) Waiting time until voltage detector operation starts (1) VCC = 3.0 to 5.0 V 100 μs

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

Note:

1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address

to 0.

Figure 5.35 Power-On Reset Circuit Electrical Characteristics

Note:

1. When VCC = 5 V.

Table 5.60 Power-On Reset Circuit

The measurement condition is Topr = -40°C to 125°C, unless otherwise specified.

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

trth External power VCC rise gradient 2.0 50000 mV/ms

tfth External power VCC fall gradient 50000 mV/ms

Vpor Voltage at which power-on reset enabled (1) 0.1 V

tw(por) Hold time at which power-on reset enabled 1.0 ms

Table 5.61 Power Supply Circuit Timing Characteristics

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

td(P-R) Time for internal power supply stabilization

during powering-on VCC = 3.0 V to 5.5V 5ms

td(R-S) STOP release time 300 μs

td(W-S) Low power mode wait mode release time 300 μs

Vpor

Internal

reset signal

OCO-S

× 128

External Power V

det0 t

rth

w(por)

rth V

det0

OCO-S

× 128

fth

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version

Figure 5.36 Power Supply Circuit Timing Diagram

5.4.8 Oscillator Electrical Characteristics

Table 5.62 On-Chip Oscillator Electrical Characteristics

VCC = 3.0 to 5.5 V, Topr = −40°C to 125°C, unless otherwise specified

Symbol Characteristic Value Unit

Min. Typ. Max.

fOCO-S 125 kHz on-chip oscillator oscillation frequency 100 125 150 kHz

fOCO40M 40 kHz on-chip oscillator oscillation frequency 32 40 48 MHz

fWDT Dedicated 125 kHz on-chip oscillator for the watchdog timer oscillation

frequency 100 125 150 kHz

CPU clock

Time to stabilize internal supply

voltage du ring powering-on

(a) Interrupt to exit from stop mode

(b) Interrupt to exit from wait mode

CPU clock (a)

(b)

Stop Operate

Recommended

operating

voltage

Voltage detection circuit

d(P-R)

STOP release time

d(R-S)

d(W-S)

Low power consumption

mode wait mode exit time

Voltage de te ction circuit

operation s tart time

d(E-A)

d(P-R)

d(R- S)

td(W-S)

d(E-A)

VC25, VC27

VCC

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

5.5 Electrical Characteristics (K-Version, VCC = 5 V)

5.5.1 Electrical Characteristics K-Version, VCC = 5 V

Table 5.63 Electrical Characteristics (1)

VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = −40°C to 125°C, f(BCLK) = 32 MHz unless otherwise specified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

VOH

HIGH output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7

IOH=−5 mA VCC−2.0 VCC V

VOH

HIGH output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7

IOH = −200 μAV

CC−−0.3 VCC V

VOH

HIGH output voltage XOUT HIGH POWER IOH = −1 mA VCC−−2.0 VCC V

LOW POWER IOH = −0.5 mA VCC−−2.0 VCC

HIGH output voltage XCOUT HIGH POWER With no load applied 2.5 V

LOW POWER With no load applied 1.6

VOL

LOW output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

IOL = 5 mA 2.0 V

VOL

LOW output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

IOL = 200 μA0.45 V

VOL

LOW output voltage XOUT HIGH POWER IOL = 1 mA 2.0 V

LOW POWER IOL = 0.5 mA 2.0

LOW output voltage XCOUT HIGH POWER With no load applied 0 V

LOW POWER With no load applied 0

VT+-VT- Hysteresis

TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7,

NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2,

CLK0 to CLK4, TA0OUT to TA4OUT,

KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV,

SD, INP C1_0 to IN PC1_7 , SSI0, S SCK0 , SCS0,

LIN0IN, CRX0, CRX1

0.2 0.4VCC V

VT+-VT- Hysteresis RESET 0.2 2.5 V

VT+-VT- Hysteresis XIN 0.2 0.8 V

IIH HIGH input current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

XIN, RESET, CNVSS

VI = 5 V 5.0 μA

IIL LOW input current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 toP9_7, P10_0 to P10_7

XIN, RESET, CNVSS

VI = 0 V −5.0 μA

RPULLUP Pull-up

resistance

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7

VI = 0 V 30 50 170 kΩ

RfXIN Feedback resistance XIN 1.5 MΩ

RfXCIN Feedback resistance XCIN 15 MΩ

VRAM RAM retention voltage At stop mode 2.0 V

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Note: 1. This indicates the memory in which the program to be executed exists.

Table 5.64 Electrical Characteristics (2)

Topr = −40°C to 125°C unless otherwise specified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

ICC

Power supply current

(VCC = 4.2 V to 5.5 V)

In single-chip mode, the

output pins are open and

other pins are VSS

High speed mode

f(BCLK) = 32 MHz,

XIN = 8 MHz (square wave), PLL multiply-by-8

125 kHz on-chip oscillator operating 25 45 mA

f(BCLK) = 20 MHz,

XIN = 20 MHz (square wave),

125 kHz on-chip oscillator operating 21 39 mA

f(BCLK) = 16 MHz,

XIN = 16 MHz (square wave),

125 kHz on-chip oscillator operating 17 mA

40 MHz on-chip oscillator

mode

Main clock stopped

40 MHz on-chip oscillator operating

125 kHz on-chip oscillator operating

No division

21 39 mA

Main clock stopped

40 MHz on-chip oscillator operating

125 kHz on-chip oscillator operating

Divide-by-8

6 mA

125 kHz on-chip oscillator

mode

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Divide-by-8

FMR22 = FMR23 = 1 (Low-current consumption

read mode)

190 580 μA

Low power mode

f(BCLK) = 32 kHz

On Flash memory (2)

FMR22 = FMR23 = 1 (Low-current consumption

read mode)

200 μA

Wait mode

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 25°C

25 μA

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 105°C

85 μA

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 125°C

125 μA

Stop mode

Topr = 25°C315

μA

Topr = 105°C60 μA

Topr = 125°C100 μA

During flash memory

program f(BCLK) = 10 MHz, PM17 = 1 (one wait)

VCC = 5.0 V 20.0 mA

During flash memory

erase f(BCLK) = 10 MHz, PM17 = 1 (one wait)

VCC = 5.0 V 30.0 mA

Idet2 Low voltage detection dissipation current 3

μA

Idet0 Reset area detection dissipation current 6

μA

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

5.5.2 Timing Requirements (Peripheral Functions and Others)

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.5.2.1 Reset Input (RESET Input)

Figure 5.37 Reset Input (RESET Input)

5.5.2.2 External Clock Input

Note:

1. The condition is VCC = 5.0V.

Figure 5.38 External Clock Input (XIN Input)

Table 5.65 Reset Input (RESET Input)

Symbol Parameter Standard Unit

Min. Max.

tw(RSTL) RESET input low pulse width 10 μs

Table 5.66 External Clock Input (XIN input) (1)

Symbol Parameter Standard Unit

Min. Max.

tcExternal clock input cycle time 50 ns

tw(H) External clock input high pulse width 20 ns

tw(L) External clock input low pulse width 20 ns

trExternal clock rise time 9ns

tfExternal clock fall time 9ns

RESET input

w(RTSL)

XIN input

w(H)

r t

f t

w(L)

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.5.2.3 Timer A Input

Figure 5.39 Timer A Input

Table 5.67 Timer A Input (Counter Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 100 ns

tw(TAH) TAiIN input high pulse width 40 ns

tw(TAL) TAiIN input low pulse width 40 ns

Table 5.68 Timer A Input (Gating Input in Timer Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 400 ns

tw(TAH) TAiIN input high pulse width 200 ns

tw(TAL) TAiIN input low pulse width 200 ns

Table 5.69 Timer A Input (External Trigger Input in One-Shot Timer Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 200 ns

tw(TAH) TAiIN input high pulse width 100 ns

tw(TAL) TAiIN input low pulse width 100 ns

Table 5.70 Timer A Input (External Trigger Input in PWM Mode, Programmable Outp ut Mode)

Symbol Parameter Standard Unit

Min. Max.

tw(TAH) TAiIN input high pulse width 100 ns

tw(TAL) TAiIN input low pulse width 100 ns

TAiIN input

TAiOUT input

w(TAH)

c(TA)

w(TAL)

c(UP)

w(UPH)

w(UPL)

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Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

Figure 5.40 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Table 5.71 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 800 ns

tsu(TAIN-TAOUT)

TAiOUT input setup time 200 ns

tsu(TAOUT-TAIN)

TAiIN input setup time 200 ns

TAiIN input

Two-phase pulse input in event counter mode

TAiOUT input

c(TA)

su(TAIN-TAOUT) t

su(TAIN-TAOUT)

su(TAOUT-TAIN)

R01DS0019EJ0110 Rev.1.10 Page 136 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.5.2.4 Timer B Input

Figure 5.41 Timer B Input

Table 5.72 Timer B Input (Counter Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time (counted on one edge) 100 ns

tw(TBH) TBiIN input high pulse width (counted on one edge) 40 ns

tw(TBL) TBiIN input low pulse width (counted on one edge) 40 ns

tc(TB) TBiIN input cycle time (counted on both edges) 200 ns

tw(TBH) TBiIN input high pulse width (counted on both edges) 80 ns

tw(TBL) TBiIN Input low pulse width (counted on both edges) 80 ns

Table 5.73 Timer B Input (Pulse Period Measurement Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time 400 ns

tw(TBH) TBiIN input high pulse width 200 ns

tw(TBL) TBiIN input low pulse width 200 ns

Table 5.74 Timer B Input (Pulse Width Measurement Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time 400 ns

tw(TBH) TBiIN input high pulse width 200 ns

tw(TBL) TBiIN input low pulse width 200 ns

TBiIN input

c(TB)

w(TBH)

w(TBL)

R01DS0019EJ0110 Rev.1.10 Page 137 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.5.2.5 Timer S Input

Figure 5.42 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)

Table 5.75 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)

Symbol Parameter Standard Unit

Min. Max.

tw(TSH) TSUDA, TSUDB input high pulse width 2μs

tw(TSL)

TSUDA, TSUDB input low pulse width 2μs

tsu(TSUDA-TSUDB)

TSUDB input set u p time 1μs

tsu(TSUDB-TSUDA)

TSUDA input setup time 1μs

TSUDA input

Two-phase pu lse input in two-phase pulse signal processing mode

w(TSH)

su(TSUDA-TSUDB)

TSUDB input

w(TSL)

su(TSUDA-TSUDB)

su(TSUDB-TSUDA)

su(TSUDB-TSUDA)t

w(TSL)

w(TSH)

Note:

1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)

are also interchanged.

R01DS0019EJ0110 Rev.1.10 Page 138 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.5.2.6 Serial Interface

Figure 5.43 Serial Interface

5.5.2.7 External Interrupt INTi Input

Figure 5.44 External Interrupt INTi Input

Table 5. 76 Seria l Int e rf ac e

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 200 ns

tw(CKH) CLKi input high pulse width 100 ns

tw(CKL) CLKi input low pulse width 100 ns

td(C-Q) TXDi output delay time 80 ns

th(C-Q) TXDi hold time 0ns

tsu(D-C) RXDi input setup time 70 ns

th(C-D) RXDi input hold time 90 ns

Table 5.77 Ext ern al Interru pt INTi Input

Symbol Parameter Standard Unit

Min. Max.

tw(INH) INTi input high pulse width 250 ns

tw(INL) INTi input low pulse width 250 ns

CLKi

TXDi

RXDi

c(CK)

w(CKH)

w(CKL) t

h(C-Q)

d(C-Q) t

su (D-C) t

h(C-D)

INTi input

w(INL)

w(INH)

R01DS0019EJ0110 Rev.1.10 Page 139 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.5.2.8 Multi-master I2C-bus

Figure 5.45 Multi-master I2C-bus

Table 5. 78 M u lt i-master I2C-bus

Symbol Parameter Standard Clock Mode Fast-mode Unit

Min. Max. Min. Max.

tBUF Bus free time 4.7 1.3 μs

tHD;STA Hold time in start condition 4.0 0.6 μs

tLOW Hold time in SCL clock 0 status 4.7 1.3 μs

tRSCL, SDA signals’ rising time 1000 20 + 0.1 Cb 300 ns

tHD;DAT Data hold time 000.9

μs

tHIGH Hold time in SCL clock 1 status 4.0 0.6 μs

fFSCL, SDA signals’ falling time 300 20 + 0.1 Cb 300 ns

tsu;DAT Data setup time 250 100 ns

tsu;STA Setup time in restart condition 4.7 0.6 μs

tsu;STO Stop condition setup time 4.0 0.6 μs

SDA

SCL p

ps Sr

LOW

HD;STA t

HD;DAT t

HIGH t

su;DAT t

su;STA

R t

HD;STA t

su;STO

BUF

R01DS0019EJ0110 Rev.1.10 Page 140 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Timing Requirements

(VCC = 5 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.5.2.9 Serial bus interface

Note:

1. 1 tCYC is 1/f1 (s).

Table 5.79 Serial Bus Interface

Symbol Characteristic Measurement

condition Standard Unit

Min. Typ. Max.

tc(SSCK) SSCK clock cycle time 250 ns

tw(SSCKH) SSCK clock high pulse width 0.4 0.6 tc(SSCK)

tw(SSCKL) SSCK clock low pulse width 0.4 0.6 tc(SSCK)

tr(SSCK) SSCK clock rising time Master 1 tCYC (1)

Slave 1 μs

tf(SSCK) SSCK clock falling time Master 1 tCYC (1)

Slave 1 μs

tsu(SSIO-SSCK) SSO, SSI data input setup time 100 ns

th(SSCK-SSIO) SSO, SSI data input hold time 1 tCYC (1)

tsu(SCS-SSCK) SCS setup time Slave 1 tCYC + 50 (1) ns

th(SSCK-SCS) SCS hold time Slave 1 tCYC + 50 (1) ns

td(SSCK-SSIO) SSO, SSI dat a output delay

time Master 1 tCYC (1)

Slave 80 ns

ten(SCS-SSI) SSI output enable time 3.0 V ≤ VCC ≤ 5.5 V 1.5 tCYC + 100 (1) ns

tdis(SCS-SSI) SSI output disable time 3.0 V ≤ VCC ≤ 5.5 V 1.5 tCYC + 100 (1) ns

R01DS0019EJ0110 Rev.1.10 Page 141 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Figure 5.46 I/O Timing of Serial Bus Interface (Master)

VIH or VOH

VIL or VOL

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS = 0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH

VIL or VOL

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS =0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 0

CPHS, CPOS: Bits in the SSMR register

w(SSCKH)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

d(SSCK-SSIO)

f(SSCK) t

r(SSCK)

su(SSIO-SSCK) t

h(SSCK-SSIO)

w(SSCKH) t

f(SSCK) t

r(SSCK)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

d(SSCK-SSIO)

su(SSIO-SSCK) t

h(SSCK-SSIO)

R01DS0019EJ0110 Rev.1.10 Page 142 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Figure 5.47 I/O Timing of Serial Bus Interface (Slave)

VIH or VOH

VIL or VOL

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH

VIL or VOL

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 0

CPHS, CPOS: Bits in the SSMR register

su(SCS-SSCK) t

w(SSCKH) t

f(SSCK) t

r(SSCK)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

su(SSIO -SSC K) t

h(SSCK-SSIO)

en(SCS-SSI) t

d(SSCK-SSIO)

h(SSCK-SCS)

dis(SCS-SSI)

su(SCS-SSCK) t

w(SSCKH) t

f(SSCK) t

r(SSCK) t

h(SSCK-SCS)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

su(SSIO-SSCK) t

h(SSCK-SSIO)

en(SCS-SSI) t

d(SSCK-SSIO) t

dis(SCS-SSI)

R01DS0019EJ0110 Rev.1.10 Page 143 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 5 V

Figure 5.48 I/O Timing of Serial Bus Interface (Synchronous Communication Mode)

Figure 5.49 Switching Characteristic Measurement Circuit

VIH or VOH

SSCK

SSO (output)

SSI (input)

VIL or VOL

w(SSCKL)

w(SSCKH)

c(SSCK)

d(SSCK-SSIO)

su(SSIO-SSCK) t

h(SSCK-SSIO)

30 pF

Pin to be

measured

MCU

R01DS0019EJ0110 Rev.1.10 Page 144 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

5.6 Electrical Characteristics (K-Version, VCC = 3 V)

5.6.1 Electrical Characteristics K-Version, VCC = 3 V

Table 5.80 Electrical Characteristics (1)

VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = −40°C to 125°C, f(BCLK)=32 MHz unless ot herwise specified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

VOH HIGH

output

voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to P6_7, P7_0 to

P7_7, P8_0 to P8_4, P8_6 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

IOH = −1 mA VCC−0.5 VCC V

VOH

HIGH output voltage XOUT HIGH POWER IOH = −0.1 mA VCC−0.5 VCC V

LOW POWER IOH = −50 μAV

CC−0.5 VCC

HIGH output voltage XCOUT HIGH POWER With no load applied 2.5 V

LOW POWER With no load applied 1.6

VOL LOW output

voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0

to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to

P10_7

IOL = 1mA 0.5 V

VOL

LOW output voltage XOUT HIGH POWER IOL = 0.1mA 0.5 V

LOW POWER IOL = 50μA0.5

LOW output voltage XCOUT HIGH POWER With no load applied 0 V

LOW POWER With no load applied 0

VT+-VT- Hysteresis

TA0IN to TA4IN, TB0IN to TB5IN, INT0

to INT7, NMI, ADTRG, CTS0 to CTS3,

SCL2, SDA2, CLK0 to CLK4, TA0OUT

to TA4OUT, KI0 to KI3, RXD0 to RXD4,

ZP, IDU, IDW, IDV, SD, INPC1_0 to

INPC1_7, SSI0, SSCK0, SCS0, LIN0IN,

CRX0, CRX1

0.4VCC V

VT+-VT- Hysteresis RESET 1.8 V

VT+-VT- Hysteresis XIN 0.8 V

IIH HIGH input

current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0

to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to

P10_7

XIN, RESET, CNVSS

VI = 3V 4.0 μA

IIL LOW input

current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0

to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to

P10_7

XIN, RESET, CNVSS

VI = 0V −4.0 μA

RPULLUP Pull-up

resistance

P0_0 to P0_7, P1_0 to P1_7, P2_0 to

P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0

to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6 to P8_7, P9_0 to

P9_7, P10_0 to P10_7

VI = 0V 50 100 500 kΩ

RfXIN Feedback resistance XIN 3.0 MΩ

RfXCIN Feedback resistance XCIN 25 MΩ

VRAM RAM retention voltage At stop mode 2.0 V

R01DS0019EJ0110 Rev.1.10 Page 145 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Table 5.81 Electrical Characteristics (2)

Topr = −40°C to 125°C unless otherwise specified.

Symbol Parameter Measuring Condition Standard Unit

Min. Typ. Max.

ICC

Power supply current

(VCC = 3.0 V to 3.6 V)

In single-chip mode, the

output pins are open and

other pins are VSS

High speed mode

f(BCLK) = 32 MHz,

XIN = 8 MHz (square wave), PLL multiply-by-8

125 kHz on-chip oscillator operating 23 43 mA

f(BCLK) = 20 MHz,

XIN = 20 MHz (square wave),

125 kHz on-chip oscillator operating 20 38 mA

f(BCLK) = 16 MHz,

XIN = 16 MHz (square wave),

125 kHz on-chip oscillator operating 16 mA

40 MHz on-chip oscillator

mode

Main clock stopped

40 MHz on-chip oscillator operating

125 kHz on-chip oscillator operating

No division

20 38 mA

Main clock stopped

40 MHz on-chip oscillator operating

125 kHz on-chip oscillator operating

Divide-by-8

6 mA

125 kHz on-chip oscillator

mode

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Divide-by-8

FMR22 = FMR23 = 1 (Low-current consumption read

mode)

190 580 μA

Low power mode

f(BCLK) = 32 kHz

On ROM

FMR22 = FMR23 = 1 (Low-current consumption read

mode)

200 μA

Wait mode

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 25°C

25 μA

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 105°C

85 μA

Main clock stopped

40 MHz on-chip oscillator stopped

125 kHz on-chip oscillator operating

Peripheral clock operating

Topr = 125°C

125 μA

Stop mode

Topr = 25°C212

μA

Topr = 105°C60 μA

Topr = 125°C100 μA

During flash memory

program f(BCLK) = 10 MHz, PM17 = 1 (one wait)

VCC = 3.0 V 20.0 mA

During flash memory

erase f(BCLK) = 10 MHz, PM17 = 1 (one wait)

VCC = 3.0 V 30.0 mA

Idet2 Low voltage detection dissipation current 3

μA

Idet0 Reset area detection dissipation current 6

μA

R01DS0019EJ0110 Rev.1.10 Page 146 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

5.6.2 Timing Requirements (Peripheral Functions and Others)

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.6.2.1 Reset Input (RESET Input)

Figure 5.50 Reset Input (RESET Input)

5.6.2.2 External Clock Input

Note:

1. The condition is VCC = 3.0V.

Figure 5.51 External Clock Input (XIN Input)

Table 5.82 Reset Input (RESET Input)

Symbol Parameter Standard Unit

Min. Max.

tw(RSTL) RESET input low pulse width 10 μs

Table 5.83 External Clock Input (XIN input) (1)

Symbol Parameter Standard Unit

Min. Max.

tcExternal clock input cycle time 50 ns

tw(H) External clock input high pulse width 20 ns

tw(L) External clock input low pulse width 20 ns

trExternal clock rise time 9ns

tfExternal clock fall time 9ns

RESET input

w(RTSL)

XIN input

w(H)

r t

f t

w(L)

R01DS0019EJ0110 Rev.1.10 Page 147 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.6.2.3 Timer A Input

Figure 5.52 Timer A Input

Table 5.84 Timer A Input (Counter Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 150 ns

tw(TAH) TAiIN input high pulse width 60 ns

tw(TAL) TAiIN input low pulse width 60 ns

Table 5.85 Timer A Input (Gating Input in Timer Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 600 ns

tw(TAH) TAiIN input high pulse width 300 ns

tw(TAL) TAiIN input low pulse width 300 ns

Table 5.86 Timer A Input (External Trigger Input in One-Shot Timer Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 300 ns

tw(TAH) TAiIN input high pulse width 150 ns

tw(TAL) TAiIN input low pulse width 150 ns

Table 5.87 Timer A Input (External Trigger Input in PWM Mode, Programmable Outp ut Mode)

Symbol Parameter Standard Unit

Min. Max.

tw(TAH) TAiIN input high pulse width 150 ns

tw(TAL) TAiIN input low pulse width 150 ns

TAiIN input

TAiOUT input

w(TAH)

c(TA)

w(TAL)

c(UP)

w(UPH)

w(UPL)

R01DS0019EJ0110 Rev.1.10 Page 148 of 156

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

Figure 5.53 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Table 5.88 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TA) TAiIN input cycle time 2μs

tsu(TAIN-TAOUT)

TAiOUT input setup time 500 ns

tsu(TAOUT-TAIN)

TAiIN input setup time 500 ns

TAiIN input

Two-phase pulse input in event counter mode

TAiOUT input

c(TA)

su(TAIN-TAOUT) t

su(TAIN-TAOUT)

su(TAOUT-TAIN)

R01DS0019EJ0110 Rev.1.10 Page 149 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.6.2.4 Timer B Input

Figure 5.54 Timer B Input

Table 5.89 Timer B Input (Counter Input in Event Counter Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time (counted on one edge) 150 ns

tw(TBH) TBiIN input high pulse width (counted on one edge) 60 ns

tw(TBL) TBiIN input low pulse width (counted on one edge) 60 ns

tc(TB) TBiIN input cycle time (counted on both edges) 300 ns

tw(TBH) TBiIN input high pulse width (counted on both edges) 120 ns

tw(TBL) TBiIN Input low pulse width (counted on both edges) 120 ns

Table 5.90 Timer B Input (Pulse Period Measurement Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time 600 ns

tw(TBH) TBiIN input high pulse width 300 ns

tw(TBL) TBiIN input low pulse width 300 ns

Table 5.91 Timer B Input (Pulse Width Measurement Mode)

Symbol Parameter Standard Unit

Min. Max.

tc(TB) TBiIN input cycle time 600 ns

tw(TBH) TBiIN input high pulse width 300 ns

tw(TBL) TBiIN input low pulse width 300 ns

TBiIN input

c(TB)

w(TBH)

w(TBL)

R01DS0019EJ0110 Rev.1.10 Page 150 of 156

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.6.2.5 Timer S Input

Figure 5.55 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)

Table 5.92 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)

Symbol Parameter Standard Unit

Min. Max.

tw(TSH) TSUDA, TSUDB input high pulse width 2μs

tw(TSL)

TSUDA, TSUDB input low pulse width 2μs

tsu(TSUDA-TSUDB)

TSUDB input setup time 1μs

tsu(TSUDB-TSUDA)

TSUDA input setup time 1μs

TSUDA input

Two-phase pu lse input in two-phase pulse signal processing mode

w(TSH)

su(TSUDA-TSUDB)

TSUDB input

w(TSL)

su(TSUDA-TSUDB)

su(TSUDB-TSUDA)

su(TSUDB-TSUDA)t

w(TSL)

w(TSH)

Note:

1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)

are also interchanged.

R01DS0019EJ0110 Rev.1.10 Page 151 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.6.2.6 Serial Interface

Figure 5.56 Serial Interface

5.6.2.7 External Interrupt INTi Input

Figure 5.57 External Interrupt INTi Input

Table 5. 93 Seria l Int e rf ac e

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 300 ns

tw(CKH) CLKi input high pulse width 150 ns

tw(CKL) CLKi input low pulse width 150 ns

td(C-Q) TXDi output delay time 160 ns

th(C-Q) TXDi hold time 0ns

tsu(D-C) RXDi input setup time 100 ns

th(C-D) RXDi input hold time 90 ns

Table 5.94 Ext ern al Interru pt INTi Input

Symbol Parameter Standard Unit

Min. Max.

tw(INH) INTi Input HIGH Pulse Width 380 ns

tw(INL) INTi Input LOW Pulse Width 380 ns

CLKi

TXDi

RXDi

c(CK)

w(CKH)

w(CKL) t

h(C-Q)

d(C-Q) t

su (D-C) t

h(C-D)

INTi input

w(INL)

w(INH)

R01DS0019EJ0110 Rev.1.10 Page 152 of 156

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M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.6.2.8 Multi-master I2C-bus

Figure 5.58 Multi-master I2C-bus

Table 5. 95 M u lt i-master I2C-bus

Symbol Parameter Standard Clock Mode Fast-mode Unit

Min. Max. Min. Max.

tBUF Bus free time 4.7 1.3 μs

tHD;STA Hold time in start condition 4.0 0.6 μs

tLOW Hold time in SCL clock 0 status 4.7 1.3 μs

tRSCL, SDA signals’ rising time 1000 20 + 0.1 Cb 300 ns

tHD;DAT Data hold time 000.9

μs

tHIGH Hold time in SCL clock 1 status 4.0 0.6 μs

fFSCL, SDA signals’ falling time 300 20 + 0.1 Cb 300 ns

tsu;DAT Data setup time 250 100 ns

tsu;STA Setup time in restart condition 4.7 0.6 μs

tsu;STO Stop condition setup time 4.0 0.6 μs

SDA

SCL p

ps Sr

LOW

HD;STA t

HD;DAT t

HIGH t

su;DAT t

su;STA

R t

HD;STA t

su;STO

BUF

R01DS0019EJ0110 Rev.1.10 Page 153 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Timing Requirements

(VCC = 3 V, VSS = 0 V, at Topr = −40°C to 125°C unless otherwise specified)

5.6.2.9 Serial bus interface

Note:

1. 1 tCYC is 1/f1 (s).

Table 5.96 Serial Bus Interface

Symbol Characteristic Measurement

condition Standard Unit

Min. Typ. Max.

tc(SSCK) SSCK clock cycle time 250 ns

tw(SSCKH) SSCK clock high pulse width 0.4 0.6 tc(SSCK)

tw(SSCKL) SSCK clock low pulse width 0.4 0.6 tc(SSCK)

tr(SSCK) SSCK clock rising time Master 1 tCYC (1)

Slave 1 μs

tf(SSCK) SSCK clock falling time Master 1 tCYC (1)

Slave 1 μs

tsu(SSIO-SSCK) SSO, SSI data input setup time 100 ns

th(SSCK-SSIO) SSO, SSI data input hold time 1 tCYC (1)

tsu(SCS-SSCK) SCS setup time Slave 1 tCYC + 50 (1) ns

th(SSCK-SCS) SCS hold time Slave 1 tCYC + 50 (1) ns

td(SSCK-SSIO) SSO, SSI dat a output delay

time Master 1 tCYC (1)

Slave 80 ns

ten(SCS-SSI) SSI output enable time 3.0 V ≤ VCC ≤ 5.5 V 1.5 tCYC + 100 (1) ns

tdis(SCS-SSI) SSI output disable time 3.0 V ≤ VCC ≤ 5.5 V 1.5 tCYC + 100 (1) ns

R01DS0019EJ0110 Rev.1.10 Page 154 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Figure 5.59 I/O Timing of Serial Bus Interface (Master)

VIH or VOH

VIL or VOL

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS = 0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH

VIL or VOL

SCS (output)

SSCK (output)

(CPOS = 1)

SSCK (output)

(CPOS =0)

SSO (output)

SSI (input)

4-Wire Bus Communication Mode, Master, CPHS = 0

CPHS, CPOS: Bits in the SSMR register

w(SSCKH)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

d(SSCK-SSIO)

f(SSCK) t

r(SSCK)

su(SSIO-SSCK) t

h(SSCK-SSIO)

w(SSCKH) t

f(SSCK) t

r(SSCK)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

d(SSCK-SSIO)

su(SSIO-SSCK) t

h(SSCK-SSIO)

R01DS0019EJ0110 Rev.1.10 Page 155 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Figure 5.60 I/O Timing of Serial Bus Interface (Slave)

VIH or VOH

VIL or VOL

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH

VIL or VOL

SCS (input)

SSCK (input)

(CPOS = 1)

SSCK (input)

(CPOS = 0)

SSO (input)

SSI (output)

4-Wire Bus Communication Mode, Slave, CPHS = 0

CPHS, CPOS: Bits in the SSMR register

su(SCS-SSCK) t

w(SSCKH) t

f(SSCK) t

r(SSCK)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

su(SSIO -SSC K) t

h(SSCK-SSIO)

en(SCS-SSI) t

d(SSCK-SSIO)

h(SSCK-SCS)

dis(SCS-SSI)

su(SCS-SSCK) t

w(SSCKH) t

f(SSCK) t

r(SSCK) t

h(SSCK-SCS)

w(SSCKL)

w(SSCKH)

w(SSCKL) t

c(SSCK)

su(SSIO-SSCK) t

h(SSCK-SSIO)

en(SCS-SSI) t

d(SSCK-SSIO) t

dis(SCS-SSI)

R01DS0019EJ0110 Rev.1.10 Page 156 of 156

Sep 01, 2011

M16C/5M Group, M16C/57 Group 5. Electrical Characteristics

K-Version, VCC = 3 V

Figure 5.61 I/O Timing of Serial Bus Interface (Synchronous Communication Mode)

Figure 5.62 Switching Characteristic Measurement Circuit

VIH or VOH

SSCK

SSO (output)

SSI (input)

VIL or VOL

w(SSCKL)

w(SSCKH)

c(SSCK)

d(SSCK-SSIO)

su(SSIO-SSCK) t

h(SSCK-SSIO)

30 pF

Pin to be

measured

MCU

A- 1

REVISION HISTORY M16C/5M Group, M16C/57 Group Datasheet

Rev. Date Description

Page Summary

1.01 Aug.16.2010 — First edition issued

1.10 Sep. 01, 2011 Overview

8, 9, 10 Table 1.7 M16C/5M Group Product List (J-Version), Table 1.8 M16C/5M Group Product

List (K-V ersion), Table 1.9 M16C/57 Group Product List (J-V ersion), and Table 1.10 M16C/

57 Group Product List (K-Version): Changed the product statuses.

25, 26

Table 1.18 Pin Functions (64-Pin, 80-Pin, and 100-Pin Packages), Table 1.19 Pin

Functions (100-Pin Package Only), Table 1.21 Pin Functions (100-Pin and 80-Pin

Package Only): Changed the explanation of the direction register in the Description

column of the I/O port row.

Electrical Characteristics

J version, Common to 3 V and 5 V

81 Table 5.1 Absolute Maximum Ratings: Deleted VREF from the VI.

92 Table 5.14 On-Chip Oscillator Electrical Characteristics: Added the Dedicated 125 kHz on-

chip oscillator for the watchdog timer oscillation frequency.

J-Version, VCC = 5 V

101 Figure 5.14 Multi-master I2C-bus: Changed tHD;DTA to tHD;DAT and tsu;DTA to tsu;DAT.

102 Table 5.31 Serial Bus Interface: Added the standard for slave to td(SSCK-SSIO).

J-Version, VCC = 3 V

114 Figure 5.27 Multi-master I2C-bus: Changed tHD;DTA to tHD;DAT and tsu;DTA to tsu;DAT.

115 Table 5.48 Serial Bus Interface: Added the standard for slave to td(SSCK-SSIO).

K version, Common to 3 V and 5 V

130 Table 5.62 On-Chip Oscillator Electrical Characteristics: Added the Dedicated 125 kHz on-

chip oscillator for the watchdog timer oscillation frequency.

K-Version, VCC = 5 V

139 Figure 5.45 Multi-master I2C-bus: Changed tHD;DTA to tHD;DAT and tsu;DTA to tsu;DAT.

140 Table 5.79 Serial Bus Interface: Added the standard for slave to td(SSCK-SSIO).

K-Version, VCC = 3 V

152 Figure 5.58 Multi-master I2C-bus: Changed tHD;DTA to tHD;DAT and tsu;DTA to tsu;DAT.

153 Table 5.96 Serial Bus Interface: Added the standard for slave to td(SSCK-SSIO).

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General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in acc ord with the directions given under Hand ling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the ope n-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. U nused

pins should be handle d as described under Handlin g of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is suppli ed.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal i s applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which res etting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provid ed for the possible future expansio n of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has bec ome

stable. When switching the clock sign al during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock sig na l produced with an external

resonator (or by an external oscillator) while program execution is in progr ess, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but ha ving different part numbers may

differ because of the differences in internal memory capacity and layo ut pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas

Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to

be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or

technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or

others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the

use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and

regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to

the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is

prohibited under any applicable domestic or foreign laws or regulations.

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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product

depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas

Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the

use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.

The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;

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implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage

range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the

use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and

malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the

possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to

redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,

please evaluate the safety of the final products or system manufactured by you.

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no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

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