fIN − Input Frequency − MHz
60
70
80
90
100
0 50 100 150 200 250 300
SFDR − dBc
G001
170 MSPS, No Dither
170 MSPS, Dither Enabled
200 MSPS, No Dither
200 MSPS, Dither Enabled
fIN − Input Frequency − MHz
70
71
72
73
74
75
76
77
78
0 50 100 150 200 250 300
SNR − dBFS
G002
200 MSPS, Dither Enabled
170 MSPS, Dither Enabled
170 MSPS, No Dither
200 MSPS, No Dither
ADS5484
ADS5485
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
16-Bit, 170/200-MSPS Analog-to-Digital Converters
Check for Samples: ADS5484 ADS5485
1FEATURES APPLICATIONS
• Wireless Infrastructure
23• 170/200-MSPS Sample Rates • Test and Measurement Instrumentation
• 16-Bit Resolution, 78 dBFS Noise Floor • Software-Defined Radio
• SFDR = 95 dBc • Data Acquisition
• On-Chip High Impedance Analog Buffer • Power Amplifier Linearization
• Efficient DDR LVDS-Compatible Outputs • Radar
• Power-Down Mode: 70 mW • Medical Imaging
• Pin-for-Pin with ADS5483/5482/5481,
135/105/80-MSPS ADCs
• QFN-64 PowerPAD™ Package
(9 mm × 9 mm footprint)
• Industrial Temperature Range:
–40°C to 85°C
DESCRIPTION
The ADS5484/ADS5485 (ADS548x) is a 16-bit family of analog-to-digital converters (ADCs) that operate from
both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. The ADS548x integrated
analog input buffer isolates the internal switching of the onboard track and hold (T & H) from disturbing the signal
source while providing a high-impedance input. An internal reference generator is provided to simplify the system
design. Internal dither is available to improve SFDR. These devices are drop-in compatible to the
ADS5483/5482/5481, creating a pin-compatible family from 80 – 200 MSPS. Designed for highest total ENOB,
the ADS548x family has outstanding low noise performance and spurious-free dynamic range.
The ADS548x family is available in a QFN-64 PowerPAD package. The devices are built on Texas Instruments
complementary bipolar process (BiCom3) and are specified over the full industrial temperature range (–40°C to
85°C). SFDR SNR
vs vs
INPUT FREQUENCY INPUT FREQUENCY
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5485 is Not Recommended for New Designs
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD TEMPERATURE
DESIGNATOR MARKING NUMBER MEDIA, QUANTITY
RANGE
ADS5484IRGCT Tape and reel, 250
ADS5484 QFN-64 RGC –40°C to 85°C AZ5484 ADS5484IRGCR Tape and reel, 2000
ADS5485IRGCT Tape and reel, 250
ADS5485 QFN-64 RGC –40°C to 85°C AZ5485 ADS5485IRGCR Tape and reel, 2000
(1) For the most current product and ordering information see the Package Option Addendum located at the end of this document, or see
the TI website at www.ti.com..
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. ADS5484, ADS5485 UNIT
AVDD5 to GND 6 V
Supply voltage AVDD3 to GND 5 V
DVDD3 to GND 5 V
AC signal. Valid when AVDD5 is within normal operating range. When
AVDD5 is off, analog inputs should be < 0.5 V. If not, the protection
Analog input to GND diode between the inputs and AVDD5 becomes forward-biased and –0.3 to (AVDD5 + 0.3) V
could be damaged or shorten device lifetime (see Figure 30). Short
transient conditions during power on/off are not a concern.
Analog INP to INM DC signal ±4 V
Valid when AVDD3 is within normal operating range. When AVDD3 is
off, clock inputs should be < 0.5 V. If not, the protection diode between
Clock input to GND the inputs and AVDD3 becomes forward-biased and could be –0.3 to (AVDD3 + 0.3) V
damaged or shorten device lifetime (see Figure 37). Short transient
conditions during power on/off are not a concern.
CLKP to CLKM ±2.5 V
Digital data output to GND –0.3 to (DVDD3 + 0.3) V
Digital data output plus-to-minus ±1 V
Operating temperature range –40 to 85 °C
Maximum junction temperature 150 °C
Storage temperature range –65 to 150 °C
ESD, human-body model (HBM) 2 kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime are available upon
request.
THERMAL CHARACTERISTICS(1)
PARAMETER TEST CONDITIONS TYP UNIT
Soldered thermal pad, no airflow 20
RθJA Soldered thermal pad, 150-LFM airflow 16 °C/W
RθJC Thermal resistance from the junction to the package case (top) 7
RθJP Thermal resistance from the junction to the thermal pad (bottom) 0.2
(1) Using 49 thermal vias ( 7 × 7 array). See PowerPAD Package in the Application Information section.
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ADS5485
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RECOMMENDED OPERATING CONDITIONS ADS5484, ADS5485 UNIT
MIN NOM MAX
SUPPLIES
AVDD5 Analog supply voltage 4.75 5 5.25 V
AVDD3 Analog supply voltage 3.15 3.3 3.45 V
DVDD3 Output driver supply voltage 3 3.3 3.6 V
ANALOG INPUT
Differential input voltage range 3 VPP
VCM Input common-mode voltage 3.1 V
DIGITAL OUTPUT (DRY, DATA)
Maximum differential output load (parasitic or intentional) 5 pF
Differential output resistance 100 Ω
CLOCK INPUT (CLK)
Max
CLK input sample rate (sine wave) 10 Rated MSPS
Clock
Clock amplitude, differential sine wave (see Figure 39) 1.5 5 VPP
Clock duty cycle (see Figure 44) 45% 50% 55%
TAOperating free-air temperature –40 +85 °C
ELECTRICAL CHARACTERISTICS (ADS5484, ADS5485)
Typical values at TA= 25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
ADS5484 ADS5485
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
Clock rate 170 200 MSPS
Resolution 16 16 Bits
ANALOG INPUTS
Differential input voltage range 3 3 VPP
Self-biased; see VCM
Analog input common-mode voltage 3.1 3.1 V
specification below
Input resistance (dc) Each input to VCM 1000 1000 Ω
Each input to GND (unsoldered
Input capacitance 3.5 3.5 pF
package)
Analog input bandwidth (–3dB) 730 730 MHz
Common-mode signal
CMRR Common-mode rejection ratio 65 65 dB
70 MHz (see Figure 26)
INTERNAL REFERENCE VOLTAGE
VREF Reference voltage 1.2 1.2 V
Analog input common-mode voltage
VCM With internal voltage reference 2.9 3.1 3.3 2.9 3.1 3.3 V
reference output
VCM temperature coefficient -1 -1 mV/°C
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS (ADS5484, ADS5485) (continued)
Typical values at TA= 25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
ADS5484 ADS5485
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
DYNAMIC ACCURACY
No missing codes,
DNL Differential nonlinearity error -0.99 ±0.5 1.0 -0.99 ±0.5 1.0 LSB
fIN = 30 MHz
INL Integral nonlinearity error fIN = 30 MHz -10 ±3 +10 -10 ±3 +10 LSB
Offset error -15 15 -15 15 mV
Offset temperature coefficient -0.02 -0.02 mV/°C
Gain error -6 ±2 6 -6 ±2 6 %FS
Gain temperature coefficient -0.01 -0.01 mV/°C
POWER SUPPLY
IAVDD5 5-V analog current 310 330 310 330 mA
IAVDD3 3.3-V analog current 126 150 126 150 mA
VIN = Full-scale, fIN = 30 MHz,
fS= Max rated, Normal operation
IDVDD3 3.3-V digital/LVDS current 60 65 60 65 mA
Total power dissipation 2.16 2.35 2.16 2.35 W
IAVDD5 5-V analog current 98 98 mA
IAVDD3 3.3-V analog current 35 35 mA
Light sleep mode (PDWNF = H,
PDWNS = L)
IDVDD3 3.3-V digital/LVDS current 0.07 0.07 mA
Total power dissipation 600 680 600 680 mW
IAVDD5 5-V analog current 13 13 mA
IAVDD3 3.3-V analog current 1 1 mA
Deep sleep mode (PDWNF = L,
PDWNS = H)
IDVDD3 3.3-V digital/LVDS current 0.07 0.07 mA
Total power dissipation 70 100 70 100 mW
Fast wake-up time (light sleep) From PDWNF disabled 600 600 μS
Slow wake-up time (deep sleep) From PDWNS disabled 6 6 mS
AVDD5 supply 60 60 dB
Power-supply rejection ratio,
Without 0.1-μF board supply
PSRR AVDD3 supply 80 80 dB
capacitors, with 1-MHz supply
noise (see Figure 46)
DVDD3 supply 95 95 dB
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz 75 76.8 73.5 75.8
fIN = 30 MHz 74.5 75.9 73 75
fIN = 70 MHz 75.7 75
SNR Signal-to-noise ratio, dither disabled dBFS
fIN = 130 MHz 73.5 75.7 72 74.8
fIN = 170 MHz 75.6 74.8
fIN = 230 MHz 74.9 74.4
fIN = 10 MHz 84 95 84 93
fIN = 30 MHz 84 91 82 90
fIN = 70 MHz 87 87
Spurious-free dynamic range, dither
SFDR dBc
disabled fIN = 130 MHz 78 86 78 85
fIN = 170 MHz 81 78
fIN = 230 MHz 73 73
fIN = 10 MHz 84 100 84 100
fIN = 30 MHz 84 95 82 95
fIN = 70 MHz 95 95
HD2 Second-harmonic, dither disabled dBc
fIN = 130 MHz 78 87 78 85
fIN = 170 MHz 81 78
fIN = 230 MHz 73 73
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ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
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ELECTRICAL CHARACTERISTICS (ADS5484, ADS5485) (continued)
Typical values at TA= 25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
ADS5484 ADS5485
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
fIN = 10 MHz 84 97 84 99
fIN = 30 MHz 84 91 82 87
fIN = 70 MHz 87 87
HD3 Third-harmonic, dither disabled dBc
fIN = 130 MHz 78 86 78 85
fIN = 170 MHz 82 81
fIN = 230 MHz 73 73
fIN = 10 MHz 84 96 84 93
fIN = 30 MHz 84 91 82 90
Worst harmonic/spur fIN = 70 MHz 90 90
(other than HD2 and HD3), dither dBc
fIN = 130 MHz 78 91 78 90
disabled fIN = 170 MHz 90 90
fIN = 230 MHz 87 87
fIN = 10 MHz 81 92 81 92
fIN = 30 MHz 81 86 79 85
fIN = 70 MHz 86 85
Total harmonic distortion, dither
THD dBc
disabled fIN = 130 MHz 75 84 75 81
fIN = 170 MHz 78 76
fIN = 230 MHz 70 70
fIN = 10 MHz 73.5 75.8 71.5 74.6
fIN = 30 MHz 73 75 71 73.8
fIN = 70 MHz 74.3 73.7
Signal-to-noise and distortion, dither
SINAD dBc
disabled fIN = 130 MHz 71.5 73.8 70 72.9
fIN = 170 MHz 72.9 71.7
fIN = 230 MHz 68.7 68.4
fIN1 = 29.5 MHz, fIN2 = 30.5 MHz, 99.1 95.9
Each at –7 dBFS
Two-tone SFDR (worst spurious or
IMD dBFS
IMD) fIN1 = 69.5 MHz, fIN2 = 70.5 MHz, 95.3 95.2
Each at –10 dBFS
Effective number of bits fIN = 10 MHz (from SINAD in dBc 11.92 12.3 11.58 12.1
ENOB Bits
at -1dBFS)
2.9 2.9 LSB rms
Noise RMS idle-channel noise Analog inputs shorted together 78 78 dBFS
LVDS DIGITAL OUTPUTS
Assumes a 100-Ωdifferential
VOD Differential output voltage (±) load on each LVDS pair and 247 350 454 247 350 454 mV
LVDS bias = 3.5 mA
VOC Common-mode output voltage 1.125 1.25 1.375 1.125 1.25 1.375 V
DIGITAL INPUTS
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IIH High-level input current PDWNF, PDWNS, DITHER 1 1 μA
IIL Low-level input current -1 -1 μA
Input capacitance 2 2 pF
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N+1 N+2
N+6
tCLKH
tCLKL
N+3
N+4
N+5
tDRY
tDATA
Sample
N
T0158-02
Latency = 5 Clock Cycles
Dx_y_P
Dx_y_M
CLKM
CLKP
DRY_M
DRY_P
Sampling
Clock Input
Data Clock
Output
Output Data OOOOOOO EEEEEEE
NN – 1
E = Even Bits = B0, B2, B4, B6, B8, B10, B12, B14
O = Odd Bits = B1, B3, B5, B7, B9, B11, B13, B15
Dx_y_P/M are LVDS outputs that have two bits per pair (EVEN and ODD). The values for x and y are 0_1, 2_3, 4_5, ... 14_15.
Aperture
Delay
ta
ADS5484
ADS5485
www.ti.com
............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
TIMING INFORMATION
Figure 1. Timing Diagram
TIMING CHARACTERISTICS(1)
Typical values at TA= 25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
taAperture delay 200 ps
Aperture jitter, rms Internal jitter of the ADC 80 fs
Latency 5 cycles
tCLK Clock period 1e9/CLK 100 ns
CLK = max rated clock for that part
tCLKH Clock pulse duration, high 0.5e9/CLK 50 ns
number
tCLKL Clock pulse duration, low 0.5e9/CLK 50 ns
tDRY CLK to DRY delay time(2) 1500 1900 2300 ps
Zero crossing, 5-pF parasitic to GND
tDATA CLK to DATA delay time(2) 1400 1900 2400 ps
tSKEW DATA to DRY skew tDATA – tDRY, 5-pF parasitic to GND –500 0 500 ps
tRISE DRY/DATA rise time 500 ps
5-pF parasitic to GND
tFALL DRY/DATA fall time 500 ps
(1) Timing parameters are assured by design or characterization, but not production tested.
(2) DRY and DATA are updated on the rising edge of CLK input. The latency must be added to tDATA to determine the overall propagation
delay.
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AGND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ADS548x
RGCPackage
(TopView)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVDD5
AVDD5
AGND
REF
NC
NC
AGND
AVDD5
AVDD3
AGND
INP
INM
AGND
AVDD5
AVDD3
VCM
AGND
AVDD5
AVDD3
AGND
CLKM
CLKP
AGND
AVDD5
AVDD3
AGND
AVDD5
AVDD3
AGND
AVDD5
AVDD3
AGND
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49 D4_5_P
D4_5_M
D2_3_P
D2_3_M
D0_1_P
D0_1_M
DVDD3
DGND
NC
NC
NC
NC
DITHER
PDWNS
PDWNF
LVDSB
DGND
DVDD3
D14_15_P
D14_15_M
D12_13_P
D12_13_M
D10_11_P
D10_11_M
D8_9_P
D8_9_M
DRY_P
DRY_M
DVDD3
DGND
D6_7_P
D6_7_M
P0056-08
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
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PIN CONFIGURATION
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
Table 2. PIN FUNCTIONS
PIN DESCRIPTION
NAME NO.
1, 2, 8, 14, 18,
AVDD5 5-V analog supply
24, 27, 30
9, 15, 19, 25,
AVDD3 3.3-V analog supply
28, 31
3, 7, 10, 13, 17,
AGND 20, 23, 26, 29, Analog ground
32
DVDD3 42, 52, 63 3.3-V digital supply
DGND 41, 51, 64 Digital ground
NC 5, 6, 37-40 No connect - leave floating
INP, INM 11, 12 Differential analog inputs (P = plus = true, M = minus = complement)
CLKM, CLKP 21, 22 Differential clock inputs (P = plus = true, M = minus = complement)
Reference voltage input/output (1.2 V nominal). To use an external reference and to turn the internal
REF 4 reference off, pull both PDWNF and PDWNS to logic high (DVDD3). A 0.1-μF capacitor to ground on
REF is recommended but not required.
Analog input common mode, output (3.1V), for use in applications that require use of the internally
VCM 16 generated common-mode. See the Applications section for more information on using VCM. A 0.1-μF
capacitor to ground on VCM is recommended but not required.
External bias resistor for LVDS bias current, normally 10 kΩto GND to provide nominal 3.5-mA LVDS
LVDSB 33 current.
Light sleep power down, fast wake-up, logic high (DVDD3) = light sleep enabled (bandgap reference
PDWNF 34 remains on)
Deep sleep power down, slow wake-up, logic high (DVDD3) = deep sleep enabled (bandgap reference
PDWNS 35 is off)
DITHER 36 Dither enable, logic high (DVDD3) = dither enabled
DRY_P, 54, 53 Data ready signal (LVDS clock out) (P = plus = true, M = minus = complement)
DRY_M
D14_15_P, 62, 61 DDR LVDS output bits 14 then 15 (15 is MSB) (P = plus = true, M = minus = complement)
D14_15_M
DE_O_P, 43-50, 55-62 DDR LVDS output bits E (even) then O (odd) (P = plus = true, M = minus = complement)
DE_O_M
D0_1_P, 44, 43 DDR LVDS output bits 0 then 1 (0 is LSB) (P = plus = true, M = minus = complement)
D0_1_M
PowerPAD 65 Analog ground (exposed pad on bottom of package)
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f − Frequency − MHz
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Amplitude − dB
G003
SFDR = 97 dBc
SINAD = 76.7 dBFS
SNR = 76.8 dBFS
THD = 96.3 dBc
0 8576.56859.55142.53425.5178.5
f − Frequency − MHz
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Amplitude − dB
G004
SFDR = 87 dBc
SINAD = 75.3 dBFS
SNR = 75.5 dBFS
THD = 87.2 dBc
08576.56859.55142.53425.5178.5
f − Frequency − MHz
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Amplitude − dB
G005
SFDR = 80 dBc
SINAD = 74.4 dBFS
SNR = 75.6 dBFS
THD = 79.6 dBc
0 8576.56859.55142.53425.5178.5
f − Frequency − MHz
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Amplitude − dB
G006
SFDR = 73 dBc
SINAD = 69.7 dBFS
SNR = 74.9 dBFS
THD = 70.3 dBc
08576.56859.55142.53425.5178.5
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
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TYPICAL CHARACTERISTICS
At TA= 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5484 - 170-MSPS Typical Data
Plots in this section are with a clock of 170 MSPS, unless otherwise specified.
ADS5484 SPECTRAL PERFORMANCE ADS5484 SPECTRAL PERFORMANCE
vs vs
FFT for 10-MHz INPUT SIGNAL FFT for 70-MHz INPUT SIGNAL
Figure 2. Figure 3.
ADS5484 SPECTRAL PERFORMANCE ADS5484 SPECTRAL PERFORMANCE
vs vs
FFT for 130-MHz INPUT SIGNAL FFT for 230-MHz INPUT SIGNAL
Figure 4. Figure 5.
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Code
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 16384 32768 49152 65536
DNL − LSB
G007
fS = 170 MSPS
fIN = 10 MHz, –1 dBFS
Code
−4
−3
−2
−1
0
1
2
3
4
0 16384 32768 49152 65536
INL − LSB
G008
fS = 170 MSPS
fIN = 10 MHz, –1 dBFS
AIN − Input Amplitude − dBFS
0
10
20
30
40
50
60
70
80
90
100
110
120
130
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
AC Performance − dB
G009
fS = 170 MSPS
fIN = 130 MHz
AIN = 0 to −100 dBFS
256k Point FFT
SFDR (dBFS,
Dither ON)
SNR (dBFS,
Dither ON)
SFDR (dBc,
Dither OFF)
SFDR (dBFS,
Dither OFF)
SFDR (dBc,
Dither ON)
SNR (dBc,
Dither ON)
AIN − Input Amplitude − dBFS
60
65
70
75
80
85
90
−40 −36 −32 −28 −24 −20 −16 −12 −8 −4 0
AC Performance − dB
G010
SFDR (dBc,
Dither OFF)
SFDR (dBc,
Dither ON)
fS = 170 MSPS
fIN = 130 MHz
AIN = 0 to −40 dBFS
256k Point FFT
ADS5484
ADS5485
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5484 DIFFERENTIAL NONLINEARITY ADS5484 INTEGRAL NONLINEARITY
Figure 6. Figure 7.
ADS5484 AC PERFORMANCE ADS5484 AC PERFORMANCE
vs vs
INPUT AMPLITUDE (130-MHz Input Signal) INPUT AMPLITUDE (130-MHz Input Signal)
Figure 8. Figure 9.
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Input Amplitude − dBFS
−150
−140
−130
−120
−110
−100
−90
−80
−70
−90 −80 −70 −60 −50 −40 −30 −20 −10 0
Performance − dBFS
G011
Dither, 2F2−F1 (dBFS) Dither, 2F1−F2 (dBFS)
Dither, Dominant Spur (dBFS)
No Dither, Dominant Spur (dBFS)
T − Temperature − °C
86
87
88
89
90
91
92
93
94
−40 −20 0 20 40 60 80
SFDR − dBc
G012
AVDD5 = 4.75 V,
AVDD3 = 3.15 V
AVDD5 = 5 V,
AVDD3 = 3.15 V
AVDD5 = 5.25 V,
AVDD3 = 3.45 V AVDD5 = 5 V,
AVDD3 = 3.3 V
AVDD5 = 5.25 V,
AVDD3 = 3.15 V
AVDD5 = 5.25 V,
AVDD3 = 3.3 V
AVDD5 = 5 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.3 V
fS = 170 MSPS,
fIN = 30 MHz
T − Temperature − °C
75.0
75.2
75.4
75.6
75.8
76.0
76.2
76.4
76.6
76.8
77.0
−40 −20 0 20 40 60 80
SNR − dBFS
G013
AVDD5 = 5.25 V,
AVDD3 = 3.15 V
AVDD5 = 5.25 V,
AVDD3 = 3.3 V
AVDD5 = 5 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.3 V
fS = 170 MSPS,
fIN = 30 MHz
AVDD5 = 4.75 V,
AVDD3 = 3.15 V AVDD5 = 5 V,
AVDD3 = 3.15 V
AVDD5 = 5 V,
AVDD3 = 3.3 V
AVDD5 = 5.25 V,
AVDD3 = 3.45 V
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5484 TWO-TONE PERFORMANCE ADS5484 30-MHz SFDR
vs vs
INPUT AMPLITUDE (f1= 69.5 MHz and f2= 70.5 MHz) AVDD5 and AVDD3 OVER TEMPERATURE
Figure 10. Figure 11.
ADS5484 30-MHz SNR
vs
AVDD5 and AVDD3 OVER TEMPERATURE
Figure 12.
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f − Frequency − MHz
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 10 20 30 40 50 60 70 80 90 100
Amplitude − dB
G018
SFDR = 93 dBc
SINAD = 75.7 dBFS
SNR = 75.8 dBFS
THD = 97 dBc
f − Frequency − MHz
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 10 20 30 40 50 60 70 80 90 100
Amplitude − dB
G019
SFDR = 88 dBc
SINAD = 74.7 dBFS
SNR = 75 dBFS
THD = 86 dBc
f − Frequency − MHz
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 10 20 30 40 50 60 70 80 90 100
Amplitude − dB
G020
SFDR = 84 dBc
SINAD = 74.1 dBFS
SNR = 75 dBFS
THD = 80.8 dBc
f − Frequency − MHz
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 10 20 30 40 50 60 70 80 90 100
Amplitude − dB
G021
SFDR = 73 dBc
SINAD = 69.5 dBFS
SNR = 74.5 dBFS
THD = 70.2 dBc
ADS5484
ADS5485
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5485 - 200-MSPS Typical Data
Plots in this section are with a clock of 200 MSPS, unless otherwise specified.
ADS5485 SPECTRAL PERFORMANCE ADS5485 SPECTRAL PERFORMANCE
vs vs
FFT for 10-MHz INPUT SIGNAL FFT for 70-MHz INPUT SIGNAL
Figure 13. Figure 14.
ADS5485 SPECTRAL PERFORMANCE ADS5485 SPECTRAL PERFORMANCE
vs vs
FFT for 130-MHz INPUT SIGNAL FFT for 230-MHz INPUT SIGNAL
Figure 15. Figure 16.
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Code
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 16384 32768 49152 65536
DNL − LSB
G022
fS = 200 MSPS
fIN = 10 MHz, –1 dBFS
Code
−4
−3
−2
−1
0
1
2
3
4
0 16384 32768 49152 65536
INL − LSB
G023
fS = 200 MSPS
fIN = 10 MHz, –1 dBFS
AIN − Input Amplitude − dBFS
0
10
20
30
40
50
60
70
80
90
100
110
120
130
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
AC Performance − dB
G024
fS = 200 MSPS
fIN = 130 MHz
AIN = 0 to −100 dBFS
256k Point FFT
SFDR (dBFS,
Dither ON)
SNR (dBFS,
Dither ON)
SFDR (dBFS,
Dither OFF)
SFDR (dBc,
Dither ON)
SNR (dBc,
Dither ON)
SFDR (dBc,
Dither OFF)
AIN − Input Amplitude − dBFS
60
65
70
75
80
85
90
−40 −36 −32 −28 −24 −20 −16 −12 −8 −4 0
AC Performance − dB
G025
SFDR (dBc,
Dither OFF)
SFDR (dBc,
Dither ON)
fS = 200 MSPS
fIN = 130 MHz
AIN = 0 to −40 dBFS
256k Point FFT
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5485 DIFFERENTIAL NONLINEARITY ADS5485 INTEGRAL NONLINEARITY
Figure 17. Figure 18.
ADS5485 AC PERFORMANCE ADS5485 AC PERFORMANCE
vs vs
INPUT AMPLITUDE (130-MHz Input Signal) INPUT AMPLITUDE (130-MHz Input Signal)
Figure 19. Figure 20.
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Input Amplitude − dBFS
−150
−140
−130
−120
−110
−100
−90
−80
−70
−90 −80 −70 −60 −50 −40 −30 −20 −10 0
Performance − dBFS
G026
Dither, 2F2−F1 (dBFS)
Dither, 2F1−F2 (dBFS)
Dither, Dominant Spur (dBFS)
No Dither, Dominant Spur (dBFS)
T − Temperature − °C
85
86
87
88
89
90
−40 −20 0 20 40 60 80
SFDR − dBc
G027
AVDD5 = 4.75 V,
AVDD3 = 3.45 V
fS = 200 MSPS,
fIN = 30 MHz
AVDD5 = 5.25 V,
AVDD3 = 3.15 V
AVDD5 = 5 V,
AVDD3 = 3.15 V
AVDD5 = 5.25 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.3 V
AVDD5 = 4.75 V,
AVDD3 = 3.15 V
AVDD5 = 5 V,
AVDD3 = 3.45 V
AVDD5 = 5.25 V,
AVDD3 = 3.3 V
AVDD5 = 5 V,
AVDD3 = 3.3 V
T − Temperature − °C
72.0
72.5
73.0
73.5
74.0
74.5
75.0
75.5
76.0
−40 −20 0 20 40 60 80
SNR − dBFS
G028
AVDD5 = 5.25 V,
AVDD3 = 3.3 V
AVDD5 = 5 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.3 V
fS = 200 MSPS,
fIN = 30 MHz
AVDD5 = 5.25 V,
AVDD3 = 3.15 V AVDD5 = 5 V,
AVDD3 = 3.3 V
AVDD5 = 5.25 V,
AVDD3 = 3.45 V
AVDD5 = 4.75 V,
AVDD3 = 3.15 V AVDD5 = 5 V,
AVDD3 = 3.15 V
ADS5484
ADS5485
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
ADS5485 TWO-TONE PERFORMANCE ADS5485 30-MHz SFDR
vs vs
INPUT AMPLITUDE (f1= 69.5 MHz and f2= 70.5 MHz) AVDD5 and AVDD3 OVER TEMPERATURE
Figure 21. Figure 22.
ADS5485 30-MHz SNR
vs
AVDD5 and AVDD3 OVER TEMPERATURE
Figure 23.
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fIN − Input Frequency − Hz
−12
−9
−6
−3
0
3
Normalized Gain Response − dB
10M 100M 1G
G033
ADS5484
ADS5483
ADS5481
ADS5482
ADS5485
Output Code
0
2
4
6
8
10
12
14
16
18
Percentage − %
G034
fs = 170 MSPS for ADS5484
fs = 200 MSPS for ADS5485
Analog Inputs Shorted to VCM ADS5484
ADS5485
32680
32682
32684
32686
32688
32690
32692
32694
32696
32698
32700
32702
32704
32706
t − time − ms
0
10
20
30
40
50
60
70
80
90
012345678910
SNR − dBFS
G066
PDWNF
PDWNS
fS = 135 MSPS
fIN = 10 MHz
PDWNF and PDWNS Tested Independently
PDWNx Disabled at 0 ms
PDWNx Enabled at ≈ 8 ms
fIN − Input Frequency − MHz
−80
−70
−60
−50
−40
−30
−20
−10
0
CMRR − dB
0.1 10 1k
G054
1 100
ADS5484
ADS5485
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TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
Typical Data, Valid for Both ADS5484/5485
Plots in this section are valid for either device or otherwise have combined plots.
NORMALIZED GAIN RESPONSE
vs
INPUT FREQUENCY NOISE HISTOGRAM WITH INPUTS SHORTED
Figure 24. Figure 25.
CMRR
vs
COMMON-MODE INPUT FREQUENCY ADC WAKE-UP TIME
Figure 26. Figure 27.
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10 50 100 150
f -InputFrequency-MHz
IN
f -SamplingFrequency-MSPS
S
SNR-dBFS
200 250 300
10
20
40
140
60
80
100
120
160
180
210
62 64 6866 70 72
M0048-08
74 74
74
74
73
73
73
72
72
72
70
70
70
76
76
75
75
75
78
75
75
75
68
68
75
74 73
73
66 64
74
74
74 76
200
ADS5484
ADS5485
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SNR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
Figure 28.
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10 50 100 150
f -InputFrequency-MHz
IN
f -SamplingFrequency-MSPS
S
SFDR-dBc
200 250 300
10
20
40
140
60
80
100
120
160
180
210
55 60 7065 75 80
M0049-08
80
80
80
80
70
70
85
85
85
85
85
70
90
90
90
100
75
75 65
75
60
85 95
200
90
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, sampling rate = max rated, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SFDR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
Figure 29.
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1000 W
1000 W
10 W
10 W
VCM
3 pF
3pF AGND
S0293-02
INP
INM
AVDD5
AVDD5
ADS548x
AGND
AGND
~ 2 nH Bond Wire
~ 2 nH Bond Wire
~ 200fF
Package
~ 200fF
Package
~ 200fF
BondPad
~ 200fF
BondPad
Analog
Inputs
Bipolar
Transistor
Buffer
Bipolar
Transistor
Buffer
TrackandHold,
1 Stage
st Pipeline
ADS5484
ADS5485
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
APPLICATIONS INFORMATION
Theory of Operation
The ADS5484/ADS5485 (ADS548x) is a 16-bit, 170/200-MSPS family of monolithic pipeline ADCs. The bipolar
analog core operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide
LVDS-compatible outputs. Prior to the track-and-hold, the analog input signal passes through a high-performance
bipolar buffer. The buffer presents a high and consistent impedance to the analog inputs. The buffer isolates the
board circuitry external to the ADC from the sampling glitches caused by the track-and-hold in the ADC. The
conversion process is initiated by the falling edge of the external input clock. At that instant, the differential input
signal is captured by the input track-and-hold, and the input sample is converted sequentially by a series of lower
resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling
clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in
a data latency of 4.5 clock cycles, after which the output data are available as a 16-bit parallel word, coded in
offset binary format.
Input Configuration
The analog input for the ADS548x consists of an analog pseudo-differential buffer followed by a bipolar transistor
T & H. The analog buffer isolates the source driving the input of the ADC from any internal switching and
presents a high impedance to drive at high input frequencies, as compared to an ADC without a buffered input.
The input common-mode is set internally through a 1000-Ωresistor connected from 3.1 V to each of the inputs.
This configuration results in a differential input impedance of 2 kΩat 0 Hz. Figure 30 estimates the package
parasitics before soldering to a board. Each board is different, but soldering to the board will likely add 1 – 2 pF
to the input capacitance.
Figure 30. Analog Input Circuit (unsoldered package)
For a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swings
symmetrically between (3.1 V + 0.75 V) and (3.1 V – 0.75 V). This range means that each input has a maximum
signal swing of 1.5 VPP for a total differential input signal swing of 3 VPP. Operation below 3 VPP is allowable, with
the characteristics of performance versus input amplitude demonstrated in Figure 8 through Figure 10. For
instance, for performance at 2 VPP rather than 3 VPP, refer to the SNR and SFDR at –3.5 dBFS (0 dBFS =
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R
50
0
W
Z
50
0
W
ADS548x
INP
INM
S0176-04
R
200 W
ACSignal
Source
n=2:1
ADS5484
ADS5485
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3 VPP). The maximum swing is determined by the internal reference voltage generator, eliminating the need for
any external circuitry for this purpose. The primary degradation visible if the maximum amplitude is kept to 2 VPP
is ~3 dBc of SNR compared to using 3 VPP, while SFDR is the same or even improved. The smaller input signal
also possibly helps any components in the signal chain prior to the ADC to be more linear and provide better
distortion.
The ADS548x performs optimally when the analog inputs are driven differentially. The circuit in Figure 31 shows
one possible configuration using an RF transformer with termination either on the primary or on the secondary of
the transformer. If voltage gain is required, a step-up transformer can be used.
Figure 31. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
Dither
The ADS548x family of devices contain a dither option that is enabled via the DITHEREN pin. Dither is a
technique applied to convert small static errors in the converter to dynamic errors, which look similar to white
noise in the output. It improves the harmonics that are a function of the static errors. The dither is a low level and
is only indicated in the output waveform as wideband noise that may slightly degrade the SNR. It is
recommended that users should allow the capability to enable/disable it in the event they would like to compare
the results during their evaluation. In addition to the plots on the first page of the data sheet, Figure 8 through
Figure 10 and Figure 19 through Figure 21 show the minor differences of dither on/off when studied.
External Voltage Reference
For systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an
external reference. The dependency on the signal amplitude to the value of the external reference voltage is
characterized typically by Figure 32 (VREF = 1.2 V is normalized to 0 dB as this is the internal reference
voltage). As can be seen in the linear fit, this equates to approximately ~1 dB of signal adjustment per 100 mV of
reference adjustment. The range of allowable variation depends on the analog input amplitude that is applied to
the inputs and the desired spectral performance, as can be seen in the performance versus external reference
graphs in Figure 33 and Figure 34.
For dc-coupled applications that use the VCM pin of the ADS548x as the common mode of the signal in the
analog signal gain path prior to the ADC inputs, Figure 36 indicates little change in VCM output as VREF is
externally adjusted. The VCM output is buffered with a 2-kΩseries output resistor.
The method for disabling the internal reference for use with an external reference is described in Table 5 . The
following VREF adjustment graphs were collected using the ADS5483, but are indicative of the behavior of the
ADS5484/5485. The absolute performance may differ from device to device, but the relative characteristics are
valid.
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Applied External VREF − V
−4
−2
0
2
4
6
8
10
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
Normalized Gain Adjustment − dB
G057
fS = 135 MSPS
fIN = 30 MHz
AIN ≤ −1 dBFS
Normalized to 1.2 VREF
Linear Fit: y = −9.8x + 11.8
Applied External VREF − V
70
75
80
85
90
95
100
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
SFDR − dBc
G058
fS = 135 MSPS
fIN = 30 MHz
Dither Enabled
Signal Amplitude Relative
to Adjusted Fullscale
AIN = −3 dBFS
AIN = −7 dBFS
AIN = −6 dBFS
AIN = −4 dBFS
AIN = −10 dBFS
AIN = −2 dBFS
AIN = −1 dBFS
Applied External VREF − V
60
62
64
66
68
70
72
74
76
78
80
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
SNR − dBc
G059
fS = 135 MSPS
fIN = 30 MHz
Dither Enabled
Signal Amplitude Relative
to Adjusted Fullscale
AIN = −6 dBFS
AIN = −10 dBFS
AIN = −7 dBFS
AIN = −4 dBFS
AIN = −3 dBFS AIN = −1 dBFS
AIN = −2 dBFS
Applied External VREF − V
1.7
1.8
1.9
2.0
2.1
2.2
2.3
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
P − Power − W
G060
fS = 135 MSPS
fIN = 30 MHz
Signal Adjusted to −1 dBFS
Applied External VREF − V
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
VCM Pin Output Voltage − V
G061
ADS5484
ADS5485
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............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
Figure 32. Signal Gain Adjustment versus External Figure 33. SFDR versus External VREF and AIN
Reference (VREF)
Figure 34. SNR versus External VREF and AIN Figure 35. Total Power Consumption versus
External VREF
Figure 36. VCM Pin Output versus External VREF
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ADS5485
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Clock Inputs
The ADS548x equivalent clock input circuit is shown in Figure 37. The clock inputs can be driven with either a
differential clock signal or a single-ended clock input, but differential is highly recommended. The characterization
of the ADS548x is typically performed with a 3-VPP differential clock, but the ADC performs well with a differential
clock amplitude down to ~1 VPP, as shown in Figure 39 and Figure 40 . The performance is optimized when the
clock amplitude is kept above 2 VPP. The clock amplitude becomes more of a factor in performance as the
analog input frequency increases. When single-ended clocking is a necessity, it is best to connect CLKM to
ground with a 0.01-μF capacitor, while CLKP is ac-coupled with a 0.01-μF capacitor to the clock source, as
shown in Figure 38.
Figure 37. Clock Input Circuit
Figure 38. Single-Ended Clock
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Clock Amplitude − VPP
50
60
70
80
90
100
110
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SFDR − dBc
G035
fS = 170 MSPS
fIN = 69.59 MHz
fIN = 130.13 MHz
fIN = 9.97 MHz
fIN = 30.13 MHzfIN = 100.33 MHz
fIN = 170.13 MHz
Clock Amplitude − VPP
65
67
69
71
73
75
77
79
81
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SNR − dBFS
G036
fS = 170 MSPS
fIN = 69.59 MHz fIN = 9.97 MHz
fIN = 30.13 MHz
fIN = 100.33 MHz
fIN = 130.13 MHz
fIN = 170.13 MHz
CLKP
CLKM
ADS548x
0.1 Fm
Clock
Source
S0194-03
ADS5484
ADS5485
www.ti.com
............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
SFDR SNR
vs vs
CLOCK AMPLITUDE CLOCK AMPLITUDE
Figure 39. Figure 40.
For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The
differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a
differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications
because the board level clock jitter is superior.
The sampling process is more sensitive to jitter using high analog input frequencies or slow clock frequencies.
Large clock amplitude levels are recommended when possible to reduce the indecision (jitter) in the ADC clock
input buffer. Whenever possible, the ideal combination is a differential clock with large signal swing (~1 – 3 VPP).
Figure 41 demonstrates a recommended method for converting a single-ended clock source into a differential
clock; it is similar to the configuration found on the evaluation board and was used for much of the
characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.
Figure 41. Differential Clock
The common-mode voltage of the clock inputs is set internally to ~2 V using internal 0.5-kΩresistors. It is
recommended to use ac coupling, but if this scheme is not possible, the ADS548x features good tolerance to
clock common-mode variation (as shown in Figure 42 and Figure 43). The internal ADC core uses both edges of
the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided. Performance
degradation as a result of duty cycle can be seen in Figure 44.
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS5484 ADS5485
ADS5485 is Not Recommended for New Designs
Clock Common-Mode Voltage − V
50
60
70
80
90
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5
SFDR − dBc
G037
30.13 MHz
230.53 MHz 100.33 MHz
69.59 MHz
CLK = 200 MSPS
Clock Common-Mode Voltage − V
66
67
68
69
70
71
72
73
74
75
76
0.5 1.0 1.5 2.0 2.5 3.0 3.5
SNR − dBFS
G038
CLK = 200 MSPS
30.13 MHz
100.33 MHz
69.59 MHz
230.53 MHz
Clock Duty Cycle − %
50
55
60
65
70
75
80
85
90
95
30 35 40 45 50 55 60 65 70
SFDR − dBc
G039
170 MSPS (ADS5484)
200 MSPS (ADS5485)
30 MHz
230 MHz
130 MHz
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
www.ti.com
Figure 42. SFDR versus Clock Common-Mode Figure 43. SNR versus Clock Common-Mode
Voltage Voltage
Figure 44. SFDR vs Clock Duty Cycle
The ADS5484 is capable of achieving 75.7 dBFS SNR at 130 MHz of analog input frequency. In order to achieve
the SNR at 130 MHz the clock source rms jitter (at the ADC clock input pins) must be at most 184 fsec in order
for the total rms jitter to be 201 fsec due to internal ADC aperture jitter of ~80 fsec. A summary of maximum
recommended rms clock jitter as a function of analog input frequency for the ADS5484 is provided in Table 3.
The equations used to create the table are presented and can be used to estimate required clock jitter for
virtually any pipeline ADC, but in particular, the ADS5481/5482/5483/5484/5485 family.
Table 3. Recommended Approximate RMS Clock Jitter for ADS5484
ANALOG INPUT FREQUENCY MEASURED SNR TOTAL JITTER MAXIMUM CLOCK JITTER
(MHz) (dBc) (fsec rms) (fsec rms)
10 76.8 2301 2299
30 75.9 851 847
70 75.7 373 364
130 75.7 201 184
170 75.6 155 133
230 74.9 124 95
24 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5484 ADS5485
ADS5485 is Not Recommended for New Designs
SNR(dBc)= 20 LOG10(2 f j )- p ´´ ´ ´
IN TOTAL
j =(j +j )
TOTAL ADC CLOCK
2 1/22
CLKP
CLKM
REF
400 MHz (To Transmit DAC)
100 MHz (To DSP)
100 MHz (To FPGA)
To Other
10 MHz
400MHz
100 MHz
Low Jitter Oscillator
BPF
LVCMOS XFMR
AMP
AMP and/or BPF Optional
BoardMaster
ReferenceClock
(Highor LowJitter)
VCO/
VCXO
CDC
(ClockDistributionChip)
Ex: TI CDCE72010
LVPECL
or
LVCMOS
ADC
TI ADS548x
B0268-01
ADS5484
ADS5485
www.ti.com
............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
(1)
(2)
where:
jTOTAL = the rms summation of the clock and ADC aperture jitter;
jADC = the ADC internal aperture jitter which is located in the data sheet;
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
fIN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034,Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI
CDCE72010 and CDCM7005. Depending on the jitter requirements, a band pass filter (BPF) is sometimes
required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too
low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be placed
between the CDC and the BPF, as its harmonics and wide-band noise are reduced by the BPF.
Figure 45 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCE72010
with the clock signal path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult
to estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost
amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter
provided by the CDC is still not adequate. The total jitter at the CDCE72010 output depends largely on the phase
noise of the VCXO/VCO selected, as well as from the CDCE72010 itself.
Consult the CDCE72010 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 45. Optimum Jitter Clock Circuit
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): ADS5484 ADS5485
ADS5485 is Not Recommended for New Designs
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
www.ti.com
Digital Outputs
The ADC provides eight LVDS-compatible, offset binary, DDR data outputs (2 bits per LVDS output driver) and a
data-ready LVDS signal (DRY). It is recommended to use the DRY signal to capture the output data of the
ADS548x (use as a clock output). DRY is source-synchronous to the DATA outputs and operates at the same
frequency, creating a full-rate DDR interface that updates data on both the rising and falling edges of DRY. It is
recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance shortens the
data-valid timing window. The values given for timing (see Figure 1) were obtained with a 5-pF parasitic board
capacitance to ground on each LVDS line. When setting the time relationship between DRY and DATA at the
receiving device, it is generally recommended that setup time be maximized, but this partially depends on the
setup and hold times of the device receiving the digital data. Since DRY and DATA are coincident, it will likely be
necessary to delay either DRY such that DATA setup time is maximized.
The LVDS outputs all require an external 100-Ωload between each output pair in order to meet the expected
LVDS voltage levels. For long trace lengths, it may be necessary to place a 100-Ωload on each digital output as
close to the ADS548x as possible and another 100-Ωdifferential load at the end of the LVDS transmission line to
terminate the transmission line and avoid signal reflections. The effective load in this case reduces the LVDS
voltage levels by half. The current of all LVDS drivers is set externally with a resistor connected between the
LVDSB (LVDS bias) pin and ground. Normal LVDS current is 3.5 mA per LVDS pair, set with a 10-kΩexternal
resistor. For systems with excessive load capacitance on the LVDS lines, reducing the resistor value in order to
increase the LVDS bias current is allowed to create a stronger LVDS drive capability. For systems with short
traces and minimal loading, increasing the resistor in order to decrease the LVDS current is allowable in order to
save power. Table 4 provides a sampling of LVDSB resistor values should deviation from the recommended
LVDS output current of 3.5 mA be considered. It is not recommended to exceed the range listed in the table. If
the LVDS bias current is adjusted, the differential load resistance should also be adjusted to maintain voltage
levels within the specification for the LVDS outputs. The signal integrity of the LVDS lines on the board layout
should be scrutinized to ensure proper LVDS signal integrity exists.
Table 4. Setting the LVDS Current Drive
LVDSB RESISTOR TO GND, ΩLVDS NOMINAL CURRENT, mA
6k 5.6
8k 4.3
10k (value for normal recommended operation) 3.5
12k 2.8
14k 2.3
16k 2.0
18k 1.7
20k 1.5
26 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5484 ADS5485
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fIN − Input Frequency − MHz
−120
−100
−80
−60
−40
−20
0
PSRR − dB
0.1 10 1k
G067
1 100
AVDD3V
DVDD3V
AVDD5V
ADS5484
ADS5485
www.ti.com
............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
Power Supplies and Sleep Modes
The ADS548x uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched
supplies generate more noise that can be coupled to the ADS548x. However, the PSRR value and plot shown in
Figure 46 were obtained without bulk supply decoupling capacitors. When bulk (0.1-μF) decoupling capacitors
are used near the supply pins, the board-level PSRR is much higher than the stated value for the ADC. The user
may be able to supply power to the device with a less-than-ideal supply and still achieve good performance. It is
not possible to make a single recommendation for every type of supply and level of decoupling for all systems. If
the noise characteristics of the available supplies are understood, a study of the PSRR data for the ADS548x
may provide the user with enough information to select noisy supplies if the performance is still acceptable within
the frequency range of interest. The power consumption of the ADS548x does not change substantially over
clock rate or input frequency.
Figure 46. PSRR versus Supply Injected Frequency
Two separate sleep modes are offered. They are differentiated by the amount of power consumed and the time it
takes for the ADC to wake-up from sleep. The light sleep mode consumes 605 mW and can be used when
wake-up of less than 600 μs is required. Deep sleep consumes 70 mW and requires 6 ms to wake-up. See the
wake-up characteristic in Figure 27. For directions on enabling these modes, see Table 5. The input clock can be
in either state when the power-down modes are enabled. The device can enter power-down mode whether using
an internal or external reference. However, the wake-up time from light sleep enabled to external reference mode
is dependent on the external reference voltage and is not necessarily 0.6 ms, but should be noticeably faster
than deep sleep wake-up. No specific power sequences are required.
Table 5. Power-Down and Reference Modes
MODE PDWNF PIN PDWNS PIN POWER CONSUMPTION WAKE-UP TIME
ADC On - Internal reference Low Low 2.16 W On
ADC On - External reference High High 2.16 W On
Light sleep High Low 600 mW when enabled 0.6 ms
Deep sleep Low High 70 mW when enabled 6 ms
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): ADS5484 ADS5485
ADS5485 is Not Recommended for New Designs
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
www.ti.com
Layout Information
The evaluation board represents a good model of how to lay out the printed circuit board (PCB) to obtain the
maximum performance from the ADS548x. Follow general design rules, such as the use of multilayer boards, a
single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors. The analog input
traces should be isolated from any external source of interference or noise, including the digital outputs as well
as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications
such as high IF sampling where low jitter is required. Besides performance-oriented rules, care must be taken
when considering the heat dissipation of the device. The thermal heat sink included on the bottom of the
package should be soldered to the board as described in the PowerPad Package section. See the ADS548x
EVM User Guide on the TI web site for the evaluation board schematic.
PowerPAD Package
The PowerPAD package is a thermally-enhanced, standard-size IC package designed to eliminate the use of
bulky heat sink and slugs traditionally used in thermal packages. This package can be easily mounted using
standard PCB assembly techniques and can be removed and replaced using standard repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This pad design provides an extremely low thermal resistance path between the die and the exterior of
the package. The thermal pad on the bottom of the IC can then be soldered directly to the PCB, using the PCB
as a heat sink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section (at the end of this data sheet).
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils (0.013 in or
0.3302 mm) in diameter. The small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25 mil (0.025 in or 0.635 mm) diameter holes under the
package, but outside the thermal pad area, to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application
report (SLMA002), both available for download at www.ti.com.
28 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5484 ADS5485
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SNR +10log10 PS
PN
SINAD +10log10 PS
PN)PD
THD +10log10 PS
PD
ADS5484
ADS5485
www.ti.com
............................................................................................................................................... SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
DEFINITION OF SPECIFICATIONS The injected frequency level is translated into dBFS,
the spur in the output FFT is measured in dBFS, and
Analog Bandwidth the difference is the PSRR in dB. The measurement
The analog input frequency at which the power of the calibrates out the benefit of the board supply
fundamental is reduced by 3 dB with respect to the decoupling capacitors.
low-frequency value. Signal-to-Noise Ratio (SNR)
Aperture Delay SNR is the ratio of the power of the fundamental (PS)
The delay in time between the rising edge of the input to the noise floor power (PN), excluding the power at
sampling clock and the actual time at which the dc and in the first five harmonics.
sampling occurs.
Aperture Uncertainty (Jitter) (4)
The sample-to-sample variation in aperture delay. SNR is either given in units of dBc (dB to carrier)
Clock Pulse Duration/Duty Cycle when the absolute power of the fundamental is used
The duty cycle of a clock signal is the ratio of the time as the reference, or dBFS (dB to full-scale) when the
the clock signal remains at a logic high (clock pulse power of the fundamental is extrapolated to the
duration) to the period of the clock signal, expressed converter full-scale range.
as a percentage. Signal-to-Noise and Distortion (SINAD)
Differential Nonlinearity (DNL) SINAD is the ratio of the power of the fundamental
An ideal ADC exhibits code transitions at analog input (PS) to the power of all the other spectral components
values spaced exactly 1 LSB apart. DNL is the including noise (PN) and distortion (PD), but excluding
deviation of any single step from this ideal value, dc.
measured in units of LSB.
Common-Mode Rejection Ratio (CMRR)
CMRR measures the ability to reject signals that are (5)
presented to both analog inputs simultaneously. The SINAD is either given in units of dBc (dB to carrier)
injected common-mode frequency level is translated when the absolute power of the fundamental is used
into dBFS, the spur in the output FFT is measured in as the reference, or dBFS (dB to full-scale) when the
dBFS, and the difference is the CMRR in dB. power of the fundamental is extrapolated to the
Effective Number of Bits (ENOB) converter full-scale range.
ENOB is a measure in units of bits of converter Temperature Drift
performance as compared to the theoretical limit Temperature drift (with respect to gain error and
based on quantization noise: offset error) specifies the change from the value at
ENOB = (SINAD – 1.76)/6.02 the nominal temperature to the value at TMIN or TMAX.
It is computed as the maximum variation the
Gain Error parameters over the whole temperature range divided
Gain error is the deviation of the ADC actual input by TMIN – TMAX.
full-scale range from its ideal value, given as a
percentage of the ideal input full-scale range. Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
Integral Nonlinearity (INL) to the power of the first five harmonics (PD).
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function. The INL at each analog input (6)
value is the difference between the actual transfer
function and this best-fit line, measured in units of THD is typically given in units of dBc (dB to carrier).
LSB. Two-Tone Intermodulation Distortion (IMD3)
Offset Error IMD3 is the ratio of the power of the fundamental (at
Offset error is the deviation of output code from frequencies f1, f2) to the power of the worst spectral
mid-code when both inputs are tied to component at either frequency 2f1– f2or 2f2– f1).
common-mode. IMD3 is given in units of either dBc (dB to carrier)
when the absolute power of the fundamental is used
Power-Supply Rejection Ratio (PSRR) as the reference, or dBFS (dB to full-scale) when the
PSRR is a measure of the ability to reject frequencies power of the fundamental is extrapolated to the
present on the power supply. converter full-scale range.
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): ADS5484 ADS5485
ADS5485 is Not Recommended for New Designs
ADS5484
ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER 2009...............................................................................................................................................
www.ti.com
REVISION HISTORY
Changes from Revision B (July 2009) to Revision C ..................................................................................................... Page
• Changed pin PDWNF from 35 to 34 ..................................................................................................................................... 9
• Changed pin PDWNS from 34 to 35 ..................................................................................................................................... 9
30 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5484 ADS5485
ADS5485 is Not Recommended for New Designs
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS5484IRGC25 ACTIVE VQFN RGC 64 25 TBD Call TI Call TI
ADS5484IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5484IRGCRG4 ACTIVE VQFN RGC 64 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5484IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5484IRGCTG4 ACTIVE VQFN RGC 64 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5485IRGC25 NRND VQFN RGC 64 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5485IRGCR NRND VQFN RGC 64 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5485IRGCRG4 NRND VQFN RGC 64 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5485IRGCT NRND VQFN RGC 64 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5485IRGCTG4 NRND VQFN RGC 64 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jul-2012
Addendum-Page 2
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS5484IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
ADS5484IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
ADS5485IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS5484IRGCR VQFN RGC 64 2000 333.2 345.9 28.6
ADS5484IRGCT VQFN RGC 64 250 333.2 345.9 28.6
ADS5485IRGCT VQFN RGC 64 250 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Aug-2012
Pack Materials-Page 2
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