(MA) MOTOROLA MCM4027A 4096-8IT DYNAMIC RANDOM ACCESS MEMORY MOS (N-CHANNEL, SILICON-GATE) The MCM4027A is a 4096 x 1 bit high-speed dynamic Random Access Memory. It has smaller die size than the MCM4027 pro- 4096-BIT DYNAMIC viding improved speed selections. The MCM4027A is fabricated RANDOM ACCESS using Motorolas highly reliable N-channel silicon-gate technology. MEMORY By multiplexing row and column address inputs, the MCM4027A requires only six address lines and permits packaging in Motorola's standard 16-pin dual-in-line packages. Complete address decoding is done on chip with address latches incorporated. All inputs are TTL compatible, and the output is 3-state TTL compatible. The MCM4027A incorporates a one-transistor cell design and dynamic storage techniques, with each of the 64 row addresses requiring a refresh cycle every 2.0 milliseconds. @ Maximum Access Time = 120 ns MCM4027AC1 1 150 ns MCM4027AC2 C SUFFIX 200 ns MCM4027AC3 FRIT-SEAL PACKAGE CASE 620 250 ns ~ MCM4027AC4 @ Maximum Read and Write Cycle Time = 320 ns MCM4027AC1, C2 375 ns MCM4027AC3, C4 @ Low Power Dissipation 470 mW Max (Active) PIN ASSIGNMENT 27 mW Max (Standby) 3-State Output for OR-Ties Yea | Vss On-Chip Latches for Address, Chip Select, and Data In Pin 2 cas @ Power Supply Pins on Package Corners for Optimum Layout we 3 Pout @ {Industry Standard 16-Pin Package RAS 4 cs @ Page-Mode Capability ao 65 A3 Compatible with the Popular 2104/MK4096/MCM6604 a2 6 a4 Second Source for MK4027 aro? AS Yoo 8 Veco TRUTH TABLE HAS aes WE Previous ome Present Cycle Power Rat Function L Lt L L Valid data High tmp. input data Full-operating Yes Write cycle L L L H Vatid data High Imp. Valid data (cell) Full-operating Yes Read cycle L L H x Valid data High imp, High Imp. Full-operating Yes Deselected-refresh L H x x Valid data Vatid data Valid data Reduced operating Yes RAS onty-refresh H L x x Valid data High imp. High Imp. Standby No Standby-output disabled H H x x Valid data Valid data Valid data Standby No Standby-output valid H = High, L = Low, X = Dont Care DMOTORCILA INC., 1977 DS 9464 R1MCM4027A BLOCK DIAGRAM WRITE | RAS Clocks zl > w Data in Buffer Deta In Address Clocks CAS Clocks Reset oO a Data Out Buffer Enable Chip Selact Input Buffer AS A4 Acidress Buffers Memory Array A3 (6) Row -of- A2 Decoder 64 Sense Refresh Amplifiers bee as Al Row and {1-0f-64) Data In/Out Gating Select Cofumn AO Memory Array Column Decoder (1-0f-32) OPERATING CHARACTERISTICS AODRESSING DATA OUTPUT The MCM4027A, has six address inputs (AOA5) and In order to simplify the memory system designed and two clock signals designated Row Address Strobe (RAS) reduce the total package count, the MCM4027A contains and Column Address Strobe (CAS). At the beginning of an input data latch and a buffered output data latch. The amemory cycle, the six low order address bits AO through state of the output latch and buffer at the end of a mem- A5 are strobed into the chip with RAS to select one of ory cycle will depend on the type of memory cycle per- the 64 rows. The row address strobe also initiates the tim- formed and whether the chip is selected or unselected for ing that will enable the 64 cotumn sense amplifiers, After that memory cycle. a specified hold tirne, the row address is removed and the A chip will be unselected during a memory cycle if: six high order address bits (AGBA11) are placed on the (1) The chip receives both RAS and CAS signals, address pins. This address is then strobed into the chip but no Chip Select signal. with CAS. Two of the 64 column sense amplifiers are (2) The chip receives a CAS signal but no RAS selected by A1 through AS. A one of two data bus select signal. With this condition, the chip will be is accomplished by AQ to complete the data selection. unselected regardless of the state of Chip The Chip Select (CS) is latched into the port along with Select input. the column addresses, If, during a read, write, or read-modify-write cycle, oo (MA) MOTOROLA Semiconductor Products inc. =__MCM4027A the chip is unselected, the output buffer will be in the high impedance state at the end of the memory cycle. The output buffer will remain in the high impedance state until the chip is selected for a memory cycle, For a chip to be selected during a memory cycle, it must receive the following signals: RAS, CAS, and Chip Select. The state of the output latch and buffer of a selected chip during the following type of memory cycles would be: (1) Read Cycle On the negative edge of CAS, the output buffer will unconditionally go to a high impedance state. !t will remain in this state until access time. At this time, the out- put latch and buffer will assume the logic state of the data read from the selected cell. This output state will be maintained until the chip receives the next CAS signal. (2) Write Cycle If the WE input is switched to a logic 0 before the CAS transition, the output fatch and buffer will be switched to the state of the data input at the end of the access time. This logic state will be maintained until the chip receives the next CAS signal. (3} Read-Modify-Write Same as read cycle. DATA INPUT Data to be written into a selected storage cel! of the memory chip is first stored in the on-chip data latch. The gating of this latch is performed with a combination of the WE and CAS signals. The last of these signals to make a negative transition will strobe the data into the latch. If the WE input is switching to a logic O in the beginning of a write cycle, the falling edge of CAS strobes the data into the latch. The data setup and hold times are then referenced to the negative edge of CAS. \f a read-modify-write cycle is being performed, the WE input would not make its negative transistion until after the CAS signal was enabled. Thus, the data would not be strobed into the latch until the negative transistion of WE. The data setup and hold times would now be ref- erenced to the negative edge of the WE signal. The only other timing constraints for a write-type-cycle is that both the CAS and WE signals remain in the logic 0 state for a sufficient time to accomplish the permanent storage of the data into the selected cell. INPUT/OUTPUT LEVELS All of the inputs to the MCM4027A are TTL-compatible, featuring high impedance and low capacitance (5 to 7 pF). The three-state data output buffer is TTL-compatible and has sufficient current sink capability (3.2 mA) to drive two TTL loads. The output buffer also has a separate Vcc pin so that it can be powered from the same supply as the logic being employed. REFRESH In order to maintain valid data, each of the 64 internal rows of the MCM4027A must be refreshed once every 2 ms. Any cycle in which a RAS signal occurs accomplishes a refresh operation. Any read, write, or read-modify-write cycle will refresh an entire internally selected row. How- ever, if a write or read-modify-write cycle is used to per- form a refresh cycle the chip must be deselected to pre- vent writing data into the selected cell. The memory can also be refreshed by employing only the RAS cycle. This refresh mode will not shorten the refresh cycle time; how- ever, the system standby power can be reduced by approx- imately 30%. If the RAS only refresh cycles are employed for an ex- tended length of time, the output buffer may eventually lose data and assume the high impedance state. Applying CAS to the chip will restore activity of the output buffer. POWER DISSIPATION Since the MCM4027A is a dynamic RAM, its power drain will be extremely small during the time the chip is unselected. The power increases when the chip is selected and most of this increase is encountered on the address strobe edge. The circuitry of the MCM4027A is largely dynamic so power is not drawn during the whole time the strobe is active. Thus the dynamic power is a function of the operating frequency rather than the active duty cycle, In a memory system, the CAS signal must be supplied to all the memory chips to ensure that the outputs of the unselected chips are switched to the high impedance state. Those chips that do not receive a RAS signal will not dissipate any power on the CAS edge except for that required to turn off the chip outputs. Thus, in order to ensure minimum system power, the RAS signal should be decoded so that only the chips to be selected receive a RAS signal. If the RAS signal is decoded, then the chip select input of all the chips can be set to a logic O state. the patent rights of Motorola or others. product(s) at any time. Circuit diagrams external to or containing Motorola products are included as a means of illustration only. Complete information sufficient for construction purposes may not be fully iHustrated. Although the information herein has been carefully checked and is believed to be reliable, Motorola assumes no responsibility for inaccuracies. Information herein does not convey to the purchaser any license under The information contained herein is for guidance only, with no warranty of any type, expressed or implied. Motorola reserves the right ta make any changes to the information and the product(s) to which the information applies and to discontinue manufacture of the 1-15MCM4027A DC OPERATING CONDITIONS AND CHARACTERISTICS (Full operating voltage and temperature range unless otherwise noted.) RECOMMENDED OPERATING CONDITIONS (Referenced to Vgg = Ground.) Parameter Symbol Min Typ Max Unit Notes Supply Voltage Vop 10.8 12.0 13.2 Vde 2 Vec Vss 5.0 Voo Vde 3 Vss 0 9 0 Vde 2 VeB -4.5 -5.0 -55 Vde 2 Logic 1 Voltage, RAS, CAS, WRITE Vinc 2.4 5.0 7.0 Vde 2,4 Logic 1 Voltage, all inputs except RAS, CAS, WRITE Vin 2.2 5.0 7.0 Vde 2,4 Logic 0 Voltage, all inputs VIL -1.0 Q 0.8 Vde 2,4 DC CHARACTERISTICS (Vop = 12 V + 10%, Vec = 5.0 V + 10%, Veg = -5.0 V * 10%, Vsg = 0 V, Ta = 0 to 70C.) Notes 1, 5 Characteristic Symbol Min Typ Max Units Notes Average Vpp Power Supply Current Ipp1 35 mA 6 Voc Power Supply Current lcc mA 7 Average Vag Power Supply Current IBB 250 uA Standby Vpp Power Supply Current Ipp2 2 mA 9 Average Vpp Power Supply Current during Ipp3 25 mA 6 RAS only cycles Input Leakage Current (any input) HL) 10 KA 8 Output Leakage Current boi) 10 HA 9,10 Output Logic 1 Voltage @ lout = -5 MA VOH 2.4 Vde Output Logic 0 Voltage @ Igyz = 3.2 MA VOL 0.4 Vde NOTES 1 through 11: 1. Ta is specified for operation at frequencies to tc > tRcimin}. Operation at higher cycle rates with reduced ambient temperatures and higher power dissipation is permissible provided that all ac parameters are met. 2. All voltages referenced to Vgs. 3. Output voltage will swing from Vsg to Voc when enabled, with no output load. For purposes of mairitaining data in standby mode, Vcc may be reduced to Vgg without affecting refresh operations or data retention. However, the VgHimin) specifica- tion is not guaranteed in this mode. 4, Device speed is not guaranteed at input voltages greater than TTL levels (0 to 5 v). 5. Several cycles are required after power-up before proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose. 6. Current is proportional to cycle rate. Ipp4(max) is measured at the cycle rate specified by tr(min). 7. lec depends on output loading. During readout of high level data Vcc is connected through a low impedance (135 2) typ} to Data Out. At all other times I consists of leakage currents only. 8. All device pins at 0 volts except Vgp which is at -5 volts and the pin under test which is at +10 volts. 9. Output is disabled (high-impedance) and RAS and CAS are both at a logic 1. Transient stabilization is required prior to measurement of this parameter. 10,0V <Vours+10V, 11. Effective capacitance is calculated frorn the equation: = 40 with av = c= av with AV = 3 volts. EFFECTIVE CAPACITANCE (Full operating voltage and temperature range, periodically sampled rather than 100% tested) Note 11 * (Vas - Vee > 4.5 V) NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS ARE EXCEEDED. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Vgg must be applied prior to Vec and Vop. Veep must also be the last power supply switched off. Characteristic Symbol Max Unit Input Capacitance (AO-AS), Din. cs Cin(EFF) 5.0 pF RAS, CAS, WRITE 10.0 Output Capacitance Cout(EFF) 70 pF ABSOLUTE MAXIMUM RATINGS (See Notes 1 and 2) Rating Symbol Value Unit Voltage on Any Pin Relative to Vag* Vine Vout -0.5 to +20 Vde Operating Temperature Range Ta Oto +70 % Storage Temperature Range Tstg ~65 to +150 96 This device contains circuitry to protect the ~ inputs against damage due to high static volt- Output Current (Short Circuit) bout 50 mAdc ages or electric fields; however, it is advised that normal precautions be taken to avoid applica- tion of any voltage higher than maximum rated vo!tages to this high impedance circuit.MCM4027A AC OPERATING CONDITIONS AND CHARACTERISTICS (Read, Write, and Read-Modify-Write Cycles) RECOMMENDED AC OPERATING CONDITIONS (Vop = 12 V 10%, Vec = 5.0 V + 10%, VaR = -5.0 V + 10%, Vgg = OV, Parameter Read or Write Read Write Time Time Row Strobe Time From Column Address and Turn-Off Time Pulse Width Pulse Width Time Lead Time mn Address Hold Time Address Hold Time Referenced to Ti Time Referenced to Time Rise and Fall Ti Time Time Command Hold Time Referenced to Command Pulse Width Write Command to Row Strobe Lead Time to Column Strobe Lead Time Time Ti Data in Referenced to Strobe Time Time mn Refresh Period Command Time Oata Out Hold Time NOTES 12 through 20: 12. AC measurements assume ty = 5 ns. 13. The specifications for tag{min) and tRyc(min) are used only to indicate cycle time at which proper operation over the full temperature range (0C < Ta < 70C) is assured. 14, Assumes that taco < tacp(max). 15, Assumes that tacp 2 tacp (max). 16. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 17, Operation within the tacp(max) timit insures that tRacimax} can be met. tacp(max) is specified as a reference point only; if trcp is greater than the specified tap(max) limit, then access time is controiled exclusively by tcac. Ta = Oto 70C.) Notes 1, 5, 12,18 MCM4027AC3 375 375 18.Vip(min) or Vip (min) anc Vj, (max) are reference levels for measuring timing of input signals. Also, transition times are measured between Vip or Vy and VIL. 19.These parameters are referenced to CAS leading edge in random write cycles and to WRITE leading edge in delayed write or read-modify write cycles. 20.twes. towo. 2nd tRwp are not restrictive operating para- meters. They are included in the data sheet as electrical charac- terisites only: If twos = tweglmin), the cycle is an early write cycle and Data Out will contain the data written into the selected cell. If tewo 2 tewplmin) and tawp 2 tawp(min), the cycle is a read-write cycle and Data Out will contain data read from the setected cell. if neither of the above sets of conditions is satisfied, the condition of Data Out (at access time) is indeterminate. (SY MOTOROLA Semiconductor Products Inc.MCM4027A PACKAGE DIMENSIONS UN eel g be K adab Io ie JL, SEATING PLANE CASE 620-04 B NOTES: 1, LEADS WITHIN 0,13 mm (0.005) RADIUS 1 || OF TRUE POSITION AT SEATING PLANE Wy, AT MAXIMUM MATERIAL CONDITION. _{ L 2. PKG. INDEX: NOTCH IN LEAD Fre NOTCH IN CERAMIC OR INK DOT. | 3. [HM A AND 8 DO NOT a ___ INCLUDE GLASS RUN-OUT. 4. DIM L TO INSIDE OF LEADS (MEASURED 0.51 mm (0.020) BELOW BODY} READ CYCLE TIMING VoL Vv RAS NH Vie Vv SKE (HC Vie tRAH tasc tCAH Vin FR AD low Column ORESSES Vin Address Address ~ Mine WRITE Vie wl . Vin Bout Vou TRAC | (SY MOTOROLA Semiconductor Products inc. __MCM4027A WRITE CYCLE TIMING Vince RAS Vie Vine CAS Vie tRAH tasc Min Row Column DRE AD SSES Vie Address Address twe WRITE Vine Vin b Vin in ViL Vix cs VoL 4 (*'poH VOH Dout open VAUD VoL DATA oo (SY MOTOROLA Semiconductor Products inc.MCM4027A READ-MODIFY-WRITE TIMING tar 4 Vin -~ V AAS tHe . %V CAS Vik tASR appresses YH Vie Address Address _ Vv WRITE Vic == IH ts ViL Vou Dout VoL Vin Din Vii RAS ONLY REFRESH TIMING tre + TR AS, Vine | RAS Vin tRAH *| tasR s VIH f POCO OOO OOOO OOO 04 ADDRESSES Vin RRRR RRR Raw address [O> SRS RIK SOLS 82 ORR K tap i Vv Bout OH Vou (SY MOTOROLA Semiconductor Products inc. --~ 1-20MCM4027A PAGE MODE READ CYCLE RAS tRAS Vinc- 1 ro tan Vin - N , {+ \_ htc SH__ > oC RSH tre ~+" ane ld ke-tROD ag ed wtcrey betas ae) eee Vince - a Vir - N Zz N tRAH -tCAH pe tcan pa CAH TASR ' Sion Pe Pras Vv 7 ow P54 soe SNF EAE HTL MHS a i | nn] whee tesc Z Vind miss XY Munn Dout Write ! coe oO boon VoH- | VaL- Open | tacs*| rnenal Vinic- Vin - are Tt iy RY tOFF | LL tres 1) tOFF -4 ;}__ PAGE MODE WRITE CYCLE + tRAS Ras. OVIHC- aR RAS Vin = s > ~tCS 4 . ke-trSHoy fe-tgp le-tRcoimy katCAS eet RP: Exe Vine = + e Vin tCAH tasA tascm| ke Vin- R i a cal 4 OO, Addresses \/'4 Gay Row CORR RORY, 55a RRR RARE oh > pe-sese | | as RRO ve Vien ~P | ARIXRYRRRRRENR ee v beet tore t-toFF tOFF P-tOOH OH 5 iP Pout voy. r . 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