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IR1176
Dynamic Electrical Characteristics
Vdd=5V, TA = 25oC, Rbias = 34.0K unless otherwise specified.
Symbol Definition Min. Typ. Max. Units
Vdd Supply voltage operating range 4.0 —5.25 VDC
Iqdd Vdd quiescent current (x1 = x2 = 0V or 5V, Iout = 0) —4 5 A
Freq Operating frequency 100 —2000 KHz
UVSET+ UVSET positive going threshold 1.10 —1.4 V
UVSET- UVSET negative going threshold 0.8 —1.1 V
Vxth+ X1/X2 Input positive going threshold —1.4 —VDC
Vxth- X1/X2 Input negative going threshold —1.0 —VDC
Tadv Externally adjustable lead time (advance) — — 500 nsec
Td Externally adjustable dead-time for Q1 and Q2 20 — — nsec
Isink Q1,Q2 output sink current (Vdd=5.0V, —4—
(peak) pulsed, 10 usec)
Isource Q1,Q2 output source current (Vdd=5.0V, —4—
(peak) pulsed, 10 usec)
VOH Q1, Q2 High level voltage (Iout = 20mA) —Vdd- 0.20 —
VOL Q1, Q2 Low level voltage (Iout = 20mA) —0.10 —
tio Input to output delay (PLL bypassed, cross coupled —20 —nsec
mode)
tr Gate turn-on rise time (C1=1000pf, Vdd=5V) —20 —nsec
tf Gate turn-off fall time (C1=1000pf, Vdd=5V) —20 —nsec
Vtr Cross-over voltage (Vdd=5Vdc, DTIN shorted to —2.5 —VDC
DTOUT, C1=1000pf) Fig. 3
Rbias Required bias resistor (1%) —34.0 —KΩ
Vbias Voltage at Rbias pin —1.25 —VDC
Tjitter Phase-lock loop output jitter -20 —20 nsec
Ichgpump Charge pump output current (at VFLTR pin) —50 —µADC
Vchgpump Charge pump output voltage (at VFLTR pin) 1.3 1.5 1.7 VDC
Kvco_dc PLL Vco DC gain (per design) —62 —KHz/
Volt
V
A