IR1176S - International Rectifier

Packages

SYNCHRONOUS RECTIFIER DRIVER

Features

•Provides constant and proper gate drive to power

MOSFETs regardless of transformer output

• Minimizes loss due to power MOSFET body

drain diode conduction

• Stand alone operation - no ties to primary side

• Schmitt trigger input with double pulse suppress-

ion allows operation in noisy environments

• High peak current drive capability - 4A

• High speed operation - 2MHz

• Adaptable to multiple topologies

Description

The IR1176 is a high speed CMOS controller designed

to drive N-channel power MOSFETs used as synchro-

nous rectifiers in high current, high frequency forward

converters with output voltages equal or below 5VDC.

Schmitt trigger inputs with double pulse suppression

allow the controller to operate in noisy environments.

The circuit does not require any ties to the primary

side and derives its operating power directly from

the secondary. The circuit functions by anticipating

transformer output transitions, then turns the power

MOSFETs on or off before the transitions of the trans-

former to minimize body drain diode conduction and

reduce associated losses. Turn on/off lead time can

be adjusted to accommodate a variety of power

MOSFET sizes and circuit conditions. The IR1176 also

provides gate drive overlap/dead-time control via

external components to further minimize diode con-

duction by nulling effects of secondary loop and de-

vice package inductance.

Vdd 5Vdc

IO+/- (peak) 4A/4A

Fmax 2MHz

Max lead time 500nsec

Product Summary

IR1176S

20 Lead Surface Mount

(SSOP-20)

IR1176

20 Lead PDIP

(MS-001AD)

IR1176SS

20 Lead SOIC (MS-013AC)

IR1176

Preliminary Data Sheet PD60185-C

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IR1176

Symbol Definition Min. Max. Units

Vdd Supply voltage —7VDC

Iin Input clamp current —+/- 10 mADC

PDPower dissipation (SSOP-20) —400 mW

(SOIC) — — —

(PDIP) — — —

RthJC Thermal resistance (SSOP-20) junction-to-case —28.5

(SOIC) junction-to-case —20

(PDIP) junction-to-case —28.1

RthJA Thermal resistance (SSOP-20) junction-to-ambient —90.5

(SOIC) junction-to-ambient —45

(PDIP) junction-to-ambient —62.4

TJJunction temperature —150

TSStorage temperature -55 150

TLLead temperature (soldering, 10 seconds) —300

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.

Symbol Definition Min. Typ. Max. Units

Vdd Supply voltage operating range —5—VDC

TAAmbient temperature -40 —85 °C

Freq Operating frequency 250 —500 KHz

Rbias Required bias resistor (+/- 1%) —34.0 —KΩ

UV Voltage at UVSET pin 1.75 —2.25 VDC

Xin Maximum voltage at X1 and X2 inputs — — 5.6 VDC

Cd1/Cd2 Capacitance at pins DTIN1 and DTIN2 — — 100 pF

Recommended Operating Conditions

°C

°C/W

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IR1176

Dynamic Electrical Characteristics

Vdd=5V, TA = 25oC, Rbias = 34.0K unless otherwise specified.

Symbol Definition Min. Typ. Max. Units

Vdd Supply voltage operating range 4.0 —5.25 VDC

Iqdd Vdd quiescent current (x1 = x2 = 0V or 5V, Iout = 0) —4 5 A

Freq Operating frequency 100 —2000 KHz

UVSET+ UVSET positive going threshold 1.10 —1.4 V

UVSET- UVSET negative going threshold 0.8 —1.1 V

Vxth+ X1/X2 Input positive going threshold —1.4 —VDC

Vxth- X1/X2 Input negative going threshold —1.0 —VDC

Tadv Externally adjustable lead time (advance) — — 500 nsec

Td Externally adjustable dead-time for Q1 and Q2 20 — — nsec

Isink Q1,Q2 output sink current (Vdd=5.0V, —4—

(peak) pulsed, 10 usec)

Isource Q1,Q2 output source current (Vdd=5.0V, —4—

(peak) pulsed, 10 usec)

VOH Q1, Q2 High level voltage (Iout = 20mA) —Vdd- 0.20 —

VOL Q1, Q2 Low level voltage (Iout = 20mA) —0.10 —

tio Input to output delay (PLL bypassed, cross coupled —20 —nsec

mode)

tr Gate turn-on rise time (C1=1000pf, Vdd=5V) —20 —nsec

tf Gate turn-off fall time (C1=1000pf, Vdd=5V) —20 —nsec

Vtr Cross-over voltage (Vdd=5Vdc, DTIN shorted to —2.5 —VDC

DTOUT, C1=1000pf) Fig. 3

Rbias Required bias resistor (1%) —34.0 —KΩ

Vbias Voltage at Rbias pin —1.25 —VDC

Tjitter Phase-lock loop output jitter -20 —20 nsec

Ichgpump Charge pump output current (at VFLTR pin) —50 —µADC

Vchgpump Charge pump output voltage (at VFLTR pin) 1.3 1.5 1.7 VDC

Kvco_dc PLL Vco DC gain (per design) —62 —KHz/

Volt

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IR1176

DTOUT2

VFLTRI

DTIN2

RADV1

VFLTR2

DTIN1

DTOUT1

RADV2

RVCO1

RVCO2

VSS

Q2*VDD

AVDD

UVSET

AVSS

RBIAS

IR1176S

(SSOP-20) IR1176SS

SOIC (wide body)

Lead Definitions and Assignments

Symbol Description

AVDD Power - + 5 VDC to MOSFET drivers

Q1 Output - gate drive for Q1 power MOSFET

DTOUT1 Output - sets dead time for Q1 output - used with DTIN1

DTIN1 Input - sets dead time for Q1 - used with DTOUT1

RADV1 Output - sets lead time (advance) for Q1

VFLTR1 Output - PLL loop filter for Q1 output

RVCO1 Output - sets PLL center frequency for Q1 output

X1 Input - transformer input for Q1

VDD Power - +5 Vdc for internal logic

UVSET Input - sets UVLO+ If this pin is pulled below 1.25VDC externally, then both Q1 and Q2

outputs will be at Vss (disabled)

RBIAS Output - connected to 34.0K +/- 1% resistor - sets operating current

AVSS Ground for MOSFET driver supply (VDD)

X2 Input - transformer input for Q2

RVCO2 Output - sets PLL center frequency for Q2 output

VFLTR2 Output - PLL loop filter for Q2

RADV2 Output - sets lead time (advance) for Q2

DTIN2 Input - sets dead time for Q2 - used with DTOUT2

DTOUT2 Output - sets dead time for Q2 - used with DTIN2

VSS Ground for logic supply (AVDD)

Q2 Output - gate drive for Q2 power MOSFET

IR1176

PDIP

DTOUT2

VFLTRI

DTIN2

RADV1

VFLTR2

DTIN1

DTOUT1

RADV2

RVCO1

RVCO2

VSS

*VDD

AVDD

UVSET

AVSS

RBIAS

DTOUT2

VFLTRI

DTIN2

RADV1

VFLTR2

DTIN1

DTOUT1

RADV2

RVCO1

RVCO2

VSS

Q2*VDD

AVDD

UVSET

AVSS

RBIAS

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IR1176

Fig. 1 Typical application circuit when supply Vout < 5.0 VDC

Fig. 2 Typical application circuit when supply Vout = 5.0 VDC

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IR1176

Fig. 3 Gate drive characteristics and definitions

Phase Lock Loop Design Equations:

1 - Resistor to set VCO Ceter Frequency:

Rvco (KΩ) = [1E2 x Vchgpump(VDC) / fvco(KHz)] x Kvco _ dc(KHz/Volt)

Example (A): Choose Vchgpump = 1.5V, desired frequency (fvco) = 300KHz

Rvco = [1E2 x 1.5 /300] x 62 Hz = 31 KΩ

2 - Small Signal gain for VCO:

Kvco_ac (KHz/Volt) = 1E2 x Kvco_dc (KHz/Volt)/Rvco(KΩ)

Example (B): Choosing same conditions as in example A:

Kvco_ac = 1E2 x 62 / 31 = 200 KHz/volt

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IR1176

Fig. 4 PLL loop filter component definitions

4 - PLL Damping factor calculations:

P = ππE-3 x Rf (KOhms) x C(nF) x fn(KHz)

Typical value for P is 0.707. (Critically damped)

5 - Advance timing:

Tadv(nsec) = RADV (KOhms)*10 - 10

Where RADV is resistance from RADV1 or RADV2 to ground.

Example C: RADV=10Kohms will result in Tadv=10*10 - 10 =90 nsec .

6- Dead time calculations:

Td(nsec)=0.69*Rdt(KOhms)*Cdt(pF) + 5 (For Vdd=5 V)

Where Rdt is resistance between pins DTIN1 and DTOUT1 or DTIN2 and

DTOUT2. Cdt is capacitance from DTIN1 or DTIN2 to ground.

3 - PLL Natural frequency:

ωωn =2ππfn(KHz)= √√ Ichpump(uA) x Kvco_ac(KHz/V) / C(nF)

Choose Cf such that

Cf=C/16

+ 6=106 nsec.

Example D: Rd=2KW and Cdt=100pF will result in Td=148.35nsec.

+ 6

Td(nsec)=0.69*Cdt(pF)*(Rdt(KΩ)+0.15) (For Vdd=5V)

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IR1176

Fig. 5 IR1176 Block Diagram

IR1176

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IR1176

100

200

300

400

500

time

100

200

300

400

500

-60 -30 030 60 90 120

T_DT (ns)@R=1K

T_DT (ns)@R=5K

T_DT (ns)@R=10K

100

200

300

400

500

time

temperature

Temperature Response

T_DT vs R_DT, C = 100pF

resistance

Response at 25oC

T_ADV vs R_ADV

temperature

Temperature Response

T_ADV vs R_ADV

resistance

Response at 25oC

T_DT vs R_DT, C = 100pF

0 2K 4K 6K 8K 10K

0 10K 20K 30K 40K 50K

time

100

200

300

400

500

-60 -30 030 60 90 120

temperature

time

T_ADV (ns)R=5K

T_ADV (ns)R=10K

T_ADV (ns)R=20K

T_ADV (ns)R=45K

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IR1176

01-6057 00

01-3078 00 (MS013AC)

20 Lead Surface Mount (SSOP-20)

Case Outline

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IR1176

01-6070 00

01-3080 00 (MS013AC)

20 Lead SOIC

Case Outline

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IR1176

01-6069 00

01-3079 00 (MS001AD)

20 Lead PDIP

Case Outline

WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105

Data and specifications subject to change without notice. 1/7/2002