PIC24EP512GU810E/BG - Microchip Technology, Inc.

dsPIC33EPXXXMU806/810/814

and PIC24EPXXXGU810/814

Data Sheet

High-Performance, 16-Bit

Digital Signal Controllers

and Microcontrollers

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-143-8

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 2 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in Calif ornia

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microper ipher als, nonvol ati le memo ry and

analog product s. In addition, Microchip ’s quality system for th e design

and manufacture of development systems is ISO 9001:2000 certified.

dsPIC33EPXXXMU806/810/814

and PIC24EPXXXGU810/814

Operating Range:

• Up to 60 MIPS Operation (at 3.0V-3.6V):

- Industrial temperature range (-40°C to +85°C)

- Extended temperature range (-40°C to +125°C)

High-Performance MCU CPU:

(All Devices)

• Modified Harvard Architecture

• C Compiler Optimized Instruction Set

• 16-bit Wide Data Path

• 24-bit Wide Instructions

• Linear Program Memory Addressing up to 4M

Instruction Words

• Linear Data Memory Addressing up to 64 Kbytes

• 73 Base Instructions: mostly with an effective

instruction execution throughput of one instruction

per cycle

• Flexible and Powerful Indirect Addressing mode

• Software Stack

• 16x16 Integer Multiply Operations

• 32/16 and 16/16 Integer Divide Operations

• Up to ±16-bit Shifts

Additional High-Performance DSC CPU

Features:

(dsPIC33EPXXXMU806/810/814 Devices

Only)

• 11 Additional Instructions

• Two 40-bit Accumulators with Rounding and

Saturation Options

• Additional Flexible and Powerful Addressing

modes:

- Modulo

- Bit-Reversed

• Single-Cycle Multiply and Accumulate:

- Accumulator write back for DSP operations

- Dual data fetch

• Single-Cycle shifts for up to 40-bit Data

• 16x16 Fractional Multiply/Divide Operations

Direct Memory Access (DMA):

• 15-Channel Hardware DMA:

- Allows for transfer of data to/from any data

memory location

• Up to 4 Kbytes Dual Ported DMA Buffer Area

(DPSRAM) to store data transferred via DMA:

- Allows for fast data transfer between RAM

and a peripheral while CPU is executing code

(no cycle stealing)

• Most Peripherals Support DMA

Interrupt Controller:

• 13-Cycle Fixed Latency or 9- to 13-Cycle Variable

Latency (user-selectable)

• Up to 116 Available Interrupt Sources

• Up to Five External Interrupts

• Seven Programmable Priority Levels

• Seven Processor Exceptions

Timers/Capture/Compare/PWM:

• Timer/Counters, up to Nine 16-bit Timers:

- Can pair up to make four 32-bit timers

- One timer runs as a Real-Time Clock with an

external 32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to 16 channels):

- Independent 16-bit time base

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

- Synchronous, Triggered and Cascaded modes

• Output Compare (up to 16 channels):

- Independent 16-bit time base

- Single or Dual 16-bit Compare mode

- 16-bit Glitchless PWM mode

- Synchronous, Triggered and Cascaded modes

• Hardware Real-Time Clock and Calendar

(RTCC):

- Provides clock, calendar, and alarm functions

High-Performance, 16-bit Digital Signal Controllers

and Microcontrollers

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Digital I/O:

• Peripheral Pin Select (PPS) Functionality

• Wake-up/Interrupt-on-Change for up to 122 pins

• Output Pins can drive from 3.0V to 3.6V

• Up to 5V Output with Open Drain Configuration

• Up to 8 or 10 mA sink on I/O pins

• Up to 8 mA or 12 mA source on I/O pins

On-Chip Flash and SRAM:

• Flash Program Memory (up to 512 Kbytes)

• Flash Auxiliary Memory (up to 24 Kbytes):

- Can be used as Bootloader space or for

EEPROM emulation without stalling the CPU

• Data SRAM (up to 52 Kbytes)

• Read/Write Security for Program Flash and

Auxiliary Memory

System Management:

• Flexible Clock Options:

- External, crystal, resonator, internal RC

- Fully integrated Phase-Locked Loop (PLL)

- Extremely low jitter PLL

- Auxiliary PLL for USB clocking

- Reference clock output

• Programmable Power-up Timer

• Oscillator Start-up Timer

• Watchdog Timer with its own RC Oscillator

• Fail-Safe Clock Monitor

• Multiple Reset Sources

Power Management:

• On-chip 1.8V Voltage Regulator

• Switch between Clock Sources in Real Time

• Idle, Sleep, and Doze modes with Fast Wake-up

CMOS Flash Technology:

• Low-Power, High-Speed Flash Technology

• Fully Static Design

• 3.3V (±10%) Operating Voltage

• Industrial and Extended Temperature

• Low-Power Consumption

Analog-to-Digital Converters (ADCs):

• 10-bit, 1.1 Msps or 12-bit, 500 Ksps Conversion:

- Two and four simultaneous samples (10-bit mode)

- Up to 32 input channels with auto-scanning

- Conversion start can be manual or

synchronized with one of 13 trigger sources

- Conversions in Sleep mode

- ±2 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

• Additional 10-bit, 1.1 Msps ADC, with up to 16

Input Channels

Data Converter Interface (DCI) Module:

(dsPIC33EPXXXMU806/810/814 Devices

Only)

• Codec Interface

• Supports I2S and AC’97 Protocols

• Up to 16-bit Data Words, up to 16 Words per

Frame:

- 4-word deep TX and RX buffers

Comparator Module:

• Three Analog Comparators with Programmable

Input/Output Configuration

• Blanking and Filtering Options

• Internal or External Voltage References

Motor Control Peripherals:

(dsPIC33EPXXXMU806/810/814 Devices

Only)

• Motor Control PWM:

- Two master time base modules can control

dual 3-phase motors simultaneously

- Up to seven PWM generators

- Two PWM outputs per PWM generator

- Individual period and duty cycle for each

PWM output

- Dead-time insertion and correction

- Duty cycle, dead time, phase shift and

frequency resolution of 8.32 ns

- Seven independent Fault and current-limit

inputs

- Center-Aligned, Edge-Aligned, Push-Pull,

Multi-Phase, Variable Phase, Fixed Off-time,

Current Reset and Current Limit modes

- Output override control

- Output Chopping (gated) mode

- Special Event Triggers

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Motor Control Peripherals (Continued):

(dsPIC33EPXXXMU806/810/814 Devices

Only)

• Quadrature Encoder Interface (QEI):

- 32-bit position counter

- 32-bit Index pulse counter

- 32-bit Interval timer

- 16-bit velocity counter

- 32-bit Position Initialization/Capture/Compare

High register

- 32-bit Position Compare Low register

- x4 Quadrature Count mode

- External Up/Down Count mode

- External Gated Count mode

- External Gated Timer mode

- Internal Timer mode

Communication Modules:

• USB On-The-Go (OTG):

- USB v2.0 On-The-Go (OTG) compliant

- Dual role capable – can act as either Host or

Peripheral

- Low-speed (1.5 Mbps) and Full-speed

(12 Mbps) USB operation in Host mode

- High-precision PLL for USB

- Supports up to 32 endpoints (16 bidirectional):

• USB module can use any RAM location on the

device as USB endpoint buffers:

- On-chip USB transceiver

- Interface for Off-chip USB transceiver

- On-chip pull-up and pull-down resistors

• 4-wire SPI (up to four modules):

- Framing supports I/O interface to simple

codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and

sampling modes

•I

2C™ (up to two modules):

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

- IPMI support

- SMBus support

Communication Modules (Continued):

• UART (up to four modules):

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

-IrDA

® encoding and decoding in hardware

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

• Enhanced CAN (ECAN™) 2.0B active (up to two

modules):

- Up to eight transmit and up to 32 receive buffers

- 16 receive filters and three masks

- Loopback, Listen Only and Listen All

- Messages modes for diagnostics and bus

monitoring

- Wake-up on CAN message

- Automatic processing of Remote

Transmission Requests

- FIFO mode using DMA

- DeviceNet™ addressing support

• Parallel Master Slave Port (PMP/EPSP):

- Supports 8-bit or 16-bit data

- Supports up to 16 address lines

• Programmable Cyclic Redundancy Check (CRC):

- Programmable bit length for the CRC

generator polynomial (up to 32-bit length)

- 4x32, 8x16 or 16x8 FIFO for data input

Packaging:

• 64-pin QFN (9x9x0.9 mm)

• 64-pin TQFP (10x10x1 mm)

• 100-pin TQFP (12x12x1 mm)

• 100-pin TQFP (14x14x1 mm)

• 121-pin BGA (10x10x1.2 mm)

• 144-pin LQFP (20x20x1.4 mm)

• 144-pin TQFP (16x16x1 mm)

Note: See Table 1 for exact peripheral features

per device.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 PRODUCT

FAMILIES

The device names, pin counts, memory sizes and

peripheral availability of each device are listed in

Table 1. Their pinout diagrams appear on the following

pages.

TABLE 1: dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814 CONTROLLER FAMILIES

Device

Pins

Packages

Program Flash Memory

(Kbyte)(1)

RAM (Kbyte)(2)

Remappable Peripherals

RTCC

I2C™

CRC Generator

10-bit/12-bit ADC(8)

USB

I/O Pins

16-bit Timer(3,4)

Input Capture

Output Compare (with PWM)

Motor Control PWM

(Channels)(5)

QEI

UART with IrDA®

SPI

ECAN™

External Interrupts(6)

DMA Controller (Channels)

DCI

Analog Comparators/

Inputs Per Comparator(7)

Parallel Master Por t

dsPIC33EP256MU806 64 QFN,

TQFP 2802891616 8 244251513/4121

2 ADC,

24 ch 1Y51

dsPIC33EP256MU810 100 TQFP 280289161612 244251513/4121

2 ADC,

32 ch 1Y83

121 BGA

dsPIC33EP256MU814 144 TQFP,

LQFP 280289161614 244251513/4121

2 ADC,

32 ch 1 Y 122

dsPIC33EP512MU810 100 TQFP 536529161612 244251513/4121

2 ADC,

32 ch 1Y83

121 BGA

dsPIC33EP512MU814 144 TQFP,

LQFP 536529161614 244251513/4121

2 ADC,

32 ch 1 Y 122

PIC24EP256GU810 100 TQFP 2802891616 0 044251503/4121

2 ADC,

32 ch 1Y83

121 BGA

PIC24EP256GU814 144 TQFP,

LQFP 2802891616 0 044251503/4121

2 ADC,

32 ch 1 Y 122

PIC24EP512GU810 100 TQFP 5365291616 0 044251503/4121

2 ADC,

32 ch 1Y83

121 BGA

PIC24EP512GU814 144 TQFP,

LQFP 5365291616 0 044251503/4121

2 ADC,

32 ch 1 Y 122

Note 1: Flash size is inclusive of 24 Kbytes of auxiliary Flash.

2: RAM size is inclusive of 4 Kbytes of DMA RAM (DPSRAM) for all devices.

3: Up to eight of these timers can be combined into four 32-bit timers.

4: Eight out of nine timers are remappable.

5: PWM faults and Sync signals are remappable.

6: Four out of five interrupts are remappable.

7: Comparator output is remappable.

8: The ADC2 module supports 10-bit mode only.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Pin Diagrams

64-Pin QFN

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See

Section 11.4 “Peripheral Pin Select” for available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0

“I/O Ports” for more information.

= Pins are up to 5V tolerant

dsPIC33EP256MU806

AN29/PWM3H/PMD5/RP85/RE5

AN31/PWM4H/PMD7/RP87/RE7

C1IND/SCK2/PMA5/RP118/RG6

C1INC/SDI2/PMA4/RPI119/RG7

C2IND/SDO2/PMA3/RP120/RG8

MCLR

C2INC/PMA2/RPI121/RG9

PGEC3/AN1/V

REF

-/RPI33/RB1

PGED3/AN0/V

REF

+/RPI32/RB0

AN30/PWM4L/PMD6/RPI86/RE6

PGEC2/SOSCO/C3INC/T1CK/RPI62/RC14

PGED2/SOSCI/C3IND/RPI61/RC13

INT0/DMH/RP64/RD0

PMCS1/RPI75/RD11

ASCL1/PMCS2/RPI74/RD10

ASDA1/DPLN/RPI73/RD9

RTCC/DMLN/RPI72/RD8

OSC2/CLKO/RC15

OSC1/RPI60/RC12

USBID/RP99/RF3

AN28/PWM3L/PMD4/RP84/RE4

AN27/PWM2H/PMD3/RPI83/RE3

AN26/PWM2L/PMD2/RP82/RE2

AN25/PWM1H/PMD1/RPI81/RE1

AN24/PWM1L/PMD0/RP80/RE0

VCMPST2/

RP97/RF1

CMPST

1/RP96/RF0

VCAP

C3INA/V

CMPST

3/RP71/RD7

C3INB/RP70/RD6

PMRD/RP69/RD5

PMWR/RP68/RD4

PMBE/RP67/RD3

DPH/RP66/RD2

VCPCON/RP65/RD1

PGEC1/AN6/RPI38/RB6

PGED1/AN7/RCV/RPI39/RB7

AN8/PMA6/RPI40/RB8

AN9PMA7//RPI41/RB9

TMS/AN10/CV

REF

/PMA13/RPI42/RB10

TDO/AN11/PMA12/RPI43/RB11

VDD

TCK/AN12/PMA11/RPI44/RB12

TDI/AN13/PMA10/RPI45/RB13

AN14/PMA1/RPI46/RB14

AN15/PMA0/RPI47/RB15

SDA2/PMA9/RP100/RF4

SCL2/PMA8/RP101/RF5

D+/RG2

D-/RG3

USB

BUS

AN5/C1INA/V

BUSON

BUSST

/RPI37/RB5

AN4/C1INB/USBOEN/RPI36/RB4

AN3/C2INA/VPIO/RPI35/RB3

AN2/C2INB/VMIO/RPI34/RB2

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Pin Diagrams (Continued)

64-Pin TQFP

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See

Section 11.4 “Peripheral Pin Select” for available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0

“I/O Port s” for more information.

= Pins are up to 5V tolerant

dsPIC33EP256MU806

AN29/PWM3H/PMD5/RP85/RE5

AN31/PWM4H/PMD7/RP87/RE7

C1IND/SCK2/PMA5/RP118/RG6

C1INC/SDI2/PMA4/RPI119/RG7

C2IND/SDO2/PMA3/RP120/RG8

MCLR

C2INC/PMA2/RPI121/RG9

AN5/C1INA/V

BUSON

BUSST

/RPI37/RB5

AN4/C1INB/USBOEN/RPI36/RB4

AN3/C2INA/VPIO/RPI35/RB3

AN2/C2INB/VMIO/RPI34/RB2

PGEC3/AN1/V

REF

-/RPI33/RB1

PGED3/AN0/V

REF

+/RPI32/RB0

AN30/PWM4L/PMD6/RPI86/RE6

PGEC2/SOSCO/C3INC/T1CK/RPI62/RC14

PGED2/SOSCI/C3IND/RPI61/RC13

INT0/DMH/RP64/RD0

PMCS1/RPI75/RD11

ASCL1/PMCS2/RPI74/RD10

ASDA1/DPLN/RPI73/RD9

RTCC/DMLN/RPI72/RD8

OSC2/CLKO/RC15

OSC1/RPI60/RC12

USBID/RP99/RF3

AN28/PWM3L/PMD4/RP84/RE4

AN27/PWM2H/PMD3/RPI83/RE3

AN26/PWM2L/PMD2/RP82/RE2

AN25/PWM1H/PMD1/RPI81/RE1

AN24/PWM1L/PMD0/RP80/RE0

VCMPST2/

RP97/RF1

CMPST

1/RP96/RF0

VCAP

C3INA/V

CMPST

3/RP71/RD7

C3INB/RP70/RD6

PMRD/RP69/RD5

PMWR/RP68/RD4

PMBE/RP67/RD3

DPH/RP66/RD2

VCPCON/RP65/RD1

PGEC1/AN6/RPI38/RB6

PGED1/AN7/RCV/RPI39/RB7

AN8/PMA6/RPI40/RB8

AN9PMA7//RPI41/RB9

TMS/AN10/CV

REF

/PMA13/RPI42/RB10

TDO/AN11/PMA12/RPI43/RB11

TCK/AN12/PMA11/RPI44/RB12

TDI/AN13/PMA10/RPI45/RB13

AN14/PMA1/RPI46/RB14

AN15/PMA0/RPI47/RB15

SDA2/PMA9/RP100/RF4

SCL2/PMA8/RP101/RF5

D+/RG2

D-/RG3

USB

BUS

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Pin Diagrams (Continued)

100-Pin TQFP

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See

Section 11.4 “Peripheral Pin Select” for available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0

“I/O Ports” for more information.

= Pins are up to 5V tolerant

100

dsPIC33EP512MU810

PGEC1/AN6/RPI38/RB6

PGED1/AN7/RCV/RPI39/RB7

REF

-/RA9

REF

+/RA10

AN8/PMA6/RPI40/RB8

AN9/PMA7//RPI41/RB9

AN10/CV

REF

/PMA13/RPI42/RB10

AN11/PMA12/RPI43/RB11

TCK/RPI17/RA1

RP109/RF13

RP108/RF12

AN12/PMA11/RPI44/RB12

AN13/PMA10/RPI45/RB13

AN14/PMA1/RPI46/RB14

AN15/PMA0/RPI47/RB15

RPI78/RD14

RP79/RD15

SDA2/PMA9/RP100/RF4

SCL2/PMA8/RP101/RF5

PGEC2/SOSCO/C3INC/T1CK/RPI62/RC14

PGED2/SOSCI/C3IND/RPI61/RC13

INT0/DMH/RP64/RD0

PMCS1/RPI75/RD11

ASCL1/PMCS2/RPI74/RD10

ASDA1/DPLN/RPI73/RD9

RTCC/DMLN/RPI72/RD8

RPI31/RA15

RPI30/RA14

OSC2/CLKO/RC15

OSC1/RPI60/RC12

TDO/RPI21/RA5

TDI/RPI20/RA4

ASDA2/RPI19/RA3

ASCL2/RPI18/RA2

RP98/RF2

USBID/RP99/RF3

AN28/PWM3L/PMD4/RP84/RE4

AN27/PWM2H/PMD3/RPI83/RE3

AN26/PWM2L/PMD2/RP82/RE2

RP125/RG13

RPI124/RG12

RP126/RG14

AN25/PWM1H/PMD1/RPI81/RE1

AN24/PWM1L/PMD0/RP80/RE0

AN23/RPI23/RA7

AN22/RPI22/RA6

RP112/RG0

RP113/RG1

CMPST

2/RP97/RF1

CMPST

1/RP96/RF0

CAP

C3INA/V

CMPST

3/RP71/RD7

C3INB/RP70/RD6

PMRD/RP69/RD5

PMWR/RP68/RD4

RPI77/RD13

RPI76/RD12

PMBE/RP67/RD3

DPH/RP66/RD2

CPCON

/RP65/RD1

D+/RG2

D-/RG3

USB

BUS

dsPIC33EP256MU810

AN29/PWM3H/PMD5/RP85/RE5

AN31/PWM4H/PMD7/RP87/RE7

C1IND/SCK2/PMA5/RP118/RG6

C1INC/SDI2/PMA4/RPI119/RG7

C2IND/SDO2/PMA3/RP120/RG8

MCLR

C2INC/PMA2/RPI121/RG9

AN2/C2INB/VMIO/RPI34/RB2

PGEC3/AN1/RPI33/RB1

PGED3/AN0/RPI32/RB0

AN30/PWM4L/PMD6/RPI86/RE6

TMS/RPI16/RA0

AN20/RPI88/RE8

AN21/RPI89/RE9

RP127/RG15

AN16/PWM5L/RPI49/RC1

AN17/PWM5H/RPI50/RC2

AN18/PWM6L/RPI51/RC3

AN19/PWM6H/RPI52/RC4

RP104/RF8

AN5/C1INA/V

BUSON

//V

BUSST

/RPI37/RB5

AN4/C1INB/USBOEN/RPI36/RB4

AN3/C2INA/VPIO/RPI35/RB3

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Pin Diagrams (Continued)

100-Pin TQFP

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See

Section 11.4 “Peripheral Pin Select” for available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0

“I/O Ports” for more information.

= Pins are up to 5V tolerant

100

PGEC1/AN6/RPI38/RB6

PGED1/AN7/RCV/RPI39/RB7

REF

-/RA9

REF

+/RA10

AN8/PMA6/RPI40/RB8

AN9/PMA7//RPI41/RB9

AN10/CV

REF

/PMA13/RPI42/RB10

AN11/PMA12/RPI43/RB11

TCK/RPI17/RA1

RP109/RF13

RP108/RF12

AN12/PMA11/RPI44/RB12

AN13/PMA10/RPI45/RB13

AN14/PMA1/RPI46/RB14

AN15/PMA0/RPI47/RB15

RPI78/RD14

RP79/RD15

SDA2/PMA9/RP100/RF4

SCL2/PMA8/RP101/RF5

PGEC2/SOSCO/C3INC/T1CK/RPI62/RC14

PGED2/SOSCI/C3IND/RPI61/RC13

INT0/DMH/RP64/RD0

PMCS1/RPI75/RD11

ASCL1/PMCS2/RPI74/RD10

ASDA1/DPLN/RPI73/RD9

RTCC/DMLN/RPI72/RD8

RPI31/RA15

RPI30/RA14

OSC2/CLKO/RC15

OSC1/RPI60/RC12

TDO/RPI21/RA5

TDI/RPI20/RA4

ASDA2/RPI19/RA3

ASCL2/RPI18/RA2

RP98/RF2

USBID/RP99/RF3

AN28/PMD4/RP84/RE4

AN27/PMD3/RPI83/RE3

AN26/PMD2/RP82/RE2

RP125/RG13

RPI124/RG12

RP126/RG14

AN25/PMD1/RPI81/RE1

AN24/PMD0/RP80/RE0

AN23/RPI23/RA7

AN22/RPI22/RA6

RP112/RG0

RP113/RG1

CMPST

2/RP97/RF1

CMPST

1/RP96/RF0

CAP

C3INA/V

CMPST

3/RP71/RD7

C3INB/RP70/RD6

PMRD/RP69/RD5

PMWR/RP68/RD4

RPI77/RD13

RPI76/RD12

PMBE/RP67/RD3

DPH/RP66/RD2

CPCON

/RP65/RD1

D+/RG2

D-/RG3

USB

BUS

AN29/PMD5/RP85/RE5

AN31/PMD7/RP87/RE7

C1IND/SCK2/PMA5/RP118/RG6

C1INC/SDI2/PMA4/RPI119/RG7

C2IND/SDO2/PMA3/RP120/RG8

MCLR

C2INC/PMA2/RPI121/RG9

AN5/C1INA/

BUSON

BUSST

/RPI37/RB5

AN4/C1INB/USBOEN/RPI36/RB4

AN3/C2INA/VPIO/RPI35/RB3

AN2/C2INB/VMIO/RPI34/RB2

PGEC3/AN1/RPI33/RB1

PGED3/AN0/RPI32/RB0

AN30/PMD6/RPI86/RE6

TMS/RPI16/RA0

AN20/RPI88/RE8

AN21/RPI89/RE9

RP127/RG15

AN16/RPI49/RC1

AN17/RPI50/RC2

AN18/RPI51/RC3

AN19/RPI52/RC4

PIC24EP512GU810

PIC24EP256GU810

RP104/RF8

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Pin Diagrams (Continued)

121-Pin BGA(1)

1234567891011

ARE4 RE3 RG13 RE0 RG0 RF1 VDD NC RD12 RD2 RD1

BNC RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14

CRE6 VDD RG12 RG14 RA6 NC RD7 RD4 NC RC13 RD11

DRC1 RE7 RE5 NC NC NC RD6 RD13 RD0 NC RD10

ERC4 RC3 RG6 RC2 NC RG1 NC RA15 RD8 RD9 RA14

FMCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15

GRE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4

HRB5 RB4 NC NC NC VDD NC VBUS VUSB RG2 RA2

JRB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3

KRB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2

LRB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5

dsPIC33EP256MU810

Note 1: Refer to Table 2 for full pin names.

= Pins are up to 5V tolerant

dsPIC33EP512MU810

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 2: PIN NAMES: dsPIC33EP256MU810 AND dsPIC33EP512MU810

DEVICES(1,2)

Number Full Pin Name Pin

Number Full Pin Name

A1 AN28/PWM3L/PMD4/RP84/RE4 E8 RPI31/RA15

A2 AN27/PWM2H/PMD3/RPI83/RE3 E9 RTCC/DMLN/RPI72/RD8

A3 RP125/RG13 E10 ASDA1/DPLN/RPI73/RD9

A4 AN24/PWM1L/PMD0/RP80/RE0 E11 RPI30/RA14

A5 RP112/RG0 F1 MCLR

A6 VCMPST2/RP97/RF1 F2 C2IND/SDO2/PMA3/RP120/RG8

A7 VDD F3 C2INC/PMA2/RPI121/RG9

A8 No Connect F4 C1INC/SDI2/PMA4/RPI119/RG7

A9 RPI76/RD12 F5 VSS

A10 DPH/RP66/RD2 F6 No Connect

A11 VCPCON/RP65/RD1 F7 No Connect

B1 No Connect F8 VDD

B2 RP127/RG15 F9 OSC1/RPI60/RC12

B3 AN26/PWM2L/PMD2/RP82/RE2 F10 VSS

B4 AN25/PWM1H/PMD1/RPI81/RE1 F11 OSC2/CLKO/RC15

B5 AN23/RPI23/RA7 G1 AN20/RPI88/RE8

B6 VCMPST1/RP96/RF0 G2 AN21/RPI89/RE9

B7 VCAP G3 TMS/RPI16/RA0

B8 PMRD/RP69/RD5 G4 No Connect

B9 PMBE/RP67/RD3 G5 VDD

B10 VSS G6 VSS

B11 PGEC2/SOSCO/C3INC/T1CK/RPI62/RC14 G7 VSS

C1 AN30/PWM4L/PMD6/RPI86/RE6 G8 No Connect

C2 VDD G9 TDO/RPI21/RA5

C3 RPI124/RG12 G10 ASDA2/RPI19/RA3

C4 RP126/RG14 G11 TDI/RPI20/RA4

C5 AN22/RPI22/RA6 H1 AN5/C1INA/VBUSON/VBUSST/RPI37/RB5

C6 No Connect H2 AN4/C1INB/USBOEN/RPI36/RB4

C7 C3INA/VCMPST3/RP71/RD7 H3 No Connect

C8 PMWR/RP68/RD4 H4 No Connect

C9 No Connect H5 No Connect

C10 PGED2/SOSCI/C3IND/RPI61/RC13 H6 VDD

C11 PMCS1/RPI75/RD11 H7 No Connect

D1 AN16/PWM5L/RPI49/RC1 H8 VBUS

D2 AN31/PWM4H/PMD7/RP87/RE7 H9 VUSB

D3 AN29/PWM3H/PMD5/RP85/RE5 H10 D+/RG2

D4 No Connect H11 ASCL2/RPI18/RA2

D5 No Connect J1 AN3/C2INA/VPIO/RPI35/RB3

D6 No Connect J2 AN2/C2INB/VMIO/RPI34/RB2

D7 C3INB/RP70/RD6 J3 PGED1/AN7/RCV/RPI39/RB7

D8 RPI77/RD13 J4 AVDD

D9 INT0/DMH/RP64/RD0 J5 AN11/PMA12/RPI43/RB11

D10 No Connect J6 TCK/RPI17/RA1

D11 ASCL1/PMCS2/RPI74/RD10 J7 AN12/PMA11/RPI44/RB12

E1 AN19/PWM6H/RPI52/RC4 J8 No Connect

E2 AN18/PWM6L/RPI51/RC3 J9 No Connect

E3 C1IND/SCK2/PMA5/RP118/RG6 J10 RP104/RF8

E4 AN17/PWM5H/RPI50/RC2 J11 D-/RG3

E5 No Connect K1 PGEC3/AN1/RPI33/RB1

E6 RP113/RG1 K2 PGED3/AN0/RPI32/RB0

E7 No Connect K3 VREF+/RA10

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “P eripheral Pin Select” for

available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

K4 AN8/PMA6/RPI40/RB8 L3 AVSS

K5 No Connect L4 AN9/PMA7//RPI41/RB9

K6 RP108/RF12 L5 AN10/CVREF/PMA13/RPI42/RB10

K7 AN14/PMA1/RPI46/RB14 L6 RP109/RF13

K8 VDD L7 AN13/PMA10/RPI45/RB13

K9 RP79/RD15 L8 AN15/PMA0/RPI47/RB15

K10 USBID/RP99/RF3 L9 RPI78/RD14

K11 RP98/RF2 L10 SDA2/PMA9/RP100/RF4

L1 PGEC1/AN6/RPI38/RB6 L11 SCL2/PMA8/RP101/RF5

L2 VREF-/RA9

TABLE 2: PIN NAMES: dsPIC33EP256MU810 AND dsPIC33EP512MU810

DEVICES(1,2) (CONTINUED)

Number Full Pin Name Pin

Number Full Pin Name

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “P eripheral Pin Select” for

available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Pin Diagrams (Continued)

121-Pin BGA(1)

1234567891011

ARE4 RE3 RG13 RE0 RG0 RF1 VDD NC RD12 RD2 RD1

BNC RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14

CRE6 VDD RG12 RG14 RA6 NC RD7 RD4 NC RC13 RD11

DRC1 RE7 RE5 NC NC NC RD6 RD13 RD0 NC RD10

ERC4 RC3 RG6 RC2 NC RG1 NC RA15 RD8 RD9 RA14

FMCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15

GRE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4

HRB5 RB4 NC NC NC VDD NC VBUS VUSB RG2 RA2

JRB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3

KRB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2

LRB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5

Note 1: Refer to Table 3 for full pin names.

= Pins are up to 5V tolerant

PIC24EP512GU810

PIC24EP256GU810

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 3: PIN NAMES: PIC24EP256GU810 AND PIC24EP512GU810

DEVICES(1,2)

Number Full Pin Name Pin

Number Full Pin Name

A1 AN28/PMD4/RP84/RE4 E8 RPI31/RA15

A2 AN27/PMD3/RPI83/RE3 E9 RTCC/DMLN/RPI72/RD8

A3 RP125/RG13 E10 ASDA1/DPLN/RPI73/RD9

A4 AN24/PMD0/RP80/RE0 E11 RPI30/RA14

A5 RP112/RG0 F1 MCLR

A6 VCMPST2/RP97/RF1 F2 C2IND/SDO2/PMA3/RP120/RG8

A7 VDD F3 C2INC/PMA2/RPI121/RG9

A8 No Connect F4 C1INC/SDI2/PMA4/RPI119/RG7

A9 RPI76/RD12 F5 VSS

A10 DPH/RP66/RD2 F6 No Connect

A11 VCPCON/RP65/RD1 F7 No Connect

B1 No Connect F8 VDD

B2 RP127/RG15 F9 OSC1/RPI60/RC12

B3 AN26/PMD2/RP82/RE2 F10 VSS

B4 AN25/PMD1/RPI81/RE1 F11 OSC2/CLKO/RC15

B5 AN23/RPI23/RA7 G1 AN20/RPI88/RE8

B6 VCMPST1/RP96/RF0 G2 AN21/RPI89/RE9

B7 VCAP G3 TMS/RPI16/RA0

B8 PMRD/RP69/RD5 G4 No Connect

B9 PMBE/RP67/RD3 G5 VDD

B10 VSS G6 VSS

B11 PGEC2/SOSCO/C3INC/T1CK/RPI62/RC14 G7 VSS

C1 AN30/PMD6/RPI86/RE6 G8 No Connect

C2 VDD G9 TDO/RPI21/RA5

C3 RPI124/RG12 G10 ASDA2/RPI19/RA3

C4 RP126/RG14 G11 TDI/RPI20/RA4

C5 AN22/RPI22/RA6 H1 AN5/C1INA/VBUSON/VBUSST/RPI37/RB5

C6 No Connect H2 AN4/C1INB/USBOEN/RPI36/RB4

C7 C3INA/VCMPST3/RP71/RD7 H3 No Connect

C8 PMWR/RP68/RD4 H4 No Connect

C9 No Connect H5 No Connect

C10 PGED2/SOSCI/C3IND/RPI61/RC13 H6 VDD

C11 PMCS1/RPI75/RD11 H7 No Connect

D1 AN16/RPI49/RC1 H8 VBUS

D2 AN31/PMD7/RP87/RE7 H9 VUSB

D3 AN29/PMD5/RP85/RE5 H10 D+/RG2

D4 No Connect H11 ASCL2/RPI18/RA2

D5 No Connect J1 AN3/C2INA/VPIO/RPI35/RB3

D6 No Connect J2 AN2/C2INB/VMIO/RPI34/RB2

D7 C3INB/RP70/RD6 J3 PGED1/AN7/RCV/RPI39/RB7

D8 RPI77/RD13 J4 AVDD

D9 INT0/DMH/RP64/RD0 J5 AN11/PMA12/RPI43/RB11

D10 No Connect J6 TCK/RPI17/RA1

D11 ASCL1/PMCS2/RPI74/RD10 J7 AN12/PMA11/RPI44/RB12

E1 AN19/RPI52/RC4 J8 No Connect

E2 AN18/RPI51/RC3 J9 No Connect

E3 C1IND/SCK2/PMA5/RP118/RG6 J10 RP104/RF8

E4 AN17/RPI50/RC2 J11 D-/RG3

E5 No Connect K1 PGEC3/AN1/RPI33/RB1

E6 RP113/RG1 K2 PGED3/AN0/RPI32/RB0

E7 No Connect K3 VREF+/RA10

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “P eripheral Pin Select” for

available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

K4 AN8/PMA6/RPI40/RB8 L3 AVSS

K5 No Connect L4 AN9/PMA7/RPI41/RB9

K6 RP108/RF12 L5 AN10/CVREF/PMA13/RPI42/RB10

K7 AN14/PMA1/RPI46/RB14 L6 RP109/RF13

K8 VDD L7 AN13/PMA10/RPI45/RB13

K9 RP79/RD15 L8 AN15/PMA0/RPI47/RB15

K10 USBID/RP99/RF3 L9 RPI78/RD14

K11 RP98/RF2 L10 SDA2/PMA9/RP100/RF4

L1 PGEC1/AN6/RPI38/RB6 L11 SCL2/PMA8/RP101/RF5

L2 VREF-/RA9

TABLE 3: PIN NAMES: PIC24EP256GU810 AND PIC24EP512GU810

DEVICES(1,2) (CONTINUED)

Number Full Pin Name Pin

Number Full Pin Name

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “P eripheral Pin Select” for

available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Pin Diagrams (Continued)

144-Pin TQFP, 144-pin LQFP

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See

Section 11.4 “Peripheral Pin Select” for available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RKx) can be used as change notification (CNAx-CNKx). See Section 11.0

“I/O Port s” for more information.

= Pins are up to 5V tolerant

108

139

dsPIC33EP512MU814

107

106

105

104

103

102

101

100

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

144

143

142

141

140

114

113

112

111

110

109

AN29/PWM3H/RP85/RE5

AN31/PWM4H/RP87/RE7

C1IND/SCK2/RP118/RG6

C1INC/SDI2/RPI119/RG7

C2IND/SDO2/RP120/RG8

MCLR

C2INC/RPI121/RG9

AN5/C1INA/V

BUSON

BUSST

/RPI37/RB5

AN4/C1INB/USBOEN/RPI36/RB4

AN3/C2INA/VPIO/RPI35/RB3

AN2/C2INB/VMIO/RPI34/RB2

PGEC3/AN1/RPI33/RB1

PGED3/AN0/RPI32/RB0

AN30/PWM4L/RPI86/RE6

TMS/RPI16/RA0

AN20/RPI88/RE8

AN21/RPI89/RE9

RK0

RK1

RJ14

RJ15

RP127/RG15

PWM7L/PMA8/RJ8

PWM7H/PMA9/RJ9

PMA10/RJ10

PMA11/RJ11

AN16/PWM5L/RPI49/RC1

AN17/PWM5H/RPI50/RC2

AN18/PWM6L/RPI51/RC3

AN19/PWM6H/RPI52/RC4

PMA12/RJ12

PMA13/RJ13

AN28/PWM3L/RP84/RE4

AN27/PWM2H/RPI83/RE3

AN26/PWM2L/RP82/RE2

RP125/RG13

RPI124/RG12

RP126/RG14

AN25/PWM1H/RPI81/RE1

AN24/PWM1L/RP80/RE0

PMA7/RJ7

PMA6/RJ6

PMA5/RJ5

PMA4/RJ4

AN23/RPI23/RA7

AN22/RPI22/RA6

RP112/RG0

RP113/RG1

CMPST

2/RP97/RF1

CMPST

1/RP96/RF0

CAP

C3INA/V

CMPST

3/RP71/RD7

C3INB/RP70/RD6

RP69/RD5

RP68/RD4

PMA3/RJ3

PMA2/RJ2

PMA1/RJ1

PMA0/RJ0

RPI77/RD13

RPI76/RD12

RP67/RD3

DPH/RP66/RD2

CPCON

/RP65/RD1

PGEC2/SOSCO/C3INC/T1CK/RPI62/RC14

PGED2/SOSCI/C3IND/RPI61/RC13

INT0/DMH/RP64/RD0

RH15

RH14

RH13

RH12

RPI75/RD11

ASCL1/RPI74/RD10

ASDA1/DPLN/RPI73/RD9

RTCC/DMLN/RPI72/RD8

RPI31/RA15

RPI30/RA14

PMCS1/RK11

PMCS2/RK12

OSC2/CLKO/RC15

OSC1/RPI60/RC12

TDO/RPI21/RA5

TDI/RPI20/RA4

ASDA2/RPI19/RA3

ASCL2/RPI18/RA2

RH11

RH10

RH9

RH8

RP104/RF8

RP98/RF2

USBID/RP99/RF3

PGEC1/AN6/RPI38/RB6

PGED1/AN7/RCV/RPI39/RB7

REF

-/RA9

REF

+/RA10

PMD0/RH0

PMD1/RH1

PMD2/RH2

PMD3/RH3

AN8/RPI40/RB8

AN9/RPI41/RB9

AN10/CV

REF

/RPI42/RB10

AN11/RPI43/RB11

PMRD/RK15

PMWR/RK14

PMBE/RK13

TCK/RPI17/RA1

RP109/RF13

RP108/RF12

AN12/RPI44/RB12

AN13/RPI45/RB13

AN14/RPI46/RB14

AN15/RPI47/RB15

PMD4/RH4

PMD5/RH5

PMD6/RH6

PMD7/RH7

RPI78/RD14

RP79/RD15

SDA2/RP100/RF4

SCL2/RP101/RF5

D+/RG2

D-/RG3

USB

BUS

dsPIC33EP256MU814

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Pin Diagrams (Continued)

144-Pin TQFP, 144-pin LQFP

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4

“Peripheral Pin Select” for available peripherals and for information on limitations.

2: Every I/O port pin (RAx-RKx) can be used as change notification (CNAx-CNKx). See Section 11.0 “I/O

Ports” for more information.

= Pins are up to 5V tolerant

108

139

107

106

105

104

103

102

101

100

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

144

143

142

141

140

114

113

112

111

110

109

AN29/RP85/RE5

AN31/RP87/RE7

C1IND/SCK2/RP118/RG6

C1INC/SDI2/RPI119/RG7

C2IND/SDO2/RP120/RG8

MCLR

C2INC/RPI121/RG9

AN5/C1INA/V

BUSON

BUSST

/RPI37/RB5

AN4/C1INB/USBOEN/RPI36/RB4

AN3/C2INA/VPIO/RPI35/RB3

AN2/C2INB/VMIO/RPI34/RB2

PGEC3/AN1/RPI33/RB1

PGED3/AN0/RPI32/RB0

AN30/RPI86/RE6

TMS/RPI16/RA0

AN20/RPI88/RE8

AN21/RPI89/RE9

RK0

RK1

RJ14

RJ15

RP127/RG15

PMA8/RJ8

PMA9/RJ9

PMA10/RJ10

PMA11/RJ11

AN16/RPI49/RC1

AN17/RPI50/RC2

AN18/RPI51/RC3

AN19/RPI52/RC4

PMA12/RJ12

PMA13/RJ13

AN28/RP84/RE4

AN27/RPI83/RE3

AN26/RP82/RE2

RP125/RG13

RPI124/RG12

RP126/RG14

AN25/RPI81/RE1

AN24/RP80/RE0

PMA7/RJ7

PMA6/RJ6

PMA5/RJ5

PMA4/RJ4

AN23/RPI23/RA7

AN22/RPI22/RA6

RP112/RG0

RP113/RG1

CMPST

2/RP97/RF1

CMPST

1/RP96/RF0

CAP

C3INA/V

CMPST

3/RP71/RD7

C3INB/RP70/RD6

RP69/RD5

RP68/RD4

PMA3/RJ3

PMA2/RJ2

PMA1/RJ1

PMA0/RJ0

RPI77/RD13

RPI76/RD12

RP67/RD3

DPH/RP66/RD2

CPCON

/RP65/RD1

PGEC2/SOSCO/C3INC/T1CK/RPI62/RC14

PGED2/SOSCI/C3IND/RPI61/RC13

INT0/DMH/RP64/RD0

RH15

RH14

RH13

RH12

RPI75/RD11

ASCL1/RPI74/RD10

ASDA1/DPLN/RPI73/RD9

RTCC/DMLN/RPI72/RD8

RPI31/RA15

RPI30/RA14

PMCS1/RK11

PMCS2/RK12

OSC2/CLKO/RC15

OSC1/RPI60/RC12

TDO/RPI21/RA5

TDI/RPI20/RA4

ASDA2/RPI19/RA3

ASCL2/RPI18/RA2

RH11

RH10

RH9

RH8

RP104/RF8

RP98/RF2

USBID/RP99/RF3

PGEC1/AN6/RPI38/RB6

PGED1/AN7/RCV/RPI39/RB7

REF

-/RA9

REF

+/RA10

PMD0/RH0

PMD1/RH1

PMD2/RH2

PMD3/RH3

AN8/RPI40/RB8

AN9/RPI41/RB9

AN10/CV

REF

/RPI42/RB10

AN11/RPI43/RB11

PMRD/RK15

PMWR/RK14

PMBE/RK13

TCK/RPI17/RA1

RP109/RF13

RP108/RF12

AN12/RPI44/RB12

AN13/RPI45/RB13

AN14/RPI46/RB14

AN15/RPI47/RB15

PMD4/RH4

PMD5/RH5

PMD6/RH6

PMD7/RH7

RPI78/RD14

RP79/RD15

SDA2/RP100/RF4

SCL2/RP101/RF5

D+/RG2

D-/RG3

USB

BUS

PIC24EP512GU814

PIC24EP256GU814

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

Table of Content s

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814 Product Families................................................................................ 6

1.0 Device Overview ........................................................................................................................................................................ 21

2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers and Microcontrollers......................................................... 27

3.0 CPU............................................................................................................................................................................................ 31

4.0 Memory Organization ................................................................................................................................................................. 41

5.0 Flash Program Memory............................................................................................................................................................ 123

6.0 Resets ..................................................................................................................................................................................... 127

7.0 Interrupt Controller ................................................................................................................................................................... 131

8.0 Direct Memory Access (DMA) .................................................................................................................................................. 145

9.0 Oscillator Configuration ............................................................................................................................................................ 161

10.0 Power-Saving Features............................................................................................................................................................ 173

11.0 I/O Ports ................................................................................................................................................................................... 187

12.0 Timer1 ...................................................................................................................................................................................... 247

13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 249

14.0 Input Capture............................................................................................................................................................................ 255

15.0 Output Compare....................................................................................................................................................................... 259

16.0 High-Speed PWM Module (dsPIC33EPXXXMU806/810/814 Devices Only)........................................................................... 265

17.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMU806/810/814 Devices Only) .............................................. 293

18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 307

19.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 313

20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 321

21.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 327

22.0 USB On-The-Go (OTG) Module............................................................................................................................................... 353

23.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 379

24.0 Data Converter Interface (DCI) Module (dsPIC33EPXXXMU806/810/814 Devices Only)....................................................... 391

25.0 Comparator Module.................................................................................................................................................................. 397

26.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 409

27.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 419

28.0 Parallel Master Port (PMP)....................................................................................................................................................... 425

29.0 Special Features ...................................................................................................................................................................... 433

30.0 Instruction Set Summary .......................................................................................................................................................... 441

31.0 Development Support............................................................................................................................................................... 451

32.0 Electrical Characteristics .......................................................................................................................................................... 455

33.0 Packaging Information.............................................................................................................................................................. 527

Appendix A: Revision History............................................................................................................................................................. 547

Index ................................................................................................................................................................................................. 553

The Microchip Web Site ..................................................................................................................................................................... 559

Customer Change Notification Service .............................................................................................................................................. 559

Customer Support.............................................................................................................................................................................. 559

Reader Response .............................................................................................................................................................................. 560

Product Identification System ............................................................................................................................................................ 561

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notific at ion Syst em

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

1.0 DEVICE OVERVIEW

This document contains device-specific information for

the dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 Digital Signal Controller

(DSC) and Microcontroller (MCU) devices. The

dsPIC33EPXXXMU806/810/814 devices contain

extensive Digital Signal Processor (DSP) functionality

with a high-performance 16-bit MCU architecture.

Figure 1-1 illustrates a general block diagram of the

core and peripheral modules in the

dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 families of devices.

Table 1-1 lists the functions of the various pins shown

in the pinout diagrams.

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXXMU806/810/814

and PIC24EPXXXGU810/814 families of

devices. It is not intended to be a compre-

hensive resource. To complement the

information in this data sheet, refer to the

related section of the “dsPIC33E/PIC24E

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com)

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

FIGURE 1-1: dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814 BLOCK DIAGRAM

PORTA

PORTB

PORTD

PORTC

Power-up

Timer

Oscillator

Start-up Timer

Instruction

Decode and

Control

OSC1/CLKI

MCLR

VDD, VSS

UART1-

Timing

Generation

ECAN1,

PCH PCL

Program Counter

16-bit ALU

X Data Bus

I2C1,

DCI(1)

PCU

ADC1,

Timers

Input

Capture

Output

Compare

16 16

16 x 16

W Reg Array

Divide

Support

Engine(1)

DSP

ROM Latch

Y Data Bus(1)

EA MUX

X RAGU

X WAGU

Y AGU(1)

AVDD, AVSS

UART4

SPI4

Interrupt

Controller PSV and Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

RAM(1) X Data

RAM

Address

Latch

Address

Latch

Control Signals

to Various Blocks

SPI1-

Data Latch

X Address Bus

Y Address Bus

Literal Data

ADC2

Program Memory

Watchdog

Timer

POR/BOR

Address Latch

PMP

Comparator

CRC

RTCC

USB OTG

I2C2

ECAN2

QEI1(1),

PWM(1)

QEI2(1)

(3 Channel)

PORTE

PORTF

PORTG

PORTH

PORTJ

PORTK

Remappable

Pins

Note 1: This feature or peripheral is only available on dsPIC33EPXXXMU806/810/814 devices.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin

Type Buffer

Type PPS Description

AN0-AN31 I Analog No Analog input channels.

CLKI

CLKO

ST/

CMOS

—

External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes.

Always associated with OSC2 pin function.

OSC1

OSC2

I/O

ST/

CMOS

—

Oscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes.

SOSCI

SOSCO

ST/

CMOS

—

32.768 kHz low-power oscillator crystal input; CMOS otherwise.

32.768 kHz low-power oscillator crystal output.

IC1-IC16 I ST Yes Capture inputs 1 through 16.

OCFA

OCFB

OCFC

OC1-OC16

—

Yes

Compare Fault A input (for Compare channels).

Compare Fault B input (for Compare channels).

Compare Fault C input (for Compare channels).

Compare outputs 1 through 16.

INT0

INT1

INT2

INT3

INT4

Yes

External interrupt 0.

External interrupt 1.

External interrupt 2.

External interrupt 3.

External interrupt 4.

RA0-RA7, RA9,

RA10, RA14, RA15

I/O ST No PORTA is a bidirectional I/O port.

RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.

RC1-RC4,

RC12-RC15

I/O ST No PORTC is a bidirectional I/O port.

RD0-RD15 I/O ST No PORTD is a bidirectional I/O port.

RE0-RE9 I/O ST No PORTE is a bidirectional I/O port.

RF0-RF5, RF8

RF12, RF13

I/O ST No PORTF is a bidirectional I/O port.

RG0, RG1

RG2, RG3

RG6-RG9,

RG12-RG15

I/O

PORTG is a bidirectional I/O port.

PORTG input pins.

PORTG is a bidirectional I/O port.

RH0-RH15 I/O ST No PORTH is a bidirectional I/O port.

RJ0-RJ15 I/O ST No PORTJ is a bidirectional I/O port.

RK0-RK1,

RK11-RK15

I/O ST No PORTK is a bidirectional I/O port.

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

PPS = Peripheral Pin Select TTL = TTL input buffer

Note 1: This pin is available on dsPIC33EPXXXMU806/810/814 devices only.

2: AVDD must be connected at all times.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

T1CK

T2CK

T3CK

T4CK

T5CK

T6CK

T7CK

T8CK

T9CK

Yes

Timer1 external clock input.

Timer2 external clock input.

Timer3 external clock input.

Timer4 external clock input.

Timer5 external clock input.

Timer6 external clock input.

Timer7 external clock input.

Timer8 external clock input.

Timer9 external clock input.

U1CTS

U1RTS

U1RX

U1TX

—

Yes

UART1 clear to send.

UART1 ready to send.

UART1 receive.

UART1 transmit.

U2CTS

U2RTS

U2RX

U2TX

—

Yes

UART2 clear to send.

UART2 ready to send.

UART2 receive.

UART2 transmit.

U3CTS

U3RTS

U3RX

U3TX

—

Yes

UART3 clear to send.

UART3 ready to send.

UART3 receive.

UART3 transmit.

U4CTS

U4RTS

U4RX

U4TX

—

Yes

UART4 clear to send.

UART4 ready to send.

UART4 receive.

UART4 transmit.

SCK1

SDI1

SDO1

SS1

I/O

—

Yes

Synchronous serial clock input/output for SPI1.

SPI1 data in.

SPI1 data out.

SPI1 slave synchronization or frame pulse I/O.

SCK2

SDI2

SDO2

SS2

I/O

—

Yes

Synchronous serial clock input/output for SPI2.

SPI2 data in.

SPI2 data out.

SPI2 slave synchronization or frame pulse I/O.

SCK3

SDI3

SDO3

SS3

I/O

—

Yes

Synchronous serial clock input/output for SPI3.

SPI3 data in.

SPI3 data out.

SPI3 slave synchronization or frame pulse I/O.

SCK4

SDI4

SDO4

SS4

I/O

—

Yes

Synchronous serial clock input/output for SPI4.

SPI4 data in.

SPI4 data out.

SPI4 slave synchronization or frame pulse I/O.

ASCL1

ASDA1

I/O

Alternate synchronous serial clock input/output for I2C1.

Alternate synchronous serial data input/output for I2C1.

SCL2

SDA2

ASCL2

ASDA2

I/O

Synchronous serial clock input/output for I2C2.

Synchronous serial data input/output for I2C2.

Alternate synchronous serial clock input/output for I2C2.

Alternate synchronous serial data input/output for I2C2.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type Buffer

Type PPS Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

PPS = Peripheral Pin Select TTL = TTL input buffer

Note 1: This pin is available on dsPIC33EPXXXMU806/810/814 devices only.

2: AVDD must be connected at all times.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TMS

TCK

TDI

TDO

—

JTAG Test mode select pin.

JTAG test clock input pin.

JTAG test data input pin.

JTAG test data output pin.

INDX1(1)

HOME1(1)

QEA1(1)

QEB1(1)

CNTCMP1(1)

—

Yes

Quadrature Encoder Index1 Pulse input.

Quadrature Encoder Home1 Pulse input.

Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer

External Clock input in Timer mode.

Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer

External Gate input in Timer mode.

Quadrature Encoder Compare Output 1.

INDX2(1)

HOME2(1)

QEA2(1)

QEB2(1)

CNTCMP2(1)

—

Yes

Quadrature Encoder Index2 Pulse input.

Quadrature Encoder Home2 Pulse input.

Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer

External Clock input in Timer mode.

Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer

External Gate input in Timer mode.

Quadrature Encoder Compare Output 2.

COFS(1)

CSCK(1)

CSDI(1)

CSDO(1)

I/O

—

Yes

Data Converter Interface frame synchronization pin.

Data Converter Interface serial clock input/output pin.

Data Converter Interface serial data input pin.

Data Converter Interface serial data output pin.

C1RX

C1TX

—

Yes

ECAN1 bus receive pin.

ECAN1 bus transmit pin.

C2RX

C2TX

—

Yes

ECAN2 bus receive pin.

ECAN2 bus transmit pin.

RTCC O — No Real-Time Clock Alarm Output.

CVREF O ANA No Comparator Voltage Reference Output.

C1INA-C1IND

C1OUT

ANA

—

Yes

Comparator 1 Inputs

Comparator 1 Output.

C2INA-C2IND

C2OUT

ANA

—

Yes

Comparator 2 Inputs.

Comparator 2 Output.

C3INA-C3IND

C3OUT

ANA

—

Yes

Comparator 3 Inputs.

Comparator 3 Output.

PMA0

PMA1

PMA2 -PMA13

PMBE

PMCS1, PMCS2

PMD0-PMD7

PMRD

PMWR

I/O

TTL/ST

—

TTL/ST

—

Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and

Output (Master modes).

Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and

Output (Master modes).

Parallel Master Port Address Bits 2 - 13 (Demultiplexed Master Modes).

Parallel Master Port Byte Enable Strobe.

Parallel Master Port Chip Select 1 and 2 Strobe.

Parallel Master Port Data (Demultiplexed Master mode) or Address/

Data (Multiplexed Master modes).

Parallel Master Port Read Strobe.

Parallel Master Port Write Strobe.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type Buffer

Type PPS Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

PPS = Peripheral Pin Select TTL = TTL input buffer

Note 1: This pin is available on dsPIC33EPXXXMU806/810/814 devices only.

2: AVDD must be connected at all times.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

FLT1-FLT7(1)

DTCMP1-DTCMP7(1)

PWM1L-PWM7L(1)

PWM1H-PWM7H(1)

SYNCI1, SYNCI2(1)

SYNCO1, SYNCO2(1)

—

Yes

PWM Fault input 1 through 7.

PWM Dead Time Compensation Input.

PWM Low output 1 through 7.

PWM High output 1 through 7.

PWM Synchronization Inputs 1 and 2.

PWM Synchronization Output 1 and 2.

VBUS

VUSB

VBUSON

D+

D-

USBID

USBOEN

VBUSST

VCPCON

VCMPST1

VCMPST2

VCMPST3

VMIO

VPIO

DMH

DPH

DMLN

DPLN

RCV

I/O

Analog

—

Analog

—

USB Bus Power Monitor.

USB Internal Transceiver Supply. If the USB module is not being used,

this pin must be connected to VDD.

USB Host and On-The-Go (OTG) Bus Power Control Output.

USB D+ I/O pin.

USB D- I/O pin.

USB OTG ID Detect.

USB Output Enabled Control (for external transceiver).

USB Boost Controller Overcurrent Detection.

USB Boost Controller PWM Signal.

USB External Comparator 1 Input.

USB External Comparator 2 Input.

USB External Comparator 3 Input.

USB Differential Minus Input/Output (external transceiver).

USB Differential Plus Input/Output (external transceiver).

D- External Pull-up Control Output.

D+ External Pull-up Control Output.

D- External Pull-down Control Output.

D+ External Pull-down Control Output.

USB Receive Input (from external transceiver).

PGED1

PGEC1

PGED2

PGEC2

PGED3

PGEC3

I/O

Data I/O pin for programming/debugging communication channel 1.

Clock input pin for programming/debugging communication channel 1.

Data I/O pin for programming/debugging communication channel 2.

Clock input pin for programming/debugging communication channel 2.

Data I/O pin for programming/debugging communication channel 3.

Clock input pin for programming/debugging communication channel 3.

MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the

device.

AVDD(2) P P No Positive supply for analog modules. This pin must be connected at all

times.

AVSS P P No Ground reference for analog modules.

VDD P — No Positive supply for peripheral logic and I/O pins.

VCAP P — No CPU logic filter capacitor connection.

VSS P — No Ground reference for logic and I/O pins.

VREF+ I Analog No Analog voltage reference (high) input.

VREF- I Analog No Analog voltage reference (low) input.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type Buffer

Type PPS Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

PPS = Peripheral Pin Select TTL = TTL input buffer

Note 1: This pin is available on dsPIC33EPXXXMU806/810/814 devices only.

2: AVDD must be connected at all times.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

2.0 GUIDELINES FOR GETTING

STARTED WITH 16-BIT

DIGITAL SIGNAL

CONTROLLERS AND

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the dsPIC33EPXXXMU806/810/814

and PIC24EPXXXGU810/814 families of 16-bit DSC and

microcontrollers requires attention to a minimal set of

device pin connections before proceeding with

development. The following is a list of pin names, which

must always be connected:

• All VDD and VSS pins

(see Section 2.2 “Decoupling Capacitors”)

• All AVDD and AVSS pins (regardless if ADC module

is not used)

(see Section 2.2 “Decoupling Capacitors”)

•V

CAP

(see Section 2.3 “CPU Logic Filter Capa ci tor

Connection (VCAP)”)

•MCLR

(see Section 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

• OSC1 and OSC2 pins when external oscillator

source is used

(see Section 2.6 “External Oscillato r Pin s”)

Additionally, the following pins may be required:

•V

USB pin is used when utilizing the USB module.

If the USB module is not used, VUSB must be

connected to VDD.

•V

REF+/VREF- pins is used when external voltage

reference for ADC module is implemented

2.2 Decoupling Capacitors

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, VUSB, AVDD

and AVSS is required.

Consider the following criteria when using decoupling

capacitors:

•Value and type of capacitor: Recommendation

of 0.1 µF (100 nF), 10-20V. This capacitor should

be a low-ESR and have resonance frequency in

the range of 20 MHz and higher. It is

recommended to use ceramic capacitors.

•Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is within

one-quarter inch (6 mm) in length.

•Handling high freque nc y nois e : If the board is

experiencing high frequency noise, above tens of

MHz, add a second ceramic-type capacitor in par-

allel to the above described decoupling capacitor.

The value of the second capacitor can be in the

range of 0.01 µF to 0.001 µF. Place this second

capacitor next to the primary decoupling capaci-

tor. In high-speed circuit designs, consider imple-

menting a decade pair of capacitances as close to

the power and ground pins as possible. For exam-

ple, 0.1 µF in parallel with 0.001 µF.

•Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB track

inductance.

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXXMU806/810/814

and PIC24EPXXXGU810/814 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to the related section of the

“dsPIC33E/PIC24E Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com)

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: The AVDD and AVSS pins must be

connected independent of the ADC

voltage reference source.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECT I ON

2.2.1 TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including DSCs to supply a local

power source. The value of the tank capacitor should

be determined based on the trace resistance that con-

nects the power supply source to the device, and the

maximum current drawn by the device in the applica-

tion. In other words, select the tank capacitor so that it

meets the acceptable voltage sag at the device. Typical

values range from 4.7 µF to 47 µF.

2.3 CPU Logic Filter Capacitor

Connection (VCAP)

A low-ESR (< 1 Ohms) capacitor is required on the

VCAP pin, which is used to stabilize the voltage

regulator output voltage. The VCAP pin must not be

connected to VDD, and must have a capacitor greater

than 4.7 µF (10 µF is recommended), 16V connected

to ground. The type can be ceramic or tantalum. See

Section 32.0 “Electrical Characteristics” for

additional information.

The placement of this capacitor should be close to the

VCAP. It is recommended that the trace length not

exceeds one-quarter inch (6 mm). See Section 29.2

“On-Chip Voltage Regulator” for details.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions:

• Device Reset

• Device Programming and Debugging

During device programming and debugging, the

resistance and capacitance that can be added to the

pin must be considered. Device programmers and

debuggers drive the MCLR pin. Consequently,

specific voltage levels (VIH and VIL) and fast signal

transitions must not be adversely affected. Therefore,

specific values of R and C will need to be adjusted

based on the application and PCB requirements.

For example, as shown in Figure 2-2, it is

recommended that the capacitor C, be isolated from

the MCLR pin during programming and debugging

operations.

Place the components as shown in Figure 2-2 within

one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

dsPIC33EP

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

VDD

MCLR

0.1 µF

Ceramic

VCAP

10 Ω

Note 1: R≤ 10 kΩ is recommended. A suggested

starting value is 10 kΩ. Ensure that the MCLR

pin VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing into

MCLR from the external capacitor C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

R1(2)

R(1)

VDD

MCLR

dsPIC33EP

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

2.5 ICSP Pins

The PGECx and PGEDx pins are used for ICSP and

debugging purposes. It is recommended to keep the

trace length between the ICSP connector and the ICSP

pins on the device as short as possible. If the ICSP con-

nector is expected to experience an ESD event, a

series resistor is recommended, with the value in the

range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin input voltage high

(VIH) and input low (VIL) requirements.

Ensure that the “Communication Channel Select” (i.e.,

PGECx/PGEDx pins) programmed into the device

matches the physical connections for the ICSP to

MPLAB® PICkit™ 3, MPLAB ICD 3, or MPLAB REAL

ICE™.

For more information on MPLAB ICD 3 and MPLAB

REAL ICE connection requirements, refer to the

following documents that are available on the

Microchip web site.

•“Using MPLAB® ICD 3” (poster) DS51765

•“MPLAB® ICD 3 Design Advisory” DS51764

•“MPLAB® REAL ICE™ In-Circuit Emulator User’s

Guide” DS51616

•“Using MPLAB® REAL ICE™” In-Circuit Emulator

(poster) DS51749

2.6 External Oscillator Pins

Many DSCs have options for at least two oscillators: a

high-frequency primary oscillator and a low-frequency

secondary oscillator. For details, see Section 9.0

“Oscillator Configuration” for details.

The oscillator circuit should be placed on the same

side of the board as the device. Also, place the

oscillator circuit close to the respective oscillator pins,

not exceeding one-half inch (12 mm) distance

between them. The load capacitors should be placed

next to the oscillator itself, on the same side of the

board. Use a grounded copper pour around the

oscillator circuit to isolate them from surrounding

circuits. The grounded copper pour should be routed

directly to the MCU ground. Do not run any signal

traces or power traces inside the ground pour. Also, if

using a two-sided board, avoid any traces on the

other side of the board where the crystal is placed. A

suggested layout is shown in Figure 2-3.

FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

2.7 Oscillator Value Conditions on

Device Start-up

If the PLL of the target device is enabled and

configured for the device start-up oscillator, the

maximum oscillator source frequency must be limited

to 3 MHz < FIN < 5.5 MHz to comply with device PLL

start-up conditions. This means that if the external

oscillator frequency is outside this range, the

application must start-up in the FRC mode first. The

default PLL settings after a POR with an oscillator

frequency outside this range will violate the device

operating speed.

Once the device powers up, the application firmware

can initialize the PLL SFRs, CLKDIV and PLLDBF to a

suitable value, and then perform a clock switch to the

Oscillator + PLL clock source. Note that clock switching

must be enabled in the device Configuration Word.

2.8 Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic-low state.

Alternatively, connect a 1k to 10k resistor between VSS

and unused pins and drive the output to logic low.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

3.0 CPU

The dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 CPU have a 16-bit (data)

modified Harvard architecture with an enhanced

instruction set, including significant support for digital

signal processing. The CPU has a 24-bit instruction

word, with a variable length opcode field. The Program

Counter (PC) is 24 bits wide and addresses up to 4M x

24 bits of user program memory space.

An instruction prefetch mechanism helps maintain

throughput and provides predictable execution. Most

instructions execute in a single-cycle effective execu-

tion rate, with the exception of instructions that change

the program flow, the double-word move (MOV.D)

instruction, PSV accesses, and the table instructions.

Overhead free program loop constructs are supported

using the DO and REPEAT instructions, both of which

are interruptible at any point.

3.1 Registers

The dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 devices have sixteen 16-bit

Working registers in the programmer’s model. Each of

the Working registers can act as a data, address or

address offset register. The 16th Working register

(W15) operates as a software Stack Pointer for

interrupts and calls.

3.2 Instruction Set

The dsPIC33EPXXXMU806/810/814 instruction set

has two classes of instructions: the MCU class of

instructions and the DSP class of instructions. The

PIC24EPXXXGU810/814 instruction set has the MCU

class of instructions and does not support DSP instruc-

tions. These two instruction classes are seamlessly

integrated into the architecture and execute from a sin-

gle execution unit. The instruction set includes many

addressing modes and was designed for optimum

C compiler efficiency.

3.3 Data Space Addressing

The base data space can be addressed as 32K words

or 64 Kbytes and is split into two blocks, referred to as

X and Y data memory. Each memory block has its own

independent Address Generation Unit (AGU). The

MCU class of instructions operate solely through the X

memory AGU, which accesses the entire memory map

as one linear data space. On dsPIC33EPXXXMU806/

810/814 devices, certain DSP instructions operate

through the X and Y AGUs to support dual operand

reads, which splits the data address space into two

parts. The X and Y data space boundary is device

specific.

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K program word boundary. The program-to-data-

space mapping feature, known as Program Space

Visibility (PSV), lets any instruction access program

space as if it were data space. Moreover, the Base

Data Space address is used in conjunction with a read

or write page register (DSRPAG or DSWPAG) to form

an Extended Data Space (EDS) address. The EDS can

be addressed as 8 Mwords or 16 Mbytes. Refer to

Section 3. “Data Memory” (DS70595) and Section 4.

“Program Memory” (DS70613) in the “dsPIC33E/

PIC24E Family Reference Manua l” for more details on

EDS, PSV and table accesses.

On dsPIC33EPXXXMU806/810/814 devices,

overhead-free circular buffers (Modulo Addressing) are

supported in both X and Y address spaces. The

Modulo Addressing removes the software boundary-

checking overhead for DSP algorithms. The X AGU

circular addressing can be used with any of the MCU

class of instructions. The X AGU also supports Bit-

Reverse Addressing to greatly simplify input or output

data reordering for radix-2 FFT algorithms.

PIC24EPXXXGU810/814 devices do not support

Modulo and Bit-Reverse Addressing.

3.4 Addressing Modes

The CPU supports these addressing modes:

• Inherent (no operand)

• Relative

•Literal

• Memory Direct

• Register Direct

• Register Indirect

Each instruction is associated with a predefined

Addressing mode group, depending upon its functional

requirements. As many as six Addressing modes are

supported for each instruction.

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXXMU806/810/814

and PIC24EPXXXGU810/814 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 2. “CPU”

(DS70359) in the “dsPIC33E/PIC24E

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

FIGURE 3-1: dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814 CPU BLOCK

DIAGRAM

Power-up

Timer

Oscillator

Start-up Timer

Instruction

Decode and

Control

OSC1/CLKI

MCLR

VDD, VSS

UART1-

Timing

Generation

ECAN1,

PCH PCL

Program Counter

16-bit ALU

X Data Bus

I2C1,

DCI(1)

PCU

ADC1,

Timers

Input

Capture

Output

Compare

16 16

16 x 16

W Reg Array

Divide

Support

Engine(1)

DSP

ROM Latch

Y Data Bus(1)

EA MUX

X RAGU

X WAGU

Y AGU(1)

AVDD, AVSS

UART4

SPI4

Interrupt

Controller PSV and Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

RAM(1) X Data

RAM

Address

Latch

Address

Latch

Control Signals

to Various Blocks

SPI1-

Data Latch

I/O Ports

X Address Bus

Y Address Bus

Literal Data

ADC2

Program Memory

Watchdog

Timer

POR/BOR

Address Latch

PMP

Comparator

CRC

RTCC

USB OTG

I2C2

ECAN2

QEI1(1),

PWM(1)

QEI2(1)

Note 1: This feature or peripheral is only available in dsPIC33EPXXXMU806/810/814 devices.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

3.5 Programmer’s Model

The programmer’s model for the

dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 is shown in Figure 3-2. All

registers in the programmer’s model are memory

mapped and can be manipulated directly by

instructions. Table 3-1 lists a description of each

In addition to the registers contained in the

programmer’s model, the dsPIC33EPXXXMU806/810/

814 and PIC24EPXXXGU810/814 devices contain

control registers for Modulo Addressing

(dsPIC33EPXXXMU806/810/814 devices only), Bit-

Reversed Addressing (dsPIC33EPXXXMU806/810/

814 devices only) and interrupts. These registers are

described in subsequent sections of this document.

All registers associated with the programmer’s model

are memory mapped, as shown in Table 4-1.

TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

W0 through W15 Working register array

ACCA, ACCB 40-bit DSP Accumulators

PC 23-bit Program Counter

SR ALU and DSP Engine Status register

SPLIM Stack Pointer Limit Value register

TBLPAG Table Memory Page Address register

DSRPAG Extended Data Space (EDS) Read Page register

DSWPAG Extended Data Space (EDS) Write Page register

RCOUNT REPEAT Loop Count register

DCOUNT(1) DO Loop Count register

DOSTARTH(1,2), DOSTARTL(1,2) DO Loop Start Address register (High and Low)

DOENDH(1), DOENDL(1) DO Loop End Address register (High and Low)

CORCON Contains DSP Engine, DO Loop control and trap status bits

Note 1: This register is available on dsPIC33EPXXXMU806/810/814 devices only.

2: The DOSTARTH and DOSTARTL registers are read-only.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

FIGURE 3-2: PROGRAMMER’S MODEL

NO V SZ C

TBLPAG

PC23 PC0

D0D15

Program Counter

Data Table Page Address

Status Register

Working/Address

Registers

DSP Operand

Registers

W0 (WREG)

W10

W11

W12

W13

Frame Pointer/W14

Stack Pointer/W15*

DSP Address

Registers

AD39 AD0

AD31

DSP

Accumulators(1) AccA

AccB

DSRPAG

OA(1) OB(1) SA(1) SB(1)

RCOUNT

15 0

Repeat Loop Counter

DCOUNT

15 0

DO Loop Counter and Stack(1)

DOSTART

23 0

DO Loop Start Address and Stack(1)

DOEND DO Loop End Address and Stack(1)

IPL2 IPL1

SPLIM* Stack Pointer Limit

AD15

23 0

SRL

IPL0

PUSH.s and POP.s shadows

Nested DO Stack

OAB(1) SAB(1)

X Data Space Read Page Address

DA(1) DC

DSWPAG X Data Space Write Page Address

Note 1: This feature or bit is available on dsPIC33EPXXXMU806/810/814 devices only.

CORCON

15 0

CPU Core Control Register

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

3.6 CPU Control Registers

R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R -0 R/W-0

OA(1) OB(1) SA(1,4) SB(1,4) OAB(1) SAB(1) DA(1) DC

bit 15 bit 8

R/W-0(2,3) R/W-0(2,3) R/W-0(2,3) R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL<2:0> RA N OV Z C

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit C = Clearable bit

-n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow Status bit(1)

1 = Accumulator A has overflowed

0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow Status bit(1)

1 = Accumulator B has overflowed

0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1,4)

1 = Accumulator A is saturated or has been saturated at some time

0 = Accumulator A is not saturated

bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1,4)

1 = Accumulator B is saturated or has been saturated at some time

0 = Accumulator B is not saturated

bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit(1)

1 = Accumulators A or B have overflowed

0 = Neither Accumulators A or B have overflowed

bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1)

1 = Accumulators A or B are saturated or have been saturated at some time

0 = Neither Accumulator A or B are saturated

bit 9 DA: DO Loop Active bit(1)

1 = DO loop in progress

0 = DO loop not in progress

bit 8 DC: MCU ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data)

of the result occurred

0 = No carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized

data) of the result occurred

Note 1: This bit is available on dsPIC33EPXXXMU806/810/814 devices only.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL, if IPL<3> = 1.

3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by

clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not

be modified using bit operations.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15, user interrupts disabled)

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU Interrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress

0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative

0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that

causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation that affects the Z bit has set it at some time in the past

0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow bit

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: This bit is available on dsPIC33EPXXXMU806/810/814 devices only.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL, if IPL<3> = 1.

3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by

clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not

be modified using bit operations.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

VAR —US<1:0>

(1) EDT(1,2) DL<2:0>(1)

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0

SATA(1) SATB(1) SATDW(1) ACCSAT(1) IPL3(3) SFA RND(1) IF(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 VAR: Variable Exception Processing Latency Control bit

1 = Variable exception processing enabled

0 = Fixed exception processing enabled

bit 14 Unimplemented: Read as ‘0’

bit 13-12 US<1:0>: DSP Multiply Unsigned/Signed Control bits

11 = Reserved

10 = DSP engine multiplies are mixed-sign

01 = DSP engine multiplies are unsigned

00 = DSP engine multiplies are signed

bit 11 EDT: Early DO Loop Termination Control bit(1,2)

1 = Terminate executing DO loop at end of current loop iteration

0 = No effect

bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits

111 = 7 DO loops active

•

001 = 1 DO loop active

000 = 0 DO loops active

bit 7 SATA: AccA Saturation Enable bit

1 = Accumulator A saturation enabled

0 = Accumulator A saturation disabled

bit 6 SATB: AccB Saturation Enable bit

1 = Accumulator B saturation enabled

0 = Accumulator B saturation disabled

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit

1 = Data space write saturation enabled

0 = Data space write saturation disabled

bit 4 ACCSAT: Accumulator Saturation Mode Select bit

1 = 9.31 saturation (super saturation)

0 = 1.31 saturation (normal saturation)

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(3)

1 = CPU interrupt priority level is greater than 7

0 = CPU interrupt priority level is 7 or less

Note 1: This bit is available on dsPIC33EPXXXMU806/810/814 devices only.

2: This bit is always read as ‘0’.

3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

bit 2 SFA: Stack Frame Active Status bit

1 = Stack frame is active. W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and DSW-

PAG values

0 = Stack frame is not active. W14 and W15 address of EDS or Base Data Space

bit 1 RND: Rounding Mode Select bit

1 = Biased (conventional) rounding enabled

0 = Unbiased (convergent) rounding enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit

1 = Integer mode enabled for DSP multiply

0 = Fractional mode enabled for DSP multiply

Note 1: This bit is available on dsPIC33EPXXXMU806/810/814 devices only.

2: This bit is always read as ‘0’.

3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

3.7 Arithmetic Logic Unit (ALU)

The dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 ALU is 16 bits wide and is

capable of addition, subtraction, bit shifts and logic

operations. Unless otherwise mentioned, arithmetic

operations are two’s complement in nature. Depending

on the operation, the ALU can affect the values of the

Carry (C), Zero (Z), Negative (N), Overflow (OV) and

Digit Carry (DC) Status bits in the SR register. The C

and DC Status bits operate as Borrow and Digit Borrow

bits, respectively, for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

Refer to the “16-bit MCU and DSC Programmer’s

Reference Manual” (DS70157) for information on the

SR bits affected by each instruction.

The core CPU incorporates hardware support for both

multiplication and division. This includes a dedicated

hardware multiplier and support hardware for 16-bit

divisor division.

3.7.1 MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier, the ALU

supports unsigned, signed, or mixed-sign operation in

several MCU multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit signed x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

3.7.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. 16-bit signed and unsigned

DIV instructions can specify any W register for both

the 16-bit divisor (Wn) and any W register (aligned)

pair (W(m + 1):Wm) for the 32-bit dividend. The divide

algorithm takes one cycle per bit of divisor, so both

32-bit/16-bit and 16-bit/16-bit instructions take the

same number of cycles to execute.

3.8 DSP Engine

(dsPIC33EPXXXMU806/810/814

Devices Only)

The DSP engine consists of a high-speed 17-bit x

17-bit multiplier, a 40-bit barrel shifter and a 40-bit

adder/subtracter (with two target accumulators, round

and saturation logic).

The DSP engine can also perform inherent accumula-

tor-to-accumulator operations that require no additional

data. These instructions are ADD, SUB and NEG.

The DSP engine has options selected through bits in

the CPU Core Control register (CORCON), as listed

below:

• Fractional or integer DSP multiply (IF)

• Signed, unsigned, or mixed-sign DSP multiply (US)

• Conventional or convergent rounding (RND)

• Automatic saturation on/off for ACCA (SATA)

• Automatic saturation on/off for ACCB (SATB)

• Automatic saturation on/off for writes to data

memory (SATDW)

• Accumulator Saturation mode selection (ACC-

SAT)

TABLE 3-2: DSP INSTRUCTIONS

SUMMARY

Instruction Algebraic

Operation ACC Write

Back

CLR A = 0 Yes

ED A = (x – y)2No

EDAC A = A + (x – y)2No

MAC A = A + (x • y) Yes

MAC A = A + x2No

MOVSAC No change in A Yes

MPY A = x • y No

MPY A = x2No

MPY.N A = – x • y No

MSC A = A – x • y Yes

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

NOTES:

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

4.0 MEMORY ORGANIZATION

The dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 architecture features sepa-

rate program and data memory spaces and buses. This

architecture also allows the direct access of program

memory from the data space during code execution.

4.1 Program Address Space

The program address memory space of the

dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 devices is 4M instructions.

The space is addressable by a 24-bit value derived

either from the 23-bit PC during program execution, or

from table operation or data space remapping as

described in Section 4.6 “Interfacing Program and

Data Memory Spaces”.

User application access to the program memory space

is restricted to the lower half of the address range

(0x000000 to 0x7FFFFF). The exception is the use of

TBLRD/TBLWT operations, which use TBLPAG<7> to

permit access to the Configuration bits and Device ID

sections of the configuration memory space.

The memory map for the dsPIC33EPXXXMU806/810/

814 and PIC24EPXXXGU810/814 devices is shown in

Figure 4-1.

FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 DEVICES(1)

Note: This data sheet summarizes the features

of the dsPIC33EPXXXMU806/810/814

and PIC24EPXXXGU810/814 families of

devices. It is not intended to be a compre-

hensive reference source. To complement

the information in this data sheet, refer to

Section 4. “Program Memory”

(DS70613) of the “dsPIC33E/PIC24E

Family Reference Manual”, which is avail-

able from the Microchip web site

(www.microchip.com).

0x000000

0x000002

0x7FFFFE

0xF80000

0xF80012

0xF80014

0xFEFFFE

0xFF0000

0xFF0002

0xF7FFFE

0x000004

0x7FFFFC

0x000200

0x0001FE

Configuration Memory Space User Memory Space

Note 1: Memory areas are not shown to scale.

2: Reset location is controlled by Reset Target Vector Select bit (RSTPRI). See Se ction 29.0 “Special Features” for more information.

Reset Address(2)

Device Configuration

User Program

Flash Memory

(87552 instructions)

Registers

DEVID (2 Words)

Unimplemented

(Read ‘0’s)

GOTO Instruction(2)

Reserved

Interrupt Vector Table

dsPIC33EP256MU806/810/814 and

Reset Address(2)

Device Configuration

User Program

Flash Memory

(175104 instructions)

Registers

DEVID (2 Words)

Unimplemented

(Read ‘0’s)

GOTO Instruction(2)

Reserved

Interrupt Vector Table

dsPIC33EP512MU810/814 and

0x055800

0x0557FE

0x02AC00

0x02ABFE

Reserved Reserved

0xFFFFFE

0x7FFFFA

0x7FC000

Flash Memory

Auxiliary Program

PIC24EP256GU810/814 PIC24EP512GU810/814

GOTO Instruction(2)

Flash Memory

0x800000

Auxiliary Program

Reset Address(2) GOTO Instruction(2)

Reset Address(2)

Reserved Reserved

Write Latch Write Latch

0xF9FFFE

0xFA0000

0xFA00FE

0xFA0100

Vector

Auxiliary Interrupt Vector

Auxiliary Interrupt

0x7FFFF8

0x7FBFFE

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

4.1.1 PROGRAM MEMORY

ORGANIZATION

The program memory space is organized in word-

addressable blocks. Although it is treated as 24 bits

wide, it is more appropriate to think of each address of

the program memory as a lower and upper word, with

the upper byte of the upper word being unimplemented.

The lower word always has an even address, while the

upper word has an odd address (Figure 4-2).

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two during code execution. This

arrangement provides compatibility with data memory

space addressing and makes data in the program

memory space accessible.

4.1.2 INTERRUPT AND TRAP VECTORS

All dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 devices reserve the

addresses between 0x00000 and 0x000200 for hard-

coded program execution vectors. A hardware Reset

vector is provided to redirect code execution from the

default value of the PC on device Reset to the actual

start of code. A GOTO instruction is programmed by the

user application at address 0x000000 of the primary

Flash memory or at address 0x7FC000 of the auxiliary

Flash memory, with the actual address for the start of

code at address 0x000002 of the primary Flash mem-

ory or at address 0x7FC002 of the auxiliary Flash

memory. Reset Target Vector Select bit (RSTPRI) in

the FPOR Configuration register controls whether

primary or auxiliary Flash Reset location is used.

A more detailed discussion of the interrupt vector

tables is provided in Section 7.1 “Interrupt Vector

Table”.

FIGURE 4-2: PROGRAM MEMORY ORGANIZATION

0816

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

least significant word

most significant word

Instruction Width

0x000001

0x000003

0x000005

0x000007

msw

Address (lsw Address)

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

4.2 Data Add ress Space

The dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 CPU has a separate 16-bit

wide data memory space. The data space is accessed

using separate Address Generation Units (AGUs) for

read and write operations. The data memory maps are

shown in Figure 4-3, Figure 4-4, Figure 4-5 and

Figure 4-6.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the data space.

This arrangement gives a base data space address

range of 64 Kbytes or 32K words.

The base data space address is used in conjunction with

a read or write page register (DSRPAG or DSWPAG) to

form an extended data space, which has a total address

range of 16 MBytes.

dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 devices implement up to

56 Kbytes of data memory. If an EA point to a location

outside of this area, an all-zero word or byte is returned.

4.2.1 DATA SPACE WIDTH

The data memory space is organized in byte

addressable, 16-bit wide blocks. Data is aligned in data

memory and registers as 16-bit words, but all data

space EAs resolve to bytes. The Least Significant

Bytes (LSBs) of each word have even addresses, while

the Most Significant Bytes (MSBs) have odd

addresses.

4.2.2 DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC® MCU

devices and improve data space memory usage

efficiency, the dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 instruction set supports both

word and byte operations. As a consequence of byte

accessibility, all effective address calculations are

internally scaled to step through word-aligned memory.

For example, the core recognizes that Post-Modified

value of Ws + 1 for byte operations and Ws + 2 for word

operations.

A data byte read, reads the complete word that

contains the byte, using the LSB of any EA to

determine which byte to select. The selected byte is

placed onto the LSB of the data path. That is, data

memory and registers are organized as two parallel

byte-wide entities with shared (word) address decode

but separate write lines. Data byte writes only write to

the corresponding side of the array or register that

matches the byte address.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word

operations, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed. If the error occurred

on a write, the instruction is executed but the write does

not occur. In either case, a trap is then executed,

allowing the system and/or user application to examine

the machine state prior to execution of the address

Fault.

All byte loads into any W register are loaded into the

LSB. The MSB is not modified.

A Sign-Extend instruction (SE) is provided to allow user

applications to translate 8-bit signed data to 16-bit

signed values. Alternatively, for 16-bit unsigned data,

user applications can clear the MSB of any W register

by executing a Zero-Extend (ZE) instruction on the

appropriate address.

4.2.3 SFR SPACE

The first 4 Kbytes of the Near Data Space, from 0x0000

to 0x0FFF, is primarily occupied by Special Function

Registers (SFRs). These are used by the

dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 core and peripheral modules

for controlling the operation of the device.

SFRs are distributed among the modules that they

control, and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’.

4.2.4 NEAR DATA SPACE

The 8 Kbyte area between 0x0000 and 0x1FFF is

referred to as the near data space. Locations in this

space are directly addressable through a 13-bit abso-

lute address field within all memory direct instructions.

Additionally, the whole data space is addressable using

MOV instructions, which support Memory Direct

Addressing mode with a 16-bit address field, or by

using Indirect Addressing mode using a working

Note: The actual set of peripheral features and

interrupts varies by the device. Refer to

the corresponding device tables and

pinout diagrams for device-specific

information.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33EP512MU810/814 DEVICES WITH 52 KB RAM

0x0000

0x0FFE

SFR Space

0xFFFE

16 bits

LSbMSb

0xFFFF

X Data

Optionally

Mapped

into Program

Memory

Unimplemented (X)

0x1000

4 Kbyte

SFR Space

0x9000

0x8FFE

0xDFFE

0xE000

52 Kbyte

SRAM Space

Near

Data

8 Kbyte

Space

0xCFFE

0xD000

LSb

Address

MSb

Address

0x0000

0x0FFF

0x1001

0x9001

0x8FFF

0xDFFF

0xE001

0xCFFF

0xD001

0x8001 0x8000

0x1FFE

0x2000

0x1FFF

0x2001

0x7FFE

0x7FFF

DMA RAM

Y Data RAM (Y)

X Data RAM (X)

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

FIGURE 4-4: DATA MEMORY MAP FOR PIC24EP512GU810/814 DEVICES WITH 52 KB RAM

0x0000

0x0FFE

SFR Space

0xFFFE

16 bits

LSbMSb

0xFFFF

X Data

Optionally

Mapped

into Program

Memory

Unimplemented (X)

0x1000

4 Kbyte

SFR Space

0xDFFE

0xE000

52 Kbyte

SRAM Space

Near

Data

8 Kbyte

Space

0xCFFE

0xD000

LSb

Address

MSb

Address

0x0000

0x0FFF

0x1001

0xDFFF

0xE001

0xCFFF

0xD001

0x8001 0x8000

0x1FFE

0x2000

0x1FFF

0x2001

0x7FFE

0x7FFF

DMA RAM

X Data RAM (X)

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33EP256MU806/810/814 DEVICES WITH 28 KB RAM

0x0000

0x0FFE

0x4FFE

0xFFFE

LSb

Address

16 bits

LSbMSb

MSb

Address

0x0001

0x0FFF

0x4FFF

0xFFFF

Optionally

Mapped

into Program

Memory

0x7FFF 0x7FFE

0x1001 0x1000

0x5001 0x5000

4 Kbyte

SFR Space

28 Kbyte

SRAM Space

0x80000x8001

0x6FFE

0x7000

0x6FFF

0x7001

Space

Data

Near

8 Kbyte

SFR

Space

X Data RAM (X)

X Data

Unimplemented (X)

DMA RAM

Y Data RAM (Y)

0x1FFE

0x2000

0x1FFF

0x2001

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

FIGURE 4-6: DATA MEMORY MAP FOR PIC24EP256GU810/814 DEVICES WITH 28 KB RAM

0x0000

0x0FFE

0xFFFE

LSb

Address

16 bits

LSbMSb

MSb

Address

0x0001

0x0FFF

0xFFFF

Optionally

Mapped

into Program

Memory

0x7FFF 0x7FFE

0x1001 0x1000

4 Kbyte

SFR Space

28 Kbyte

SRAM Space

0x80000x8001

0x6FFE

0x7000

0x6FFF

0x7001

Space

Data

Near

8 Kbyte

SFR

Space

X Data RAM (X)

X Data

Unimplemented (X)

DMA RAM

0x1FFE

0x2000

0x1FFF

0x2001

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

4.2.5 X AND Y DATA SPACES

The dsPIC33EPXXXMU806/810/814 core has two

data spaces, X and Y. These data spaces can

be considered either separate (for some DSP

instructions), or as one unified linear address range (for

MCU instructions). The data spaces are accessed

using two Address Generation Units (AGUs) and

separate data paths. This feature allows certain

instructions to concurrently fetch two words from RAM,

thereby enabling efficient execution of DSP algorithms

such as Finite Impulse Response (FIR) filtering and

Fast Fourier Transform (FFT).

The PIC24EPXXXGU810/814 devices do not have a Y

data space and a Y AGU. For these devices, the entire

data space is treated as X data space.

The X data space is used by all instructions and

supports all addressing modes. X data space has

separate read and write data buses. The X read data

bus is the read data path for all instructions that view

data space as combined X and Y address space. It is

also the X data prefetch path for the dual operand DSP

instructions (MAC class).

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide

two concurrent data read paths.

Both the X and Y data spaces support Modulo

Addressing mode for all instructions, subject to

addressing mode restrictions. Bit-Reversed

Addressing mode is only supported for writes to X data

space. Modulo Addressing and Bit-Reversed

Addressing are not present in PIC24EPXXXGU810/

814 devices.

All data memory writes, including in DSP instructions,

view data space as combined X and Y address space.

The boundary between the X and Y data spaces is

device-dependent and is not user-programmable.

4.2.6 DMA RAM

Each dsPIC33EPXXXMU806/810/814 and

PIC24EPXXXGU810/814 device contains 4 Kbytes of

dual ported DMA RAM located at the end of Y data

RAM and is part of Y data space. Memory locations in

the DMA RAM space are accessible simultaneously by

the CPU and the DMA Controller module. DMA RAM is

utilized by the DMA controller to store data to be trans-

ferred to various peripherals using DMA, as well as

data transferred from various peripherals using DMA.

The DMA RAM can be accessed by the DMA controller

without having to steal cycles from the CPU.

When the CPU and the DMA controller attempt to

concurrently write to the same DMA RAM location, the

hardware ensures that the CPU is given precedence in

accessing the DMA RAM location. Therefore, the DMA

RAM provides a reliable means of transferring DMA

data without ever having to stall the CPU.

Note 1: DMA RAM can be used for general

purpose data storage if the DMA function

is not required in an application.

2: On PIC24EPXXXGU810/814 devices,

DMA RAM is located at the end of X data

RAM and is part of X data space.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

W0 0000 W0 (WREG) 0000

W1 0002 W1 0000

W2 0004 W2 0000

W3 0006 W3 0000

W4 0008 W4 0000

W5 000A W5 0000

W6 000C W6 0000

W7 000E W7 0000

W8 0010 W8 0000

W9 0012 W9 0000

W10 0014 W10 0000

W11 0016 W11 0000

W12 0018 W12 0000

W13 001A W13 0000

W14 001C W14 0000

W15 001E W15 0000

SPLIM 0020 SPLIM 0000

ACCAL 0022 ACCAL 0000

ACCAH 0024 ACCAH 0000

ACCAU 0026 Sign-extension of ACCA<39> ACCAU 0000

ACCBL 0028 ACCBL 0000

ACCBH 002A ACCBH 0000

ACCBU 002C Sign-extension of ACCB<39> ACCBU 0000

PCL 002E PCL —0000

PCH 0030 —————————PCH

0000

DSRPAG 0032 ——————DSRPAG

0001

DSWPAG 0034 ———————DSWPAG

0001

RCOUNT 0036 RCOUNT 0000

DCOUNT 0038 DCOUNT 0000

DOSTARTL 003A DOSTARTL —0000

DOSTARTH 003C ——————————DOSTARTH

0000

DOENDL 003E DOENDL —0000

DOENDH 0040 —————————— DOENDH 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000

CORCON 0044 VAR — US<1:0> EDT DL<2:0> SATA SATB SATDW ACCSAT IPL3 SFA RND IF 0020

MODCON 0046 XMODEN YMODEN —— BWM<3:0> YWM<3:0> XWM<3:0> 0000

XMODSRT 0048 XMODSRT<15:0> —0000

XMODEND 004A XMODEND<15:0> —0001

YMODSRT 004C YMODSRT<15:0> —0000

YMODEND 004E YMODEND<15:0> —0001

XBREV 0050 BREN XBREV<14:0> 0000

DISICNT 0052 — — DISICNT<13:0> 0000

TBLPAG 0054 ———————— TBLPAG<7:0> 0000

MSTRPR 0058 MSTRPR<15:0> 0000

TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY (CONTINUED)

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-2: CPU CORE REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

W0 0000 W0 (WREG) 0000

W1 0002 W1 0000

W2 0004 W2 0000

W3 0006 W3 0000

W4 0008 W4 0000

W5 000A W5 0000

W6 000C W6 0000

W7 000E W7 0000

W8 0010 W8 0000

W9 0012 W9 0000

W10 0014 W10 0000

W11 0016 W11 0000

W12 0018 W12 0000

W13 001A W13 0000

W14 001C W14 0000

W15 001E W15 0000

SPLIM 0020 SPLIM 0000

PCL 002E PCL —0000

PCH 0030 — — — — — — — — —PCH

0000

DSRPAG 0032 — — — — — — DSRPAG<9:0> 0001

DSWPAG 0034 — — — — — — — DSWPAG<8:0> 0001

RCOUNT 0036 RCOUNT<15:0> 0000

SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000

CORCON 0044 VAR —— — — — — — — — — — IPL3 SFA — — 0020

DISICNT 0052 — — DISICNT<13:0> 0000

TBLPAG 0054 — — — — — — — — TBLPAG<7:0> 0000

MSTRPR 0058 MSTRPR<15:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF

0000

IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF

0000

IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF

0000

IFS3 0806 — RTCIF DMA5IF DCIIF DCIEIF QEI1IF PSEMIF C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF

0000

IFS4 0808 — — — —QEI2IF— PSESMIF — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF —

0000

IFS5 080A PWM2IF PWM1IF IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF USB1IF —— U3TXIF U3RXIF U3EIF —

0000

IFS6 080C — — — — — — — — — — — PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF

0000

IFS7 080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — —

0000

IFS8 0810 — ICDIF IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF — DMA14IF DMA13IF DMA12IF IC12IF OC12IF 0000

IEC0 0820 NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE

0000

IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE

0000

IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE

0000

IEC3 0826 — RTCIE DMA5IE DCIIE DCIEIE QEI1IE PSEMIE C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE

0000

IEC4 0828 — — — —QEI2IE— PSESMIE — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE —

0000

IEC5 082A PWM2IE PWM1IE IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE USB1IE —— U3TXIE U3RXIE U3EIE —

0000

IEC6 082C — — — — — — — — — — — PWM7IE PWM6IE PWM5IE PWM4IE PWM3IE

0000

IEC7 082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — —

0000

IEC8 0830 — ICDIE IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE — DMA14IE DMA13IE DMA12IE IC12IE OC12IE 0000

IPC0 0840 — T1IP<2:0> —OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0>

4444

IPC1 0842 — T2IP<2:0> —OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0>

4444

IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0>

4444

IPC3 0846 —NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0>

4444

IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0>

4444

IPC5 084A — IC8IP<2:0> —IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0>

4444

IPC6 084C — T4IP<2:0> —OC4IP<2:0> —OC3IP<2:0>— DMA2IP<2:0>

4444

IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0>

4444

IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0>

4444

IPC9 0852 — IC5IP<2:0> —IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0>

4444

IPC10 0854 — OC7IP<2:0> —OC6IP<2:0> —OC5IP<2:0>—IC6IP<2:0>

4444

IPC11 0856 — T6IP<2:0> — DMA4IP<2:0> — PMPIP<2:0> — OC8IP<2:0>

4444

IPC12 0858 — T8IP<2:0> —MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0>

4444

IPC13 085A C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0>

4444

IPC14 085C — DCIEIP<2:0> — QEI1IP<2:0> — PSEMIP<2:0> — C2IP<2:0>

4444

IPC15 085E — — — — —RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0>

0444

IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — —

4440

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0>

4444

IPC18 0864 — QEI2IP<2:0> — — — — — PSESMIP<2:0> — — — —

4040

IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — —

4440

IPC21 086A — U4EIP<2:0> — USB1IP<2:0> — — — — — — — —

4400

IPC22 086C — SPI3IP<2:0> — SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0>

4444

IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — IC9IP<2:0> — OC9IP<2:0>

4444

IPC24 0870 — PWM6IP<2:0> — PWM5IP<2:0> — PWM4IP<2:0> — PWM3IP<2:0>

4444

IPC25 0872 — — — — — — — — — — — — — PWM7IP<2:0>

0004

IPC29 087A — DMA9IP<2:0> — DMA8IP<2:0> — — — — — — — —

4400

IPC30 087C — SPI4IP<2:0> — SPI4EIP<2:0> — DMA11IP<2:0> —DMA10IP<2:0>

4444

IPC31 087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0>

4444

IPC32 0880 — DMA13IP<2:0> — DMA12IP<2:0> — IC12IP<2:0> — OC12IP<2:0>

4444

IPC33 0882 — IC13IP<2:0> — OC13IP<2:0> — — — — —DMA14IP<2:0>

4404

IPC34 0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0>

4444

IPC35 0886 — — — — — ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0>

0444

INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —

0000

INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP

8000

INTCON3 08C4 — — — — — — — — —UAEDAEDOOVR— — — — 0000

INTCON4 08C6 — — — — — — — — — — — — — — —SGHT

0000

INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000

TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY (CONTINUED)

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF

0000

IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF

0000

IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF

0000

IFS3 0806 — RTCIF DMA5IF DCIIF DCIEIF QEI1IF PSEMIF C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF

0000

IFS4 0808 — — — —QEI2IF— PSESMIF — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF —

0000

IFS5 080A PWM2IF PWM1IF IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF USB1IF —— U3TXIF U3RXIF U3EIF —

0000

IFS6 080C — — — — — — — — — — — — PWM6IF PWM5IF PWM4IF PWM3IF

0000

IFS7 080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — —

0000

IFS8 0810 — ICDIF IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF — DMA14IF DMA13IF DMA12IF IC12IF OC12IF 0000

IEC0 0820 NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE

0000

IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE

0000

IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE

0000

IEC3 0826 — RTCIE DMA5IE DCIIE DCIEIE QEI1IE PSEMIE C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE

0000

IEC4 0828 — — — —QEI2IE— PSESMIE — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE —

0000

IEC5 082A PWM2IE PWM1IE IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE USB1IE —— U3TXIE U3RXIE U3EIE —

0000

IEC6 082C — — — — — — — — — — — — PWM6IE PWM5IE PWM4IE PWM3IE

0000

IEC7 082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — —

0000

IEC8 0830 — ICDIE IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE — DMA14IE DMA13IE DMA12IE IC12IE OC12IE 0000

IPC0 0840 — T1IP<2:0> —OC1IP<2:0> —IC1IP<2:0>— INT0IP<2:0>

4444

IPC1 0842 — T2IP<2:0> —OC2IP<2:0> —IC2IP<2:0>— DMA0IP<2:0>

4444

IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0>

4444

IPC3 0846 — NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0>

4444

IPC4 0848 —CNIP<2:0> —CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0>

4444

IPC5 084A —IC8IP<2:0> —IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0>

4444

IPC6 084C — T4IP<2:0> —OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0>

4444

IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0>

4444

IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0>

4444

IPC9 0852 —IC5IP<2:0> —IC4IP<2:0> —IC3IP<2:0>— DMA3IP<2:0>

4444

IPC10 0854 — OC7IP<2:0> —OC6IP<2:0> — OC5IP<2:0> —IC6IP<2:0>

4444

IPC11 0856 — T6IP<2:0> — DMA4IP<2:0> — PMPIP<2:0> — OC8IP<2:0>

4444

IPC12 0858 — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0>

4444

IPC13 085A C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0>

4444

IPC14 085C — DCIEIP<2:0> — QEI1IP<2:0> — PSEMIP<2:0> — C2IP<2:0>

4444

IPC15 085E — — — — — RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0>

0444

IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — —

4440

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0>

4444

IPC18 0864 — QEI2IP<2:0> — — — — — PSESMIP<2:0> — — — —

4040

IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — —

4440

IPC21 086A — U4EIP<2:0> — USB1IP<2:0> — — — — — — — —

4400

IPC22 086C — SPI3IP<2:0> — SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0>

4444

IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> —IC9IP<2:0>— OC9IP<2:0>

4444

IPC24 0870 — PWM6IP<2:0> — PWM5IP<2:0> — PWM4IP<2:0> — PWM3IP<2:0>

4444

IPC29 087A — DMA9IP<2:0> — DMA8IP<2:0> — — — — — — — —

4400

IPC30 087C — SPI4IP<2:0> — SPI4EIP<2:0> —DMA11IP<2:0>— DMA10IP<2:0>

4444

IPC31 087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0>

4444

IPC32 0880 — DMA13IP<2:0> — DMA12IP<2:0> — IC12IP<2:0> — OC12IP<2:0>

4444

IPC33 0882 — IC13IP<2:0> — OC13IP<2:0> — — — — — DMA14IP<2:0>

4404

IPC34 0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0>

4444

IPC35 0886 — — — — — ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0>

0444

INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —

0000

INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP

8000

INTCON3 08C4 — — — — — — — — — UAE DAE DOOVR — — — — 0000

INTCON4 08C6 — — — — — — — — — — — — — — —SGHT

0000

INTTREG 08C8 — — — — — ILR<3:0> VECNUM<7:0> 0000

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY (CONTINUED)

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF

0000

IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF

0000

IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF

0000

IFS3 0806 — RTCIF DMA5IF DCIIF DCIEIF QEI1IF PSEMIF C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF

0000

IFS4

0808 — — — —QEI2IF—PSESMIF — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF —

0000

IFS5

080A PWM2IF PWM1IF IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF USB1IF —— U3TXIF U3RXIF U3EIF —

0000

IFS6

080C — — — — — — — — — — — — — — PWM4IF PWM3IF

0000

IFS7

080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — —

0000

IFS8 0810

—ICDIF

IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF

— DMA14IF DMA13IF DMA12IF IC12IF OC12IF

0000

IEC0

0820

NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE

0000

IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE

0000

IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE

0000

IEC3 0826 — RTCIE DMA5IE DCIIE DCIEIE QEI1IE PSEMIE C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE

0000

IEC4

0828 — — — —QEI2IE—PSESMIE — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE —

0000

IEC5

082A PWM2IE PWM1IE IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE USB1IE —— U3TXIE U3RXIE U3EIE —

0000

IEC6

082C — — — — — — — — — — — — — —PWM4IEPWM3IE

0000

IEC7

082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — —

0000

IEC8 0830

— ICDIE

IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE

— DMA14IE DMA13IE DMA12IE IC12IE OC12IE

0000

IPC0 0840 — T1IP<2:0> —OC1IP<2:0> —IC1IP<2:0>— INT0IP<2:0>

4444

IPC1 0842 — T2IP<2:0> —OC2IP<2:0> —IC2IP<2:0>— DMA0IP<2:0>

4444

IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0>

4444

IPC3 0846 — NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0>

4444

IPC4 0848 —CNIP<2:0> —CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0>

4444

IPC5 084A — IC8IP<2:0> — IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0>

4444

IPC6 084C — T4IP<2:0> —OC4IP<2:0> —OC3IP<2:0>— DMA2IP<2:0>

4444

IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0>

4444

IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0>

4444

IPC9 0852 — IC5IP<2:0> — IC4IP<2:0> —IC3IP<2:0>— DMA3IP<2:0>

4444

IPC10 0854 — OC7IP<2:0> —OC6IP<2:0> —OC5IP<2:0>—IC6IP<2:0>

4444

IPC11 0856 — T6IP<2:0> — DMA4IP<2:0> — PMPIP<2:0> —OC8IP<2:0>

4444

IPC12 0858 — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0>

4444

IPC13 085A C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0>

4444

IPC14 085C — DCIEIP<2:0> — QEI1IP<2:0> — PSEMIP<2:0> — C2IP<2:0>

4444

IPC15 085E — — — — —RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0>

0444

IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — —

4440

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0>

4444

IPC18 0864 — QEI2IP<2:0> — — — — — PSESMIP<2:0> — — — —

4040

IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — —

4440

IPC21 086A —U4EIP<2:0> — USB1IP<2:0> — — — — — — — —

4400

IPC22 086C — SPI3IP<2:0> —SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0>

4444

IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> —IC9IP<2:0>—OC9IP<2:0>

4444

IPC24 0870 — — — — — — — — — PWM4IP<2:0> — PWM3IP<2:0>

0044

IPC29 087A — DMA9IP<2:0> — DMA8IP<2:0> — — — — — — — —

4400

IPC30

087C — SPI4IP<2:0> —SPI4EIP<2:0> — DMA11IP<2:0> —DMA10IP<2:0>

4444

IPC31

087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0>

4444

IPC32

0880 — DMA13IP<2:0> —DMA12IP<2:0> — IC12IP<2:0> — OC12IP<2:0>

4444

IPC33

0882 — IC13IP<2:0> — OC13IP<2:0> — — — — —DMA14IP<2:0>

4404

IPC34

0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0>

4444

IPC35

0886 — — — — — ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0>

0444

INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —

0000

INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP

8000

INTCON3 08C4 — — — — — — — — — UAE DAE DOOVR — — — —

0000

INTCON4 08C6 — — — — — — — — — — — — — — —

SGHT 0000

INTTREG

08C8 — — — — —ILR<3:0>

VECNUM<7:0> 0000

TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY (CONTINUED)

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICE S ONLY

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF

0000

IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF

0000

IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF

0000

IFS3 0806 — RTCIF DMA5IF — — — — C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF

0000

IFS4

0808 — — — — — — — — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF —

0000

IFS5

080A —— IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF USB1IF —— U3TXIF U3RXIF U3EIF —

0000

IFS7

080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — —

0000

IFS8 0810

— ICDIF

IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF

— DMA14IF DMA13IF DMA12IF IC12IF OC12IF

0000

IEC0

0820

NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE

0000

IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE

0000

IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE

0000

IEC3 0826 — RTCIE DMA5IE — — — — C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE

0000

IEC4

0828 — — — — — — — — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE —

0000

IEC5

082A —— IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE USB1IE —— U3TXIE U3RXIE U3EIE —

0000

IEC7

082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — —

0000

IEC8 0830

— ICDIE

IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE

— DMA14IE DMA13IE DMA12IE IC12IE OC12IE

0000

IPC0 0840 — T1IP<2:0> —OC1IP<2:0> —IC1IP<2:0>— INT0IP<2:0>

4444

IPC1 0842 — T2IP<2:0> —OC2IP<2:0> —IC2IP<2:0>— DMA0IP<2:0>

4444

IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> —SPI1EIP<2:0>— T3IP<2:0>

4444

IPC3 0846 — NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0>

4444

IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0>

4444

IPC5 084A —IC8IP<2:0> —IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0>

4444

IPC6 084C — T4IP<2:0> —OC4IP<2:0> —OC3IP<2:0>— DMA2IP<2:0>

4444

IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0>

4444

IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> —SPI2EIP<2:0>

4444

IPC9 0852 —IC5IP<2:0> —IC4IP<2:0> —IC3IP<2:0>— DMA3IP<2:0>

4444

IPC10 0854 — OC7IP<2:0> —OC6IP<2:0> —OC5IP<2:0>—IC6IP<2:0>

4444

IPC11 0856 — T6IP<2:0> — DMA4IP<2:0> — PMPIP<2:0> —OC8IP<2:0>

4444

IPC12 0858 — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0>

4444

IPC13 085A C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0>

4444

IPC14 085C — — — — — — — — — — — — — C2IP<2:0>

0004

IPC15 085E — — — — —RTCIP<2:0> — DMA5IP<2:0> — — — —

0440

IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — —

4440

IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0>

4444

IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — —

4440

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

IPC21 086A — U4EIP<2:0> — USB1IP<2:0> — — — — — — — —

4400

IPC22 086C — SPI3IP<2:0> — SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0>

4444

IPC23 086E — — — — — — — — —IC9IP<2:0>—OC9IP<2:0>

0044

IPC29 087A — DMA9IP<2:0> — DMA8IP<2:0> — — — — — — — —

4400

IPC30

087C — SPI4IP<2:0> — SPI4EIP<2:0> —DMA11IP<2:0>—DMA10IP<2:0>

4444

IPC31

087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0>

4444

IPC32

0880 —DMA13IP<2:0> — DMA12IP<2:0> — IC12IP<2:0> — OC12IP<2:0>

4444

IPC33

0882 — IC13IP<2:0> — OC13IP<2:0> — — — — —DMA14IP<2:0>

4404

IPC34

0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0>

4444

IPC35

0886 — — — — —ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0>

4444

INTCON1 08C0 NSTDIS — — — — — — — — DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —

0000

INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP

8000

INTCON3 08C4 — — — — — — — — — UAE DAE DOOVR — — — —

0000

INTCON4 08C6 — — — — — — — — — — — — — — —

SGHT 0000

INTTREG

08C8 — — — — —ILR<3:0>

VECNUM<7:0> 0000

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY (CONTINUED)

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-7: TIMER1 THROUGH TIMER9 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TMR1 0100 Timer1 Register xxxx

PR1 0102 Period Register 1 FFFF

T1CON 0104 TON —TSIDL—————— TGATE TCKPS<1:0> —TSYNCTCS —0000

TMR2 0106 Timer2 Register xxxx

TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx

TMR3 010A Timer3 Register xxxx

PR2 010C Period Register 2 FFFF

PR3 010E Period Register 3 FFFF

T2CON 0110 TON —TSIDL—————— TGATE TCKPS<1:0> T32 —TCS—0000

T3CON 0112 TON —TSIDL—————— TGATE TCKPS<1:0> ——TCS—0000

TMR4 0114 Timer4 Register xxxx

TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) xxxx

TMR5 0118 Timer5 Register xxxx

PR4 011A Period Register 4 FFFF

PR5 011C Period Register 5 FFFF

T4CON 011E TON —TSIDL—————— TGATE TCKPS<1:0> T32 —TCS—0000

T5CON 0120 TON —TSIDL—————— TGATE TCKPS<1:0> ——TCS—0000

TMR6 0122 Timer6 Register xxxx

TMR7HLD 0124 Timer7 Holding Register (for 32-bit operations only) xxxx

TMR7 0126 Timer7 Register xxxx

PR6 0128 Period Register 6 FFFF

PR7 012A Period Register 7 FFFF

T6CON 012C TON —TSIDL—————— TGATE TCKPS<1:0> T32 —TCS—0000

T7CON 012E TON —TSIDL—————— TGATE TCKPS<1:0> ——TCS—0000

TMR8 0130 Timer8 Register xxxx

TMR9HLD 0132 Timer9 Holding Register (for 32-bit operations only) xxxx

TMR9 0134 Timer9 Register xxxx

PR8 0136 Period Register 8 FFFF

PR9 0138 Period Register 9 FFFF

T8CON 013A TON —TSIDL—————— TGATE TCKPS<1:0> T32 —TCS—0000

T9CON 013C TON —TSIDL—————— TGATE TCKPS<1:0> ——TCS—0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-8: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 16 REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

IC1CON1 0140 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC1CON2 0142 ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC1BUF 0144 Input Capture 1 Buffer Register xxxx

IC1TMR 0146 Input Capture 1 Timer 0000

IC2CON1 0148 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC2CON2 014A ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC2BUF 014C Input Capture 2 Buffer Register xxxx

IC2TMR 014E Input Capture 2 Timer 0000

IC3CON1 0150 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC3CON2 0152 ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC3BUF 0154 Input Capture 3 Buffer Register xxxx

IC3TMR 0156 Input Capture 3 Timer 0000

IC4CON1 0158 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC4CON2 015A ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC4BUF 015C Input Capture 4 Buffer Register xxxx

IC4TMR 015E Input Capture 4 Timer 0000

IC5CON1 0160 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC5CON2 0162 ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC5BUF 0164 Input Capture 5 Buffer Register xxxx

IC5TMR 0166 Input Capture 5 Timer 0000

IC6CON1 0168 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC6CON2 016A ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC6BUF 016C Input Capture 6 Buffer Register xxxx

IC6TMR 016E Input Capture 6 Timer 0000

IC7CON1 0170 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC7CON2 0172 ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC7BUF 0174 Input Capture 7 Buffer Register xxxx

IC7TMR 0176 Input Capture 7 Timer 0000

IC8CON1 0178 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC8CON2 017A ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC8BUF 017C Input Capture 8 Buffer Register xxxx

IC8TMR 017E Input Capture 8 Timer 0000

IC9CON1 0180 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC9CON2 0182 ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC9BUF 0184 Input Capture 9 Buffer Register xxxx

IC9TMR 0186 Input Capture 9 Timer 0000

IC10CON1 0188 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC10CON2 018A ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

IC10BUF 018C Input Capture 10 Buffer Register xxxx

IC10TMR 018E Input Capture 10 Timer 0000

IC11CON1 0190 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC11CON2 0192 ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC11BUF 0194 Input Capture 11 Buffer Register xxxx

IC11TMR 0196 Input Capture 11 Timer 0000

IC12CON1 0198 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC12CON2 019A ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC12BUF 019C Input Capture 12 Buffer Register xxxx

IC12TMR 019E Input Capture 12 Timer 0000

IC13CON1 01A0 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC13CON2 01A2 ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC13BUF 01A4 Input Capture 13 Buffer Register xxxx

IC13TMR 01A6 Input Capture 13 Timer 0000

IC14CON1 01A8 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC14CON2 01AA ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC14BUF 01AC Input Capture 14 Buffer Register xxxx

IC14TMR 01AE Input Capture 14 Timer 0000

IC15CON1 01B0 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC15CON2 01B2 ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC15BUF 01B4 Input Capture 15 Buffer Register xxxx

IC15TMR 01B6 Input Capture 15 Timer 0000

IC16CON1 01B8 —— ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000

IC16CON2 01BA ——————— IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D

IC16BUF 01BC Input Capture 16 Buffer Register xxxx

IC16TMR 01BE Input Capture 16 Timer 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-8: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 16 REGISTER MAP (CONTINUED)

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-9: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 16 REGISTER MAP

File Name Addr . Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

OC1CON1

0900

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC1CON2

0902

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC1RS

0904

Output Compare 1 Secondary Register

xxxx

OC1R

0906

Output Compare 1 Register

xxxx

OC1TMR

0908

Timer Value 1 Register

xxxx

OC2CON1

090A

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC2CON2

090C

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC2RS

090E

Output Compare 2 Secondary Register

xxxx

OC2R

0910

Output Compare 2 Register

xxxx

OC2TMR

0912

Timer Value 2 Register

xxxx

OC3CON1

0914

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC3CON2

0916

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC3RS

0918

Output Compare 3 Secondary Register

xxxx

OC3R

091A

Output Compare 3 Register

xxxx

OC3TMR

091C

Timer Value 3 Register

xxxx

OC4CON1

091E

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC4CON2

0920

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC4RS

0922

Output Compare 4 Secondary Register

xxxx

OC4R

0924

Output Compare 4 Register

xxxx

OC4TMR

0926

Timer Value 4 Register

xxxx

OC5CON1

0928

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC5CON2

092A

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC5RS

092C

Output Compare 5 Secondary Register

xxxx

OC5R

092D

Output Compare 5 Register

xxxx

OC5TMR

0930

Timer Value 5 Register

xxxx

OC6CON1

0932

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC6CON2

0934

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC6RS

0936

Output Compare 6 Secondary Register

xxxx

OC6R

0938

Output Compare 6 Register

xxxx

OC6TMR

093A

Timer Value 6 Register

xxxx

OC7CON1

093C

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC7CON2

093E

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC7RS

0940

Output Compare 7 Secondary Register

xxxx

OC7R

0942

Output Compare 7 Register

xxxx

OC7TMR

0944

Timer Value 7 Register

xxxx

Legend:

— = unimplemented, read as ‘

’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

OC8CON1

0946

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC8CON2

0948

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC8RS

094A

Output Compare 8 Secondary Register

xxxx

OC8R

094C

Output Compare 8 Register

xxxx

OC8TMR

094E

Timer Value 8 Register

xxxx

OC9CON1

0950

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC9CON2

0952

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC9RS

0954

Output Compare 9 Secondary Register

xxxx

OC9R

0956

Output Compare 9 Register

xxxx

OC9TMR

0958

Timer Value 9 Register

xxxx

OC10CON1

095A

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC10CON2

095C

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC10RS

095E

Output Compare 10 Secondary Register

xxxx

OC10R

0960

Output Compare 10 Register

xxxx

OC10TMR

0962

Timer Value 10 Register

xxxx

OC11CON1

0964

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC11CON2

0966

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC11RS

0968

Output Compare 11 Secondary Register

xxxx

OC11R

096A

Output Compare 11 Register

xxxx

OC11TMR

096C

Timer Value 11 Register

xxxx

OC12CON1

096E

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC12CON2

0970

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC12RS

0972

Output Compare 12 Secondary Register

xxxx

OC12R

0974

Output Compare 12 Register

xxxx

OC12TMR

0976

Timer Value 12 Register

xxxx

OC13CON1

0978

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC13CON2

097A

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC13RS

097C

Output Compare 13 Secondary Register

xxxx

OC13R

097E

Output Compare 13 Register

xxxx

OC13TMR

0980

Timer Value 13 Register

xxxx

OC14CON1

0982

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC14CON2

0984

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC14RS

0986

Output Compare 14 Secondary Register

xxxx

OC14R

0988

Output Compare 14 Register

xxxx

OC14TMR

098A

Timer Value 14 Register

xxxx

TABLE 4-9: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 16 REGISTER MAP (CONTINUED)

File Name Addr . Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend:

— = unimplemented, read as ‘

’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

OC15CON1

098C

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC15CON2

098E

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC15RS

0990

Output Compare 15 Secondary Register

xxxx

OC15R

0992

Output Compare 15 Register

xxxx

OC15TMR

0994

Timer Value 15 Register

xxxx

OC16CON1

0996

—— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0>

0000

OC16CON2

0998

FLTMD FLTOUT FLTTRIEN OCINV — DCB<1:0> OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>

000C

OC16RS

099A

Output Compare 16 Secondary Register

xxxx

OC16R

099C

Output Compare 16 Register

xxxx

OC16TMR

099E

Timer Value 16 Register

xxxx

TABLE 4-9: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 16 REGISTER MAP (CONTINUED)

File Name Addr . Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend:

— = unimplemented, read as ‘

’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-10: PWM REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PTCON 0C00 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000

PTCON2 0C02 — — — — — — — — — — — — — PCLKDIV<2:0> 0000

PTPER 0C04 PTPER<15:0> FFF8

SEVTCMP 0C06 SEVTCMP<15:0> 0000

MDC 0C0A MDC<15:0> 0000

STCON 0C0E — — — SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000

STCON2 0C10 — — — — — — — — — — — — — PCLKSEL<2:0> 0000

STPER 0C12 STPER<15:0> FFF8

SSEVTCMP 0C14 SSEVTCMP<15:0> 0000

CHOP 0C1A CHPCLKEN — — — — — CHOPCLK<9:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-11: PWM GENERATOR 1 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000

IOCON1 0C22 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

FCLCON1 0C24 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

PDC1 0C26 PDC1<15:0> 0000

PHASE1 0C28 PHASE1<15:0> 0000

DTR1 0C2A — — DTR1<13:0> 0000

ALTDTR1 0C2C — — ALTDTR1<13:0> 0000

SDC1 0C2E SDC1<15:0> 0000

SPHASE1 0C30 SPHASE1<15:0> 0000

TRIG1 0C32 TRGCMP<15:0> 0000

TRGCON1 0C34 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000

PWMCAP1 0C38 PWMCAP1<15:0> 0000

LEBCON1 0C3A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000

LEBDLY1 0C3C — — — — LEB<11:0> 0000

AUXCON1 0C3E — — — — BLANKSEL<3:0> —— CHOPCLK<3:0> CHOPHEN CHOPLEN 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-12: PWM GENERATOR 2 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PWMCON2 0C40 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000

IOCON2 0C42 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

FCLCON2 0C44 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

PDC2 0C46 PDC2<15:0> 0000

PHASE2 0C48 PHASE2<15:0> 0000

DTR2 0C4A — — DTR2<13:0> 0000

ALTDTR2 0C4C — — ALTDTR2<13:0> 0000

SDC2 0C4E SDC2<15:0> 0000

SPHASE2 0C50 SPHASE2<15:0> 0000

TRIG2 0C52 TRGCMP<15:0> 0000

TRGCON2 0C54 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000

PWMCAP2 0C58 PWMCAP2<15:0> 0000

LEBCON2 0C5A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000

LEBDLY2 0C5C — — — — LEB<11:0> 0000

AUXCON2 0C5E — — — — BLANKSEL<3:0> —— CHOPSEL<3:0> CHOPHEN CHOPLEN 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-13: PWM GENERATOR 3 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PWMCON3 0C60 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000

IOCON3 0C62 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

FCLCON3 0C64 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

PDC3 0C66 PDC3<15:0> 0000

PHASE3 0C68 PHASE3<15:0> 0000

DTR3 0C6A — — DTR3<13:0> 0000

ALTDTR3 0C6C — — ALTDTR3<13:0> 0000

SDC3 0C6E SDC3<15:0> 0000

SPHASE3 0C70 SPHASE3<15:0> 0000

TRIG3 0C72 TRGCMP<15:0> 0000

TRGCON3 0C74 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000

PWMCAP3 0C78 PWMCAP3<15:0> 0000

LEBCON3 0C7A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000

LEBDLY3 0C7C — — — — LEB<11:0> 0000

AUXCON3 0C7E — — — — BLANKSEL<3:0> —— CHOPSEL<3:0> CHOPHEN CHOPLEN 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-14: PWM GENERATOR 4 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PWMCON4 0C80 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000

IOCON4 0C82 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

FCLCON4 0C84 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

PDC4 0C86 PDC4<15:0> 0000

PHASE4 0C88 PHASE4<15:0> 0000

DTR4 0C8A — — DTR4<13:0> 0000

ALTDTR4 0C8C — — ALTDTR4<13:0> 0000

SDC4 0C8E SDC4<15:0> 0000

SPHASE4 0C90 SPHASE4<15:0> 0000

TRIG4 0C92 TRGCMP<15:0> 0000

TRGCON4 0C94 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000

PWMCAP4 0C98 PWMCAP4<15:0> 0000

LEBCON4 0C9A PHR PHF PLR PLF FLTLEBEN CLLEBEN ———— BCH BCL BPHH BPHL BPLH BPLL 0000

LEBDLY4 0C9C — — — — LEB<11:0> 0000

AUXCON4 0C9E — — — — BLANKSEL<3:0> —— CHOPSEL<3:0> CHOPHEN CHOPLEN 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-15: PWM GENERATOR 5 REGISTER MAP FOR dsPIC33EPXXXMU810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PWMCON5 0CA0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000

IOCON5 0CA2 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

FCLCON5 0CA4 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

PDC5 0CA6 PDC5<15:0> 0000

PHASE5 0CA8 PHASE5<15:0> 0000

DTR5 0CAA — — DTR5<13:0> 0000

ALTDTR5 0CAC — — ALTDTR5<13:0> 0000

SDC5 0CAE SDC5<15:0> 0000

SPHASE5 0CB0 SPHASE5<15:0> 0000

TRIG5 0CB2 TRGCMP<15:0> 0000

TRGCON5 0CB4 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000

PWMCAP5 0CB8 PWM Capture<15:0> 0000

LEBCON5 0CBA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000

LEBDLY5 0CBC —— —— LEB<11:0> 0000

AUXCON5 0CBE —— —— BLANKSEL<3:0> —— CHOPSEL<3:0> CHOPHEN CHOPLEN 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-16: PWM GENERATOR 6 REGISTER MAP FOR dsPIC33EPXXXMU810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PWMCON6 0CC0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000

IOCON6 0CC2 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

FCLCON6 0CC4 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

PDC6 0CC6 PDC6<15:0> 0000

PHASE6 0CC8 PHASE6<15:0> 0000

DTR6 0CCA — — DTR6<13:0> 0000

ALTDTR6 0CCC — — ALTDTR6<13:0> 0000

SDC6 0CCE SDC6<15:0> 0000

SPHASE6 0CD0 SPHASE6<15:0> 0000

TRIG6 0CD2 TRGCMP<15:0> 0000

TRGCON6 0CD4 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000

PWMCAP6 0CD8 PWMCAP6<15:0> 0000

LEBCON6 0CDA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000

LEBDLY6 0CDC — — — — LEB<11:0> 0000

AUXCON6 0CDE — — — — BLANKSEL<3:0> —— CHOPSEL<3:0> CHOPHEN CHOPLEN 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-17: PWM GENERATOR 7 REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PWMCON7 0CE0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000

IOCON7 0CE2 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

FCLCON7 0CE4 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

PDC7 0CE6 PDC7<15:0> 0000

PHASE7 0CE8 PHASE7<15:0> 0000

DTR7 0CEA — — DTR7<13:0> 0000

ALTDTR7 0CEC — — ALTDTR7<13:0> 0000

SDC7 0CEE SDC7<15:0> 0000

SPHASE7 0CF0 SPHASE7<15:0> 0000

TRIG7 0CF2 TRGCMP<15:0> 0000

TRGCON7 0CF4 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000

PWMCAP7 0CF8 PWMCAP7<15:0> 0000

LEBCON7 0CFA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000

LEBDLY7 0CFC — — — — LEB<11:0> 0000

AUXCON7 0CFE — — — — BLANKSEL<3:0> —— CHOPSEL<3:0> CHOPHEN CHOPLEN 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-18: QEI1 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

QEI1CON 01C0 QEIEN — QEISIDL PIMOD<2:0> IMV<1:0> — INTDIV<2:0> CNTPOL GATEN CCM<1:0> 0000

QEI1IOC 01C2 QCAPEN FLTREN QFDIV<2:0> OUTFNC<1:0> SWPAB HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA 000x

QEI1STAT 01C4 —— PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN 0000

POS1CNTL 01C6 POSCNT<15:0> 0000

POS1CNTH 01C8 POSCNT<31:16> 0000

POS1HLD 01CA POSHLD<15:0> 0000

VEL1CNT 01CC VELCNT<15:0> 0000

INT1TMRL 01CE INTTMR<15:0> 0000

INT1TMRH 01D0 INTTMR<31:16> 0000

INT1HLDL 01D2 INTHLD<15:0> 0000

INT1HLDH 01D4 INTHLD<31:16> 0000

INDX1CNTL 01D6 INDXCNT<15:0> 0000

INDX1CNTH 01D8 INDXCNT<31:16> 0000

INDX1HLD 01DA INDXHLD<15:0> 0000

QEI1GECL 01DC QEIGEC<15:0> 0000

QEI1ICL 01DC QEIIC<15:0> 0000

QEI1GECH 01DE QEIGEC<31:16> 0000

QEI1ICH 01DE QEIIC<31:16> 0000

QEI1LECL 01E0 QEILEC<15:0> 0000

QEI1LECH 01E2 QEILEC<31:16> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-19: QEI2 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

QEI2CON 05C0 QEIEN — QEISIDL PIMOD<2:0> IMV<1:0> — INTDIV<2:0> CNTPOL GATEN CCM<1:0> 0000

QEI2IOC 05C2 QCAPEN FLTREN QFDIV<2:0> OUTFNC<1:0> SWPAB HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA 000x

QEI2STAT 05C4 —— PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN 0000

POS2CNTL 05C6 POSCNT<15:0> 0000

POS2CNTH 05C8 POSCNT<31:16> 0000

POS2HLD 05CA POSHLD<15:0> 0000

VEL2CNT 05CC VELCNT<15:0> 0000

INT2TMRL 05CE INTTMR<15:0> 0000

INT2TMRH 05D0 INTTMR<31:16> 0000

INT2HLDL 05D2 INTHLD<15:0> 0000

INT2HLDH 05D4 INTHLD<31:16> 0000

INDX2CNTL 05D6 INDXCNT<15:0> 0000

INDX2CNTH 05D8 INDXCNT<31:16> 0000

INDX2HLD 05DA INDXHLD<15:0> 0000

QEI2GECL 05DC QEIGEC<15:0> 0000

QEI2ICL 05DC QEIIC<15:0> 0000

QEI2GECH 05DE QEIGEC<31:16> 0000

QEI2ICH 05DE QEIIC<31:16> 0000

QEI2LECL 05E0 QEILEC<15:0> 0000

QEI2LECH 05E2 QEILEC<31:16> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-20: I2C1 and I2C2 REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

I2C1RCV 0200 — — — — — — — — Receive Register 0000

I2C1TRN 0202 — — — — — — — — Transmit Register 00FF

I2C1BRG 0204 — — — — — — — Baud Rate Generator 0000

I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000

I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000

I2C1ADD 020A — — — — — — Address Register 0000

I2C1MSK 020C — — — — — — Address Mask 0000

I2C2RCV 0210 — — — — — — — — Receive Register 0000

I2C2TRN 0212 — — — — — — — — Transmit Register 00FF

I2C2BRG 0214 — — — — — — — Baud Rate Generator 0000

I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000

I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000

I2C2ADD 021A — — — — — — Address Register 0000

I2C2MSK 021C — — — — — — Address Mask 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-21: UART1, UART2, UART3, and UART4 REGISTER MAP

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

0000

U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

0110

U1TXREG 0224 — — — — — — — Transmit Register

xxxx

U1RXREG 0226 — — — — — — — Receive Register

0000

U1BRG 0228 Baud Rate Generator Prescaler

0000

U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

0000

U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

0110

U2TXREG 0234 — — — — — — — Transmit Register

xxxx

U2RXREG 0236 — — — — — — — Receive Register

0000

U2BRG 0238 Baud Rate Generator Prescaler

0000

U3MODE 0250 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

0000

U3STA 0252 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

0110

U3TXREG 0254 — — — — — — — Transmit Register

xxxx

U3RXREG 0256 — — — — — — — Receive Register

0000

U3BRG 0258 Baud Rate Generator Prescaler

0000

U4MODE 02B0 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

0000

U4STA 02B2 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

0110

U4TXREG 02B4 — — — — — — — Transmit Register

xxxx

U4RXREG 02B6 — — — — — — — Receive Register

0000

U4BRG 02B8 Baud Rate Generator Prescaler

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-22: SPI1, SPI2, SPI3, and SPI4 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

SPI1STAT 0240 SPIEN —SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000

SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000

SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000

SPI1BUF 0248 SPIx Transmit and Receive Buffer Register 0000

SPI2STAT 0260 SPIEN —SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000

SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000

SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000

SPI2BUF 0268 SPIx Transmit and Receive Buffer Register 0000

SPI3STAT 02A0 SPIEN —SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000

SPI3CON1 02A2 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000

SPI3CON2 02A4 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000

SPI3BUF 02A8 SPIx Transmit and Receive Buffer Register 0000

SPI4STAT 02C0 SPIEN —SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000

SPI4CON1 02C2 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000

SPI4CON2 02C4 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000

SPI4BUF 02C8 SPIx Transmit and Receive Buffer Register 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-23: ADC1 and ADC2 REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

ADC1BUF0 0300 ADC Data Buffer 0 xxxx

ADC1BUF1 0302 ADC Data Buffer 1 xxxx

ADC1BUF2 0304 ADC Data Buffer 2 xxxx

ADC1BUF3 0306 ADC Data Buffer 3 xxxx

ADC1BUF4 0308 ADC Data Buffer 4 xxxx

ADC1BUF5 030A ADC Data Buffer 5 xxxx

ADC1BUF6 030C ADC Data Buffer 6 xxxx

ADC1BUF7 030E ADC Data Buffer 7 xxxx

ADC1BUF8 0310 ADC Data Buffer 8 xxxx

ADC1BUF9 0312 ADC Data Buffer 9 xxxx

ADC1BUFA 0314 ADC Data Buffer 10 xxxx

ADC1BUFB 0316 ADC Data Buffer 11 xxxx

ADC1BUFC 0318 ADC Data Buffer 12 xxxx

ADC1BUFD 031A ADC Data Buffer 13 xxxx

ADC1BUFE 031C ADC Data Buffer 14 xxxx

ADC1BUFF 031E ADC Data Buffer 15 xxxx

AD1CON1 0320 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> SSRCG SIMSAM ASAM SAMP DONE 0000

AD1CON2 0322 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS SMPI<4:0> BUFM ALTS 0000

AD1CON3 0324 ADRC —— SAMC<4:0> ADCS<7:0> 0000

AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB ————— CH123NA<1:0> CH123SA 0000

AD1CHS0 0328 CH0NB —— CH0SB<4:0> CH0NA —— CH0SA<4:0> 0000

AD1CSSH 032E CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 CSS23(1) CSS22(1) CSS21(1) CSS20(1) CSS19(1) CSS18(1) CSS17(1) CSS16(1) 0000

AD1CSSL 0330 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

AD1CON4 0332 — — — — — — — ADDMAEN —————DMABL<2:0>0000

ADC2BUF0 0340 ADC Data Buffer 0 xxxx

ADC2BUF1 0342 ADC Data Buffer 1 xxxx

ADC2BUF2 0344 ADC Data Buffer 2 xxxx

ADC2BUF3 0346 ADC Data Buffer 3 xxxx

ADC2BUF4 0348 ADC Data Buffer 4 xxxx

ADC2BUF5 034A ADC Data Buffer 5 xxxx

ADC2BUF6 034C ADC Data Buffer 6 xxxx

ADC2BUF7 034E ADC Data Buffer 7 xxxx

ADC2BUF8 0350 ADC Data Buffer 8 xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: These bits are not available on dsPIC33EP256MU806 devices.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

ADC2BUF9 0352 ADC Data Buffer 9 xxxx

ADC2BUFA 0354 ADC Data Buffer 10 xxxx

ADC2BUFB 0356 ADC Data Buffer 11 xxxx

ADC2BUFC 0358 ADC Data Buffer 12 xxxx

ADC2BUFD 035A ADC Data Buffer 13 xxxx

ADC2BUFE 035C ADC Data Buffer 14 xxxx

ADC2BUFF 035E ADC Data Buffer 15 xxxx

AD2CON1 0360 ADON — ADSIDL ADDMABM —— FORM<1:0> SSRC<2:0> SSRCG SIMSAM ASAM SAMP DONE 0000

AD2CON2 0362 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS SMPI<4:0> BUFM ALTS 0000

AD2CON3 0364 ADRC —— SAMC<4:0> ADCS<7:0> 0000

AD2CHS123 0366 — — — — — CH123NB<1:0> CH123SB ————— CH123NA<1:0> CH123SA 0000

AD2CHS0 0368 CH0NB —— CH0SB<4:0> CH0NA —— CH0SA<4:0> 0000

AD2CSSL 0270 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

AD2CON4 0272 — — — — — — — ADDMAEN —————DMABL<2:0>0000

TABLE 4-23: ADC1 and ADC2 REGISTER MAP (CONTINUED)

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: These bits are not available on dsPIC33EP256MU806 devices.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-24: DCI REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY

File

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

DCICON1 0280 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD UNFM CSDOM DJST — — — COFSM<1:0> 0000

DCICON2 0282 ———— BLEN<1:0> — COFSG<3:0> — WS<3:0> 0000

DCICON3 0284 ———— BCG<11:0> 0000

DCISTAT 0286 ———— SLOT<3:0> ———— ROV RFUL TUNF TMPTY 0000

TSCON 0288 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 0000

RSCON 028C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 0000

RXBUF0 0290 Receive 0 Data Register uuuu

RXBUF1 0292 Receive 1 Data Register uuuu

RXBUF2 0294 Receive 2 Data Register uuuu

RXBUF3 0296 Receive 3 Data Register uuuu

TXBUF0 0298 Transmit 0 Data Register 0000

TXBUF1 029A Transmit 1 Data Register 0000

TXBUF2 029C Transmit 2 Data Register 0000

TXBUF3 029E Transmit 3 Data Register 0000

Legend: x = Unknown, u = unchanged. Shaded locations indicate reserved space in SFR map for future module expansion. Read reserved locations as ‘0’s.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-25: USB OTG REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

U1OTGIR 0488 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF

0000

U1OTGIE 048A — — — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE

0000

U1OTGSTAT 048C — — — — — — — —ID —LSTATE— SESVD SESEND — VBUSVD

0000

U1OTGCON 048E — — — — — — — — DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS

0000

U1PWRC 0490 — — — — — — — —UACTPND

(4) ——USLPGRD—— USUSPND USBPWR

0000

U1IR(1) 04C0 — — — — — — — — STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF

0000

U1IR(2) 04C0 — — — — — — — — STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF

0000

U1IE(1) 04C2 — — — — — — — — STALLIE — RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE

0000

U1IE(2) 04C2 — — — — — — — — STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE DETACHIE

0000

U1EIR(1) 04C4 — — — — — — — — BTSEF BUSACCEF DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF

0000

U1EIR(2) 04C4 — — — — — — — — BTSEF BUSACCEF DMAEF BTOEF DFN8EF CRC16EF EOFEF PIDEF

0000

U1EIE(1) 04C6 — — — — — — — — BTSEE BUSACCEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE

0000

U1EIE(2) 04C6 — — — — — — — — BTSEE BUSACCEE DMAEE BTOEE DFN8EE CRC16EE EOFEE PIDEE

0000

U1STAT 04C8 — — — — — — — — ENDPT<3:0>(3) DIR PPBI

— —

0000

U1CON(1) 04CA — — — — — — — — —SE0PKTDIS— HOSTEN RESUME PPBRST USBEN

0000

U1CON(2) 04CA — — — — — — — — JSTATE SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN

0000

U1ADDR 04CC — — — — — — — —LSPDEN

(1) USB Device Address (DEVADDR)

0000

U1BDTP1 04CE — — — — — — — — BDTPTRL<7:1> —

0000

U1FRML 04D0 — — — — — — — — FRML<7:0>

0000

U1FRMH 04D2 — — — — — — — — — — — — — FRMH<2:0>

0000

U1TOK(3) 04D4 — — — — — — — — PID<3:0> EP<3:0>

0000

U1SOF(3) 04D6 — — — — — — — — CNT<7:0>

0000

U1BDTP2 04D8 — — — — — — — —BDTPTRH<7:0>

0000

U1BDTP3 04DA — — — — — — — —BDTPTRU<7:0>

0000

U1CNFG1 04DC — — — — — — — —UTEYEUOEMON — USBSIDL — — — —

0000

U1CNFG2 O4DE — — — — — — — — — — UVCMPSEL PUVBUS EXTI2CEN UVBUSDIS UVCMPDIS UTRDIS 0000

U1EP0 04E0 — — — — — — — — LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP1 04E2 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP2 04E4 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP3 04E6 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP4 04E8 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This bit is available when the module is operating in Device mode.

2: This bit is available when the module is operating in Host mode

3: Device mode only. These bits are always read as ‘0’ in Host mode.

4: The reset value for this bit is undefined.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

U1EP5 04EA — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP6 04EC — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP7 04EE — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP8 04F0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP9 04F2 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP10 04F4 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP11 04F6 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP12 04F8 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP13 04FA — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP14 04FC — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1EP15 04FE — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

0000

U1PWMRRS 0580 DC<7:0> PER<7:0> 0000

U1PWMCON 0582 PWMEN — — — — — PWMPOL CNTEN

— — — — — — — —

0000

TABLE 4-25: USB OTG REGISTER MAP (CONTINUED)

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This bit is available when the module is operating in Device mode.

2: This bit is available when the module is operating in Host mode

3: Device mode only. These bits are always read as ‘0’ in Host mode.

4: The reset value for this bit is undefined.

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814

TABLE 4-26: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 OR 1

File Name

Addr.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

C1CTRL1 0400 —— CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — CANCAP ——WIN0480

C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0> 0000

C1VEC 0404 ———FILHIT<4:0> — ICODE<6:0> 0040

C1FCTRL 0406 DMABS<2:0> — — — — — — — —FSA<4:0>0000

C1FIFO 0408 ——FBP<5:0> —— FNRB<5:0> 0000

C1INTF 040A —— TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000

C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000

C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000

C1CFG1 0410 — — — — — — — — SJW<1:0> BRP<5:0> 0000

C1CFG2 0412 —WAKFIL— — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000

C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF

C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000

C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-27: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0

File Name

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

— 0400-

041E

See Table 4-26 —

C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000

C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000

C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000

C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000

C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI<1:0> 0000

C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI<1:0> TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI<1:0> 0000

C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI<1:0> TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI<1:0> 0000

C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI<1:0> TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI<1:0> xxxx

C1RXD 0440 Received Data Word xxxx

C1TXD 0442 Transmit Data Word xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.