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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
1
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
General Description
Features
Functional Diagram
The HMC661LC4B is a SiGe monolithic, fully
differential, single rank, track-and-hold (T/H) that
provides unprecedented bandwidth and dynamic-range
performance to wideband sampled signal systems.
The T/H offers precision signal sampling over 18 GHz
bandwidth, with 9 - 10-bit linearity from DC to beyond
5 GHz input frequency, 1.05 mV noise, and <70 fs
random aperture jitter. The device can be clocked to 4
GS/s with minimal dynamic range loss. The T/H can be
used to expand the bandwidth and/or high-frequency
linearity of high-speed A/D conversion and signal
acquisition systems.
18 GHz Input bandwidth (1 Vp-p Full Scale)
4 GS/s Maximum Sampling Rate
68 dB SFDR (4 GHz / 0.5 Vp-p Input, CLK = 1 GS/s)
57 dB SFDR (4 GHz / 1 Vp-p Input, CLK = 1 GS/s)
Direct-Coupled I/O
Ultra-Clean Output Waveforms, Minimal Glitching
>60 dB Hold Mode Feedthrough Rejection
1.05 mV RMS Hold Mode Output Noise
Single / Dual Rank Evaluation Boards are Available
RoHS Compliant 4x4 mm SMT Package
Typical Applications
The HMC661LC4B is ideal for:
• RF ATE Applications
• Digital Sampling Oscilloscopes
• RF Demodulation Systems
• Digital Receiver Systems
• High Speed Peak Detectors
• Software Dened Radio
• Radar, ECM & ELINT Systems
• High Speed DAC De-Glitching
Electrical Specications TA = +25 °C, See Test Conditions on following page herein.
Parameter Conditions Test Level Min. Typ. Max. Units
Analog Inputs (INP, INN)
Differential Full Scale Range Full-scale input for linearity test 1 1 Vpp
Input Resistance Each lead to ground 3 50
Return Loss 0 to 12 GHz 3 -23 dB
Return Loss 12 to 18 GHz 3 -8 dB
Input Common Mode Voltage 3-0.1 00.1 V
Clock Inputs (CLKP, CLKN)
DC Differential Clock High Voltage (Track Mode) 3 20 40 2000 mV
DC Differential Clock Low Voltage (Hold Mode) 3 -2000 -40 -20 mV
Amplitude (Sinusoidal Input) Per Port 2-6 010 dBm
Input Common Mode Voltage 3-0.5 00.5 V
Clock Slew Rate Recommended for best linearity 3 2 - 4 V/ns
Return Loss 0 to 3 GHz 3 -24 dB
Return Loss 3 to 6 GHz 3 -18 dB
Input Resistance Each Lead to Ground 3 50
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
2
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Electrical Specications (continued)
Parameter Conditions Test Level Min. Typ. Max. Units
Analog Outputs (OUTP, OUTN)
Differential Full Scale Range 4 1 Vp-p
Common Mode Output Voltage 4 0 V
Output Impedance Per Port 350
Return Loss 0 to 3 GHz 3 -18 dB
Return Loss 3 to 6 GHz 3 -11 dB
Track Mode Dynamics
Baseband Gain 1-1.5 00.5 dB
Track Mode Bandwidth @ 1 Vp-p Input 4 6 GHz
Integrated Noise [2] 30.95 mV RMS
Hold Mode Dynamics
Sampling Bandwidth @ -3 dB Gain, 1 Vp-p Input Level 3 18 GHz
Differential Droop Rate (Linear Component) 1-1.4 %/ns
Differential Droop Rate Magnitude
(Fixed Component) 10.9 mV/ns
Feedthrough Rejection @ 3 GHz 3 ≥ 60 dB
Integrated Noise [2] 500 MHz Clock Frequency 3 1.05 mV RMS
Maximum Hold Time 3 2 ns
Single Tone THD/SFDR @ 0.995 GHz Full Scale Input (1 Vp-p) [1] 3 -56 / 56 dB
Single Tone THD/SFDR @ 1.995 GHz Full Scale Input (1 Vp-p) [1] 3 -56 / 56 dB
Single Tone THD/SFDR @ 2.995 GHz Full Scale Input (1 Vp-p) [1] 3 -57 / 57 dB
Single Tone THD/SFDR @ 3.995 GHz Full Scale Input (1 Vp-p) [1] 1 -57 / 57 dB
Single Tone THD/SFDR @ 4.995 GHz Full Scale Input (1 Vp-p) [1] 3 -56 / 56 dB
Single Tone THD/SFDR @ 5.995 GHz Full Scale Input (1 Vp-p) [1] 3 -49 / 50 dB
Single Tone THD/SFDR @ 7.995 GHz Full Scale Input (1 Vp-p) [1] 3 -42 / 43 dB
Single Tone THD/SFDR @ 9.995 GHz Full Scale Input (1 Vp-p) [1] 3 -35 / 38 dB
Single Tone THD/SFDR @ 11.995 GHz Full Scale Input (1 Vp-p) [1] 3 -31 / 33 dB
Single Tone THD/SFDR @ 0.995 GHz Half Full Scale Input (0.5 Vp-p) [1] 3 -65 / 67 dB
Single Tone THD/SFDR @ 1.995 GHz Half Full Scale Input (0.5 Vp-p) [1] 3 -64 / 65 dB
Single Tone THD/SFDR @ 2.995 GHz Half Full Scale Input (0.5 Vp-p) [1] 3 -64 / 66 dB
Single Tone THD/SFDR @ 3.995 GHz Half Full Scale Input (0.5 Vp-p) [1] 3 -66 / 68 dB
Single Tone THD/SFDR @ 4.995 GHz Half Full Scale Input (0.5 Vp-p) [1] 3 -64 / 67 dB
Single Tone THD/SFDR @ 5.995 GHz Half Full Scale Input (0.5 Vp-p) [1] 3 -57 / 62 dB
Single Tone THD/SFDR @ 7.995 GHz Half Full Scale Input (0.5 Vp-p) [1] 3 -53 / 55 dB
Single Tone THD/SFDR @ 9.995 GHz Half Full Scale Input (0.5 Vp-p) [1] 3 -43 / 45 dB
Single Tone THD/SFDR @ 11.995 GHz Half Full Scale Input (0.5 Vp-p) [1] 3 -38 / 40 dB
Track-to-Hold & Hold-and-Track Switching
Aperture Delay Simulated Value -6 ps
Random Aperture Jitter Full-scale Input @ 1 GHz [1] 3<70 fs
Differential Pedestal (Linear Component) 1 GHz Clock Frequency,
6 dBm Clock Power 3-1.0 %
Differential Pedestal Magnitude (Fixed Component), 32.8 mV
Clock Frequency @ 50% Duty Cycle 3 250 4000 MHz
[1] 1 GS/s Clock, Clock Power = 6 dBm / input terminal. [3] Production tested @ 500 MS/s Clock, Clock Power = 10 dBm
[2] Noise bandwidth limited by output amplier bandwidth of ~7 GHz.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
3
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Test Levels
1. 100% production tested at TA = +25 °C
2. Guaranteed by design/characterization testing
3. Characterization Sample Tested
4. Typical value only
Sampling Transfer Function
Parameter Conditions Test Level Min. Typ. Max. Units
Clock Buffer Pipeline Delay Simulated Value 35 ps
Acquisition Time to 1 mV Simulated Value 132 ps
Settling Time to 1 mV Simulated Value 135 ps
Output buffer delay (from hold-node to output) Simulated Value 43 ps
Power Supply Requirements
VccTH Voltage 1.9 22.1 V
VccTH Current 182 mA
VccOF Voltage 1.9 22.1 V
VccOF Current 140 mA
VccOB Voltage 1.9 22.1 V
VccOB Current 173 mA
VccCLK Voltage 1.9 22.1 V
VccCLK Current 126 mA
Vee Voltage -5 -4.75 -4.5 V
(Vee + VeeCLK) Current 1 -242 mA
Power Consumption 11.59 W
Electrical Specications (continued)
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0246810
DIFFERENTIAL OUTPUT VOLTAGE(V)
TIME(ns)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
0 4000 8000 12000 16000 20000
MAGNITUDE (dB)
FREQUENCY (MHz)
Ideal 18GHz Single Pole Lowpass
Sampling Transfer Function
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0246810
DIFFERENTIAL OUTPUT VOLTAGE (V)
TIME (ns)
Track&Hold Mode
Track Mode
Time Domain Output Waveform
@ fclk = 500 MHz, fin = 1.125 GHz
Time Domain Output Waveform
@ fclk = 500 MHz, fin = 10.125 GHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
4
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Hold-Mode SFDR vs. Frequency
& Input Power @ fclk = 1 GHz @ +6 dBm
Hold-Mode THD vs. Frequency
& Input Power @ fclk = 1 GHz @ +6 dBm
Hold-Mode THD vs. Frequency & Input
Power @ fclk = 500 MHz @ +10 dBm
Hold-Mode SFDR vs. Frequency & Input
Power @ fclk = 500 MHz @ +10 dBm [1] [2]
[1] FS = Full-Scale input level, HFS = Half-Full-Scale input level
[2] The measurement dynamic range for half-full-scale and full-scale inputs is about 68 dB and 74 dB, respectively, due to measurement noise oor
limitations. Hence the measured spurious products tend to limit at these levels.
Hold-Mode SFDR vs. Frequency
& Input Power @ fclk = 2 GHz @ 0 dBm
Hold-Mode THD vs. Frequency
& Input Power @ fclk = 2 GHz @ 0 dBm
30
40
50
60
70
80
024681012
2nd FS SFDR
3rd FS SFDR
2nd HFS SFDR
3rd HFS SFDR
SFDR (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
THD FS
THD HFS
-THD (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
THD FS
THD HFS
-THD (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
2nd FS SFDR
3rd FS SFDR
2nd HFS SFDR
3rd HFS SFDR
SFDR (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
THD FS
THD HFS
-THD (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
2nd FS SFDR
3rd FS SFDR
2nd HFS SFDR
3rd HFS SFDR
SFDR (dB)
FREQUENCY (GHz)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
5
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Hold-Mode SFDR vs. Frequency & Clock
Power @ Full Scale Input Level (1 Vp-p),
fclk = 500 MHz SINUSOID
Hold-Mode SFDR vs. Frequency & Clock
Power @ Full Scale Input Level (1 Vp-p),
fclk = 1 GHz SINUSOID
Hold-Mode SFDR vs. Frequency
& Input Power @ fclk = 3 GHz @ 0 dBm
Hold-Mode THD vs. Frequency
& Input Power @ fclk = 3 GHz @ 0 dBm
Hold-Mode SFDR vs. Frequency
& Input Power @ fclk = 4 GHz @ 0 dBm
Hold-Mode THD vs. Frequency
& Input Power @ fclk = 4 GHz @ 0 dBm
30
40
50
60
70
80
024681012
2nd FS SFDR
3rd FS SFDR
2nd HFS SFDR
3rd HFS SFDR
SFDR (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
THD FS
THD HFS
-THD (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
2nd FS SFDR
3rd FS SFDR
2nd HFS SFDR
3rd HFS SFDR
SFDR (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
THD FS
THD HFS
-THD (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
Pclk = -6 dBm
Pclk = 0 dBm
Pclk = 6 dBm
Pclk = 10 dBm
SFDR (dB)
FREQUENCY (GHz)
30
40
50
60
70
80
024681012
Pclk = -6 dBm
Pclk = 0 dBm
Pclk = 6 dBm
SFDR (dB)
FREQUENCY (GHz)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
6
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Aperture Delay: The delay of the exact sample time relative to the time that the hold command is applied to the
device. It is the difference between the delay of the clock switching transition to the hold node and the input signal
group delay to the hold node. If the input signal group delay to the hold node exceeds the clock delay this quantity
can be negative.
Aperture Jitter: The standard deviation of the sample instant in time.
Acquisition Time: The interval between the internal hold-to-track transition and the time at which the hold-node
signal is tracking the input signal within a specied accuracy. It does not include the pipeline delay of the clock
buffer.
Differential Pedestal: A component in the sample value caused by charge redistribution in the T/H switch during the
sampling transition. In general, the pedestal can consist of three components: a xed offset, a component that is
linearly related to input signal amplitude, and a component that is nonlinearly related to input signal amplitude.
The majority of the pedestal is usually linear. The value of the pedestal can be approximated by
P = Po + Plin Vin
where, Po is the xed pedestal component, Plin is the linear pedestal component, and Vin is the sampled signal
level.
Differential Droop Rate: The slow drift in the differential output voltage of a held sample while the T/H is in hold-mode.
It is typically caused by current leakage on the hold capacitors and corresponds to a decay in the held voltage
with increasing time. The droop can be approximated as the sum of a xed component and a component that is
linearly related to the held sample voltage. The total droop can be approximated by D = Do + Dlin Vin where Do is
the xed component, Dlin is the linear droop constant and Vin is the sampled signal level. The sign of Do tends to
be random so only the magnitude is specied. Since the droop is mostly linear, it causes little nonlinearity.
Feedthrough Rejection: A measure of the off-state (hold-mode) isolation of the T/H’s internal switch. It is dened as
the ratio of the amplitude of the output signal (for a sinusoidal input) feeding through during the hold mode to the
amplitude of the output signal during track mode. Normalization by the track-mode signal gives the true switch
isolation without the effects of the output amplier bandwidth limiting.
Full Scale Range: The voltage range between the minimum and maximum signal levels that can be handled by the
T/H while still meeting the specications.
Sampling Bandwidth: The -3 dB bandwidth of the sampled signal levels represented by the held sample amplitudes.
It includes both the bandwidth of the transfer function from the signal input to the hold-node and any band-limiting
effects associated with the nite time duration of the sampling aperture.
Settling Time: The interval between the internal track-hold transition and the time at which the held output signal is
settled to within a specied accuracy. It does not include the pipeline delay of the clock buffer but does include
the group delay of the output amplier.
Spurious Free Dynamic Range (SFDR): The ratio (usually expressed in dB) between the sinusoidal output signal
amplitude and the amplitude of the largest non-linearity product falling within one Nyquist bandwidth. It may be
specied for both full scale input and some fraction(s) of full scale input. A SFDR based only on 2nd order nonlinear
products is referred to as the 2nd order SFDR (SFDR2). A SFDR based only on 3rd order products is referred to as
the 3rd order SFDR (SFDR3).
Total Harmonic Distortion (THD): The ratio of the total power in the non-linearity-generated harmonics and harmonic
aliases (measured in one Nyquist band) to the output signal power.
Denition of Specications
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
7
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Application Notes
General: The HMC661LC4B ultra-wideband single rank T/H amplier is optimized for use in microwave data
conversion applications requiring maximum sampling bandwidth, high linearity over a very wide bandwidth, and
low noise. A key application of this device is front end sampling for high speed A/D converters to enhance their
input bandwidth and/or high frequency linearity. Although several high speed A/D converters offer enhanced
sample rates, few of them offer input bandwidth beyond a few GHz. In addition, maintenance of good sampling
linearity at frequencies beyond the UHF band is technologically challenging and most A/D converters suffer
rapidly degraded linearity above 1 or 2 GHz signal frequency. The HMC661LC4B can address these limitations
with its 18 GHz input bandwidth and excellent broadband linearity. Once sampling takes place within the T/H,
the low bandwidth held output waveform can be processed by an A/D with substantially reduced bandwidth. In
addition, A/D converter linearity performance limitations at high input frequencies are also mitigated because the
settled waveform is processed with the optimal baseband linearity of the A/D converter.
The single rank T/H has one T/H amplier and produces an output which consists of two segments. In the track
mode interval of the output waveform (positive differential clock voltage) the device behaves as a unity gain
amplier which replicates the input signal at the output subject to the input bandwidth and the output amplier
bandwidth limitations. At the positive to negative clock transition the device samples the input signal with a
very narrow sampling time aperture and holds the output relatively constant during the negative clock interval
at a value which is representative of the signal at the instant of sampling. The single rank device (as opposed
to a dual rank T/H) is often preferable for front end sampling with A/D converters because most high-speed
A/Ds already have a T/H, usually with much less bandwidth, integrated at the front end of the converter. Hence,
the HMC661LC4B forms a composite dual rank assembly (or triple rank if there is a dual rank device in the
converter) with the T/H in the converter. For equal technologies and designs, a single rank device will usually have
better linearity and noise than a dual rank device, since the single rank has fewer stages. Hence, the single rank
device is often the optimum choice for front end sampling with high speed A/Ds.
ESD: On-chip ESD protection networks are incorporated on the terminals, but the RF/microwave compatible interfaces
provide minimal protection and ESD precautions should be used.
Power Supply Sequencing: The recommended power supply startup sequence is VccOB, VccOF, VccTH, VccCLK,
Vee / VeeCLK if biased from independent supplies. VccOB, VccOF, VccTH and VccCLK can be connected to one
+2 V supply if desired.
Input Signal Drive: For best results, the inputs should be driven differentially. The input can be driven single-ended
but the linearity of the device will be degraded somewhat. The unused input should be terminated in 50 Ohms
when driving the device single-ended.
Clock Input: The device is in track-mode when (CLKP – CLKN) is high and it is in hold-mode when (CLKP – CLKN)
is low. The clock inputs should be driven differentially if possible. The clock inputs can be driven single-ended
if desired but the single-ended amplitude/slew rate should be similar to the full differential amplitude / slew rate
recommended for differential drive. The unused input should be terminated in 50 Ohms.
The T/H-mode linearity of the device varies somewhat with clock power at lower clock frequencies as shown in
the performance data plots. This results from a weak dependence of the linearity on clock zero crossing slew rate
for slew rates beneath a critical value. For optimal linearity, a clock zero-crossing slew rate of roughly 2 - 4 V/ns
(per clock input) or more is recommended. For sinusoidal clock inputs, 4 V/ns corresponds to a sinusoidal clock
power per differential half-circuit input of -6 dBm at 4 GHz, 0 dBm at 2 GHz, and 6 dBm at 1 GHz. Regardless of
the clock frequency, a minimum clock amplitude of -6 dBm is recommended (per differential half-circuit input)..
Outputs: The outputs should be sensed differentially for the cleanest output waveforms. The output impedance is
50 Ohms resistive returned to the VccOB supply. The output stage is designed to drive 50 Ohms terminated to
ground on each differential half-circuit output. The device offers a true ground-referenced common mode output
that is usually within ±50 mV of ground; however it is possible to adjust the VccOB power supply slightly to ne
tune the output common-mode level to precisely 0 V if desired. Additionally, the common-mode output level may
be adjusted within the range of approximately ±0.5 V by adjusting the VccOB power supply according to the
approximate relation Vocm=(VccOB-2)/2 where Vocm is the output common mode voltage and VccOB can be
varied in the range of +1 V < VccOB < +3 V.
The bandwidth of the output amplier that buffers the T/H signal between the hold-node and the 50 Ohm outputs
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
8
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Linearity Measurement
Application Notes (Continued)
When characterizing the linearity of a T/H, the transfer function linearity of the held samples (referred to as T/H-mode
linearity) is usually the quantity of most interest to the user. These samples contain the signal information that is
ultimately digitized by the downstream A/D converter. Since the T/H-mode linearity is often different than the track-
mode linearity, this presents a unique measurement issue for the signal rank T/H in that the linearity of only the hold-
portion of the analog output waveform must be selectively measured.
This issue is aggravated for high speed T/Hs because there are few wide-band time domain instruments (oscilloscopes
or A/D converters) with sufficient linearity to characterize a high linearity T/H operating at high clock rates. Therefore
a frequency domain instrument (spectrum analyzer) and measurement technique are used which allow selective
characterization of the hold-mode portion of the waveform
A common approach to this requirement has been to cascade two T/Hs in a dual rank conguration such that the
second T/H (T/H 2) re-samples the output of the rst T/H (T/H 1). The two T/Hs are usually clocked 180 degrees out-
of-phase in master-slave operation to eliminate the track-mode portion of the output waveform from the rst T/H. This
arrangement produces an output waveform that consists of two time segments. The rst segment is the T/H 1 hold-
mode output as observed through the T/H 2 track-mode transfer function. The second time segment is the T/H 1 hold-
mode output re-sampled and held by the T/H 2 device. This measurement approach is not a perfect representation
of the linearity of a single T/H due to the impact of the second T/H on the overall linearity. However, it does eliminate
is approximately 7 GHz. Hence, the output amplitude of the sampled waveform may be somewhat larger than the
track-mode response at high input frequencies due to the effect of the output amplier bandwidth. In particular,
frequencies beyond the output amplier bandwidth will be attenuated by the transfer function of the output buffer
while the held signal (which looks like DC to the settled output amplier) will suffer little attenuation.
The broad output buffer bandwidth is maintained to support the fast settling times required for users operating
at high clock rates. However, because of the broad bandwidth, the output amplier noise contribution to the total
output noise is signicant. Users operating at lower clock rates (such as < 1 GHz) may optimize their signal-to-
noise ratio by ltering the output to a lower bandwidth than the output amplier bandwidth of 7 GHz. Such an
output lter will not reduce the sampled front-end noise (which is frozen into the signal samples and represents
the majority of the T/H noise because of the wide front-end bandwidth) but it can reduce the output amplier
noise contribution. The user can lter the output to the lowest bandwidth that still retains the maximum settling
time required to support the chosen clock rate. Typically this optimal bandwidth is of the order of 2 to 3 times the
clock rate and it can be realized with a simple single pole RC lter if desired (for example a shunt capacitance on
the outputs). For example, a user operating at a clock rate of 350 MHz with a 1 GHz noise bandwidth output lter
can achieve approximately 1 dB lower noise relative to the unltered output condition.
The output will have very sharp transitions at the clock edges due to the broad output amplier bandwidth.
The user should be aware that any signicant length of cable between the chip output and the load will cause
frequency response roll-off and dispersion that can produce low amplitude tails with relatively long time-constants
in the settling of the output waveform into the load. This effect is most noticeable when operating in a lab setting
with output cables of a few feet length, even with high quality cable. Output cables between the T/H and the load
should be of very high quality and 2 ft or less in length.
Reections between the load and the device will also degrade the hold mode response. The output cable length
can be adjusted to minimize the reection perturbations to some extent. In general, the round trip transit time of
the cable should be an integer number of clock periods to obtain the minimal reection perturbation in the hold
mode portion of the waveform. The optimal performance is obtained when the T/H is within 50 ps or less of the
load since this gives a reection duration equal to the approximate settling time of the device. In A/D converter
applications the T/H should be placed as close as possible to the A/D converter to minimize reection effects on
the path between the T/H output and the input of the A/D converter.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
9
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Linearity Measurement (Continued)
the track-mode portion of the T/H 1 output and permits a spectrum analyzer linearity measurement of the cascaded
devices. Since T/H 2 only has to sample the held waveform from T/H 1, the linearity impact of T/H 2 is primarily
associated with its DC linearity. An often used approximation is that the DC linearity of T/H 2 is much higher than the
slew-rate dependent, high frequency linearity of T/H 1 so that the total non-linearity of the cascade is dominated by
the high frequency linearity of T/H 1. In this case, the dual rank conguration has a net linearity that closely resembles
the linearity of a single T/H, particularly at high frequencies. However, this approximation is not always valid. If not, the
dual rank conguration fails to represent the linearity of a single T/H. The HMC661LC4B represents such a case; the
3rd order nonlinearity of this device varies relatively slowly with frequency and is high enough over the T/H bandwidth
that the DC linearity of the 2nd T/H signicantly impacts the overall dual rank conguration for signals frequencies <5
GHz.
In order to address the weakness of the dual rank technique for the single rank T/H linearity characterization, Hittite
has developed a modied approach referred to as the attenuated dual rank technique. This method involves using
a dual rank T/H conguration with signicant attenuation A(dB) inserted between the 1st T/H and the 2nd T/H. A
typical attenuation value is A = 10 dB although more can be used for improved linearity measurement accuracy at
the expense of measurement dynamic range. This conguration still outputs a dual rank waveform that eliminates
the track mode component but the attenuation of the signal into the 2nd device substantially reduces the contribution
of its nonlinear products to the total spectrum such that the linearity of the 1st device dominates the overall linearity.
This results from the fact that the device follows the normal nonlinear order dependence: the 2nd order product level
relative to the fundamental is lowered by 10 dB for every 10 dB decrease in input level while the 3rd order product
level relative to the fundamental is lowered by 20 dB for every 10 dB decrease in input level. The phase of the T/H 2
nonlinear products relative to the T/H 1 products can vary depending on the product frequency and the path length
between the two devices. A worst case analysis of the uncertainty generated by the presence of the lower level T/H
2 products assuming identical devices for the two T/Hs and worst case phasing can be performed. Under these
conditions, the worst case error bounds in the determination of T/H 1 spurious-free dynamic range (SFDR,) due to the
presence of lower level T/H 2 non linear products is given by:
∆SFDR2(dB) = 20 log (1±10 -A/20) = +2.4, -3.3 dB for A = 10 dB
∆SFDR3(dB) = 20 log (1±10 -A/10) = +0.83, -0.92 dB for A = 10 dB
Where ∆SFDR2 and ∆SFDR3 are the errors in the 2nd order and 3rd order limited spurious-free dynamic ranges for
T/H 1 respectively.
Over the range of DC - 5 GHz the 3rd order products tend to dominate the spurious-free dynamic range so the typical
accuracy in assessing T/H 1 SFDR is of the order of ±0.9 dB for this measurement method. At higher frequencies, the
total linearity is dominated by the high frequency nonlinearity of T/H 1 and the contribution of T/H 2 DC nonlinearity is
much lower than that indicated by ∆SFDR2 above (which simplistically assumes equal linearity across the bandwidth).
So the T/H 1 linearity determination error over the entire frequency range is of the order ±0.9 dB for the attenuated
dual rank measurement method with A = 10 dB.
Another linearity measurement issue unique to the T/H device is the need for output waveform frequency response
correction. In the case of a dual rank T/H, the output waveform resembles a square wave with duration equal to the
clock period. Mathematically, the output can be viewed as the convolution of an ideal delta-function sample train
with a single square pulse of duration equal to one clock period. This weights the output spectral content with a
SIN(πf/fs )/(πf/fs) (Sinc) function frequency response envelope which has nulls at harmonics of the clock frequency fs
and substantial response reduction beyond half the clock frequency. This spectral content and envelope function are
observed during spectrum analyzer measurement because the analyzer simply reproduces the entire spectrum of the
incoming waveform. However, the spectral content of the held samples without the envelope weighting is required for
proper measurement of the sample’s linearity, as would be measured by a downstream A/D converter that samples
a time instant in the held waveform. Either the impact of the response envelope must be corrected in the data or a
measurement method must be used that heterodynes the relevant nonlinear harmonic products to low frequencies
to avoid signicant envelope response weighting. This latter method is referred to as the low frequency beat-product
technique.
The low frequency beat-product technique is commonly used for high-speed T/H linearity measurements, although
the measurement does impose restrictions on the specic input signal and clock frequencies that can be used. For
example, with a clock frequency of 512.5 MHz, a single tone input at 995 MHz beats with the 2nd harmonic of the
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
10
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Absolute Maximum Ratings
VccTH, VccOF, VccCLK 2.1 Vdc
VccOB 3 Vdc
Vee, VeeCLK -5.25 Vdc
CLKP, CLKN Input Power +10 d Bm
INP, INN Input Power +10 d Bm
Junction Temperature 125 °C
Continuous Pdiss (T= 85 °C) 2 W
Thermal Resistance
(junction to package bottom) 20 °C/W
Storage Temperature -65 to +150 °C
Operating Temperature -40 to +85 °C
ESD Sensitivity (HBM) Class 1B
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
sampling frequency (through the sampling process) to produce a 1st order beat product at 30 MHz. Likewise, the 2nd
and 3rd harmonics of the input signal (generated via distortion in the T/H) beat with the 4th and 6th harmonics of the
sampling frequency respectively to produce 2nd and 3rd order beat products at 60 MHz and 90 MHz. In this manner,
the T/H nonlinearity in the vicinity of 1 GHz can be measured even though the 995 MHz fundamental and the 1.99 GHz
and 2.985 GHz nonlinear harmonics are well beyond the 256 MHz 4 dB bandwidth of the SINx/x response envelope.
The possible input frequency choices are overly limited when the low frequency beat-product technique is used at high
clock rates. A related high frequency beat-product measurement utilizing correction for the SINx/x envelope weighting
must be employed to measure linearity over a wide range of input frequencies. Hittite uses both low frequency and
high frequency beat product methods to measure linearity for a wide range of clock and signal frequencies. Our high
frequency beat-product measurement avoids excessive envelope correction error by maintaining all beat products
within the 4 dB bandwidth of the Sinc function, where the envelope response is well behaved and easily modeled.
Linearity Measurement (Continued)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
11
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Outline Drawing
NOTES:
1. PACKAGE BODY MATERIAL: ALUMINA
2. LEAD AND PADDLE PLATING: 30-80 MICROINCHES GOLD OVER
50 MICROINCHES MINIMUM NICKEL.
3. DIMENSIONS ARE IN INCHES [MILLIMETERS].
4. LEAD SPACING TOLERANCE IS NON-CUMULATIVE
5. PACKAGE WARP SHALL NOT EXCEED 0.05 mm DATUM -C-
6. ALL GROUND LEADS MUST BE SOLDERED TO PCB RF GROUND.
PACKAGE BASE MUST BE SOLDERED TO Vee PLANE.
Package Information
Part Number Package Body Material Lead Finish MSL Rating Package Marking [2]
HMC661LC4B Alumina, White Gold over Nickel MSL3 [1] H661
XXXX
[1] Max peak reow temperature of 260 °C
[2] 4-Digit lot number XXXX
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
12
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Pin Number Function Description Interface Schematic
1, 2, 5, 13,
14, 17, 18 GNDa
Analog ground. This ground and clock ground must
be connected to the same DC potential but they can be
RF-isolated from each other if desired.
3INP
Positive T/H input. Has on-chip DC 50 Ω termination,
nominal max single-ended input level = ±0.25 V (-2 dBm)
for specied performance, +10 dBm max.
4INN
Negative T/H input. Has on-chip DC 50 Ω termination,
nominal max single-ended input level = ±0.25 V (-2 dBm)
for specied performance, +10 dBm max.
6VeeCLK
Negative clock buffer supply. VeeCLK and Vee must be
connected to the same potential. Total (Vee+VeeCLK)
nominal current is -242 mA at -4.75 V.
7VccCLK Clock buffer power. Requires 26 mA nominal current at 2 V.
8, 11, 12 GNDc
Clock ground. This ground and analog ground must be
connected to the same DC potential but they can be
RF-isolated from each other.
9,10 CLKN, CLKP Negative CLK input, Positive CLK input. Has on-chip 50
termination, +10 dBm max.
15, 16 OUTP, OUTN
Positive T/H RF output, Negative T/H RF output. 50
output impedance, nominal DC common mode output
voltage = 0 V. 50 load impedance can be DC or AC
coupled.
19, 21, 24,
Package
Base
Vee Negative analog supply. Total (Vee+VeeCLK) current is
-242 mA @ -4.75 V
20 VccOB
50 Ω output buffer power. VccOB current is 73 mA @ 2 V.
The output common mode voltage can be adjusted by the
user by varying VccOB in the range of +1 V to +3 V such
that Vocm~1/2(VccOB-2) for DC coupled output.
22 VccOF Output buffer supply. Requires a nominal current of 40 mA
at 2 V.
23 VccTH T/H core supply.
Requires nominal current of 82 mA at 2 V.
Pin Descriptions
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
13
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Evaluation PCB
The circuit board used in the application should use
RF circuit design techniques. Signal lines should
have 50 ohm impedance while the package ground
leads should be connected directly to the ground
plane similar to that shown. The package base is
internally connected to the Vee and VeeCLK supply
and should be connected to a Vee supply plane
for heat sinking. A sufficient number of via holes
should be used to connect the top and bottom
ground planes in order to provide good RF ground-
ing. The evaluation circuit board shown is available
from Hittite upon request.
Item Description
J1, J2, J5, J6 SRI K-Connector
J3, J4 SRI SMA-Connector
J7 HEADER, 0.9”, 9 pin, THRUHOLE, TIN
C7 - C12 0.01 µF Capacitor, 0402 Pkg.
C13 - C18 4.7 µF Capacitor, Tantalum
L1 - L4 Ferrite, 0402, Steward LI0402E300R-10
L5 Ferrite, 1206, Steward HF1206J150R-10
L6 Ferrite, 0603, Steward LI0603E470R-10
U1 HMC661LC4B Track-and-Hold Amplier
PCB [2] 128722 Evaluation Board
[1] Reference this number when ordering complete evaluation PCB
[2] Circuit Board Material: Arlon 25FR or Rogers 4350
List of Materials for Evaluation PCB
EVAL01-HMC661LC4B [1]
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
DATA CONVERTERS - SMT
14
HMC661LC4B
v03.0615
ULTRA-WIDEBAND 4 GS/S TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Application Circuit for Evaluation PCB
