1
GLT41016-10E
64k x 16 Embedded EDO DRAM
F
EATURES
◆
Logical organization: 64k x 16 bits
◆
Physical organization: 256 x 256 x 16
◆
Single 3.3V
±
0.3V power supply
◆
256 cycle refresh in 4 ms
◆
Refresh modes: RAS only, CBR, and Hidden
◆
Dual CAS for Byte Write and Byte Read control
◆
Separate I/O operation
◆
100 MHz page mode EDO cycle
◆
30 ns row access time
◆
Redundancy: 2 WL/256K, 2 CS/1M
G
ENERAL
D
ESCRIPTION
The 1 Mbit Embedded DRAM (EmDRAM) is an asynchro-
nous design with non-multiplexed row and column
addressing scheme. The memory operations are con-
trolled by RAS, CASH/CASL, and WE. Byte access is
controlled by CASH (upper byte) and CASL (lower byte).
The EmDRAM has been designed to support 200Mbyte
data rate with a 30 ns latency when operated in the page
mode with extended data output (EDO). this maximum
rate can be sustained for one page of 12 bytes.
Performance Data
Parameter -30
Max. RAS access time, t
RAC
30 ns
Max. column address access time, t
AA
12 ns
Max. CAS access time, t
CAC
8 ns
Min. extended data out page mode cycle time, t
PC
10 ns
Min. read/write cycle time, t
RC
60 ns
May 1997 (Rev. 1)
2G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
F
UNCTIONAL
B
LOCK
D
IAGRAM
1. On-chip power supply to the EmDRAM should be separated from the Logic portion.
RAS Timing
Generator
LCAS
Column
Address
Buffers
Internal
Address
Counter
Row
Address
Buffers
Refresh
Control
Clock
Column Decoders
Sense Amps
Memory Cells
Word Drivers
Row Decoders
A[8:0]
I/O Selector
Output
Buffer
Input
Buffer
DQ[15:8]
VSS
VCC
Output
Buffer
Input
Buffer
DQ[7:0]
UCAS
I/O Controller I/O Controller
WE
OE
Figure 1. GLT44016 - 256K X 16
Y[8:0]
X[8:0]
Signal Descriptions
[1]
Symbol Type Description
DI[15:0] Input Data in.
DO[15:0] Output Data out.
XRA[7:0] Input Row address.
XCA[7:0] Input Column address.
RAS Input Row address strobe (active low).
CASH Input Column address strobe, access DI/DO[15:8] (active low)
CASL Input Column address strobe, access DI/DO[7:0] (active low)
WE Input Write enable (active low).
OE Input Output enable (active low).
V
DD
Supply 3.3v voltage supply, 2 pairs double bond minimum
V
SS
Supply Ground (voltage return), 2 pairs double bond minimum
3
G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
Function T able
Input Pin DQ Pin
Functional ModeRAS LCAS UCAS WE OE DQ[7:0] DQ[15:8]
H–––– High-Z High-Z Standby
L H H – – High-Z High-Z Refresh
LLHHL D
OUT
High-Z Lower Byte Read
LHLHL High-Z Dout Upper Byte Read
L L L H L Dout Dout Word Read
LLHLH Din Don’t Care Lower Byte Write
L H L L H Don’t Care Din Upper Byte Write
LLLLH Din DinWord Write
L L L H H High-Z High Z –
T ruth Table
Function RAS CAS WE OE Address DQM0 DQM1 DQM2 DQM3 DI[31:0] DO[31:0]
Standby H H X X X XXXX XHigh-Z
Read L L H L Row/Col XXXX XData Out
Write (Early) L L L X Row/Col HHHHData In High-Z
Write DI[7:0] L L L X Row/Col L H H H Data In High-Z
Write DI[15:8] L L L X Row/Col H L H H Data In High-Z
Write DI[23:16] L L L X Row/Col H H L H Data In High-Z
Write DI[31:24] L L L X Row/Col H H H L Data In High-Z
Read-Write L L H
→
LL
→
H Row/Col HHHHData In Data Out
Page-Mode Read (First Cycle) L H
→
L H L Row/Col XXXX XData Out
Page-Mode Read (Subsequent Cycles) H
→
LHLCol XXXX XData Out
Page-Mode Write (First Cycle) L H
→
L L X Row/Col HHHHData In High-Z
Page-Mode Write (Subsequent Cycle) L H
→
LLXCol HHHHData In High-Z
Page-Mode R-W (First Cycle) L H
→
LH
→
LL
→
H Row/Col HHHHData In Data Out
Page-Mode R-W (Subsequent Cycle) L H
→
LH
→
LL
→
HCol HHHHData In Data Out
CBR Refresh H
→
LLXX X XXXX XHigh-Z
RAS-only Refresh L H X X Row XXXX XHigh-Z
4G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
E
LECTRICAL
S
PECIFICATIONS
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1. I
CC
Max. is specified for I
CC
for the output open condition.
2. Address can be changed once or less while RAS = V
IL
.
3. Address can be changed once or less while CAS = V
IH
.
Absolute Maximum Ratings
[1]
Symbol Parameter Conditions Value Unit
V
T
Voltage on any pin relative to V
SS
T
A
= 25 ˚C -0.5 to +4.6 V
I
OS
Short circuit output current T
A
= 25 ˚C 50 mA
P
D
Power dissipation T
A
= 25 ˚C 1 W
T
OPR
Operating temperature – 0 to +70
°
C
T
STG
Storage temperature – -55 to +150
°
C
Recommended Operating Conditions (T
A
= 0
°
C to +70
°
C)
Symbol Parameter Min Typ Max Unit
V
CC
Power supply voltage 3.0 3.3 3.6 V
V
SS
000V
V
IH
Input high voltage 2.4 – V
CC
+1 V
V
IL
Input low voltage -1.0 – 0.8 V
Capacitance (V
CC
= 5V
±
10%, T
A
= 25
°
C, f = 1 MHz)
Symbol Parameter Min Typ Max Unit
C
IN1
Input capacitance (A[8:0]) – 1 pF
C
IN2
Input capacitance (RAS, LCAS, UCAS, WE, OE)–1pF
C
I/O
Input/Output capacitance (DQ[15:0]) – 1 pF
DC Characteristics (V
CC
= 5V
±
10%, T
A
= 0
°
C to +70
°
C)
Symbol Parameter Condition
-30
Units
Note
Min Max
V
OH
Output High Voltage I
OH
= -2 mA 2.4 V
CC
V
V
OL
Output Low Voltage I
OL
= -1.0mA 0 0.4 V
I
LI
Input Leakage Current 0V
≤
V
IN
≤
V
CC
-2 -2
µ
A
I
LO
Output Leakage Current DQi Disable 0V
≤
V
O
≤
3.6V -10 -10
µ
A
I
CC1
Average Power Supply Current
(Operating)
RAS, CAS Cycling, t
RC
=Min. 200 mA
[1] [2]
I
CC2
Power Supply Current (Standby) RAS, CAS = V
IH
mA
[1]
I
CC3
Average Power Supply Current
(RAS-only Refresh)
RAS -Cycling, CAS = V
IH,
t
RC
= Min. 200 mA
[1] [2]
I
CC4
Average Power Supply Current
(Fast Page Mode)
RAS = V
IL,
CAS Cycling, t
HCP
= Min. 140 mA
[1] [3]
I
CC5
Average Power Supply Current
(CAS-before-RAS Refresh)
RAS Cycling, CAS-before-RAS 200 mA
5
G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
1. Maximum CASH to CASL skew is 1 ns.
2. Last CASx LOW.
3. Last CASx HIGH.
4. First CASx LOW.
5. First CASx HIGH.
6. Last CASx LOW to first CASx HIGH.
7. Last CASx HIGH to first CASx LOW.
AC Characteristics (V
CC
= 3.3 V
±
10%, T
A
= 0
°
C - 70
°
C, C
L
= 1 pF)
Symbol Description Min Max Units Notes
t
RC
Random Read/Write cycle time 60 – ns
t
PC Page Mode Read/Write cycle 10 – ns [1] [2]
tOFF Read Data valid from RAS high 0 – ns [3]
tDOH Read Data valid from next CAS low 3 – ns [4]
tAA Access time from Column Address – 12 ns
tRAC Access time from RAS low – 30 ns
tCAC Access time from CAS low – 8 ns [2]
tCPA Access time from CAS precharge – 14 ns [3]
tRAS RAS pulse width 30 – ns
tRCD RAS to CAS delay time 15 35 ns
tCSH CAS hold time for RAS 30 [5]
tCAS CAS pulse width 4 – ns [6]
tASR Row Address setup time 3 – ns
tRAH Row Address hold time 3 – ns
tASC Column Address setup time 3 – ns [4]
tCAH Column Address hold time 3 – ns [2]
tCP CAS precharge time 4 – ns [7]
tDS Write Data setup time 3 – ns [4]
tDH Write Data hold time 3 – ns [2]
tRP RAS precharge time 20 – ns
tCRP CAS to RAS precharge time 15 – ns [3]
tRSH CAS low to RAS high hold time 10 – ns [2]
tRCS Read command setup time 0 – ns [4]
tRCH Read command hold time from CAS high 0 – ns [3]
tRRH Read command hold time from RAS high 0 – ns
tWCS Write command setup time 5 – ns
tWCH Write command hold time 5 – ns
tWP WE pulse width 8 – ns
tTTransition time (rise and fall) – 1.5 ns
tRWL Write command to RAS high 8 – ns
tCWL Write command to CAS high 8 – ns [5]
6 G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
Figure 2. Read Cycle (RAS Output Control) Don’t Care
RAS
tRC
tRAS tRP
tRSH
tCAS
tRCD
tCRP
LCAS, UCAS
tAR
tRAL
tRAD
tCAH
tRAH
tASR tASC
A[8:0]
WE
OE
DQ
tCSH
tRCS
tAA
tRRH
tRCH
tOEA
tROH
tCAC
tOEZ
tOFF
tRAC
Hi-Z
ROW COLUMN
VALID DATA
Figure 3. Read Cycle (CAS Output Control)
Don’t Care
RAS
tRC
tRAS tRP
tRSH
tCAS
tRCD
tCRP
LCAS, UCAS
tAR
tRAL
tRAD
tCAH
tRAH
tASR tASC
A[8:0]
WE
OE
DQ
tCSH
tRCS
tAA
tRRH
tOEA
tROH
tCAC
tOEZ
tOFF
tRAC
Hi-Z VALID DATA
ROW COLUMN
7G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
Figure 4. Early Write (LCAS and UCAS Active) Don’t Care
RAS
tRC
tRAS tRP
tRSH
tCAS
tRCD
tCRP
LCAS, UCAS
tAR
tRAL
tRAD
tCAH
tRAH
tASR tASC
A[8:0]
WE
OE
DQ
tCSH
tWP
tWSC tWCH
tWCR
tCWL
tRWL
tDS tDH
tDHR
Hi-ZVALID DATA
COLUMNROW
RAS
Figure 5. Late Write (LCAS and UCAS Active)
tRC
tRAS tRP
tRSH
tCAS
tRCD
tCRP
LCAS, UCAS
tAR
tRAL
tRAD
tCAH
tRAH
tASR tASC
tCWL
tRWL
tWP
tRCS
tWCR
tOEH
tDH
tDS
A[8:0]
WE
OE
DQ
tCSH
Don’t Care
ROW COLUMN
VALID DATA
8 G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
RAS
Figure 6. Read Modify Write Cycle (LCAS and UCAS Active)
tRMW
tRAS tRP
tCSH
tRSH
tCAS
tRCD
tCRP
LCAS, UCAS
tAR
tRAL
tRAD
tCAH
tRAH
tASR tASC
tRCS
A[8:0]
WE
tAWD tCWL
tRWL
tWP
tOEH
tRWD
tCWD
tDZO tOEA
tOEZ tDS tDH
tDZC tCAC
tOED
tRAC
DQ
OE
Don’t Care
ROW COLUMN
OUT IN
Figure 7. Fast Page Mode Read Cycle with Extended Data Out
RAS
tRC
tRASP
tCRP tRCD tCAS tCP tCAS tCP tCAS
tCSH tPC tRSH
tRP
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
tRAD tRAL
tAR
tRCS tRCH
tRRH
tOEA
tCAC
tAA
HZ
tCAC
tCOH
tCAC
tCOH
tOEZ
tREZ
tRAC
tCPA
tAA tAA
LCAS, UCAS
A[8:0]
WE
OE
DQ
tCPA
Don’t Care
ROW COLUMN COLUMN COLUMN
VALID DATA VALID DATA VALID DATA
9G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
VALID
DATA
tOEA
tOEZ
tRCH tRCS
tCP
tASC
RAS
Figure 8. Fast Page Mode Read Hi-Z Operation
LCAS, UCAS
tCRP
tRASP
tRC tRP
tCSH
tAR
tRCD tCAS
tHPC
tCAS tCP tCAS tCP tCAS
tRSH
tCRP
tRAD
tCAH tCAH tCAH tCAH
tRAL
tRAH
tASR tASC tASC tASC
tRCS tRCH
tRRH
tWEP
tRAC tCHO tOCH
tOEP tOEP
tCAC tCAC
tAA
tCAC tCPA tAA tCAC
tAA tCOH tOEZ tOEA
tOEA tWEZ tAA tREZ
WE
OE
DQ
A[8:0]
Don’t Care
ROW COLUMN
VALID DATA
COLUMN COLUMN COLUMN
VALID DATA VALID
DATA VALID DATA
Figure 9. Fast Page Mode Early Write Cycle
RAS
tRC
tRASP
tCRP tRCD tCAS tCP tCAS tCP tCAS
tCSH tPC tRSH
tRP
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
tRAD tRAL
tAR
LCAS, UCAS
A[8:0]
WE
OE
DQ
tCWL
tWCS tWCH
tCWL
tWCS
tWP
tWCH tWCS
tWP
tWCH
tCWL
tDS tDH tDS tDH tDS tDH
tWP
Don’t Care
ROW COLUMN COLUMN COLUMN
INPUT DATAINPUT DATAINPUT DATA
10 G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
tASC
tCWL
tCWL
Figure 10. Fast Page Mode Read Modify Write Cycle
RAS
tRC
tRASP
tCRP tRCD tCAS tCP
tRP
tASR
tRAL
tAR
A[8:0]
WE
OE
DQ
tCP
tCSH tRSH
tCAS tCAS
tPRMW
tRAH tASC tASC tCAH tCAH
tRAD
tCAH
tAWD tWP
tCWD
tRCS
tWP
tAWD
tCWD
tWP
tCWL
tAWD
tCWD
tOEA tOEZ tOEA tOEZ tOEA tOEZ
tAA tDS
tCAC tDH
tAA
tCAC
tDS
tDH tCAC
tAA tDS
tDH
Don’t Care
LCAS, UCAS
ROW COLUMN COLUMN COLUMN
OUT OUT OUTIN IN IN
Figure 11. CAS-before-RAS Refresh Cycle
RAS
A[8:0]
WE
OE
DQ
tRC
tRAS tRP
tRP
tRPC tCSR tCHR tRPC
tOFF
HZ
INHIBIT FALLING TRANSITION
Don’t Care
LCAS, UCAS
11G-LINK Technology
GLT41016-10E
May 1997 (Rev. 1)
Figure 12. Hidden Refresh Cycle
RAS
tRC
tRP
tAR
A[8:0]
WE
OE
DQ
tRAS tRAS
tCRP tRCD tCHR
tASR tRAH tASC tCAH
tRAD tRAL
tRSH
tRRH
tOEA
tROH
tOEZ
tAA
tCAC
tRAC
HZ
tOFF
tRCS
LCAS, UCAS
Don’t Care
ROW COLUMN
VALID DATA
Figure 13. RAS-Only Refresh Cycle
Don’t Care
RAS
tRC
tRAS tRP
tCRP
LCAS, UCAS
tRAH
tASR
A[8:0]
DQ Hi-Z
tRPC
WE, OE
ROW
© 2001 G-LINK Technology
All rights reserved. No part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior written consent of
G-LINK Technology.
Circuit diagrams utilizing G-LINK products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for design purposes is
not necessarily given.
G-LINK Technology reserves the right to change products or specifications without notice.
The information contained in this document does not convey any license under copyrights, patent rights or trademarks claimed and owned by G-LINK or its subsidiaries.
G-LINK assumes no liability for G-LINK applications assistance, customer’s product design, or infringement of patents arising from use of semiconductor devices in such
systems’ designs. Nor does G-LINK warrant or represent that any patent right, copyright, or other intellectual property right of G-LINK covering or relating to any combination,
machine, or process in which such semiconductor devices might be or are used.
G-LINK Technology’s products are not authorized for use in life support devices or systems. Life support devices or systems are device or systems which are: a) intended for
surgical implant into the human body and b) designed to support or sustain life; and when properly used according to label instructions, can reasonably be expected to cause
significant injury to the user in the event of failure.
The information contained in this document is believed to be entirely accurate. However, G-LINK Technology assumes no responsibility for inaccuracies.
GLT41016-10E
www.glinktech.com
G-LINK Technology
1753 South Main Street
Milpitas, California, 95035, USA
TEL: 408-240-1380 • FAX: 408-240-1385
G-LINK Technology Corporation, Taiwan
6F, No. 24-2, Industry E. Rd. IV
Science-Based Industrial Park
Hsin Chu, Taiwan, R.O.C.
TEL: 03-578-2833 • FAX: 03-578-5820
Printed in USA
