0 XC9536 In-System Programmable CPLD R DS064 (v6.3) April 3, 2006 0 5 Product Specification Features Description * * 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz * * * 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3V or 5V I/O capability Advanced CMOS 5V FastFLASHTM technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 44-pin VQFP, 48-pin CSP packages The XC9536 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 for the architecture overview. * * * * * * * * * * Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9536 device. (83) e manc erfor High P Typical ICC (mA) * * Power Management (50) (50) er w Pow Lo (30) 0 50 100 Clock Frequency (MHz) DS064_01_110101 Figure 1: Typical ICC vs. Frequency for XC9536 (c) 1996-2006 Xilinx, Inc. All rights reserved. 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DS064 (v6.3) April 3, 2006 Product Specification www.xilinx.com 1 R XC9536 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 Function Block 1 18 I/O Macrocells 1 to 18 I/O Fast CONNECT II Switch Matrix I/O I/O I/O Blocks I/O I/O I/O 36 Function Block 2 18 Macrocells 1 to 18 I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS DS064_02_110101 Figure 2: XC9536 Architecture Function block outputs (indicated by the bold line) drive the I/O blocks directly. 2 www.xilinx.com DS064 (v6.3) April 3, 2006 Product Specification R XC9536 In-System Programmable CPLD Absolute Maximum Ratings Symbol Description Value Units -0.5 to 7.0 V VCC Supply voltage relative to GND VIN Input voltage relative to GND -0.5 to VCC + 0.5 V VTS Voltage applied to 3-state output -0.5 to VCC + 0.5 V TSTG Storage temperature (ambient) -65 to +150 oC +150 oC TJ Junction temperature Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and input buffers Supply voltage for output drivers for 5V operation Commercial TA = 0oC to 70oC Industrial TA = -40oC to +85oC Commercial TA = 0oC to 70oC Industrial TA = -40oC to +85oC Supply voltage for output drivers for 3.3V operation Min Max Units 4.75 5.25 V 4.5 5.5 4.75 5.25 4.5 5.5 3.0 3.6 V VIL Low-level input voltage 0 0.80 V VIH High-level input voltage 2.0 VCCINT + 0.5 V VO Output voltage 0 VCCIO V Quality and Reliability Characteristics Symbol Parameter TDR Data Retention NPE Program/Erase Cycles (Endurance) Min Max Units 20 - Years 10,000 - Cycles DC Characteristic Over Recommended Operating Conditions Symbol Min Max Units IOH = -4.0 mA, VCC = Min 2.4 - V Output high voltage for 3.3V outputs IOH = -3.2 mA, VCC = Min 2.4 - V Output low voltage for 5V outputs IOL = 24 mA, VCC = Min - 0.5 V Output low voltage for 3.3V outputs IOL = 10 mA, VCC = Min - 0.4 V IIL Input leakage current VCC = Max VIN = GND or VCC - 10 A IIH I/O high-Z leakage current VCC = Max VIN = GND or VCC - 10 A CIN I/O capacitance VIN = GND f = 1.0 MHz - 10 pF ICC Operating supply current (low power mode, active) VI = GND, No load f = 1.0 MHz 30 (Typical) VOH VOL Parameter Output high voltage for 5V outputs DS064 (v6.3) April 3, 2006 Product Specification Test Conditions www.xilinx.com mA 3 R XC9536 In-System Programmable CPLD AC Characteristics Symbol Parameter XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Min Max Min Max Min Max Min Max Min - 5.0 - 6.0 - 7.5 - 10.0 - 15.0 ns 3.5 - 3.5 - 4.5 - 6.0 - 8.0 - ns Max Units TPD I/O to output valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - 0 - 0 - 0 - ns GCK to output valid - 4.0 - 4.0 - 4.5 - 6.0 - 8.0 ns 16-bit counter frequency 100.0 - 100.0 - 125.0 - 111.1 - 95.2 - MHz Multiple FB internal operating frequency 100.0 - 100.0 - 83.3 - 66.7 - 55.6 - MHz TPSU I/O setup time before p-term clock input 0.5 - 0.5 - 0.5 - 2.0 - 4.0 - ns TPH I/O hold time after p-term clock input 3.0 - 3.0 - 4.0 - 4.0 - 4.0 - ns P-term clock output valid - 7.0 - 7.0 - 8.5 - 10.0 - 12.0 ns TOE GTS to output valid - 5.0 - 5.0 - 5.5 - 6.0 - 11.0 ns TOD GTS to output disable - 5.0 - 5.0 - 5.5 - 6.0 - 11.0 ns TPOE Product term OE to output enabled - 9.0 - 9.0 - 9.5 - 10.0 - 14.0 ns TPOD Product term OE to output disabled - 9.0 - 9.0 - 9.5 - 10.0 - 14.0 ns TWLH GCK pulse width (High or Low) 4.0 - 4.0 - 4.0 - 4.5 - 5.5 - ns Asynchronous preset/reset pulse width (High or Low) 7.0 - 7.0 - 7.0 - 7.5 - 8.0 - ns TCO fCNT (1) fSYSTEM (2) TPCO TAPRPW Notes: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. VTEST R1 Output Type VCCIO VTEST R1 R2 CL 5.0V 5.0V 160 120 35 pF 3.3V 3.3V 260 360 35 pF Device Output R2 CL DS067_03_110101 Figure 3: AC Load Circuit 4 www.xilinx.com DS064 (v6.3) April 3, 2006 Product Specification R XC9536 In-System Programmable CPLD Internal Timing Parameters Symbol Parameter XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Min Max Min Max Min Max Min Max Min Max Units Buffer Delays TIN Input buffer delay - 1.5 - 1.5 - 2.5 - 3.5 - 4.5 ns TGCK GCK buffer delay - 1.5 - 1.5 - 1.5 - 2.5 - 3.0 ns TGSR GSR buffer delay - 4.0 - 4.0 - 4.5 - 6.0 - 7.5 ns TGTS GTS buffer delay - 5.0 - 5.0 - 5.5 - 6.0 - 11.0 ns TOUT Output buffer delay - 2.0 - 2.0 - 2.5 - 3.0 - 4.5 ns TEN Output buffer enable/disable delay - 0 - 0 - 0 - 0 - 0 ns Product Term Control Delays TPTCK Product term clock delay - 3.0 - 3.0 - 3.0 - 3.0 - 2.5 ns TPTSR Product term set/reset delay - 1.0 - 1.0 - 2.0 - 2.5 - 3.0 ns TPTTS Product term 3-state delay - 5.5 - 5.5 - 4.5 - 3.5 - 5.0 ns - 0.5 - 0.5 - 0.5 - 1.0 - 3.0 ns Internal Register and Combinatorial Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 2.5 - 2.5 - 1.5 - 2.5 - 3.5 - ns THI Register hold time 1.0 - 1.0 - 3.0 - 3.5 - 4.5 - ns TCOI Register clock to output valid time - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 ns TAOI Register async. S/R to output delay - 6.0 - 6.0 - 6.5 - 7.0 - 8.0 ns TRAI Register async. S/R recover before clock 5.0 - 5.0 - 7.5 - 10.0 - 10.0 - ns TLOGI Internal logic delay - 1.0 - 1.0 - 2.0 - 2.5 - 3.0 ns TLOGILP Internal low power logic delay - 9.0 - 9.0 - 10.0 - 11.0 - 11.5 ns - 6.0 - 6.0 - 8.0 - 9.5 - 11.0 ns TPTA(1) Incremental product term allocator delay - 0.8 - 0.8 - 1.0 - 1.0 - 1.0 ns TSLEW - 3.5 - 3.5 - 4.0 - 4.5 - 5.0 ns Feedback Delays TF FastCONNECT feedback delay Time Adders Slew-rate limited delay Notes: 1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet. DS064 (v6.3) April 3, 2006 Product Specification www.xilinx.com 5 R XC9536 In-System Programmable CPLD XC9536 I/O Pins Function BSca n Function BSca n Block Macroce ll PC44 VQ44 CS48 Order Block Macroce ll PC44 VQ44 CS48 Order 1 1 2 40 D6 105 2 1 1 39 D7 51 1 2 3 41 C7 102 2 2 44 38 E5 48 1 3 5[1] 43[1] B7[1] 99 2 3 42[1] 36[1] E6[1] 45 1 4 4 42 C6 96 2 4 43 37 E7 42 5 6[1] 44[1] B6[1] 5 40[1] 34[1] F6[1] 39 33[1] G7[1] 36 1 93 2 6 8 2 A6 90 2 6 39[1] 1 7 7[1] 1[1] A7[1] 87 2 7 38 32 G6 33 1 8 9 3 C5 84 2 8 37 31 F5 30 1 9 11 5 B5 81 2 9 36 30 G5 27 1 10 12 6 A4 78 2 10 35 29 F4 24 1 11 13 7 B4 75 2 11 34 28 G4 21 1 12 14 8 A3 72 2 12 33 27 E3 18 1 13 18 12 B2 69 2 13 29 23 F2 15 1 14 19 13 B1 66 2 14 28 22 G1 12 1 15 20 14 C2 63 2 15 27 21 F1 9 1 16 22 16 C3 60 2 16 26 20 E2 6 1 17 24 18 D2 57 2 17 25 19 E1 3 1 18 - - - 54 2 18 - - - 0 1 Notes: : 1. Global control pin. XC9536 Global, JTAG and Power Pins 6 Pin Type PC44 VQ44 CS48 I/O/GCK1 5 43 B7 I/O/GCK2 6 44 B6 I/O/GCK3 7 1 A7 I/O/GTS1 42 36 E6 I/O/GTS2 40 34 F6 I/O/GSR 39 33 G7 TCK 17 11 A1 TDI 15 9 B3 TDO 30 24 G2 TMS 16 10 A2 VCCINT 5V 21, 41 15, 35 C1,F7 VCCIO 3.3V/5V 32 26 G3 GND 23, 10, 31 17, 4, 25 A5, D1, F3 No Connects -- -- C4, D3, D4, E4 www.xilinx.com DS064 (v6.3) April 3, 2006 Product Specification R XC9536 In-System Programmable CPLD Device Part Marking and Ordering Combination Information R XC95xxx TQ144 Device Type Package This line not related to device part number 7C Speed Operating Range 1 Sample package with part marking. Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line: * * * * Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxx. Line 2 = Not related to device part number. Line 3 = Not related to device part number. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package code: C1 = CS48. Device Ordering and Part Marking Number XC9536-5PC44C XC9536-5PCG44C XC9536-5VQ44C XC9536-5VQG44C XC9536-5CS48C XC9536-5CSG48C XC9536-6PC44C XC9536-6PCG44C XC9536-6VQ44C XC9536-6VQG44C XC9536-7PC44C XC9536-7PCG44C XC9536-7VQ44C XC9536-7VQG44C XC9536-7CS48C XC9536-7CSG48C XC9536-7PC44I XC9536-7PCG44I XC9536-7VQ44I XC9536-7VQG44I XC9536-10PC44C XC9536-10PCG44C XC9536-10VQ44C DS064 (v6.3) April 3, 2006 Product Specification Speed (pin-to-pin delay) 5 ns 5 ns 5 ns 5 ns 5 ns 5 ns 6 ns 6 ns 6 ns 6 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns Pkg. Symbol PC44 PCG44 VQ44 VQG44 CS48 CSG48 PC44 PCG44 VQ44 VQG44 PC44 PCG44 VQ44 VQG44 CS48 CSG48 PC44 PCG44 VQ44 VQG44 PC44 PCG44 VQ44 No. of Pins 44-pin 44-pin 44-pin 44-pin 48-ball 48-ball 44-pin 44-pin 44-pin 44-pin 44-pin 44-pin 44-pin 44-pin 48-ball 48-ball 44-pin 44-pin 44-pin 44-pin 44-pin 44-pin 44-pin Package Type Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Chip Scale Package (CSP) Chip Scale Package (CSP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Chip Scale Package (CSP) Chip Scale Package (CSP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Very Thin Quad Flat Pack (VQFP) www.xilinx.com Operating Range(1) C C C C C C C C C C C C C C C C I I I I C C C 7 R XC9536 In-System Programmable CPLD Device Ordering and Part Marking Number XC9536-10VQG44C XC9536-10CS48C XC9536-10CSG48C XC9536-10PC44I XC9536-10PCG44I XC9536-10VQ44I XC9536-10VQG44I XC9536-10CS48I XC9536-10CSG48I XC9536-15PC44C XC9536-15PCG44C XC9536-15VQ44C XC9536-15VQG44C XC9536-15PC44I XC9536-15PCG44I XC9536-15VQ44I XC9536-15VQG44I Speed (pin-to-pin delay) 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns Pkg. Symbol VQG44 CS48 CSG48 PC44 PCG44 VQ44 VQG44 CS48 CSG48 PC44 PCG44 VQ44 VQG44 PC44 PCG44 VQ44 VQG44 No. of Pins 44-pin 48-ball 48-ball 44-pin 44-pin 44-pin 44-pin 48-ball 48-ball 44-pin 44-pin 44-pin 44-pin 44-pin 44-pin 44-pin 44-pin Package Type Very Thin Quad Flat Pack (VQFP); Pb-Free Chip Scale Package (CSP) Chip Scale Package (CSP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Chip Scale Package (CSP) Chip Scale Package (CSP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Operating Range(1) C C C I I I I I I C C C C I I I I Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = -40 to +85C. Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Revision History The following table shows the revision history for this document. 8 Date Version Revision 12/04/98 5.0 Revised datga sheet to remove PCI compliancy statement and remove TLF. 06/18/03 6.0 Updated format. 08/21/03 6.1 Updated Package Device Marking Pin 1 orientation. 04/15/05 6.2 Added Asynchronous Preset Reset Pulse Width Specification (TAPRPW) 04/03/06 6.3 Added Warranty Disclaimer. Added Pb-Free package ordering information. www.xilinx.com DS064 (v6.3) April 3, 2006 Product Specification