DS064 (v6.3) April 3, 2006 www.xilinx.com 1
Product Specification
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• 5 ns pin-to-pin logic delays on all pins
•f
CNT to 100 MHz
• 36 macrocells with 800 usable gates
• Up to 34 user I/O pins
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design
protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 44-pin PLCC, 44-pin VQFP, 48-pin CSP
packages
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architecture
overview.
Power Management
Power dissipation can be reduced in the XC9536 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9536 device.
0
XC9536 In-System
Programmable CPLD
DS064 (v6.3) April 3, 2006 05Product Specification
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Figure 1:
Typical ICC vs. Frequency for XC9536
Clock Frequency (MHz)
Typical ICC (mA)
050
(50)
(30)
(83)
(50)
100
High Performance
Low Power
DS064_01_110101
XC9536 In-System Programmable CPLD
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Product Specification
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Figure 2:
XC9536 Architecture
Function block outputs (indicated by the bold line) drive the I/O blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
DS064_02_110101
1
Function
Block 2
36
18
18
Fast CONNECT II Switch Matrix
XC9536 In-System Programmable CPLD
DS064 (v6.3) April 3, 2006 www.xilinx.com 3
Product Specification
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Absolute Maximum Ratings
Recommended Operation Conditions
Quality and Reliability Characteristics
DC Characteristic Over Recommended Operating Conditions
Symbol Description Value Units
VCC Supply voltage relative to GND –0.5 to 7.0 V
VIN Input voltage relative to GND –0.5 to VCC + 0.5 V
VTS Voltage applied to 3-state output –0.5 to VCC + 0.5 V
TSTG Storage temperature (ambient) –65 to +150 oC
TJJunction temperature +150 oC
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Parameter Min Max Units
VCCINT Supply voltage for internal logic
and input buffers
Commercial TA = 0oC to 70oC 4.75 5.25 V
Industrial TA = –40oC to +85oC4.5 5.5
VCCIO Supply voltage for output drivers
for 5V operation
Commercial TA = 0oC to 70oC 4.75 5.25 V
Industrial TA = –40oC to +85oC4.5 5.5
Supply voltage for output drivers for 3.3V operation 3.0 3.6
VIL Low-level input voltage 0 0.80 V
VIH High-level input voltage 2.0 VCCINT + 0.5 V
VOOutput voltage 0 VCCIO V
Symbol Parameter Min Max Units
TDR Data Retention 20 - Years
NPE Program/Erase Cycles (Endurance) 10,000 - Cycles
Symbol Parameter Test Conditions Min Max Units
VOH Output high voltage for 5V outputs IOH = –4.0 mA, VCC = Min 2.4 - V
Output high voltage for 3.3V outputs IOH = –3.2 mA, VCC = Min 2.4 - V
VOL Output low voltage for 5V outputs IOL = 24 mA, VCC = Min - 0.5 V
Output low voltage for 3.3V outputs IOL = 10 mA, VCC = Min - 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCC
-±10μA
IIH I/O high-Z leakage current VCC = Max
VIN = GND or VCC
-±10μA
CIN I/O capacitance VIN = GND
f = 1.0 MHz
-10pF
ICC Operating supply current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
30 (Typical) mA
XC9536 In-System Programmable CPLD
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Product Specification
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AC Characteristics
Symbol Parameter
XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15
UnitsMin Max Min Max Min Max Min Max Min Max
TPD I/O to output valid - 5.0 - 6.0 - 7.5 - 10.0 - 15.0 ns
TSU I/O setup time before GCK 3.5 - 3.5 - 4.5 - 6.0 - 8.0 - ns
THI/O hold time after GCK 0 - 0 - 0 - 0 - 0 - ns
TCO GCK to output valid - 4.0 - 4.0 - 4.5 - 6.0 - 8.0 ns
fCNT(1) 16-bit counter frequency 100.0 - 100.0 - 125.0 - 111.1 - 95.2 - MHz
fSYSTEM(2) Multiple FB internal operating
frequency
100.0 - 100.0 - 83.3 - 66.7 - 55.6 - MHz
TPSU I/O setup time before p-term
clock input
0.5 - 0.5 - 0.5 - 2.0 - 4.0 - ns
TPH I/O hold time after p-term clock
input
3.0 - 3.0 - 4.0 - 4.0 - 4.0 - ns
TPCO P-term clock output valid - 7.0 - 7.0 - 8.5 - 10.0 - 12.0 ns
TOE GTS to output valid - 5.0 - 5.0 - 5.5 - 6.0 - 11.0 ns
TOD GTS to output disable - 5.0 - 5.0 - 5.5 - 6.0 - 11.0 ns
TPOE Product term OE to output
enabled
- 9.0 - 9.0 - 9.5 - 10.0 - 14.0 ns
TPOD Product term OE to output
disabled
- 9.0 - 9.0 - 9.5 - 10.0 - 14.0 ns
TWLH GCK pulse width (High or Low) 4.0 - 4.0 - 4.0 - 4.5 - 5.5 - ns
TAPRPW Asynchronous preset/reset
pulse width (High or Low)
7.0 - 7.0 - 7.0 - 7.5 - 8.0 - ns
Notes:
1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
Figure 3:
AC Load Circuit
Device Output
Output Type VTEST
5.0V
3.3V
VTEST
R1
160Ω
260Ω
R1
R2CL
R2
120Ω
360Ω
CL
35 pF
35 pF
DS067_03_110101
VCCIO
5.0V
3.3V
XC9536 In-System Programmable CPLD
DS064 (v6.3) April 3, 2006 www.xilinx.com 5
Product Specification
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Internal Timing Parameters
Symbol Parameter
XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15
UnitsMinMaxMinMaxMinMaxMinMaxMinMax
Buffer Delays
TIN Input buffer delay - 1.5 - 1.5 - 2.5 - 3.5 - 4.5 ns
TGCK GCK buffer delay - 1.5 - 1.5 - 1.5 - 2.5 - 3.0 ns
TGSR GSR buffer delay - 4.0 - 4.0 - 4.5 - 6.0 - 7.5 ns
TGTS GTS buffer delay - 5.0 - 5.0 - 5.5 - 6.0 - 11.0 ns
TOUT Output buffer delay - 2.0 - 2.0 - 2.5 - 3.0 - 4.5 ns
TEN Output buffer enable/disable delay - 0 - 0 - 0 - 0 - 0 ns
Product Term Control Delays
TPTCK Product term clock delay - 3.0 - 3.0 - 3.0 - 3.0 - 2.5 ns
TPTSR Product term set/reset delay - 1.0 - 1.0 - 2.0 - 2.5 - 3.0 ns
TPTTS Product term 3-state delay - 5.5 - 5.5 - 4.5 - 3.5 - 5.0 ns
Internal Register and Combinatorial Delays
TPDI Combinatorial logic propagation delay - 0.5 - 0.5 - 0.5 - 1.0 - 3.0 ns
TSUI Register setup time 2.5 - 2.5 - 1.5 - 2.5 - 3.5 - ns
THI Register hold time 1.0 - 1.0 - 3.0 - 3.5 - 4.5 - ns
TCOI Register clock to output valid time - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 ns
TAOI Register async. S/R to output delay - 6.0 - 6.0 - 6.5 - 7.0 - 8.0 ns
TRAI Register async. S/R recover before
clock
5.0 - 5.0 - 7.5 - 10.0 - 10.0 - ns
TLOGI Internal logic delay - 1.0 - 1.0 - 2.0 - 2.5 - 3.0 ns
TLOGILP Internal low power logic delay - 9.0 - 9.0 - 10.0 - 11.0 - 11.5 ns
Feedback Delays
TFFastCONNECT feedback delay - 6.0 - 6.0 - 8.0 - 9.5 - 11.0 ns
Time Adders
TPTA(1) Incremental product term allocator
delay
- 0.8 - 0.8 - 1.0 - 1.0 - 1.0 ns
TSLEW Slew-rate limited delay - 3.5 - 3.5 - 4.0 - 4.5 - 5.0 ns
Notes:
1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet.
XC9536 In-System Programmable CPLD
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Product Specification
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XC9536 I/O Pins
XC9536 Global, JTAG and Power Pins
Function
Block
Macroce
ll PC44 VQ44 CS48
BSca
n
Order
Function
Block
Macroce
ll PC44 VQ44 CS48
BSca
n
Order
1 1 2 40 D6 105 2 1 1 39 D7 51
1 2 3 41 C7 102 2 2 44 38 E5 48
1 3 5[1] 43[1] B7[1] 99 2 3 42[1] 36[1] E6[1] 45
1 4 4 42 C6 96 2 4 43 37 E7 42
1 5 6[1] 44[1] B6[1] 93 2 5 40[1] 34[1] F6[1] 39
1 6 8 2A690 2 6 39
[1] 33[1] G7[1] 36
1 7 7[1] 1[1] A7[1] 87 2 7 38 32 G6 33
1 8 9 3C584 2 8 3731F530
1 9 11 5B581 2 9 3630G527
110 12 6 A4 78 2 10 35 29 F4 24
111 13 7 B4 75 2 11 34 28 G4 21
112 14 8 A3 72 2 12 33 27 E3 18
113 18 12 B2 69 2 13 29 23 F2 15
114 19 13 B1 66 2 14 28 22 G1 12
115 20 14 C2 63 2 15 27 21 F1 9
116 22 16 C3 60 2 16 26 20 E2 6
117 24 18 D2 57 2 17 25 19 E1 3
118––-54 218---0
Notes: :
1. Global control pin.
Pin Type PC44 VQ44 CS48
I/O/GCK1 5 43 B7
I/O/GCK2 6 44 B6
I/O/GCK3 7 1 A7
I/O/GTS1 42 36 E6
I/O/GTS2 40 34 F6
I/O/GSR 39 33 G7
TCK 17 11 A1
TDI 15 9 B3
TDO 30 24 G2
TMS 16 10 A2
VCCINT 5V 21, 41 15, 35 C1,F7
VCCIO 3.3V/5V 32 26 G3
GND 23, 10, 31 17, 4, 25 A5, D1, F3
No Connects — — C4, D3, D4, E4
XC9536 In-System Programmable CPLD
DS064 (v6.3) April 3, 2006 www.xilinx.com 7
Product Specification
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Device Part Marking and Ordering Combination Information
Device Ordering and
Part Marking Number
Speed
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins Package Type
Operating
Range(1)
XC9536-5PC44C 5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9536-5PCG44C 5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9536-5VQ44C 5 ns VQ44 44-pin Very Thin Quad Flat Pack (VQFP) C
XC9536-5VQG44C 5 ns VQG44 44-pin Very Thin Quad Flat Pack (VQFP); Pb-Free C
XC9536-5CS48C 5 ns CS48 48-ball Chip Scale Package (CSP) C
XC9536-5CSG48C 5 ns CSG48 48-ball Chip Scale Package (CSP); Pb-Free C
XC9536-6PC44C 6 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9536-6PCG44C 6 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9536-6VQ44C 6 ns VQ44 44-pin Very Thin Quad Flat Pack (VQFP) C
XC9536-6VQG44C 6 ns VQG44 44-pin Very Thin Quad Flat Pack (VQFP); Pb-Free C
XC9536-7PC44C 7.5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9536-7PCG44C 7.5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9536-7VQ44C 7.5 ns VQ44 44-pin Very Thin Quad Flat Pack (VQFP) C
XC9536-7VQG44C 7.5 ns VQG44 44-pin Very Thin Quad Flat Pack (VQFP); Pb-Free C
XC9536-7CS48C 7.5 ns CS48 48-ball Chip Scale Package (CSP) C
XC9536-7CSG48C 7.5 ns CSG48 48-ball Chip Scale Package (CSP); Pb-Free C
XC9536-7PC44I 7.5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) I
XC9536-7PCG44I 7.5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC9536-7VQ44I 7.5 ns VQ44 44-pin Very Thin Quad Flat Pack (VQFP) I
XC9536-7VQG44I 7.5 ns VQG44 44-pin Very Thin Quad Flat Pack (VQFP); Pb-Free I
XC9536-10PC44C 10 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9536-10PCG44C 10 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9536-10VQ44C 10 ns VQ44 44-pin Very Thin Quad Flat Pack (VQFP) C
XC95xxx
TQ144
7C
De vice Type
Package
Speed
Operating Range
This line not
related to device
part number
Sample package with part marking.
R
1
Notes:
1. Due to the small size of chip scale packages, part marking on these packages does not follow the above
sample and the complete part number cannot be included in the marking. Part marking on chip scale
packages by line:
· Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxx.
· Line 2 = Not related to device part number.
· Line 3 = Not related to device part number.
· Line 4 = Package code, speed, operating temperature, three digits not related to device
part number. Package code: C1 = CS48.
XC9536 In-System Programmable CPLD
8www.xilinx.com DS064 (v6.3) April 3, 2006
Product Specification
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Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Revision History
The following table shows the revision history for this document.
XC9536-10VQG44C 10 ns VQG44 44-pin Very Thin Quad Flat Pack (VQFP); Pb-Free C
XC9536-10CS48C 10 ns CS48 48-ball Chip Scale Package (CSP) C
XC9536-10CSG48C 10 ns CSG48 48-ball Chip Scale Package (CSP); Pb-Free C
XC9536-10PC44I 10 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) I
XC9536-10PCG44I 10 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC9536-10VQ44I 10 ns VQ44 44-pin Very Thin Quad Flat Pack (VQFP) I
XC9536-10VQG44I 10 ns VQG44 44-pin Very Thin Quad Flat Pack (VQFP); Pb-Free I
XC9536-10CS48I 10 ns CS48 48-ball Chip Scale Package (CSP) I
XC9536-10CSG48I 10 ns CSG48 48-ball Chip Scale Package (CSP); Pb-Free I
XC9536-15PC44C 15 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9536-15PCG44C 15 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9536-15VQ44C 15 ns VQ44 44-pin Very Thin Quad Flat Pack (VQFP) C
XC9536-15VQG44C 15 ns VQG44 44-pin Very Thin Quad Flat Pack (VQFP); Pb-Free C
XC9536-15PC44I 15 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) I
XC9536-15PCG44I 15 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC9536-15VQ44I 15 ns VQ44 44-pin Very Thin Quad Flat Pack (VQFP) I
XC9536-15VQG44I 15 ns VQG44 44-pin Very Thin Quad Flat Pack (VQFP); Pb-Free I
Notes:
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C.
Date Version Revision
12/04/98 5.0 Revised datga sheet to remove PCI compliancy statement and remove TLF
.
06/18/03 6.0 Updated format.
08/21/03 6.1 Updated Package Device Marking Pin 1 orientation.
04/15/05 6.2 Added Asynchronous Preset Reset Pulse Width Specification (TAPRPW)
04/03/06 6.3 Added Warranty Disclaimer. Added Pb-Free package ordering information.
Device Ordering and
Part Marking Number
Speed
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins Package Type
Operating
Range(1)
