Order this document by MPC2510/D SEMICONDUCTOR TECHNICAL DATA The MPC2510 is a 3.3V compatible, PLL based zero delay buffer targeted for high performance clock tree designs. With 11 outputs at frequencies of up to 125MHz and output skews of 200ps the MPC2510 is ideal for the most demanding clock tree designs. The device employs a fully differential PLL design to minimize cycle-to-cycle and phase jitter. The device is compliant to the 1.2 revision of the PC100 design document. * * * * * * LOW VOLTAGE PLL ZERO DELAY BUFFER Fully Integrated PLL Output Frequency up to 125MHz in PLL Mode Outputs Disable to a Logic Low TQFP Packaging 50ps Cycle-to-Cycle Jitter On Board Series Damping Resistors The analog VCC pin of the device also serves as a PLL bypass select pin. When driven low the AVCC pin will route the REF_CLK input around the PLL directly to the outputs. The OE input is a logic enable for all of the outputs except QFB. A low on the OE pin forces Q0-Q9 to a logic low state. DT SUFFIX 24-LEAD TSSOP PACKAGE CASE 948H-01 The MPC2510 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the ability to drive terminated 50 transmission lines. The output impedance of the MPC2510 is 40W with IV curves that are PC100 Rev 1.2 compliant. The device is packaged in a 24-lead TSSOP package to provide the optimum combination of board density and performance. OE Q0 REF_CLK PLL Q9 FB_CLK QFB AVCC Figure 1. Block Diagram This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 11/98 Motorola, Inc. 1998 1 REV 0 MPC2510 AGND REF_CLK VCC FUNCTION TABLES AVCC AVCC Q0 VCC 1 0 Q1 Q9 Q2 Q8 OE MPC2510 GND GND 1 0 GND Function PLL Enabled PLL Bypass Function Q0 - Q9 Enabled Q0 - Q9 Low GND Q3 Q7 Q4 Q6 VCC Q5 OE VCC QFB FB_CLK Figure 2. 24-Lead Pinout (Top View) ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit VCC Supply Voltage -0.3 4.6 V VI Input Voltage -0.3 VDD + 0.3 V IIN Input Current 20 mA TStor Storage Temperature Range 125 C -40 * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. MOTOROLA 2 ECLinPS and ECLinPS Lite DL140 -- Rev 3 MPC2510 DC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%) Symbol Characteristic Min Typ Max Unit 3.6 V 0.8 V 2.0 Condition VIH Input HIGH Voltage LVCMOS Inputs VIL Input LOW Voltage LVCMOS Inputs VOH Output HIGH Voltage V IOH = -6mA, Note 1. VOL Output LOW Voltage 0.55 V IOL = 6mA, Note 1. IIN Input Current 120 A CIN Input Capacitance 4 pF Cpd Power Dissipation Capacitance ICC Maximum Quiescent Supply Current 2.4 40 ICCPLL Maximum PLL Supply Current 15 1. The MPC953 outputs can drive series terminated 50 transmission lines on the incident edge. pF Per Output mA All VCC Pins mA VCCA Pin Only PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70C) Symbol Characteristic Min Max Unit fref Reference Input Frequency 66.66 125 MHz frefDC Reference Input Duty Cycle 25 75 % Condition AC CHARACTERISTICS (TA = 0C to 70C, VCC = 3.3V 5%) Symbol Characteristic Min Typ Unit 1.0 ns 55 % tr, tf Output Rise/Fall Time tpw Output Duty Cycle tsk(O) Output-to-Output Skews fmax Maximum Output Frequency tpd(lock) Input to Ext_FB Delay (with PLL Locked) (Including Jitter) tPLZ,HZ Output Disable Time 7 ns tPZL Output Enable Time 7 ns tjitter Cycle-to-Cycle Jitter (Peak-to-Peak) 50 ps tlock Maximum PLL Lock Time ECLinPS and ECLinPS Lite DL140 -- Rev 3 0.10 Max 45 PLL Mode 50 66.66 X-150 X 200 ps 125 MHz X+150 ps 10 3 Condition 0.8 to 2.0V fref = 100MHz ms MOTOROLA MPC2510 capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. It is recommended that the user start with an 8-10 resistor to avoid potential VCC drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed. Power Supply Filtering The MPC2510 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC2510 provides separate power supplies for the output buffers (VCCO) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC2510. 3.3V RS=5-15 VCCA 22F MPC2510 Figure 3 illustrates a typical power supply filter scheme. The MPC2510 is most susceptible to noise with spectral content in the 1KHz to 10MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC2510. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 3 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual MOTOROLA 0.01F VCC 0.01F Figure 3. Power Supply Filter Although the MPC2510 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. 4 ECLinPS and ECLinPS Lite DL140 -- Rev 3 MPC2510 OUTLINE DIMENSIONS DT SUFFIX TSSOP PACKAGE CASE 948H-01 ISSUE O 24X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S 2X 24 L/2 B -U- L PIN 1 IDENT. 12 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. 13 S A -V- DIM A B C D F G H J J1 K K1 L M C 0.10 (0.004) -T- SEATING PLANE G D H -W- MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ DETAIL E N 0.25 (0.010) K EE CC CC EE K1 J1 M N F SECTION N-N DETAIL E J ECLinPS and ECLinPS Lite DL140 -- Rev 3 5 MOTOROLA MPC2510 Motorola reserves the right to make changes without further notice to any products herein. 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