SEMICONDUCTOR TECHNICAL DATA Order this document
by MPC2510/D
1REV 0
Motorola, Inc. 1998
11/98
The MPC2510 is a 3.3V compatible, PLL based zero delay buffer
targeted for high performance clock tree designs. With 11 outputs at
frequencies of up to 125MHz and output skews of 200ps the MPC2510 is
ideal for the most demanding clock tree designs. The device employs a
fully differential PLL design to minimize cycle–to–cycle and phase jitter.
The device is compliant to the 1.2 revision of the PC100 design
document.
•Fully Integrated PLL
•Output Frequency up to 125MHz in PLL Mode
•Outputs Disable to a Logic Low
•TQFP Packaging
•50ps Cycle–to–Cycle Jitter
•On Board Series Damping Resistors
The analog VCC pin of the device also serves as a PLL bypass select
pin. When driven low the AVCC pin will route the REF_CLK input around
the PLL directly to the outputs. The OE input is a logic enable for all of the
outputs except QFB. A low on the OE pin forces Q0–Q9 to a logic low
state.
The MPC2510 is fully 3.3V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the
ability to drive terminated 50Ω transmission lines. The output impedance
of the MPC2510 is
40
W
with IV curves that are PC100 Rev 1.2
compliant. The device is packaged in a 24–lead TSSOP package to
provide the optimum combination of board density and performance.
Figure 1. Block Diagram
REF_CLK
FB_CLK
PLL
AVCC
Q0
Q9
QFB
OE
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
LOW VOLTAGE
PLL ZERO DELAY BUFFER
DT SUFFIX
24–LEAD TSSOP PACKAGE
CASE 948H–01
MPC2510
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
2
AGND
VCC
Q0
Q1
Q2
GND
Q3
REF_CLK
AVCC
VCC
Q9
Q8
GND
MPC2510
FUNCTION TABLES
AVCC Function
1
0PLL Enabled
PLL Bypass
OE Function
1
0Q0 – Q9 Enabled
Q0 – Q9 Low
Figure 2. 24–Lead Pinout (Top View)
Q4
VCC
QFB
Q6
Q5
GND GND
Q7
OE VCC
FB_CLK
ABSOLUTE MAXIMUM RATINGS*
Symbol Parameter Min Max Unit
VCC Supply Voltage –0.3 4.6 V
VIInput Voltage –0.3 VDD + 0.3 V
IIN Input Current ±20 mA
TStor Storage Temperature Range –40 125 °C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
MPC2510
ECLinPS and ECLinPS Lite
DL140 — Rev 3 3 MOTOROLA
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol Characteristic Min Typ Max Unit Condition
VIH Input HIGH Voltage LVCMOS Inputs 2.0 3.6 V
VIL Input LOW Voltage LVCMOS Inputs 0.8 V
VOH Output HIGH Voltage 2.4 V IOH = –6mA, Note 1.
VOL Output LOW Voltage 0.55 V IOL = 6mA, Note 1.
IIN Input Current ±120 µA
CIN Input Capacitance 4 pF
Cpd Power Dissipation Capacitance pF Per Output
ICC Maximum Quiescent Supply Current 40 mA All VCC Pins
ICCPLL Maximum PLL Supply Current 15 mA VCCA Pin Only
1. The MPC953 outputs can drive series terminated 50Ω transmission lines on the incident edge.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol Characteristic Min Max Unit Condition
fref Reference Input Frequency 66.66 125 MHz
frefDC Reference Input Duty Cycle 25 75 %
AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)
Symbol Characteristic Min Typ Max Unit Condition
tr, tfOutput Rise/Fall Time 0.10 1.0 ns 0.8 to 2.0V
tpw Output Duty Cycle 45 50 55 %
tsk(O) Output–to–Output Skews 200 ps
fmax Maximum Output Frequency PLL Mode 66.66 125 MHz
tpd(lock) Input to Ext_FB Delay (with PLL Locked)
(Including Jitter) X–150 X X+150 ps fref = 100MHz
tPLZ,HZ Output Disable T ime 7 ns
tPZL Output Enable T ime 7 ns
tjitter Cycle–to–Cycle Jitter (Peak–to–Peak) 50 ps
tlock Maximum PLL Lock T ime 10 ms
MPC2510
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
4
Power Supply Filtering
The MPC2510 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC2510 provides separate
power supplies for the output buffers (VCCO) and the
phase–locked loop (VCCA) of the device. The purpose of this
design technique is to try and isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC2510.
Figure 3 illustrates a typical power supply filter scheme.
The MPC2510 is most susceptible to noise with spectral
content in the 1KHz to 10MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC2510. From the data sheet the IVCCA current
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 3 must have a resistance of 10–15Ω to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. It is recommended that the user start
with an 8–10Ω resistor to avoid potential VCC drop problems
and only move to the higher value resistors when a higher
level of attenuation is shown to be needed.
Figure 3. Power Supply Filter
VCCA
VCC
MPC2510 0.01
µ
F22
µ
F
0.01
µ
F
3.3V
RS=5–15
Ω
Although the MPC2510 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
MPC2510
ECLinPS and ECLinPS Lite
DL140 — Rev 3 5 MOTOROLA
OUTLINE DIMENSIONS
DT SUFFIX
TSSOP PACKAGE
CASE 948H–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A7.70 7.90 0.303 0.311
B4.30 4.50 0.169 0.177
C––– 1.20 ––– 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L–U–
SEATING
PLANE
0.10 (0.004)
–T–
ÇÇ
ÇÇ
SECTION N–N
DETAIL E
J
J1
K
K1
ÉÉ
ÉÉ
DETAIL E
F
M
–W–
0.25 (0.010)
13
24
12
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
–V–
24X REFK
N
N
MPC2510
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
6
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MPC2510/D
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