TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 LOW-VOLTAGE I/O TOUCH SCREEN CONTROLLER Check for Samples: TSC2046E-Q1 FEATURES APPLICATIONS * * * * * * * * * * * * 1 234 * Qualified for Automotive Applications Same Pinout as ADS7846 2.2-V to 5.25-V Operation 1.5-V to 5.25-V Digital I/O Internal 2.5-V Reference Direct Battery Measurement (0 V to 6 V) On-Chip Temperature Measurement Touch-Pressure Measurement QSPITM and SPITM 3-Wire Interface Auto Power-Down Exceeds IEC 61000-4-2 ESD Requirements - 15kV Contact Discharge - No External Components Needed Available In a TSSOP-16 (PW) Package Touch Screen Monitors PW PACKAGE (TOP VIEW) +VCC X+ Y+ X- Y- GND VBAT AUX 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DCLK CS DIN BUSY DOUT PENIRQ IOVDD VREF DESCRIPTION The TSC2046E is the next-generation version of the ADS7846 4-wire touch screen controller, supporting a low-voltage I/O interface from 1.5 V to 5.25 V. The TSC2046E is 100% pin-compatible with the existing ADS7846, and drops into the same socket. This design allows for an easy upgrade of current applications to the new version. The TSC2046E also has an on-chip 2.5-V reference that can be used for the auxiliary input, battery monitor, and temperature measurement modes. The reference can also be powered down when not used to conserve power. The internal reference operates down to a supply voltage of 2.7 V, while monitoring the battery voltage from 0 V to 6 V. The low power consumption of less than 0.75 mW (typ) at 2.7 V (reference off), high-speed (up to 125-kHz sample rate), and on-chip drivers make the TSC2046E an ideal choice for battery-operated systems such as personal digital assistants (PDAs) with resistive touch screens, pagers, cellular phones, and other portable equipment. The TSC2046E is available in a TSSOP-16 package and is specified over the -40C to +125C temperature range. ORDERING INFORMATION (1) TA -40C to 125C (1) PACKAGE TSSOP - PW Reel of 2000 ORDERABLE PART NUMBER TSC2046EQPWRQ1 TOP-SIDE MARKING T2046EQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. QSPI, SPI are trademarks of Motorola Inc. Microwire is a trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010, Texas Instruments Incorporated TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PENIRQ P e n D e tec t +VCC X+ T e m pe ra ture X- SAR Se n sor IOVDD Y+ DOUT TSC2046E Y- BUSY Comparator 6-Channel MUX Serial Data In/Out CDAC DCLK Battery Monitor VBAT CS DIN AUX Internal 2.5V Reference VRE F TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION +VCC 1 Power supply X+ 2 X+ position input Y+ 3 Y+ position input X- 4 X- position input Y- 5 Y- position input GND 6 Ground VBAT 7 Battery monitor input AUX 8 Auxiliary input to ADC VREF 9 Voltage reference input/output IOVDD 10 Digital I/O power supply PENIRQ 11 Pen interrupt DOUT 12 Serial data output. Data are shifted on the falling edge of DCLK. This output is high impedance when CS is high. BUSY 13 Busy output. This output is high impedance when CS is high. DIN 14 Serial data input. If CS is low, data sre latched on the rising edge of DCLK. CS 15 Chip select input. Controls conversion timing and enables the serial input/output register. CS high = power-down mode (ADC only). DCLK 16 External clock input. This clock runs the SAR conversion process and synchronizes serial data I/O. 2 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range +VCC, IOVDD -0.3 V to 6 V Digital inputs -0.3 V to +VCC + 0.3 V Analog inputs -0.3 V to +VCC + 0.3 V VI Input voltage range PD Power dissipation qJA Package thermal impedance, junction to free air TA Operating free-air temperature range TJ Maximum junction temperature Tstg Storage temperature range 250 mW 150C -65C to 150C IEC Contact Discharge (3) (1) (2) (3) 108.4C -40C to 125C X+, X-, Y+, Y- 15kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are referenced to GND. Test method based on IEC Std 61000-4-2. Contact Texas Instruments for test details. ELECTRICAL CHARACTERISTICS TA = -40C to 125C, +VCC = 2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 x fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD, +VCC IOVDD (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V Analog Input VI Full-scale input voltage span Positive Input-Negative Input 0 VREF Positive Input -0.2 +VCC + 0.2 Negative Input -0.2 +0.2 VI Absolute input voltage V Ci Capacitance 25 pF Ileak Leakage current 0.1 A 12 bits System Performance Resolution No missing codes 11 bits 2 LSB (1) Integral linearity error Offset error Gain error External VREF Vn Noise Including internal VREF, RMS PSRR Power-supply rejection ratio 6 LSB 4 LSB 70 V 70 dB Sampling Dynamics Conversion time 12 Acquisition time CLK cycles 3 Throughput rate 125 Multiplexer settling time CLK cycles kHz 500 ns Aperture delay 30 ns Aperture jitter 100 ns 100 dB 5 Channel-to-channel isolation VIN = 2.5 Vpp at 50 kHz Switch Drivers Y+, X+ on-resistance Y-, X- on-resistance Drive current (2) (1) (2) 6 Duration 100 ms 50 mA LSB = least significant bit. With VREF equal to 2.5 V, one LSB is 610 V. Specified by design. Exceeding 50-mA source current may result in device degradation. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 3 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = -40C to 125C, +VCC = 2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 x fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD, +VCC IOVDD (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.45 2.50 2.55 UNIT Reference Output Internal reference voltage Internal reference drift IQ Quiescent current PD1 = 1, PD0 = 0, SDA and SCL high V 15 ppm/ C 500 A Reference Input VI Input voltage Input impedance 1 SER/DFR = 0, PD1 = 0, Internal reference off +VCC 1 Internal reference on V G 250 Battery Monitor VI Input voltage ZI Input impedance Accuracy 0.5 Sampling battery 6 10 Battery monitor off V k 1 G VBAT = 0.5 V to 5.5 V, External VREF = 2.5 V -2 +2 VBAT = 0.5 V to 5.5 V, Internal reference -3 +3 -40 125 % Temperature Measurement Temperature range Resolution Accuracy Differential method (3) 1.6 TEMP0 (4) 0.3 Differential method (3) 2 TEMP0 (4) C C C 3 Digital Input/Output VIH High-level input voltage | IIH | 5 A 0.7 x IOVDD IOVDD + 0.3 V VIL Low-level input voltage | IIL | 5 A -0.3 0.3 x IOVDD V VOH High-level output voltage IOH = -250 A VOL Low-level output voltage IOL = 250 A Ci Input capacitance All digital control input pins 0.8 x IOVDD V 5 0.4 V 15 pF Power Supply Requirements +VCC Supply voltage (5) IOVDD Supply voltage (6) IQ Quiescent current Specified performance 2.7 3.6 Operating range 2.5 5.25 1.5 +VCC Internal reference off 280 Internal reference on 970 fSAMPLE = 12.5 kHz 220 Power-down mode, CS = DCLK = DIN = IOVDD PD Power dissipation 10 +VCC = 2.7 V V V 650 A 28 1.8 mW 125 C Temperature Range TA (3) (4) (5) (6) 4 Operating free-air temperature Specified performance -40 Difference between TEMP0 and TEMP1 measurement. No calibration necessary. Temperature drift is -2.1 mV/C.s TSC2046E operates down to 2.2V. IOVDD must be +VCC. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 TYPICAL CHARACTERISTICS At TA = +25C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, fCLK = 16 x fSAMPLE = 2MHz (unless otherwise noted) +VCC SUPPLY CURRENT vs TEMPERATURE IOVDD SUPPLY CURRENT vs TEMPERATURE 30 350 IOVDD Supply Current (A) +VCC Supply Current (A) 400 300 250 200 150 100 -40 -20 0 20 40 60 80 25 20 15 10 5 - 40 100 -20 Temperature (C) 0 20 40 60 80 100 4.5 5.0 4.5 5.0 Temperature (C) POWER-DOWN SUPPLY CURRENT vs TEMPERATURE +VCC SUPPLY CURRENT vs +VCC 140 450 400 +VCC Supply Current (A) Supply Current (nA) 120 100 80 60 fSAMPLE = 125kHz 350 300 250 200 f SAMPLE = 12.5kHz 150 100 40 -40 -20 0 20 40 60 80 100 2.0 2.5 3.0 Temperature (C) 3.5 4.0 +VCC (V) IOVDD SUPPLY CURRENT vs IOVDD MAXIMUM SAMPLE RATE vs +VCC 60 1M Sample Rate (Hz) IOVDD Supply Current (A) +VCC IOVDD 50 40 fSAMPLE = 125kHz 30 20 10 100k 10k fSAMPLE = 12.5kHz 0 1k 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 IOVDD (V) 2.5 3.0 3.5 4.0 +VCC (V) Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 5 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, fCLK = 16 x fSAMPLE = 2MHz (unless otherwise noted) CHANGE IN OFFSET vs TEMPERATURE 0.6 0.10 0.4 Delta from +25C (LSB) Delta from +25C (LSB) CHANGE IN GAIN vs TEMPERATURE 0.15 0.05 0 -0.05 -0.10 -0.15 - 40 -20 0 20 40 60 80 0.2 0 -0.2 -0.4 -0.6 - 40 100 - 20 0 Temperature (C) 40 60 80 100 REFERENCE CURRENT vs TEMPERATURE REFERENCE CURRENT vs SAMPLE RATE 14 18 12 16 Reference Current (A) Reference Current (A) 20 Temperature (C) 10 8 6 4 14 12 10 8 2 6 -40 0 0 25 50 75 100 125 -20 0 20 40 60 80 100 Temperature (C) Sample Rate (kHz) SWITCH ON-RESISTANCE vs TEMPERATURE (X+, Y+: +VCC to Pin; X-, Y-: Pin to GND) SWITCH ON- RESISTANCE vs +VCC (X+, Y+: +VCC to Pin; X-, Y-: Pin to GND) 8 8 Y- 7 7 6 6 RON () RON () Y- 5 X+, Y+ 5 X- 4 X- 3 X+, Y+ 4 2 1 3 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 -20 6 0 20 40 60 80 100 Temperature (C) +VCC (V) Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, fCLK = 16 x fSAMPLE = 2MHz (unless otherwise noted) MAXIMUM SAMPLING RATE vs RIN INTERNAL VREF vs TEMPERATURE 2.5080 INL: RIN = 500 INL: RIN = 2k DNL: RIN = 500 DNL: RIN = 2k 1.8 1.6 1.4 2.5075 2.5070 Internal VREF (V) Max Absolute Delta Error from RIN = 0 (LSB) 2.0 1.2 1.0 0.8 0.6 2.5065 2.5060 3.5055 2.5050 2.5045 0.4 2.5040 0.2 2.5035 2.5030 20 40 60 80 100 120 140 Sampling Rate (kHz) 160 180 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 0 200 Temperature (C) INTERNAL VREF vs TURN- ON TIME INTERNAL VREF vs +VCC 100 2.510 No Cap (42s) 12-Bit Settling 80 Internal VREF (%) Internal VREF (V) 2.505 2.500 2.495 2.490 1F Cap (124s) 12-Bit Settling 60 40 20 2.485 2.480 0 2.5 3.0 3.5 4.0 4.5 0 5.0 200 400 600 800 1000 1200 1400 Turn-On Time (s) +VCC (V) TEMP DIODE VOLTAGE vs TEMPERATURE TEMP0 DIODE VOLTAGE vs +VCC 850 604 750 90.1mV TEMP1 700 650 600 550 TEMP0 135.1mV 500 450 TEMP0 Diode Voltage (mV) TEMP Diode Voltage (mV) 800 602 600 598 596 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 594 2.7 3.0 3.3 +VCC (V) Temperature (C) Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 7 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, fCLK = 16 x fSAMPLE = 2MHz (unless otherwise noted) TEMP1 DIODE VOLTAGE vs +VCC TEMP1 Diode Voltage (mV) 720 718 716 714 712 710 2.7 3.0 3.3 +VCC (V) 8 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 THEORY OF OPERATION The TSC2046E is a classic successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on capacitive redistribution, which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6m CMOS process. The basic operation of the TSC2046E is shown in Figure 1. The device features an internal 2.5-V reference and an internal clock. Operation is maintained from a single supply of 2.7 V to 5.25 V. The internal reference can be overdriven with an external, low-impedance source between 2 V and +VCC. The value of the reference voltage directly sets the input range of the converter. The analog input (X-, Y-, and Z-position coordinates, auxiliary inputs, battery voltage, and chip temperature) to the converter is provided via a multiplexer. A unique configuration of low on-resistance switches allows an unselected ADC input channel to provide power and an accompanying pin to provide ground for an external device. By maintaining a differential input to the converter and a differential reference architecture, it is possible to negate the error from each touch panel driver switch on-resistance (if this is a source of error for the particular measurement). +2.7V to +5V 1F + to 10F (Optional) Touch Screen 0.1 F TSC2046E B1 +VCC DCLK A2 C1 +VCC CS A3 Serial/Conversion Clock Chip Select Serial Data In D1 X+ DIN A4 E1 Y+ BUSY A5 Converter Status G2 X- DOUT A6 Serial Data Out G3 Y- PENIRQ B7 Pen Interrupt To Battery Auxiliary Input Voltage Regulator G6 VBAT IOVDD C7 E7 AUX VREF D7 GND G4 G5 GND NOTE: VFBGA package and pin names shown. Figure 1. Basic Operation Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 9 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com Analog Input Figure 2 shows a block diagram of the input multiplexer on the TSC2046E, the differential input of the ADC, and the differential reference of the converter. Table 1 and Table 2 show the relationship between the A2, A1, A0, and SER/DFR control bits and the configuration of the TSC2046E. The control bits are provided serially via the DIN pin--see the Digital Interface section of this data sheet for more details. When the converter enters the Hold mode, the voltage difference between the +IN and -IN inputs (see Figure 2) is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25 pF). After the capacitor has been fully charged, there is no further input current. The amount of charge transfer from the analog source to the converter is a function of conversion rate. +VCC PENIRQ IOVDD Level Shifter TEMP1 50k or 90k VREF TEMP0 Logic A2- A0 (Shown 001B) SER/DFR (Shown Low) X+ X- Ref On/Off Y+ +IN Y- +REF ADC 2.5V Reference -IN -REF 7.5k VBAT 2.5k Battery On AUX GND Figure 2. Simplified Diagram of the Analog Input Table 1. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR High) A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 10 VBAT AUXIN Temp Y- X+ Y+ YPosition XPosition Z1Position Z2Position +IN (TEMP0) +IN Measure +IN +IN Measure +IN Measure +IN Measure +IN +IN (TEMP1) Submit Documentation Feedback XDrivers YDrivers Off Off Off On Off Off X-, On Y+, On X-, On Y+, On On Off Off Off Off Off Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 Table 2. Input Configuration (DIN), Differential Reference Mode (SER/DFR Low) A2 A1 A0 +REF -REF Y- X+ Y+ 0 0 1 Y+ Y- +IN 0 1 1 Y+ X- +IN 1 0 0 Y+ X- 1 0 1 X+ X- Y-Position X-Position Z1-Position Z2-Position Measure Y+, YMeasure +IN Y+, XMeasure +IN Drivers Measure Y+, XX+, X- Internal Reference The TSC2046E has an internal 2.5-V voltage reference that can be turned on or off with the power-down control bit, PD1 (see Table 5 and Figure 3). Typically, the internal reference voltage is only used in the single-ended mode for battery monitoring, temperature measurement, and for using the auxiliary input. Optimal touch screen performance is achieved when using the differential mode. The internal reference voltage of the TSC2046E must be commanded to be off to maintain compatibility with the ADS7843. Therefore, after power-up, a write of PD1 = 0 is required to ensure the reference is off (see the Typical Characteristics for power-up time of the reference from power-down). Reference Power-Down Band Gap VREF Buffer To CDAC Optional Figure 3. Simplified Diagram of the Internal Reference Reference Input The voltage difference between +REF and -REF (see Figure 2) sets the analog input range. The TSC2046E operates with a reference in the range of 1V to +VCC. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code (referred to as LSB size) is also reduced. The LSB (least significant bit) size is equal to the reference voltage divided by 4096 in 12-bit mode. Any offset or gain error inherent in the ADC appears to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, it is typically 5LSBs with a 1V reference. In each case, the actual offset of the device is the same, 1.22mV. With a lower reference voltage, more care must be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low-ripple) power supply, a low-noise reference (if an external reference is used), and a low-noise input signal. The voltage into the VREF input directly drives the capacitor digital-to-analog converter (CDAC) portion of the TSC2046E. Therefore, the input current is very low (typically less than 13A). There is also a critical item regarding the reference when making measurements while the switch drivers are ON. For this discussion, it is useful to consider the basic operation of the TSC2046E (see Figure 1). This particular application shows the device being used to digitize a resistive touch screen. A measurement of the current Y-Position of the pointing device is made by connecting the X+ input to the ADC, turning on the Y+ and Ydrivers, and digitizing the voltage on X+ (Figure 4 shows a block diagram). For this measurement, the resistance in the X+ lead does not affect the conversion (it does affect the settling time, but the resistance is usually small enough that this is not a concern). However, because the resistance between Y+ and Y- is fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it is not possible to achieve a 0V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 11 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com +VCC VREF Y+ X+ +IN +REF Converter -IN -REF Y- GND Figure 4. Simplified Diagram of Single-Ended Reference (SER/DFR High, Y Switches Enabled, X+ is Analog Input) This situation can be remedied as shown in Figure 5. By setting the SER/DFR bit low, the +REF and -REF inputs are connected directly to Y+ and Y-, respectively, making the analog-to-digital conversion ratiometric. The result of the conversion is always a percentage of the external resistance, regardless of how it changes in relation to the on-resistance of the internal switches. Note that there is an important consideration regarding power dissipation when using the ratiometric mode of operation (see the Power Dissipation section for more details). +VCC Y+ X+ +IN +REF Converter - IN - REF Y- GND Figure 5. Simplified Diagram of Differential Reference (SER/DFR Low, Y Switches Enabled, X+ is Analog Input) As a final note about the differential reference mode, it must be used with +VCCas the source of the +REF voltage and cannot be used with VREF. It is possible to use a high-precision reference on VREF and single-ended reference mode for measurements that do not need to be ratiometric. In some cases, it is possible to power the converter directly from a precision reference. Most references can provide enough power for the TSC2046E, but might not be able to supply enough current for the external load (such as a resistive touch screen). 12 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 Touch Screen Settling In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (for example, noise generated by the LCD panel or backlight circuitry). These capacitors provide a low-pass filter to reduce the noise, but cause a settling time requirement when the panel is touched that typically shows up as a gain error. There are several methods for minimizing or eliminating this issue. The problem is that the input and/or reference has not settled to the final steady-state value prior to the ADC sampling the input(s) and providing the digital output. Additionally, the reference voltage may still be changing during the measurement cycle. Option 1 is to stop or slow down the TSC2046E DCLK for the required touch screen settling time. This option allows the input and reference to have stable values for the Acquire period (3 clock cycles of the TSC2046E; see Figure 9). This option works for both the single-ended and the differential modes. Option 2 is to operate the TSC2046E in the differential mode only for the touch screen measurements and command the TSC2046E to remain on (touch screen drivers ON) and not go into power-down (PD0 = 1). Several conversions are made, depending on the settling time required and the TSC2046E data rate. Once the required number of conversions have been made, the processor commands the TSC2046E to go into its power-down state on the last measurement. This process is required for X-Position, Y-Position, and Z-Position measurements. Option 3 is to operate in the 15 Clock-per-Conversion mode, which overlaps the analog-to-digital conversions and maintains the touch screen drivers on until commanded to stop by the processor (see Figure 13). Temperature Measurement In some applications, such as battery recharging, a measurement of ambient temperature is required. The temperature measurement technique used in the TSC2046E relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The ambient temperature can be predicted in applications by knowing the +25C value of the VBEvoltage and then monitoring the delta of that voltage as the temperature changes. The TSC2046E offers two modes of operation. The first mode requires calibration at a known temperature, but only requires a single reading to predict the ambient temperature. A diode is used (turned on) during this measurement cycle. The voltage across the diode is connected through the MUX for digitizing the forward bias voltage by the ADC with an address of A2 = 0, A1 = 0, and A0 = 0 (see Table 1 and Figure 6 for details). This voltage is typically 600mV at +25C with a 20A current through the diode. The absolute value of this diode voltage can vary by a few millivolts. However, the temperature coefficient (TC) of this voltage is very consistent at -2.1mV/C. During the final test of the end product, the diode voltage would be stored at a known room temperature, in memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3C/LSB (in 12-bit mode). +VCC TE MP 0 T E M P1 MUX ADC Figure 6. Temperature Measurement Functional Block Diagram Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 13 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com The second mode of operation does not require a test temperature calibration, but uses a two-measurement method to eliminate the need for absolute temperature calibration and for achieving 2C accuracy. This mode requires a second conversion with an address of A2 = 1, A1 = 1, and A0 = 1, with a 91 times larger current. The voltage difference between the first and second conversion using 91 times the bias current is represented by Equation 1: V = kT x ln(N) q (1) where: N = the current ratio = 91 k = Boltzmann's constant = 1.3807 x 10-23 J/K (joules/kelvin) q = the electron charge = 1.6022 x 10-19 C (coulombs) T = the temperature in kelvin (K) This method can provide improved absolute temperature measurement, but at a lower resolution of 1.6C/LSB. The resulting equation that solves for T is: T= q - DV k x ln(N) (2) where: V = VBE(TEMP1) - VBE(TEMP0) (in mV) \ T = 2.573 x V (in K) or T = 2.573 x V - 273 (in C) NOTE The bias current for each diode temperature measurement is only on for three clock cycles (during the acquisition mode) and, therefore, does not add any noticeable increase in power, especially if the temperature measurement only occurs occasionally. Battery Measurement An added feature of the TSC2046E is the ability to monitor the battery voltage on the other side of the voltage regulator (dc/dc converter), as shown in Figure 7. The battery voltage can vary from 0V to 6V, while maintaining the voltage to the TSC2046E at 2.7V, 3.3V, etc. The input voltage (VBAT) is divided down by four so that a 5.5V battery voltage is represented as 1.375V to the ADC. This design simplifies the multiplexer and control logic. In order to minimize the power consumption, the divider is only on during the sampling period when A2 = 0, A1 = 1, and A0 = 0 (see Table 1 for the relationship between the control bits and configuration of the TSC2046E). DC/DC Converter Battery 0.5V + to 5.5V 2.7V +VCC 0.125V to 1.375V VBAT ADC 7.5k 2.5k Figure 7. Battery Measurement Functional Block Diagram 14 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 Pressure Measurement Measuring touch pressure can also be done with the TSC2046E. To determine pen or finger touch, the pressure of the touch needs to be determined. Generally, it is not necessary to have very high performance for this test; therefore, the 8-bit resolution mode is recommended (however, calculations shown here are in the 12-bit resolution mode). There are several different ways of performing this measurement. The TSC2046E supports two methods. The first method requires knowing the X-plate resistance, measurement of the X-Position, and two additional cross panel measurements (Z1 and Z2) of the touch screen, as shown in Figure 8. Using Equation 3 calculates the touch resistance: RTOUCH = R X-Plate x o X-Position ae Z2 - 1// c 4096 ce Z1 o (3) The second method requires knowing both the X-Plate and Y-Plate resistance, measurement of X-Position and Y-Position, and Z1. Equation 4 calculates the touch resistance using the second method: RTOUCH = o R X-Plate x X-Position ae 4096 - 1// - R Y-Plate cc 4096 e Z1 o Measure X-Position Y-Position o ae c1 - / 4096 o e (4) Measure Z1-Position Y+ X+ X+ Y+ Y+ X+ Touch Touch Touch X-Position Z1-Position Z2-Position X- Y- X- X- Y- Y- Measure Z2-Position Figure 8. Pressure Measurement Block Diagram Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 15 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com Digital Interface See Figure 9 for the typical operation of the TSC2046E digital interface. This diagram assumes that the source of the digital signals is a microcontroller or digital signal processor with a basic serial interface. Each communication between the processor and the converter, such as SPI, SSI, or MicrowireTM synchronous serial interface, consists of eight clock cycles. One complete conversion can be accomplished with three serial communications for a total of 24 clock cycles on the DCLK input. Control Byte The control byte (on DIN), as shown in Table 3, provides the start conversion, addressing, ADC resolution, configuration, and power-down of the TSC2046E. Figure 9, Table 3 and Table 4 give detailed information regarding the order and description of these control bits within the control byte. Initiate START--The first bit, the S bit, must always be high and initiates the start of the control byte. The TSC2046E ignores inputs on the DIN pin until the start bit is detected. Addressing--The next three bits (A2, A1, and A0) select the active input channel(s) of the input multiplexer (see Table 1, Table 2, and Figure 2), touch screen drivers, and the reference inputs. MODE--The mode bit sets the resolution of the ADC. With this bit low, the next conversion has 12-bit resolution, whereas with this bit high, the next conversion has 8-bit resolution. SER/DFR--The SER/DFR bit controls the reference mode, either single-ended (high) or differential (low). The differential mode is also referred to as the ratiometric conversion mode and is preferred for X-Position, Y-Position, and Pressure-Touch measurements for optimum performance. The reference is derived from the voltage at the switch drivers, which is almost the same as the voltage to the touch screen. In this case, a reference voltage is not needed as the reference voltage to the ADC is the voltage across the touch screen. In the single-ended mode, the converter reference voltage is always the difference between the VREF and GND pins (see Table 1 and Table 2, and Figure 2 through Figure 5, for further information). Table 3. Order of the Control Bits in the Control Byte BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) S A2 A1 A0 MODE SER/DFR PD1 PD0 Table 4. Descriptions of the Control Bits within the Control Byte 16 BIT NAME 7 S DESCRIPTION 6-4 A2-A0 Channel Select bits. Along with the SER/DFR bit, these bits control the setting of the multiplexer input, touch driver switches, and reference inputs (see Table 1 and Figure 13). 3 MODE 12-Bit/8-Bit Conversion Select bit. This bit controls the number of bits for the next conversion: 12-bits (low) or 8-bits (high). 2 SER/DFR Single-Ended/Differential Reference Select bit. Along with bits A2-A0, this bit controls the setting of the multiplexer input, touch driver switches, and reference inputs (see Table 1 and Table 2). 1-0 PD1-PD0 Power-Down Mode Select bits. See Table 5 for details. Start bit. Control byte starts with first high bit on DIN. A new control byte can start every 15th clock cycle in 12-bit conversion mode or every 11th clock cycle in 8-bit conversion mode (see Figure 13). Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 CS t ACQ DCLK 1 DIN S 8 A2 A1 A0 MO D E SER/ DFR 8 1 1 8 PD1 PD0 (START) Idle Conversion Acquire Idle BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 (MSB) 0 Zero Filled... (LSB) (1) Drivers 1 and 2 (SER/DFR High) Off Drivers 1 and 2(1, 2) (SER/DFR Low) Off On Off On Off NOTES: (1) For Y-Position, Driver 1 is on X+ is selected, and Driver 2 is off. For X-Position, Driver 1 is off, Y+ is selected, and Driver 2 is on. Y- will turn on when power-down mode is entered and PD0 = 0. (2) Drivers will remain on if PD0 = 1 (no power down) until selected input channel, reference mode, or p ower-down mode is changed, or CS is high. Figure 9. Conversion Timing, 24 Clocks-per-Conversion, 8-Bit Bus Interface No DCLK Delay Required With Dedicated Serial Port If X-Position, Y-Position, and Pressure-Touch are measured in the single-ended mode, an external reference voltage is needed. The TSC2046E must also be powered from the external reference. Caution should be observed when using the single-ended mode such that the input voltage to the ADC does not exceed the internal reference voltage, especially if the supply voltage is greater than 2.7V. NOTE The differential mode can only be used for X-Position, Y-Position, and Pressure-Touch measurements. All other measurements require the single-ended mode. PD0 and PD1--Table 5 describes the power-down and the internal reference voltage configurations. The internal reference voltage can be turned on or off independently of the ADC. This feature can allow extra time for the internal reference voltage to settle to the final value prior to making a conversion. Make sure to also allow this extra wake-up time if the internal reference is powered down. The ADC requires no wake-up time and can be instantaneously used. Also note that the status of the internal reference power-down is latched into the part (internally) with BUSY going high. In order to turn the reference off, an additional write to the TSC2046E is required after the channel has been converted. Table 5. Power-Down and Internal Reference Selection PD1 PD0 PENIRQ DESCRIPTION 0 0 Enabled Power-Down Between Conversions. When each conversion is finished, the converter enters a low-power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to ensure full operation, and the very first conversion is valid. The Yswitch is on when in power-down. 0 1 Disabled Reference is off and ADC is on. 1 0 Enabled Reference is on and ADC is off. 1 1 Disabled Device is always powered. Reference is on and ADC is on. PENIRQ Output The pen-interrupt output function is shown in Figure 10. While in power-down mode with PD0 = 0, the Y-driver is on and connects the Y-plane of the touch screen to GND. The PENIRQ output is connected to the X+ input through two transmission gates. When the screen is touched, the X+ input is pulled to ground through the touch screen. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 17 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com In most of the TSC2046E models, the internal pullup resistor value is nominally 50k, but this value may vary between 36k and 67k given process and temperature variations. In order to assure a logic low of 0.35 (+VCC) is presented to the PENIRQ circuitry, the total resistance between the X+ and Y- terminals must be less than 21k. IOVDD +V CC Level Shifter 50k or 90k +VCC TEMP0 Y+ PENIRQ High except when TEMP0, TEMP1 activated. X+ TEMP1 TEMP DIODE Y- On Y+ or X+ drivers on, or TEMP0, TEMP1 measurements activated. Figure 10. PENIRQ Functional Block Diagram The -90 version of the TSC2046E uses a nominal 90k pullup resistor that allows the total resistance between the X+ and Y- terminals to be as high as 30k. Note that the higher pullup resistance causes a slower response time of the PENIRQ to a screen touch, so user software should take this into account. The PENIRQ output goes low due to the current path through the touch screen to ground, initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-Position, the X+ input is disconnected from the PENIRQ internal pull-up resistor. This disconnection is done to eliminate any leakage current from the internal pull-up resistor through the touch screen, thus causing no errors. Furthermore, the PENIRQ output is disabled and low during the measurement cycle for X-, Y-, and Z-Position. The PENIRQ output is disabled and high during the measurement cycle for battery monitor, auxiliary input, and chip temperature. If the last control byte written to the TSC2046E contains PD0 = 1, the pen-interrupt output function is disabled and is not able to detect when the screen is touched. In order to re-enable the pen-interrupt output function under these circumstances, a control byte needs to be written to the TSC2046E with PD0 = 0. If the last control byte written to the TSC2046E contains PD0 = 0, the pen-interrupt output function is enabled at the end of the conversion. The end of the conversion occurs on the falling edge of DCLK after bit 1 of the converted data is clocked out of the TSC2046E. It is recommended that the processor mask the interrupt that PENIRQ is associated with whenever the processor sends a control byte to the TSC2046E. This masking prevents false triggering of interrupts when the PENIRQ output is disabled in the cases discussed in this section. 16 Clocks-per-Conversion The control bits for conversion n + 1 can be overlapped with conversion n to allow for a conversion every 16 clock cycles, as shown in Figure 11. This figure also shows possible serial communication occurring with other serial peripherals between each byte transfer from the processor to the converter. (16 clocks cycles are possible, provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that is captured on the input sample-and-hold may droop enough to affect the conversion result.) Note that the TSC2046E is fully powered while other serial communications are taking place during a conversion. 18 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 CS DCLK 1 DIN 8 8 1 1 8 1 S S Control Bits Control Bits BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 11 10 9 0 Figure 11. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface No DCLK Delay Required With Dedicated Serial Port Digital Timing Figure 9, Figure 12, and Table 6 provide detailed timing for the digital interface of the TSC2046E. CS tCL t CH tCSS tBD tBD tCSH tDO DCLK tDH t DS PD0 DIN tBDV tBTR BUSY tDV tTR DOUT 11 10 Figure 12. Detailed Timing Diagram Table 6. Timing Specifications (1) SYMBOL (1) DESCRIPTION MIN TYP MAX UNIT tACQ Acquisition Time 1.5 s tDS DIN Valid Prior to DCLK Rising 100 ns tDH DIN Hold After DCLK High tDO DCLK Falling to DOUT Valid 50 200 ns ns tDV CS Falling to DOUT Enabled 200 ns 200 ns tTR CS Rising to DOUT Disabled tCSS CS Falling to First DCLK Rising tCSH CS Rising to DCLK Ignored tCH tCL tBD DCLK Falling to BUSY Rising/Falling 200 ns tBDV CS Falling to BUSY Enabled 200 ns tBTR CS Rising to BUSY Disabled 200 ns 100 ns 10 ns DCLK High 200 ns DCLK Low 200 ns TA = -40C to +125C, +VCC = 2.7V, +VCC IOVDD 1.5V, CLOAD = 50pF Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 19 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com 15 Clocks-per-Conversion Figure 13 provides the fastest way to clock the TSC2046E. This method does not work with the serial interface of most microcontrollers and digital signal processors, as they are generally not capable of providing 15 clock cycles per serial transfer. However, this method can be used with field-programmable gate arrays (FPGAs) or application- specific integrated circuits (ASICs). Note that this effectively increases the maximum conversion rate of the converter beyond the values given in the specification tables, which assume 16 clock cycles per conversion. Power-Down CS DCLK 1 DIN 15 S A2 A1 A0 MOD E SER/ DFR 1 15 S A2 A1 A0 PD1 PD0 SER/ MODE DFR 1 S A2 A1 A0 PD1 PD0 BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 Figure 13. Maximum Conversion Rate, 15 Clocks-per-Conversion Data Format The TSC2046E output data is in Straight Binary format, as shown in Figure 14. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. FS = Full- Scale Voltage = VREF(1) 1LSB = VREF(1)/4096 1LSB 11...111 Output Code 11...110 11...101 00...010 00...001 00...000 FS - 1LSB 0V Input Voltage(2) (V) NOTES: (1) Reference voltage at converter: +REF - (-REF); see Figure 2. (2) Input voltage at converter, after multiplexer: +IN - (-IN); see Figure 2. Figure 14. Ideal Input Voltages and Output Codes 8-Bit Conversion The TSC2046E provides an 8-bit conversion mode that can be used when faster throughput is needed and the digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier. Not only does this shorten each conversion by four bits (25% faster throughput), but each conversion can actually occur at a faster clock rate. This faster rate occurs because the internal settling time of the TSC2046E is not as critical--settling to better than 8 bits is all that is needed. The clock rate can be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion rate. 20 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 TSC2046E-Q1 www.ti.com SBAS510 - JUNE 2010 Power Dissipation There are two major power modes for the TSC2046E: full-power (PD0 = 1) and auto power-down (PD0 = 0). When operating at full speed and 16 clocks-per-conversion (see Figure 11), the TSC2046E spends most of the time acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Therefore, the difference between full-power mode and auto power-down is negligible. If the conversion rate is decreased by slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion but conversions are done less often, the difference between the two modes is dramatic. Figure 15 shows the difference between reducing the DCLK frequency (scaling DCLK to match the conversion rate) or maintaining DCLK at the highest frequency and reducing the number of conversions per second. In the latter case, the converter spends an increasing percentage of time in power-down mode (assuming the auto power-down mode is active). 1000 Supply Current (A) fCLK = 16 fSAMPLE 100 f CLK = 2MHz Supply Current from + V C C and IOVDD 10 TA = 25C +VCC = 2.7V IOVDD = 1.8V 1 1k 10k 100k 1M fSAMPLE (Hz) Figure 15. Supply Current vs Directly Scaling the Frequency of DCLK with Sample Rate or Maintaining DCLK at the Maximum Possible Frequency Another important consideration for power dissipation is the reference mode of the converter. In the single-ended reference mode, the touch panel drivers are ON only when the analog input voltage is being acquired (see Figure 9 and Table 1). The external device (for example, a resistive touch screen), therefore, is only powered during the acquisition period. In the differential reference mode, the external device must be powered throughout the acquisition and conversion periods (see Figure 9). If the conversion rate is high, it could substantially increase power dissipation. CS also puts the TSC2046E into power-down mode. When CS goes high, the TSC2046E immediately goes into power-down mode and does not complete the current conversion. The internal reference, however, does not turn off with CS going high. To turn the reference off, an additional write is required before CS goes high (PD1 = 0). When the TSC2046E first powers up, the device draws about 20A of current until a control byte is written to it with PD0 = 0 to put it into power-down mode. This current draw can be avoided if the TSC2046E is powered up with CS = 0 and DCLK = IOVDD. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 21 TSC2046E-Q1 SBAS510 - JUNE 2010 www.ti.com Layout The following layout suggestions provide the most optimum performance from the TSC2046E. Many portable applications, however, have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices have fairly clean power and grounds because most of the internal components are very low power. This situation means less bypassing for the converter power and less concern regarding grounding. Still, each situation is unique and the following suggestions should be reviewed carefully. For optimum performance, care should be taken with the physical layout of the TSC2046E circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches can originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input. Because of the SAR architecture sensitvity, power to the TSC2046E should be clean and well bypassed. A 0.1F ceramic bypass capacitor should be placed as close to the device as possible. A 1F to 10F capacitor may also be needed if the impedance of the connection between +VCC or IOVDD and the power supplies is high. Low-leakage capacitors should be used to minimize power dissipation through the bypass capacitors when the TSC2046E is in power-down mode. A bypass capacitor is generally not needed on the VREF pin because the internal reference is buffered by an internal op amp. If an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation. The TSC2046E architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appears directly in the digital results. Whereas high-frequency noise can be filtered out, voltage variation bacause of line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin must be connected to a clean ground point. In many cases, this is the analog ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Although resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Longer connections are a source of error, much like the on-resistance of the internal switches. Likewise, loose connections can be a source of error when the contact resistance changes with flexing or vibrations. As indicated previously, noise can be a major source of error in touch screen applications (such as in applications that require a backlit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screen and cause flickering of the converted data. Several things can be done to reduce this error; for instance, using a touch screen with a bottom-side metal layer connected to ground to shunt the majority of noise to ground. Additionally, filtering capacitors from Y+, Y-, X+, and X- pins to ground can also help. Caution should be observed under these circumstances for settling time of the touch screen, especially operating in the single-ended mode and at high data rates. 22 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 PACKAGE OPTION ADDENDUM www.ti.com 16-Jul-2010 PACKAGING INFORMATION Orderable Device TSC2046EQPWRQ1 Status (1) Package Type Package Drawing ACTIVE TSSOP PW Pins Package Qty 16 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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