PIC16LF72T-I/MLG - Microchip Technology

 2002 Microchip Technology Inc. DS39597B

PIC16F72

Data Sheet

28-Pin, 8-Bit CMOS FLASH

Microcontroller with A/D Converter

DS39597B - page ii  2002 Microchip Technology Inc.

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Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip Tech-

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dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

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Mode and Total Endurance are trademarks of Microchip

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Serialized Quick Turn Programming (SQTP) is a service mark

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Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g

devices, Serial EEPRO Ms, micrope riphera ls,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

•The PICmicro family meets the specifications contained in the Microchip Data Sheet.

•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

•Microchip is willing to work with the customer who is concerned about the integrity of their code.

•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter , please contact the local sales off ice nearest to you.

 2002 Microchip Technology Inc. DS39597B-page 1

MPIC16F72

Device Included:

•PIC16F72

High Performance RISC CPU:

•Only 35 single word instructions to learn

•All single cycle instructions except for program

branches, which are two-cycle

•Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

•2K x 14 words of Program Memory,

128 x 8 bytes of Data Memory (RAM)

•Pinout compatible to PIC16C72/72A and

PIC16F872

•Interrupt capability

•Eight-level deep hardware stack

•Direct, Indirect and Relative Addressing modes

Peripheral Feat ures:

•High Sink/Source Current: 25 mA

•Timer0: 8-bit timer/counter with 8-bit prescaler

•Timer1: 16-bit timer/counter with prescaler,

can be increm en ted duri ng SLEEP via external

crystal/clock

•Timer2: 8-bit timer/counter with 8-bit period

•Capt ure, Compare, PWM ( CCP) module

- Capture is 16-bit, max. resolution is 12.5 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM max. resolution is 10-bit

•8-bit, 5-channel analog-to-digital converter

•Synchronous Serial Port (SSP) with

SPI™ (Master/Slave) and I2C™ (Slave)

•Brown-out detection circuitry for

Brown-out Reset (BOR)

CMOS Technology:

•Low power, high speed CMOS FLASH technology

•Fully static design

•Wide operating voltage range: 2.0V to 5.5V

•Industri al tem pera ture range

•Low power consumption:

- < 0.6 mA typical @ 3V, 4 MHz

-20 µA typical @ 3V, 32 kHz

-< 1 µA typical standby current

Pin Diagrams

Special Microcontroller Features:

•1,000 erase/write cycle FLASH program memory

typical

•Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

•Watchdog Timer (WDT) with its own on-chip

RC oscillator for reliable operation

•Programmable code protection

•Power saving SLEEP mode

•Select ab le os cil la t or options

•In-Circuit Serial Programming™ (ICS P ™) vi a 2 pins

•Process or read acces s to progra m me mo ry

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/AN4/SS

VSS

OSC1/CLKI

OSC2/CLKO

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RB7/PGD

RB6/PGC

RB5

RB4

RB3

RB2

RB1

RB0/INT

VDD

VSS

RC7

RC6

RC5/SDO

RC4/SDI/SDA

• 1

PDIP, SOIC, SSOP

QFN

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/AN4/SS

OSC1/CLKI

OSC2/CLKO

RB3

RB2

RB1

RB0/INT

VDD

VSS

RC7

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6

232425262728 22

RA1/AN1

RA0/AN0

MCLR/VPP

RB7/PGD

RB6/PGC

RB5

RB4

10 118 9 12 13 14

PIC16F72

28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter

PIC16F72

DS39597B-page 2  2002 Microchip Technology Inc.

Key Reference Manual Features PIC16F72

Operating Frequency DC - 20 MHz

RESETS and (Delays) POR, BOR, (PWRT, OST)

FLASH Program Memory - (14-bit words, 1000 E/W cycles) 2K

Data Memory - RAM (8-bit bytes) 128

Interrupts 8

I/O Ports PORTA, PORTB, PORTC

Timers Ti me r0, Timer1, Timer2

Capture/Compare/PWM Modules 1

Serial Commun ic ati ons SSP

8-bit A/D Converter 5 channels

Instruction Set (No. of Instructions) 35

 2002 Microchip Technology Inc. DS39597B-page 3

PIC16F72

Table of Con tents

1.0 Device Overview .......................................................................................................................................................................... 5

2.0 Memory O rganization................................................................................................................................................................... 7

3.0 I/O Ports.................... ...... ................. ...... ................. ...... ................. ................. ...... ..................................................................... 21

4.0 Reading Program Memory .................................. .. .... .... ......... .... .. .... .... ......... .. .... .... ......... .... .. .................................................... 27

5.0 Timer0 Module ........................................................................................................................................................................... 29

6.0 Timer1 Module ........................................................................................................................................................................... 31

7.0 Timer2 Module ........................................................................................................................................................................... 35

8.0 Capture/Compare/PWM (CCP) Module .......................................................... ...... ................. ...... .............................................. 37

9.0 Syn chronous Serial Port (SS P) Mo dule ..................................................................................................................................... 43

10.0 Analog-to-Digital Converter (A/D) Module. ................................................................................................................................. 53

11.0 Spe cial Featur e s of th e CPU................ ...... ....... ...... ................. ...... ...... ....... ................. ...... ........................................................ 59

12.0 Instruction Set Summary............................................................................................................................................................ 73

13.0 Development Support. ................................................................................................................................................................ 81

14.0 Electrical Characteristics............................................................................................................................................................ 87

15.0 DC and AC Characteristics Graphs and Tables............................................ .... .... .. ......... .... .... .. .... .......................................... 107

16.0 Package Marking Information................................................................................................................................................... 117

Appendix A: Revision History .............. .... ...... ........... .... .... .... ........... .... .... ........... ...... .... ........... ...................................................... 123

Appendix B: Conversion Considerations..................... .... .. .... ....... .. .. .... .. .... ..... .... .. .... .. .. ....... .... .. .. .... .............................................. 123

Index .................................................................................................................................................................................................. 125

On-Line Support......... ....... .... .. .... .... ....... .... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. .... .... ................................................................. 131

Reader Response.............................................................................................................................................................................. 132

Product Identification System ............................................................................................................................................................ 133

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PIC16F72

DS39597B-page 4  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. DS39597B-page 5

PIC16F72

1.0 DEVICE OVERVIEW

This do cu me n t conta i ns dev ic e spec if i c in f orm at i on fo r

the operati on of th e P IC16F72 devic e. Additi ona l inf or-

mation may be found in the PICmicro™ Mid-Range

MCU Reference Manual (DS33023), which may be

downloaded from the Microchip website. The Refer-

ence Manual should be considered a complementary

document to this data sheet, and is highly recom-

mended reading for a better understanding of the

device architecture and operation of the peripheral

modules.

The PIC16F72 belongs to the Mid-Range family of the

PICmicro devices. A block diagram of the device is

shown in Figur e 1-1.

The program memory contains 2K words, which trans-

late to 2048 instructions, since each 14-bit program

memory word is the same width as each device

instruction. The data m emory (RAM) contains 128 bytes.

There are 22 I/O pins that are user configurable on a

pin-to-pin basis. Some pins are multiplexed with other

device functions. These functions include:

•External inte rrup t

•Change on PORTB interrupt

•Ti mer0 clock input

•Timer1 clock/oscillator

•Capture/Compare/PWM

•A/D conver ter

•SPI/I2C

Table 1-1 details the pinout of the device with

descriptions and details for each pin.

FIGURE 1-1: PIC16F72 BLOCK DIAGRAM

FLASH

Memory

2K x 14

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8-Level Stack

(13-bit)

RAM

File

Registers

128 x 8

Direct Addr 7

RAM Addr(1) 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKI

OSC2/CLKO

MCLR VDD, VSS

Timer0

A/D Synchronous

Seri a l Po r t

PORTA

PORTC RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6

RC7

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

CCP1

Timer1 Timer2

RA4/T0CKI

RA5/AN4/SS

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

Program

PORTB RB0/INT

RB1

RB2

RB3

RB4

RB5

RB6/PGC

RB7/PGD

PIC16F72

DS39597B-page 6  2002 Microchip Technology Inc.

TABLE 1-1: PIC16F72 PINOUT DESCRIPTION

Pin Name

PDIP,

SOIC,

SSOP

Pin#

MLF

Pin# I/O/P

Type Buffer

Type Description

OSC1/CLKI 9 6 I ST/CMOS(3) Os cillator crys tal input/external clock source input.

OSC2/CLKO 10 7 O —Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. In RC mode, the OSC2 pin outputs CLKO, which has

1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR/VPP 1 26 I/P ST Master Clear (Reset) input or programming voltage input. This pin is

an active low RESET to the device.

PORTA is a bi-directional I/O port.

RA0/AN0 2 27 I/O TTL RA0 can also be analog input0.

RA1/AN1 3 28 I/O TTL RA1 can also be analog input1.

RA2/AN2 4 1 I/O TTL RA2 can also be analog input2.

RA3/AN3/VREF 5 2 I/O TTL RA3 can also be analog input3 or analog reference voltage.

RA4/T0CKI 6 3 I/O ST RA4 can also be the clock input to the Timer0 module. Output is

open drain type.

RA5/AN4/SS 7 4 I/O TTL RA5 can also be analog input4 or the slave select for the

synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs.

RB0/INT 21 18 I/O TTL/ST(1) R B0 can also be the external interrupt pin.

RB1 22 19 I/O TTL

RB2 23 20 I/O TTL

RB3 24 21 I/O TTL

RB4 25 22 I/O TTL Interrupt-on-change pin.

RB5 26 23 I/O TTL Interrupt-on-change pin.

RB6/PGC 27 24 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming clock.

RB7/PGD 28 25 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO/

T1CKI 1 1 8 I/O ST RC0 can also be the Timer1 oscillator output or Ti mer1 clock input.

RC1/T1OSI 12 9 I/O ST RC1 can also be the Timer1 oscillator input.

RC2/CCP1 13 10 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output.

RC3/SCK/SCL 14 1 1 I/O ST RC3 can also be the synchronous serial clock input/output for both

SPI and I2C modes.

RC4/SDI/SDA 15 12 I/O ST RC 4 can also be the SPI Data In (SPI mode) or

Data I/O (I2C mode).

RC5/SDO 16 13 I/O ST RC 5 can also be the SPI Data Out (SPI mode).

RC6 17 14 I/O ST

RC7 18 15 I/O ST

VSS 8, 19 5, 16 P —Ground reference for logic and I/O pins.

VDD 20 17 P —Positive supply for logic and I/O pins.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

 2002 Microchip Technology Inc. DS39597B-page 7

PIC16F72

2.0 MEMORY ORGANIZATION

There are two memory bloc ks in the PIC16F72 dev ic e.

These are the program memory and the data memory.

Each block has separate buses so that concurrent

access can occur. Program memory and data memory

are explained in this section. Program memory can be

read internally by the user code (see Section 4.0).

The data memory can further be broken down into the

general purpose RAM and the Special Function

Registers (SFRs). The operation of the SFRs that

control the “core” are described here. The SFRs used

to control the peripheral modules are described in the

section discussing each individual peripheral module.

Addit ional informat ion on devi ce memory may be found

in the PICmicro™ Mid-Range Reference Manual,

(DS33023).

2.1 Program Memory Organization

PIC16F72 devices have a 13-bit program counter capa-

ble of addressing a 8K x 14 program memory space.

The address range for this prog ram memory is 0000h -

07FFh. Accessing a location above the physically

implemented address will cause a wraparound.

The RESET Vector is at 000 0h and the Inte rrupt V ec tor

is at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK

2.2 Data Memory Organization

The Dat a Memory is partiti oned into mult iple banks th at

cont ain the Genera l Purpose Reg isters and the Special

Function Registers. Bits RP1 (STATUS<6>) and RP0

(STATUS<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Functio n Register s. Above the Spe cial Function Regis-

ters are General Purpose Registers, implemented as

static RAM.

All impl ement ed ban ks co nta in SFRs. Some “h igh us e”

SFRs from on e b ank m ay be m irro red in an othe r b ank ,

for code reduction and quicker access (e.g., the

STAT US register is in Ban k s 0 - 3) .

2.2. 1 GENERAL PURPOSE REGISTER

FILE

The registe r file can be accesse d either dire ctly , or ind i-

rectly, through the File Select Register FSR (see

Section 2.5).

PC<12:0>

0000h

0004h

0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0800h

User Memory

Space

RP1:RP0 Bank

00 0

01 1

10 2

11 3

PIC16F72

DS39597B-page 8  2002 Microchip Technology Inc.

FIGURE 2-2: PIC16F72 REGISTER FILE MAP

Indirect addr.(*)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION

PCL

STATUS

FSR

TRISA

TRISB

TRISC

PCLATH

INTCON

PIE1

PCON

PR2

SSPSTAT

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

7Fh FFh

Bank 0 Bank 1

File

Address

Indirect addr.(*) Indirect add r.(*)

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

17Fh 1FFh

Bank 2 Bank 3

Indirect addr.(*)

TMR0 OPTION

ADRES

ADCON0 ADCON1

General

Purpose

20h-7Fh

TRISB

PORTB

96 Bytes

10Ch

10Dh

10Eh

10Fh

110h

18Ch

18Dh

18Eh

18Fh

190h

PMDATL

PMADRL PMCON1

PMDATH

PMADRH

Uni mplemented data memory locati ons, r ead as ‘0’.

* Not a physical register.

File

Address

File

Address

File

Address

SSPADD

120h

11Fh 1A0h

19Fh

General

Purpose

32 Bytes BFh

C0h

accesses

40h-7Fh

accesses

A0h -BFh 1BFh

1C0h

accesses

40h -7Fh

 2002 Microchip Technology Inc. DS39597B-page 9
PIC16F72
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Ta ble 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY 
Address Name Bit 7 B it  6 Bit 5 Bit 4 Bit 3 Bit 2  Bit 1 B i t  0 Value on
POR, BOR Details on 
page:
   Bank 0
00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19
01h TMR0 Timer0 Module’s Regist er xxxx xxxx 29,13
02h(1) PCL Program Co unter's (PC)  Leas t Significant Byte 0000 0000 18
03h(1) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 12
04h(1) FSR Indirect  Data Memory Address Pointer xxxx xxxx 19
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 21
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 23
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 25
08h —Unimplemented — —
09h —Unimplemented — —
0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 18
0Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 16
0Dh —Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant  Byte of the 16-bit TMR1 Register xxxx xxxx 31
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 31
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 31
11h TMR2 Timer2 Module’s Register 0000 0000 35
12h T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 36
13h SSPBUF Synchronous Serial Port Rec eiv e Buffer/Transmit Register xxxx xxxx 43,48
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 45
15h CCPR1L Capture/Compar e/PWM Register (LSB) xxxx xxxx 38,39,41
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 38,39,41
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 37
18h-1Dh —Unimplemented — —
1Eh ADRES A/D Result Register xxxx xxxx 53
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON 0000 00-0 53
Legend: x = unknown, u = unchanged, q = value depend s on condition, - = unimplemented,  read as ‘0’, r = reserved. 
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: The upper byte of the program counter is no t directly accessible. PCLATH is a holding register for the PC<12:8> whose 
contents are transferred to t he upper byte of the program counter.
3: Thi s bi t alway s read s as  a  ‘1’.

PIC16F72
DS39597B-page 10  2002 Microchip Technology Inc.
   Bank 1
80h(1) INDF Addressing this location uses contents of FSR  to address data memory (not a physical register) 0000 0000 19
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13
82h(1) PCL Progr am Co unter’s (PC) Le a st Si g n i fica nt Byte 0000 0000 18
83h(1) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12
84h(1) FSR Indirect  Data Memory Address Pointer xxxx xxxx 19
85h TRISA — — PORTA Data Direction Register --11 1111 21
86h TRISB PORTB Data Direction Register 1111 1111 23
87h TRISC PORTC Data Direction Register 1111 1111 25
88h —Unimplemented — —
89h —Unimplemented — —
8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 18
8Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 15
8Dh —Unimplemented — —
8Eh PCON — — — — — — POR BOR ---- --qq 17
8Fh —Unimplemented — —
90h —Unimplemented — —
91h —Unimplemented — —
92h PR2 Timer2 Pe riod Register 1111 1111 41
93h SSPADD Synch ronous Serial Port (I2C mode) Address  Regis ter 0000 0000 43,48
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 44
95h —Unimplemented — —
96h —Unimplemented — —
97h —Unimplemented — —
98h —Unimplemented — —
99h —Unimplemented — —
9Ah —Unimplemented — —
9Bh —Unimplemented — —
9Ch —Unimplemented — —
9Dh —Unimplemented — —
9Eh —Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000  54
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY  (CONTINUED)
Address Name Bit 7 B it  6 Bit 5 Bit 4 Bit 3 Bit 2  Bit 1 B i t  0 Value on
POR, BOR Details on 
page:
Legend: x = unknown, u = unchanged, q = value depend s on condition, - = unimplemented,  read as ‘0’, r = reserved. 
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: The upper byte of the program counter is no t directly accessible. PCLATH is a holding register for the PC<12:8> whose 
contents are transferred to t he upper byte of the program counter.
3: Thi s bi t alway s read s as  a  ‘1’.

 2002 Microchip Technology Inc. DS39597B-page 11
PIC16F72
   Bank 2
100h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19
101h TMR0 Timer0 Module’s Register xxxx xxxx 29
102h(1 PCL Program Counter's (PC) Least Significant Byte 0000 0000 18
103h(1) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12
104h(1) FSR Indirect Data Memory Address Pointer xxxx xxxx 19
105h —Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 23
107h —Unimplemented — —
108h —Unimplemented — —
109h —Unimplemented — —
10Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 18
10Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14
10Ch PMDATL Data Register Low Byte xxxx xxxx 27
10Dh PMADRL Address Register Low Byte xxxx xxxx 27
10Eh PMDATH — — Data Register High Byte --xx xxxx 27
10Fh PMADRH — — — Address Register High Byte ---x xxxx 27
   Bank 3
180h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19
181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13
182h(1) PCL Program Counter's (PC)  Least Significant Byte 0000 0000 18
183h(1) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12
184h(1) FSR Indirect Data Memory Address Pointer xxxx xxxx 19
185h —Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 23
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 18
18Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14
18Ch PMCON1 — (3) — — — — — — RD 1--- ---0 27
18Dh —Unimplemented — —
18Eh —Reserved, maintain clear 0000 0000 —
18Fh —Reserved, maintain clear 0000 0000 —
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY  (CONTINUED)
Address Name Bit 7 B it  6 Bit 5 Bit 4 Bit 3 Bit 2  Bit 1 B i t  0 Value on
POR, BOR Details on 
page:
Legend: x = unknown, u = unchanged, q = value depend s on condition, - = unimplemented,  read as ‘0’, r = reserved. 
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: The upper byte of the program counter is no t directly accessible. PCLATH is a holding register for the PC<12:8> whose 
contents are transferred to t he upper byte of the program counter.
3: Thi s bi t alway s read s as  a  ‘1’.

PIC16F72

DS39597B-page 12  2002 Microchip Technology Inc.

2.2.2.1 STATUS Register

The STATUS register, shown in Register 2-1, contains

the ar ithmetic st atus of th e ALU, the RESET st atus and

the bank select bits for data memory.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For exam pl e, CLRF STATUS wil l clear the upper thre e

bits and set t he Z bit. T his leav es the STA T US regist er

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affe ct the Z, C or D C bits from th e ST ATUS register. For

other instructions, not affecting any status bits, see

Section 12.0, Instruction Set Summary.

Note 1: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub-

traction. See the SUBLW and SUBWF

instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1,2)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand.

2: For rot ate (RRF, RLF) i nstruc tions , this bit is loade d wi th either th e high or low orde r

bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS39597B-page 13

PIC16F72

2.2.2.2 OPTION Register

The OPTION register is a readable and writable regis-

ter that contains various control bits to configure the

TMR0 prescaler/WDT postscaler (single assignable

Interrupt, TMR0, and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to

the Watchdog Timer.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Inter nal i nstruction cycle c lock ( CLKO)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16F72

DS39597B-page 14  2002 Microchip Technology Inc.

2.2.2.3 INTCON Register

The INTCO N Register is a read able and writ able regis-

ter that contains various enable and flag bits for the

TMR0 register overflow, RB Port change and External

RB0/INT pin interrupts.

Note: Interru pt fla g bit s get set when an in terru pt

conditi on occ urs , re gardless of the st a te of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Chan ge Inter rupt Enab le bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

A mism atc h c on dit ion w il l c on tinu e t o s et flag bit RBIF. Readi ng PO R T B wi ll end the misma tch

condition and allow flag bit RBIF to be cleared.

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS39597B-page 15

PIC16F72

2.2.2.4 PIE1 Register

This register contains the individual enable bits for the

peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

—ADIE — — SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIE: A/D Converter Interrupt Enab le bit

1 = Enables the A/D converter interrupt

0 = Disables the A/D converter interrupt

bit 5-4 Unimplemented: Read as ‘0’

bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 over flow interr upt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F72

DS39597B-page 16  2002 Microchip Technology Inc.

2.2.2.5 PIR1 Register

This register contains the individual flag bits for the

Peripheral interrupts.

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

—ADIF — — SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D convers ion comple ted

0 = The A/D conversion is not complete

bit 5-4 Unimplemented: Read as ‘0’

bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit

1 = The SSP interru pt condition has occurred, and must b e cleared in software before returning

from the Interrupt Service Routine.

The conditions that will set this bit are a transmission/reception has taken place.

0 = No SSP interrupt condition has occurred

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 re gister capture occur red

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TM R1 register compare match occurred

PWM mo de:

Unused in this mode

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS39597B-page 17

PIC16F72

2.2.2.6 PCON Register

The Power Control (PCON) register contains a flag bit

to allow differentiation between a Power-on Reset

(POR), a Brown-out Reset, an external MCLR Reset

and WDT Reset.

Note: Interru pt fla g bit s get set when an in terru pt

conditi on oc curs, rega rdle ss of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked

on subsequent RESETS to see if BOR is

clear, indicati ng a brown-ou t has occurre d.

The BOR status bit is a ‘don't care’ and is

not necessarily predictable if the brown-out

circuit is disabled (by clearing the BOREN

bit in the Configuration word).

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x

— — — — — — POR BOR

bit 7 bit 0

bit 7-2 Unimplemented: Read as ‘0’

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is se t ‘0’ = Bit is cleared x = Bit is unknown

PIC16F72

DS39597B-page 18  2002 Microchip Technology Inc.

2.3 PCL and PCLATH

The pr ogra m cou nter (PC) sp eci fie s th e a ddre ss of th e

instruction to fetch for execution. The PC is 13-bits

wide. The low byte is called the PCL register. This reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<12:8>

bits an d is n ot d irec tly re adable or wri table. All upd ate s

to the PCH register go through the PCLATH register.

Figure 2-3 shows the four situations for the loading of

the PC.

•Example 1 shows ho w the PC is loa ded on a w rite

to PCL (PCLATH<4:0> → PCH).

•Example 2 shows how the PC is loaded during a

GOTO instructi on (PCL ATH<4:3> → PCH).

•Example 3 shows how the PC is loaded during a

CALL instructi on (PCL ATH<4:3> → PCH), with

the PC loaded (PUSH’d) onto the Top-of-Stack.

•Example 4 shows how the PC is loaded during

one of the return instructions, where the PC is

loaded (POP’d) from the Top-of-Stack.

FIGURE 2-3: LOADING OF PC IN DIFFERENT SITUATIONS

12 8 7 0

5PCLATH<4:0>

PCLATH ALU result

Opcode <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

Example 1 - Instruction with PCL as destination

Example 2 - GOTO Instruction

Stack (13-bits x 8)

Top-of-Stack

Stack (13-bits x 8)

Top-of-Stack

Opcode <10:0>

PC 12 11 10 0

11PCLATH<4:3>

PCLATH

PCH PCL

Example 3 - CALL Instruction Stack (13-bits x 8)

Top-of-Stack

Opcode <10:0>

12 11 10 0

PCLATH

PCH PCL

Example 4 - RETURN, RETFIE, or RETLW Instruction Stack (13-bits x 8)

Top-of-Stack

Note: PCLATH is not updated with the contents of PCH.

 2002 Microchip Technology Inc. DS39597B-page 19

PIC16F72

2.3.1 COMPUTED GOTO

A comput ed GOTO is a ccom pli shed by a ddi ng a n offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be ex ercise d if th e t able loca tion c rosse s a PCL

memory boundary (each 256-byte block). Refer to the

Application Note, “Implementing a Table Read"

(AN556).

2.3.2 STACK

The stack allows a combination of up to eight program

calls and interrupts to occur. The stack contains the

return address from this branch in program execution.

Mid-range devices have an 8-level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readable or writable. The PC is PUSH’d onto the stack

when a CALL instruction is executed, or an interrupt

causes a branch. The stack is POP’d in the event of a

RETURN, RETLW or a RETFIE instruction execution.

PCLATH is no t modif ied when the stack is PUSH’d o r

POP’d.

After the st a ck has bee n PUSH ’d eight times, the ninth

push ov erwrit es the v alue tha t was stor ed from th e first

push. The tenth p us h ov erwrites the se co nd p us h (an d

so on). An example of the overwriting of the stack is

shown in Figur e 2-4.

FIGURE 2-4: STACK MODIFICATION

2.4 Program Memory Paging

The CALL and GOTO instructions provide 11 bits of

address to allow branching within any 2K program

memory page. When doing a CALL or GOTO instruction,

the upper two bits of the address are provided by

PCLATH<4:3>. When doing a CALL or GOTO instruc-

tion, the us er must ensu re tha t the p age sele ct bi t s are

programmed so that the desired program memory

page is addressed. If a return from a CALL instructi on

(or interrupt) is executed, the entire 13-bit PC is pushed

onto the stack. Therefore, manipulation of the

PCLATH<4:3> bits is not required for the return

instructions (which POPs the address from the stack).

2.5 Indirect Addressing, INDF and

FSR Registers

The IN DF r egi ster is no t a phy sica l reg ist er. Address-

ing INDF actually addresses the register whose

address is contained in the FSR register (FSR is a

pointer). This is in dir ec t addr essi ng.

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown i n Example 2-1.

EXAMPLE 2-1: INDIR ECT ADDRESS ING

An ef fective 9-b it address is obtained by conca tenating

the 8-bit FSR reg ister and the IRP bi t (ST A TU S<7>), as

shown in Figure 2-5.

Note 1: There a re no stat us bits to indic ate stack

overflow or st ac k und erfl ow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions, or the vectoring to an

interr upt add res s.

Push1 Push9

Push2 Push10

Push3

Push4

Push5

Push6

Push7

Push8

Top-of-Stack

Stack

Note: The PIC16F72 device ignores the paging

bit PCLATH<4:3>. The use of

PCLATH<4:3> as a general purpose read/

write bit is not recommended, since this

may af fec t upwa rd comp ati bility with future

products.

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;NO, clear next

CONTINUE

: ;YES, continue

PIC16F72

DS39597B-page 20  2002 Microchip Technology Inc.

FIGURE 2-5: DIRECT/INDIRECT ADDRESSING

Note 1: Fo r regi ster file map detail, see Figure 2-2.

Data

Memory(1)

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1:RP0 6 0

From Opcode IRP FSR Register

Bank Select Location Select

00 01 10 11

Bank 0 Bank 1 Bank 2 Bank 3

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

 2002 Microchip Technology Inc. DS39597B-page 21

PIC16F72

3.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

Addit ion al inf orm atio n o n I/O por t s ma y be foun d i n th e

PICmicro™ Mid-Range MCU Reference Manual,

(DS33023).

3.1 PORTA and the TRISA Register

PORTA is a 6-bit wide, bi-directional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding POR T A pin

an input (i.e., put the corresponding output driver in a

Hi-Impedance mode). Clearing a TRISA bit (= 0) will

make the correspon ding POR TA pin an out put (i.e., put

the contents of the output latch on the selected pin).

Reading the PORTA register, reads the status of the

pins, where as wri tin g to i t will wri te to th e po rt latch. All

write operations are read-modify-write operations.

Therefore , a write to a port implies that the port pins are

read, this value is modified and then written to the port

data l atch.

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin. The RA4/T0CKI

pin is a Schm itt Trigger inp ut and an ope n drai n outpu t.

All other RA port pins have TTL input levels and full

CMOS output drivers.

Other PORTA pins are multiplexed with analog inputs

and analog VREF input. The operation of each pin is

selected by clearing/setting the control bits in the

ADCON1 register (A/D Control Register1).

The TRISA register controls the direction of the RA

pins, ev en when they are be ing us ed as ana lo g inputs .

The user mu st ensure the bit s in the TRISA regi ster are

maintained set when using t hem as analog inputs.

EXAMPLE 3- 1: INITIALIZING PORTA

FIGURE 3-1: BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS

FIGURE 3-2: BLOCK DIAGRAM OF

RA4/T0CKI PIN

Note: On a Pow er-on Reset, these pins are con-

figured as analog inputs and read as ‘0’.

BANKSEL PORTA ; select bank for PORTA

CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches

BANKSEL ADCON1 ; Select Bank for ADCON1

MOVLW 0x06 ; Configure all pins

MOVWF ADCON1 ; as digital inputs

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA<3:0> as inputs

; RA<5:4> as outputs

; TRISA<7:6> are always

; read as ‘0’.

Data

Bus

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD Port

VSS

VDD

I/O pi n

Analog

Input

Mode

TTL

Input

Buffer

To A/D Converter

VDD

VSS

Data

Bus

Port

TRIS

RD Po rt

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Input

Buffer

VSS

I/O pin

TMR0 Clock Input

VSS

PIC16F72

DS39597B-page 22  2002 Microchip Technology Inc.

TABLE 3-1: PORTA FUNCTIONS

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0 bit 0 TTL Input/output or analog input.

RA1/AN1 bit 1 TTL Input/output or analog input.

RA2/AN2 bit 2 TTL Input/output or analog input.

RA3/AN3/VREF bit 3 TTL Input/output or analog input or VREF.

RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0. Output is open drain type.

RA5/AN4/SS bit 5 TTL Input/output or analog input or slave select input for synchronous serial port.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000

85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.

Shaded cells are not used by PORTA.

Note: When using the SSP module in SPI Slave mode and SS enabl ed, the A /D P or t Co nfi gura tio n C ontr ol b its

(PCFG2:PC FG0) in the A/D Cont rol Re gister ( ADCON1) m ust be set to o ne of the followi ng con figurat ions:

100, 101, 11x.

 2002 Microchip Technology Inc. DS39597B-page 23

PIC16F72

3.2 PORTB and the TRISB Register

PORTB is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISB bit (= 0) will

make the co rresponding POR TB pin an output (i.e., put

the contents of the output latch on the selected pin).

EXAMPLE 3- 2: INITIALIZING PORTB

Each of th e POR TB pins has a we ak inte rnal pul l-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (OPTION<7>). The weak

pull-up is automatically turned off when the port pin is

configu red as an outpu t. The pull- ups are di sabled on a

Power-on Reset.

FIGURE 3-3: BLOCK DIAGRAM OF

RB3:RB0 PINS

Four of POR TB’s pi ns, RB7:RB4, hav e an interrupt-o n-

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt

on change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’d together to generate the RB Port Change

Interrupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interr upt in the foll owin g man ner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.

A mism at c h c ond it i on wi ll co nti n ue to s et f lag bi t RB IF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

This interrupt-on-mismatch feature, together with soft-

ware configurable pull-ups on these four pins, allow

easy interface to a keypad and make it possible for

wake-up on key depression. Refer to the Embedded

Control Handbook, “Implementing Wake-Up on Key

Stroke” (AN552).

RB0/INT is an external interrupt input pin and is

configured using the INTEDG bit (OPTION<6>).

FIGURE 3-4: BLOCK DIAGRAM OF

RB7:RB4 PINS

BANKSEL PORTB ; Select bank for PORTB

CLRF PORTB ; Initialize PORTB by

; clearing output

; data latches

BANKSEL TRISB ; Select Bank for TRISB

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Data Latch

RBPU(1) P

VDD

Data

RD TRIS

RD Port

Weak

Pull-up

RD Port

RB0/INT

I/O pin

TTL

Input

Buffer

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)

Schmitt Trigger

Buffer

TRIS Latch

VDD

VSS

and clear the RBPU bit (OPTION<7>).

Bus

Port

TRIS

Data Latch

From Other

RBPU(1) P

VDD

I/O pin

Data

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 Pins

Weak

Pull-up

RD Port

Latch

TTL

Input

Buffer

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)

Buffer

RB7:RB6 in Serial Programming Mode Q3

VDD

VSS

and clear the RBPU bit (OPTION<7>).

Bus

Port

TRIS

PIC16F72

DS39597B-page 24  2002 Microchip Technology Inc.

TABLE 3-3: PORTB FUNCTIONS

TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit# Buffer Function

RB0/INT bit 0 TTL/ST(1) Input/output pin or external interrupt input. Internal software

programmable weak pull-up.

RB1 bit 1 TTL Input/output pin. Internal software programmable weak pull-up.

RB2 bit 2 TTL Input/output pin. Internal software programmable weak pull-up.

RB3 bit 3 TTL Input/output pin. Internal software programmable weak pull-up.

RB4 bit 4 TTL Input/outpu t pin (with interrup t-on-change). In ternal software pro grammable

weak pull-up.

RB5 bit 5 TTL Input/outpu t pin (with interrup t-on-change). In ternal software pro grammable

weak pull-up.

RB6 bit 6 TTL/ST(2) Input/outpu t pin (with interrup t-on-change). Interna l software program mable

weak pull-up . Serial programming clock.

RB7 bit 7 TTL/ST(2) Input/outpu t pin (with interrup t-on-change). Interna l software program mable

weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

86h, 186h TRISB POR TB Dat a Direc tio n Re gister 1111 1111 1111 1111

81h, 181h OPTIO N RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by P ORTB.

 2002 Microchip Technology Inc. DS39597B-page 25

PIC16F72

3.3 PORTC and the TRISC Register

PORTC is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISC bit (= 0) will

make th e corresponding PO RTC pin an output (i.e., put

the contents of the output latch on the selected pin).

PORT C is multip lexed with s everal periphe ral function s

(Table 3-5). PORTC pins have Schmitt Trigger input

buffers.

When enabling peripheral functions, care should be

taken in defini ng TRIS bit s fo r each POR TC pin. Some

peripherals override the TRIS bit to make a pin an out-

put, while other peripherals override the TRIS bit to

make a pin an input. Since the TRIS bit override is in

effect while the peripheral is enabled, read-modify-

write instructions (BSF, BCF, XORWF) with TRISC as

dest ination shoul d be avoided. The user s hould refer to

the corresponding peripheral section for the correct

TRIS bit settings.

EXAMPLE 3- 3: INITIALIZING PORTC

FIGURE 3-5: PORTC BLOCK DIAGRAM

(PERIPHERAL OUTPUT

OVERRIDE)

BANKSEL PORTC ; Select Bank for PORTC

CLRF PORTC ; Initialize PORTC by

; clearing output

; data latches

BANKSEL TRISC ; Select Bank for TRISC

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISC ; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

Port/Peripheral Select(1)

Data

Port

TRIS

Data Latch

TRIS Latch

RD TRIS Schmitt

Trigger

Peripheral Data Out 0

VDD

VSS

Port

Peripheral

OE(2)

Peripheral Input

Note 1: Port/Peripheral select signal selects

between port data and peripheral output.

2: Peripheral OE (output enable) is only

activated if peripheral select is active.

VSS

I/O

VDD

Bus

PIC16F72

DS39597B-page 26  2002 Microchip Technology Inc.

TABLE 3-5: PORTC FUNCTIONS

TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.

RC1/T1OSI bit 1 ST Input/output port pin or Timer1 oscillator input.

RC2/CCP1 bit 2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1

output.

RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and I2C

modes.

RC4/SDI/SDA bit 4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).

RC5/SDO bit 5 ST Input/output port pin or Synchronous Serial Port data output.

RC6 bit 6 ST Input/output port pin.

RC7 bit 7 ST Input/output port pin.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged

 2002 Microchip Technology Inc. DS39597B-page 27

PIC16F72

4.0 READING PROGRAM MEMORY

The FLASH Program Memory is readable during nor-

mal operation over the entire VDD range. It is indirectly

addressed through Special Function Registers (SFR).

Up to 14 -bit wide num bers can be stored in m emory for

use as calibration parameters, serial numbers, packed

7-bit ASCII, e tc. Executing a p rogram me mo ry l oc atio n

containing data that forms an invalid instruction results

in a NOP.

There are five SFRs used to read the program and

memory:

•PMCON1

•PMDATL

•PMDATH

•PMADRL

•PMADRH

The program memory allows word reads. Program

memory access allows for checksum calculation and

reading ca libration t abl es .

When interfacing to the program memory block, the

PMDATH:PMDATL registers form a two-byte word,

which holds the 14-bit data for reads. The

PMADRH:PMADRL registers form a two-byte word,

which holds the 13-bit address of the FLASH location

being accessed. This device has up to 2K words of

program FLASH, with an address range from 0h to

07FFh. The unused upper bits PMDATH<7:6> and

PMADRH<7:5> are not implemented and read as

zeros.

4.1 PMADR

The addres s registers can addres s up to a maximum of

8K words of program FLASH.

When selecting a program address value, the MSByte

of the address is written to the PMADRH register and

the LSByte is written to the PMADRL register. The

upper MSbits of PMADRH must always be clear.

4.2 PMCON1 Register

PMCON1 is the control register for memory accesses.

The control bit RD initiates read operations. This bit

cannot be cl eared, only set, in so ftware . It is cleare d in

hardware at the completion of the read operation.

R-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0

reserved — — — — — — RD

bit 7 bit 0

bit 7 Reserved: Read as ‘1’

bit 6-1 Unimplemented: Read as ‘0’

bit 0 RD: Read Control bit

1 = Ini tiates a FLASH read, RD is cleared i n hardware. The RD bit can only be s et (not c leared)

in software.

0 = Does not initiate a FLASH read

Legend:

W = Writable bit U = Unimplemented bit, read as ‘0’

R = Readable bit S = Settable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F72

DS39597B-page 28  2002 Microchip Technology Inc.

4.3 Reading the FLASH Program

Memory

To read a program memory location, the user must

write two bytes of the address to the PMADRL and

PMADRH registers and then set control bit, RD

(PMCON1<0>). Once the read control bit is set, the

progra m me mory F LASH con troller will use t he se cond

instruc tion cy cle afte r to read the data . This ca uses the

second instruction immediately following the “BSF

PMCON1,RD” instruction to be ignored. The data is

available in the very next cycle in the PMDATL and

PMDATH registers; therefore, it can be read as two

bytes in the following instructions. PMDATL and

PMDATH registers will hold this value until another

read, or until it is written to by the user (during a write

operation).

4.4 Operation During Code Protect

The FLASH program memory control can read any-

where within the program memory, whether or not the

program memory is code protected.

This does not compromise the code, because there is

no way to rewrite a portion of the program memory, or

leave con ten ts of a program me mo ry read in a register

while changing modes.

EXAMPLE 4-1: FLASH PROGRAM READ

TABLE 4-1: REGISTERS ASSOCIATED WITH PROGRAM FLASH

BANKSEL PMADRH ; Select Bank for PMADRH

MOVLW MS_PROG_EE_ADDR ;

MOVWF PMADRH ; MS Byte of Program Address to read

MOVLW LS_PROG_EE_ADDR ;

MOVWF PMADRL ; LS Byte of Program Address to read

BANKSEL PMCON1 ; Select Bank for PMCON1

BSF PMCON1, RD ; EE Read

;

NOP ; Any instructions here are ignored as program

NOP ; memory is read in second cycle after BSF PMCON1,RD

;

; First instruction after BSF PMCON1,RD executes normally

BANKSEL PMDATL ; Select Bank for PMDATL

MOVF PMDATL, W ; W = LS Byte of Program PMDATL

MOVF PMDATH, W ; W = MS Byte of Program PMDATL

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

10Dh PMADRL Address Register Low Byte xxxx xxxx uuuu uuuu

10Fh PMADRH ———Address Register High Byte xxxx xxxx uuuu uuuu

10Ch PMDATL Data Register Low Byte xxxx xxxx uuuu uuuu

10Eh PMDATH — — Data Register High Byte xxxx xxxx uuuu uuuu

18Ch PMCON1 —(1) ——————RD 1--- ---0 1--- ---0

Legend: x = unknown, u = unc hanged, r = reserved , - = unimpleme nted, read as ' 0'.

Shaded cells are not used during FLASH acc ess.

Note 1: This bit alwa ys reads as a ‘1’.

 2002 Microchip Technology Inc. DS39597B-page 29

PIC16F72

5.0 TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

•8-bit timer/counter

•Readable and writable

•8-bit software programmable prescaler

•Internal or external clock select

•Interrupt on overflow from FFh to 00h

•Edge select for external clock

Figure 5-1 is a block diagram of the T ime r0 module and

the prescaler shared with the WDT.

Additional information on the Timer0 module is

available in the PICmicro™ Mid-Range MCU Family

Reference Manual (DS33023).

5.1 Timer0 Operation

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In Timer mode, the Timer0 module will

increm ent ev ery ins tru cti on cycle (w i tho ut p r es ca ler). If

the TMR0 register is written, the increment is inhibited

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 registe r.

Counter mode is selected by setting bit T0CS

(OPTION<5>). In Counter mode, Timer0 will incre-

ment, either on every rising or falling edge of pin RA4/

T0CKI. The incrementing edge is determined by the

Timer0 Source Edge Select bit T0SE (OPTION<4>).

Clearing bit T0SE selects the rising edge. Restrictions

on the external clock input are discussed in detail in

Section 5.3.

The prescaler is mutually exclusively shared between

the Timer0 module a nd t he W a tchdo g T im er. The pres -

caler i s not readabl e or wr it able. Sectio n 5.4 d eta ils th e

operation of the prescaler.

5.2 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

TMR0IF (INTCON<2>). The interrupt can be masked

by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF

must be cleared in software by the Timer0 module

Interrupt Service Rou tin e, b efo re re -en abl ing thi s inter-

rupt. The TM R0 interrupt c annot awake n the proce ssor

from SLEEP, since the timer is shut-off during SLEEP.

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

RA4/T0CKI

T0SE

CLKO (= FOSC/4)

SYNC

Cycles TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

PSA

WDT Enable bit

Data Bus

Set Flag bi t T M R 0 IF

on Overflow

PSA

T0CS

PRESCALER

PIC16F72

DS39597B-page 30  2002 Microchip Technology Inc.

5.3 Using Timer0 with an External

Clock

When no pr escal er is used, t he ex tern al clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI, with the internal phase clocks, is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T0CKI to be high for at least 2 TOSC (and

a small RC delay of 20 ns) and low for at least 2 TOSC

(and a small RC delay of 20 ns). Refer to the electrical

specification of the desired device.

5.4 Prescaler

There i s only one pres caler a vailable , whic h is mutu ally

exclus ively shar ed between th e T imer0 mod ule and the

Watchdog Timer. A prescaler assignment for the

T i mer0 m odule m eans that t here i s no presc aler fo r the

Watchdog Timer, and vice-versa. This prescaler is not

readable or writable (see Figure 5-1).

The PSA and PS2:PS0 bit s (OP TION<3:0>) de termine

the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 regi ster (e.g., CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer. The

prescaler is not readable or writable.

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

Note: Writing to TMR0 when the prescaler is

assign ed to T imer0 , will clear th e prescaler

count but will not change the prescaler

assignment.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

01h,101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

0Bh,8Bh,

10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unkno wn, u = unc ha nge d, - = unimplemented locations read as ‘0’. Shaded cell s a re not us ed by Timer0.

 2002 Microchip Technology Inc. DS39597B-page 31

PIC16F72

6.0 TIMER1 MODULE

The Timer1 module timer/counter has the following

features:

•16-bit timer/counter

(Two 8-bit registers; TMR1H and TMR1L)

•Readable and writable (both registers)

•Internal or external clock select

•Interrupt on overflow from FFFFh to 0000h

•RESET from CCP module trigger

Timer1 has a control register, shown in Register 6-1.

Timer1 can be enabled/disabled by setting/clearing

control bit TMR1O N (T1CO N<0 >).

Figure 6-2 is a simplified block diagram of the Timer1

module.

Additional information on timer modules is available in

the PICmicro™ Mid-Range MCU Reference Manual,

(DS33023).

6.1 Timer1 Operation

Timer 1 can ope rate in one of these mo des :

•As a timer

•As a synchronous counter

•As an asynchronous counter

The Operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

In Timer mode, Timer1 increments every instruction

cycle. In Counter mode, it increments on every rising

edge of the external clock input.

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored.

Timer1 also has an internal “RESET input”. This

RESET can be generated by the CCP module

(Section 8.0).

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 =1:8 Prescale value

10 =1:4 Prescale value

01 =1:2 Prescale value

00 =1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled

0 = Oscillator is shut-off (The oscillator inverter is turned off to eliminate power drain.)

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = ‘0’.

bit 1 TMR1CS: T imer1 C loc k Source Sele ct bit

1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 O n bit

1 = Enables T i me r1

0 = S top s Timer1

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = B it is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F72

DS39597B-page 32  2002 Microchip Technology Inc.

6.2 Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS

(T1CON<1>) bit. In this mode, the input clock to the

timer is FOSC/4. The synchronize control bit T1SYNC

(T1CON<2>) has no effect, since the internal clock is

always in sync.

6.3 Timer1 Counter Operation

Timer1 may operate in Asynchronous or Synchronous

mode, depending on the setting of the TMR1CS bit.

When Timer1 is being incremented via an external

source, increments occur on a rising edge. Af ter Time r1

is enab led in Coun ter mode, the module must first have

a falling edge before the counter begins to increment.

6.4 Timer1 Operation in Synchr onized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In

this mode, the timer increments on every rising edge of

clock input on pin RC1/T1OSI when bit T1OSCEN is

set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN

is cl eare d.

If T1SYNC is cleared, then the external clock input is

synchronized with internal phase clocks. The synchro-

nization is done after the prescaler stage. The

prescaler stage is an asynchronous ripple counter.

In this configuration, during SLEEP mode, Timer1 will

not increment even if the external clock is present,

since the synchronization circuit is shut-off. The

prescaler, however, will contin ue to increment.

FIGURE 6-1: TIMER1 INCREMENTING EDGE

FIGURE 6-2: TIMER1 BLOCK DIAGRAM

T1CKI

(Default High)

T1CKI

(Default Low)

Note: Arrows indicate counter increments.

TMR1H TMR1L

T1OSC T1SYNC

TMR1CS

T1CKPS1:T1CKPS0 Q Clock

T1OSCEN

Enable

Oscillator(1)

FOSC/4

Internal

Clock

TMR1ON

On/Off

Prescaler

1, 2, 4, 8 Synchronize

det

Synchronized

Clock Input

RC0/T1OSO/T1CKI

RC1/T1OSI

Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.

Set Flag bit

TMR1IF on

Overflow TMR1

(2)

 2002 Microchip Technology Inc. DS39597B-page 33

PIC16F72

6.5 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during SLEEP and can

generate an inte rrupt on overflo w, that will w ake-u p the

processor. However, special precautions in software

are needed to read/write the timer (Section 6.5.1).

In Asynchronous Counter mode, Timer1 cannot be

used as a time base for capture or compare operations.

6.5.1 READING AND WRITING T IMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an e xternal asy nchronous cl ock will ens ure a valid

read (taken care of in hardware). However, the user

should keep i n min d that re ading t he 16-b it time r in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For write s, it is re commend ed that the us er simply stop

the timer and write the desired values. A write conten-

tion may occur by writing to the timer registers, while

the register is incrementing. This may produce an

unpredictable value in the timer register. Data in the

Timer1 register (TMR1) may become corrupted. Cor-

ruption occurs when the timer enable is turned off at the

same instant that a ripple carry occurs in the timer

module.

Reading the 16-bit value requires some care. Exam-

ples 1 2-2 an d 12-3 i n t he PIC micro™ Mid - Rang e MCU

Family Reference Manual (DS33023) show how to

read and write Timer1 when it is running in

Asynchronous mode.

6.6 Timer1 Oscillator

A crystal oscillator circuit is built between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control b it T1OSCEN (T1CON<3>). The osc illa-

tor is a low power oscillator rated up to 200 kHz. It will

continue to run during SLEEP. It is primarily intended

for a 32 kHz crystal. Table 6-1 shows the capacitor

selection for the Timer1 os cillator.

The Timer1 oscillator is identical to the LP oscillator.

The user m us t pro vi de a sof tware time delay to en su re

proper oscillator start-up.

T ABLE 6-1: CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

6.7 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR1 interrupt, if enabled, is generated on overflow,

which is latched i n interrupt f lag bit TMR1IF (PI R1<0>).

This interrupt can be enabled/disabled by setting/

clearin g TMR1 interrupt enable bit TMR1IE (PIE 1<0>).

6.8 Resetting Timer1 Using a CCP

Trigger Output

If the CCP module is configured in Compare mode to

generate a “special event trigger" signal

(CCP1M3:CCP1M0 = 1011), the signal will reset

Timer1 and start an A/D conversion (if the A/D module

is enabled).

T imer 1 must be co nfigured fo r either T i mer or Synch ro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this RESET operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

In this mode of o peration, the CCPR1H:CCPR1L regis-

ters pair effectively becomes the period register for

Timer1.

Osc Type Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 kHz 15 pF 15 pF

200 kHz 15 pF 15 pF

Thes e values are fo r de si gn guidanc e only.

Note 1: Higher capacitance increases the stability

of oscillator , but also increases the start-up

time.

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

Note: The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

PIC16F72

DS39597B-page 34  2002 Microchip Technology Inc.

6.9 Resetting Timer1 Register Pair

(TMR1H, TMR1L)

TMR1H an d TMR1L reg isters are not rese t to 00h on a

POR, or any o ther RESET, except by the CCP1 special

event triggers.

T1CON re gister is re set to 00h o n a Power-on Rese t or

a Brown-out Reset, which shuts off the timer and

leaves a 1:1 prescale. In all other RESETS, the register

is unaffected.

6.10 Timer1 Prescaler

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.

TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

0Bh,8Bh,

10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TM R1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

 2002 Microchip Technology Inc. DS39597B-page 35

PIC16F72

7.0 TIMER2 MODULE

The Timer2 module timer has the following features:

•8-bit timer (TMR2 register)

•8-bit period register (PR2)

•Readable and writable (both registers)

•Software programmable prescaler (1:1, 1:4, 1:16)

•Software programmable postscaler (1:1 to 1:16)

•Interrupt on TMR2 match of PR2

•SSP module optional use of TMR2 output to

generate clock shift

Timer2 has a control register, shown in Register 7-1.

Time r2 c an b e s hu t-off by clea ring c ontrol bi t T MR2O N

(T2CON<2>) to minimize power consumption.

Figure 7-1 is a simplified block diagram of the Timer2

module.

Additional information on timer modules is available in

the PICmicro™ Mid-Range MCU Reference Manual,

(DS33023).

7.1 Timer2 Operation

Timer2 can be used as the PWM time-base for PWM

mode of the CCP module.

The TMR2 register is readable and writable, and is

cleared on any device RESET.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits

T2CKPS1:T2CKPS0 (T2CON<1: 0>).

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

7.2 Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared

when any of the following occurs:

•A write to the TMR2 register

•A write to the T2CON register

•Any device RESET (Power-on Reset, MCLR ,

WDT Reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

7.3 Timer2 Interrupt

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon RESET.

7.4 Output of TMR2

The output of TMR2 (before the postscaler) is fed to the

Synchron ous Serial Port mod ule, which opti onally use s

it to generate a shift clock.

FIGURE 7-1: TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets Flag

TMR2 reg

Output(1)

RESET

Postscaler

Prescaler

PR2 reg

FOSC/4

1:1 1:16

1:1, 1:4, 1:1 6

bit TMR2IF

Note 1: TMR2 register output can be software

selected by the SSP module as a baud clock.

PIC16F72

DS39597B-page 36  2002 Microchip Technology Inc.

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 =1:1 Postscale

0001 =1:2 Postscale

0010 =1:3 Postscale

•

1111 =1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale S elect bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Address Name Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

0Bh,8Bh,

10Bh, 18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000

8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000

11h TMR2 Timer2 Module Register 0000 0000 0000 0000

12h T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

92h PR2 Timer2 Period Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

 2002 Microchip Technology Inc. DS39597B-page 37

PIC16F72

8.0 CAPTURE/COMPARE/ PWM

(CCP) MODULE

The CCP (C ap ture /Com p a r e/PW M) m od ule co nt ai ns a

16-bit register that can operate as a:

• 16-bit capture register

• 16-bit compare register

• PWM master/slave duty cycle register.

Table 8-1 shows the timer resources of the CCP

Module modes.

Capture/Compare/PWM Register1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP1. All are readable and writable.

Additional information on the CCP module is available

in the PICmicro™ Mid-Ra nge MCU Referenc e Manua l,

(DS33023).

TABLE 8-1: CCP MODE - TIMER

RESOURCE

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1

Timer2

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

bit 7-6 Unimplemented: Read as '0'

bit 5-4 CCPxX:CCPxY: PWM Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, set output on match (CCPxIF bit is set)

1001 = Compare mode, clear output on match (CCPxIF bit is set)

1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set,

CCPx pin is unaffected)

1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);

CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)

11xx = PWM mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F72

DS39597B-page 38  2002 Microchip Technology Inc.

8.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit val ue of the TMR1 register when an event occu rs

on pin RC2/CCP1. An event is defined as:

•Every falling edge

•Every rising edge

•Every 4th rising edge

•Every 16th rising edge

An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR1<2>) is set. It must

be cleared in software. If another capture occurs before

the value in register CCPR1 is read, the old captured

value is overwritten by the new captured value.

8.1.1 CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be

configured as an input by setting the TRISC<2> bit.

FIGURE 8-1: CAP TURE MODE

OPERATION BLOCK

DIAGRAM

8.1.2 T IMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode for the CCP module to use the

capture feature. In Asynchronous Counter mode, the

capture operation may not work.

8.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit CCP1IF, following any such

change in Operating mode .

8.1.4 CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in Capture mode,

the prescaler counter is cleared. This means that any

RESET will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleare d, therefore , the first cap ture may be from

a non-zero prescaler. Example 8-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

EXAMPLE 8-1: CHANGIN G BETWEEN

CAPTURE PRESCALERS

Note: If the RC2/CCP1 is configured as an out-

put, a write to the por t can cause a captu re

condition.

CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

(PIR1<2>)

Capture

Enable

Q’sCCP1CON<3:0>

RC2/CCP1

Prescaler

÷ 1, 4, 16

and

edge detect

pin CLRF CCP1CON ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load the W reg with

; the new prescaler

; mode value and CCP ON

MOVWF CCP1CON ; Load CCP1CON with

; this value

 2002 Microchip Technology Inc. DS39597B-page 39

PIC16F72

8.2 Compare Mode

In C ompare mo de, t he 16- bit CC PR1 re gist er va lue is

constantly compared against the TMR1 register pair

value. Whe n a match occu rs, the RC2/CCP1 pin is:

•Driven High

•Driven Low

•Remains Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

The outp ut may beco me inverted wh en the mo de of the

module is changed from Compare/Clear on Match

(CCPxM<3:0> = ‘1001’) to Compare/Set on Match

(CCPxM<3:0> = ‘1000’). This may occur as a result of

any operation t hat selectiv el y c le ars bit C CPxM 0, s uc h

as a BCF instruction.

When this condition occurs, the output becomes

inverted when the i ns truc tio n i s ex ecuted. It wi ll rem ai n

inverted for all following Compare operations, until the

module is reset.

FIGURE 8-2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

8.2.1 CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an

output by clearing the TRISC<2> bit.

8.2.2 TIMER1 MODE SEL ECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode, if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

8.2.3 SOFTWARE INTERRUPT MODE

When genera te software in terrupt is chose n, the CCP1

pin is not af fected. On ly a CCP interrupt is generated (if

enabled).

8.2.4 SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

that may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 re giste r pai r. Thi s al low s the CC PR 1 reg is ter t o

ef fectively b e a 16-bit progra mmable pe riod registe r for

Timer1.

The special trigger output of CCP1 resets the TMR1

module is enabled).

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

ROutput

Logic

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<2>)

Match

RC2/CCP1

TRISC<2> CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will:

•RESET Timer1, but not set interrupt flag bit TMR1IF

(PIR1<0>)

•Set bit GO/DONE (ADCON0<2>) bit, which starts an A/D

conversion

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default l ow le vel . Thi s i s n ot th e da t a la tc h.

Note: The special event trigger from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

PIC16F72

DS39597B-page 40  2002 Microchip Technology Inc.

TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

0Bh,8Bh

10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000

8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh T MR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h CCPR1L Capture/Com pare/PWM Register1 (LSB ) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Ti mer1.

 2002 Microchip Technology Inc. DS39597B-page 41

PIC16F72

8.3 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pin is multiplexed with the PORTC dat a latch,

the TRISC<2> bit must be cleared to make the CCP1

pin an output.

Figure 8-3 shows a simplified block diagram of the

CCP module in PWM mo de.

For a st ep by step pr ocedure on h ow to set up the CCP

module for PWM operation, see Section 8.3.3.

FIGURE 8-3: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 8-4) has a time-base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 8-4: PWM OUTPUT

8.3.1 PWM PE RIOD

The PWM p eriod is specifi ed by writing to the PR 2 reg-

ister. The PWM period can be calculated using the

formula in Equa tio n 8-1.

EQUATION 8-1: PWM PERIOD

PWM frequency is defined as 1 / [PWM period].

When TM R2 is equal to PR2, t he following three event s

occur on the next increment cycle:

•TMR2 is cleared

•The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

•The PWM duty cycle is latched from C CPR1L into

CCPR1H

8.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available: the CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. Equation 8-2 is used to

calculate the PWM duty cycle in time.

EQUATION 8-2: PWM DUTY CYCLE

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read only register.

The CCPR1H register and a 2-bit internal latch are

used to dou ble buf fer th e PWM duty cycle. Thi s doubl e

buffering is essential for glitchl ess PWM operation.

When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCP1 pin is cleared.

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

TRISC<2>

RC2/CCP1

Note 1: 8-bit timer is concatenated with 2-bit internal Q cloc k

or 2 bits of the prescaler to create 10-bit time-base.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR 2

Note: The Timer2 postsc al er (s ee Sec ti on 7.0) is

not used in the determination of the PWM

frequenc y . T he posts caler coul d be used to

have a servo update rate at a different

frequency than the PWM output.

PWMperiod= [(PR2)+1]•4•TOSC •

(TMR 2 pr e sc ale value)

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC •(TMR2 prescale value)

PIC16F72

DS39597B-page 42  2002 Microchip Technology Inc.

Maximum PWM resolution (bits) for a given PWM

frequency is calculated using Equation 8-3.

EQUATION 8-3: PWM MAX RESOLUTION

For a sample PWM period and duty cycle calculation,

see the PICmicro™ Mid-Range MCU Reference

Manual (DS33023).

8.3.3 SET-UP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PW M peri od by w riting to the PR2 r egiste r.

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the

TRISC<2> bit.

4. Set the TMR2 prescale v alue and enable T imer2

by writing to T2CON.

5. Configure the CCP1 modu le for PWM operation.

TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

TABLE 8-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Note: If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

log ( FPWM

log(2)

FOSC )bits

PWM Maximum Resolution =

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 5.5

Ad d r ess Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

0Bh,8Bh

10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000

8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

1 1h TMR2 Timer2 Modu le Regist er 0000 0000 0000 0000

92h PR2 Ti mer2 Module Perio d Regist er 1111 1111 1111 1111

12h T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.

 2002 Microchip Technology Inc. DS39597B-page 43

PIC16F72

9.0 SYNCHRONOUS SERIAL PORT

(SSP) MODULE

9.1 SSP Module Overview

The Synchronous Serial Port (SSP) module is a serial

interface useful for communicating with other periph-

eral or microcontroller devices. These peripheral

devices may be Serial EEPROMs, shift registers, dis-

play d riv ers, A/D converte rs, et c. The SSP m odu le ca n

operate in one of two modes:

•Serial Peripheral Interface (SPI)

•Inter-Integrated Circuit (I2C)

An overview of I2C operations and additional informa-

tion on the SSP module can be found in the PICmicro™

Mid-Range MCU Family Reference Manual

(DS33023).

Refer to Application Note AN578, “Use of the SSP

Module in the I2C Multi-Master Environment.”

9.2 SPI Mode

This section contains register definitions and

operational characteristics of the SPI module.

SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. T o accomplish

communication, typically three pins are used:

•Serial Data Out (SDO) RC5/SDO

•Serial Data In (SDI) RC4/SDI/SDA

•Serial Clock (SCK) RC3/SCK/SCL

Additionally, a fourth pin may be used when in a Slave

mode of operation:

•Slave Select (SS) RA5/AN4/SS

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits in the SSPCON register (SSPCON<5:0>)

and SSPSTAT<7:6>. These control bits allow the

follow ing to be speci fie d:

•Master mode (SC K is the clock output)

•Slave mode (SCK is the clock input)

•Clock Polarity (IDLE state of SCK)

•Clock edge (output data on rising/falling edge of

SCK)

•Clock Rate (Ma s ter mode only)

•Slave Select mode (Slave mode only)

PIC16F72

DS39597B-page 44  2002 Microchip Technology Inc.

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A PSR/WUA BF

bit 7 bit 0

bit 7 SMP: SPI Data Input Sample Phase bits

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time (Microwire®)

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

I2 C mode:

This bit must be maintained clear

bit 6 CKE: SPI Clock Edge Select bits (Figure 9-2, Figure 9-3, and Figure 9-4)

SPI mode, CKP = 0:

1 = Data transmitted on rising edge of SCK (Microwire alternate)

0 = Data transmitted on falling edge of SCK

SPI mode, CKP = 1:

1 = Data transmitted on falling edge of SCK (Microwire default)

0 = Data transmitted on rising edge of SCK

I2 C mode:

This bit must be maintained clear

bit 5 D/A: Data/Address bit (I2C mode only)

1 = Indicates th at the last by te received or transmitted was data

0 = Indicate s that the last byte receiv ed or transmitted was address

bit 4 P: STOP bit (I2C mode only) – This bit is cleared when the SSP module is disabled, or when

the START bit is detected last. SSPEN is cleared.

1 = Indicates that a STOP bit has been detected last (this bit is ‘0’ on RESET)

0 = STOP bit was not detected last

bit 3 S: START bit (I2C mode only) – This bit is cleared when the SSP module is disabled, or when

the STOP bit is detected last. SSPEN is cleared.

1 = Indicates that a START bit has been detected last (this bit is ‘0’ on RESET)

0 = START bit was not detected last

bit 2 R/W: Rea d/Write Informa tion bit (I2C mode on ly) – This bit hold s the R/W bit information fo llow-

ing the last address match. This bit is only valid from the address match to the next START bit,

STOP bit, or ACK bit.

1 =Read

0 = Write

bit 1 UA: Update Address bit (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

Receive (SPI and I2 C modes):

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Transmit (I2 C mode only):

1 = Transmit in progress, SSPBUF is full

0 = Transmit complete, SSPBUF is empty

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS39597B-page 45

PIC16F72

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

bit 7 WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be

cleared i n softwar e)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit

In SPI mode:

1 = A new byte is receive d while the SSPBUF register is still ho lding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user

must read the SSPBUF, even if only transmit ting dat a , to avo id settin g ov erfl ow. In Master

mode, the overflow bit is not set since each new reception (and transmission) is initiated

by writing to the SSPBUF register.

0 = No overflow

In I2 C mode:

1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV

is a "don’t care" in Transmit mode. SSPOV must be cleared in software in either mode.

0 = No overflow

bit 5 SSPEN: Synchronous Serial Port Enable bit

In SPI mode:

1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins

0 = Disables serial port and configures these pins as I/O port pins

In I2 C mode:

1 = Enables the serial port and configures the SDA and SCL pins as serial port pins

0 = Disables serial port and configures these pins as I/O port pins

In both modes, when enabled, these pins must be properly configured as input or output.

bit 4 CKP: Clock Polarity Select bit

In SPI mode:

1 = IDLE state for clock is a high level (Microwire® default)

0 = IDLE state for clock is a low level (Microwire alternate)

In I2 C mode:

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch - used to ensure data setup time)

bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000 = SPI Master mode, clock = FOSC/4

0001 = SPI Master mode, clock = FOSC/16

0010 = SPI Master mode, clock = FOSC/64

0011 = SPI Master mode, clock = TMR2 output/2

0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101 = SPI Slave mod e, clo ck = SCK p in. SS pi n c ont rol dis ab led . SS can be used as I/O pin.

0110 =I

2C Slave mode, 7-bit address

0111 =I

2C Slave mode, 10-bit address

1011 =I

2C firmware controlled Master mode (Slave IDLE)

1110 =I

2C Slave mode, 7-bit address with START and STOP bit interrupts enabled

1111 =I

2C Slave mode, 10-bit address with START and STOP bit interrupts enabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F72

DS39597B-page 46  2002 Microchip Technology Inc.

FIGURE 9-1: SSP BLOCK DIAGRAM

(SPI MODE) To enable the serial port, SSP enable bit, SSPEN

(SSPCON<5>) must be set. To reset or reconfigure SPI

mode, clear bit SSPEN, re-initialize the SSPCON reg-

ister, and then s et bit SSPEN. This config ures the SDI,

SDO, SCK, and SS pins as serial port pins. For the pins

to behave as the serial port function, they must have

their data direction bits (in the TRISC register)

appropriately programmed. That is:

•SDI must have TRISC<4> set

•SDO must have TRISC<5> cleared

•SCK (Master mode) must have TRISC<3>

cleared

•SCK (Slave mode) must have TRISC<3> set

•SS must have TRISA<5> set and ADCON must

be configured such that RA5 is a digital I/O

TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION

Read Write

Internal

Data Bus

RC4/SDI/SDA

RC5/SDO

RA5/AN4/SS

RC3/SCK/

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0 Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 Output

TCY

Prescaler

4, 16, 64

TRISC<3>

Edge

Select

SCL

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPCON<3:0> = 0100),

the SPI module will reset if the SS pin is

set to VDD.

2: If the SPI is used in Slave mode with

CKE = ‘1’, then the SS pin control mu st be

enabled.

Addr e s s Na me Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

0Bh,8Bh

10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000

8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

13h SS PB UF S ynchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111

94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.

 2002 Microchip Technology Inc. DS39597B-page 47

PIC16F72

FIGURE 9-2: SPI MODE TIMING, MASTER MODE

FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)

FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)

SCK (CKP = 0,

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SDI (SMP = 1)

SCK (CKP = 0,

SCK (CKP = 1,

SDO

bit7

bit7 bit0

bit0

CKE = 0)

CKE = 1)

CKE = 0)

CKE = 1)

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

SS (optional)

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

PIC16F72

DS39597B-page 48  2002 Microchip Technology Inc.

9.3 SSP I 2C Mode Operation

The SSP module in I2C m ode fully i mplement s all slave

functions, except general call support and provides

interrupts on START and STOP bits in hardware to

facilitate firmware implementations of the master func-

tions. The SSP modu le impl ements th e S t andard m ode

specifications, as well as 7-bit and 10-bit addressing.

T wo pins are used for da ta transfer . These are the RC3/

SCK/SCL pin, which is the clock (SCL), and the RC4/

SDI/S DA pin, which i s the data ( SDA). T he user mu st

configure these pins as inputs or outputs through the

TRISC<4:3> bits.

The SSP mod ule fun ctions a re enabl ed by settin g SSP

Enable bit SSPEN (SSPCON<5>).

FIGURE 9-5: SSP BLOCK DIAGRAM

(I2C MODE)

The SSP module has five registers for I2C operation:

•SSP Control Register (SSPCON)

•SSP Status Register (SSPSTAT)

•Serial Receive/Transmit Buffer (SSPBUF)

•SSP Shift Register (SSPSR) - Not directly

accessible

•SSP Address Register (SSPADD)

The SSPCON register allows control of the I2C opera-

tion. Four mode selection bits (SSPCON<3:0>) allow

one of the following I2C modes to be selected:

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

•I2C Slave mode (7-bit address), with START and

STOP bit interrupts enabled

•I2C Slave mo de (10-bit address) , with START and

STOP bit interrupts enabled

•I2C Firmware controlled Master operation, Slave

is IDLE

Selection of any I2C mode, with the SSPEN bit set,

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits.

Additional information on SSP I2C operation may be

found in the PICmicro™ Mid-Range MCU Reference

Manual (DS33023).

9.3.1 SLAVE MODE

In Slave mod e, the SCL and SDA pin s must be co nfig-

ured as input s (TRISC<4 :3> set). The SSP module will

override the input state with the output data when

required (slave -tran smit ter).

When an address is matched or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse, and

then load the SSPBUF reg is ter wi th th e re ceive d valu e

currently in the SSPSR register.

Either or both of the following conditions will cause the

SSP module not to give this ACK pulse.

a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

b) The overflow b it SSPOV (SSPCON<6>) was set

before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set.

Table 9-2 shows what happens when a data transfer

byte is received, given the status of bits BF and

SSPOV. The shaded cells show the condition where

user softwa re did not properl y clear the ove rflow condi-

tion. Flag bit BF is cleared by reading the SSPBUF

The SCL clock input must have a minimum high and

low fo r pro per ope rati on. The high an d l ow ti me s of the

I2C specification, as well as the requirement of the SSP

module are shown in timing parameter #100 and

parameter #101.

9.3.1.1 Addressing

Once the SSP module has been enabled, it waits for a

START conditi on to occur. Following the START condi-

tion, the eight bits are shifted into the SSPSR register.

All incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

a) The SSPSR register value is loaded into the

SSPBUF register.

b) The buffer full bit, BF is set.

c) An ACK pulse is generated.

d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set

(interrupt is generated, if enabled) - on the falling

edge of the ninth SCL pulse.

Read Write

SSPSR Reg

Match Detect

SSPADD Reg

START and

ST OP Bit Det e ct

SSPBUF Reg

Internal

Data Bus

Addr Match

Set, RESET

S, P Bits

(SSPSTAT Reg)

RC3/SCK/SCL

RC4/

Shift

Clock

MSb

SDI/ LSb

SDA

 2002 Microchip Technology Inc. DS39597B-page 49

PIC16F72

In 10-bit Address mode, two address bytes need to be

received by the slave device. The five Most Significant

bits (MSbs) of the first address byte specify if this is a

10-bit address. Bit R/W (SSPSTAT<2>) must specify a

write so the slave device will receive the second

address byte. For a 10-bit address the first byte would

equal ‘1111 0 A9 A8 0’, where A9 and A8 are the

two MSbs of the address.

The sequence of events for 10-bit address is as

follows, with steps 7- 9 for slave-transmitter:

1. Receive first (high) byte of address (bits SSPIF,

BF, and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

4. Receive second (low) byte of address (bits

SSPIF, BF, and UA are set).

5. Update the SSPADD registe r with the first (high)

byte of Ad dress , if match releas es SCL li ne, thi s

will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

7. Receive Repeated START condition.

8. Receive first (high) byte of address (bits SSPIF

and BF are set).

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

9.3.1.2 Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overflow condition exists, then

a no Acknowledge (ACK) pulse is given. An overflow

condition is indicated if either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON<6>) is set.

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the byte.

9.3.1.3 Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit, and pin RC3/SCK/SCL is held

low. The transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR regis-

ter. Then pin RC 3 /SCK /SCL s ho uld be e na ble d by se t-

ting bit CKP (SSPCON<4>). The master device must

monitor the SCL pin prior to asserting another clock

pulse. T he slave devices may be h olding of f th e master

device by stretching the clock. The eight data bits are

shifted out on the falling edge of the SCL input. This

ensures that the SDA signal is valid during the SCL

high time (Figure 9-7).

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. Flag bit SSPIF is set on the falling edge of

the ninth clock pulse.

As a s lav e-t rans mi tte r, the ACK pulse from the mast er-

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then

the dat a tran sfer is com plete. When th e ACK is latched

by the slave device, the slave logic is reset (resets

SSPSTAT register) and the slav e de vi ce then mon itor s

for anoth er occurrence of th e ST AR T bit. If th e SDA line

was low (ACK), the transmit data must be loaded into

the SSPBUF register , which also loads the SSPSR reg-

ister. Then, pin RC3/SCK/SCL should be enabled by

setting bit CKP.

TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received SSPSR → SSPBUF Generate ACK Pulse Set bit SSPIF

(SSP Interrupt occurs if enabled)

BF SSPOV

00 Yes Yes Yes

10 No No Yes

11 No No Yes

0 1 No No Yes

Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.

PIC16F72

DS39597B-page 50  2002 Microchip Technology Inc.

FIGURE 9-6: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

FIGURE 9-7: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1SDA

SCL 123456789123456789123

Bus Master

terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK Receiving Data

Receiving Data D0

D3D4

D6D7

ACK

R/W = 0

Receiving Address

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent.

SDA

SCL

SSPIF (PIR 1<3>)

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Transmitting DataR/W = 1Receiving Address

123456789 123456789 P

Cleared in softwar e

SSPBUF is written in software From SSP Interrupt

Service Routine

Set bit after writing to SSPBUF

SData is

sampled SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written to

before the CKP bit can be set)

 2002 Microchip Technology Inc. DS39597B-page 51

PIC16F72

9.3.2 MASTER MODE OPERATIO N

Master mode operation is supported in firmware using

interr upt gen eration on th e detecti on of th e START an d

STOP conditions. The STOP (P) and START (S) bits

are cleared from a RESET or when the SSP module is

disabl ed. The STO P (P) and START (S) bit s will toggl e,

based on the START and STOP conditions. Control of

the I2C bus may be taken when the P bit is set, or the

bus is IDLE and both the S and P bits are clear.

In Master mode operation, the SCL and SDA lines are

manipulated in firmware by clearing the corresponding

TRISC<4:3> bit(s). The output level is always low, irre-

spective of the value(s) in PORTC<4:3>. So, when

transmitting data, a ‘1’ data bit must have the

TRISC<4> bit set (input) and a ‘0’ data bit must have

the TRISC<4 > bit cl eare d (output). The sa me sce nari o

is true for the SCL line with the TRISC<3> bit.

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP Interrupt if enabled):

•START condition

•STOP condition

•Data transfer byte transmitted/received

Master mode operation can be done with either the

Slave mod e IDLE (SSPM3:SSPM0 = 1011), or with the

Slave m ode ac tiv e. W he n bo th M as ter mo de oper atio n

and Slave modes are used, the software needs to

differentiate the source(s) of the interrupt.

For more information on Master mode operation, see

AN554 - Software Implementation of I2C Bus Master.

9.3.3 MULTI-MASTER MODE OPERATION

In Multi-Master mode operation, the interrupt genera-

tion on the detection of the START and STOP condi-

tions allows the determination of when the bus is free.

The STOP (P) and START (S) bits are cleared from a

RESET or when the SSP module is disabled. The

STOP (P) an d START (S) bi ts will tog gl e, b ased o n th e

START and STOP conditions. Control of the I2C bus

may be taken when bit P (SSPSTAT<4>) is set, or the

bus is IDLE and both the S and P bits clear. When the

bus is busy, enabling the SSP interrupt will generate

the interrupt when the STOP condition occurs.

In Mul ti -Mast er mode o per atio n, t he SD A li ne m ust be

monitore d to see if the signa l le vel is the e xpe cted out-

put level. This check only needs to be done when a

high lev el is output. If a high lev el is expec ted and a low

level is present, the device needs to release the SDA

and SCL line s (set TRISC<4:3 >). There are two sta ges

where this arbitration can be lost:

•Address Transfer

•Data Transfe r

When the slave logic is e nab le d, t he Slave de vic e co n-

tinues to receive. If arbitration was lost during the

address transfer stage, communication to the device

may be in progr ess. If addres sed, a n ACK puls e wi ll be

generated. If arbitration was lost during the data trans-

fer stage, the device will need to retransfer the data at

a later time.

For more information on Multi-Master mode operation,

see AN578 - Use of the SSP Module in the I2C

Multi-Master Environment.

TABLE 9-3: REGISTERS ASSOCIATED WITH I2C OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all othe r

RESETS

0Bh, 8Bh,

10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000

8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

93h SSPADD Syn chronous Serial Port (I2C mode) Ad dress Regist er 0000 0000 0000 0000

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

94h SSPSTAT SMP(1) CKE(1) D/A PSR/WUA BF 0000 0000 0000 0000

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.

Shaded cells are not used by SSP module in SPI mode.

Note 1: M aintain these bits clear in I2C mode.

PIC16F72

DS39597B-page 52  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. DS39597B-page 53

PIC16F72

10.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The analog-to-digital (A/D) converter module has five

inputs for the PIC16F72.

The A/D allo ws co nversion of an anal og inp ut signal to

a corres pondi ng 8- bit di git al num ber. The output of the

sample and hold is the input into the converter, which

generates the result via successive approximation. The

analog reference voltage is software selectable to

either the device’s positive supply voltage (VDD) or the

voltage level on the RA3/AN3/VREF pin.

The A/D converter has a unique feature of being able

to opera te while th e device i s in SLEEP mod e. To oper-

ate in SLEEP, the A/D conversion clock must be

derived from the A/D’s internal RC oscillator.

The A/D module has three registers:

•A/D Result Register ADRES

•A/D Control Register 0 ADCON0

•A/D Control Register 1 ADCON1

A device RESET forces all registers to their RESET

state. This forces the A/D module to be turned off and

any conve r si on is aborted .

The ADCON0 register, shown in Register 10-1, con-

trols the operation of the A/D module. The ADCON1

tions of the port pins. The port pins can be configured

as analo g input s (RA3 ca n also be a volta ge referenc e)

or a digital I/O.

For more information on use of the A/D Converter, see

AN546 - Use of A/D Converter, or refer to the

PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON

bit 7 bit 0

bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits

00 =F

OSC/2

01 =F

OSC/8

10 =F

OSC/32

11 =F

RC (clock derived from the internal A/D module RC oscillator)

bit 5-3 CHS<2:0>: Analog Channel Select bits

000 = Channel 0, (RA0/AN0)

001 = Channel 1, (RA1/AN1)

010 = Channel 2, (RA2/AN2)

011 = Channel 3, (RA3/AN3)

100 = Channel 4, (RA5/AN4)

bit 2 GO/DONE: A/D Conversion Status bit

If ADON = 1:

1 = A/D conversion in progress (setting this bit starts the A/D conversion)

0 = A/D c onversion n ot in progress (this bit is automatically cleared by h ardware when the A/D

conversion is complete)

bit 1 Unimplemented: Read as ‘0’

bit 0 ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shut-off and consumes no operating current

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F72

DS39597B-page 54  2002 Microchip Technology Inc.

The ADRES re gister co ntains the resul t of the A/D co n-

version. When the A/D conversion is complete, the

result is loaded into the ADRES register , the GO/DONE

bit (ADCON0<2>) is cleared, and A/D interrupt flag bit

ADIF is set. The block diagram of the A/D module is

shown in Figure 10-1.

The value in the ADRES register is not modified for a

Power-on Reset. The ADRES register will contain

unknown data after a Power-on Reset.

After the A/D module has been configured as desired,

the sele cted cha nne l m ust be acq uire d b efore the co n-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 10.1.

After this acquisition time has elapsed, the A/D

conversion can be started.

The following steps should be followed for doing an

A/D conver sion:

1. Configure the A/D module:

•Config ure ana log pins /vo ltage refer enc e and

digital I/O (ADCON1)

•Select A/D input channel (ADCON0)

•Select A/D conversion cl oc k (ADCON0)

•Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

•Clear ADIF bit

•Set ADIE bit

•Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

•Set GO/DONE bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

•Polling for the GO/DONE bit to be cleared

•Waiting for the A/D interrupt

6. Read A/D Result register (ADRES), clear bit

ADIF if required.

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0

bit 7 bit 0

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 PCFG<2:0>: A/D Port Configuration Control bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

A = Analog input D = Digital I/O

PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 VREF

000 AAAAAVDD

001 AAAAVREF RA3

010 AAAAAV

011 AAAAVREF RA3

100 AADDAV

101 AADDVREF RA3

11x DDDDDV

 2002 Microchip Technology Inc. DS39597B-page 55

PIC16F72

FIGURE 10-1: A/D BLOCK DIAGRAM

FIGURE 10-2: ANALOG INPUT MODEL

(Input Voltage)

VAIN

VREF

(Reference

Voltage)

VDD

PCFG2:PCFG0

CHS2:CHS0

000 or

010 or

100

001 or

011 or

101

RA5/AN4

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

100

011

010

001

000

A/D

Converter

CPIN

Rs ANx

5 pF

VDD

VT = 0.6 V

VT = 0.6 V I leakage

RIC ≤ 1 k

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567891011

( kΩ )

VDD

= 51.2 pF

± 500 nA

Legend: CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage c urrent at the pin due to

= interconnec t resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

PIC16F72

DS39597B-page 56  2002 Microchip Technology Inc.

10.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 10-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance va rie s over the dev ice vol tag e

(VDD). The sour ce impedanc e af fects th e offse t voltag e

at the analog input (due to pin leakage current).

The maximum recommended impedance for ana-

log sources is 10 kΩ. After the ana log input chann el is

selected (changed), this acquisition must be done

before the conversion can be started.

To calculate the minimum acquisition time, TACQ, see

the PICmicro™ Mid-Range MCU Reference Manual,

(DS3302 3). In gen eral , ho wev er, given a max of 10 kΩ

and at a temperature of 100°C, TACQ will be no more

than 16 µs.

10.2 Selecting the A/D Conversion

Clock

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 9.0 TAD per 8-bit conversion.

The source of the A/D conversion clock is software

selectable. The four possible options for TAD are:

•2T

OSC

•8TOSC

•32 TOSC

•Internal RC oscillator (2 - 6 µs)

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

as small as possible, but no less than 1.6 µs and not

greater than 6.4 µs.

Table 10-1 shows the resultant TAD t im es de riv e d f rom

the device operating frequencies and the A/D clock

sour ce se lec ted .

10.3 Configuring Analog Port Pins

The ADCON1, and TRISA registers control the opera-

tion of the A/D port pins. The port pins that are desired

as analog inputs must have their corresponding TRIS

bits set (input). If the TRIS bit is cleared (output), the

digital output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS<2:0> bits and the TRIS bits .

10.4 A/D Conversions

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The ADRES register will

NOT be updated with the partially completed A/D con-

version sample. That is, the ADRES register will con-

tinue to contain the value of the last completed

conversio n (or th e last v alue wri tten to the AD RES reg-

ister). Aft er t he A/D c onv ers io n i s abo rted , a 2 TAD wait

is required before the next acquisition is started. After

this 2 TAD wait, an acquisition is automatically started

on the selected channel. The GO/DONE bit can then

be set to start the conversion.

TABLE 10-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))

Note 1: When reading the port register, all pins

configured as analog input channels will

read as cleared (a low level). Pins config-

ured as digital inputs, will convert an

analog input. Analog levels on a digitally

configured input will not affect the

conversion accuracy.

2: Analog le vels on any pin that is defined as

a digital input (including the AN4:AN0

pins), may cause the input buffer to

consume current out of the device

specification.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

AD Clock Source (TAD) Maximum Device Frequency

Operation ADCS<1:0> Max.

2 TOSC 00 1.25 MHz

8 TOSC 01 5 MHz

32 TOSC 10 20 MHz

RC(1, 2) 11 (Note 1)

Note 1: The RC source has a typical TAD time of 4 µs, but can vary between 2-6 µs.

2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only

recommended for SLEEP operation.

 2002 Microchip Technology Inc. DS39597B-page 57

PIC16F72

10.5 A/D Operation During SLEEP

The A/D module can operate during SLEEP mode. This

requires that the A/D clock source be set to RC

(ADCS1:ADCS0 = 11). When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the SLEEP

instruction to be executed, which eliminates all digital

switchi ng noise fro m the conv ersion. Whe n the conver-

sion is completed, the GO/DONE bit will be cleared,

and the result loaded into the ADRES register. If the

A/D interrupt is enabled, the device will wake-up from

SLEEP. If the A/D interr upt is not enabled, the A/D mod-

ule will then be turned off, although the ADON bit will

remain set.

When the A/D clock sour ce is anoth er clock optio n (not

RC), a SLEEP instruction will cause the present conver-

sion t o be aborte d and the A/D mod ule to be turned of f,

though the ADON bit will remain set.

Turnin g off the A/D places the A/D module in it s lowes t

current consumption state.

10.6 Effects of a RESET

A device RESET forces all registers to their RESET

state. The A/D module is disabled and any conversion

in progres s is aborted. All A/D inp ut pins are confi gured

as analog inputs.

The ADRES register will contain unknown data after a

Power-on Reset.

10.7 Use of the CCP Trigger

An A/D convers ion can be st arted by th e “special event

trigger” of the CCP1 module. This requires that the

CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-

gram med as 1011 an d th at th e A/D m od ule is enabled

(ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, s tarting t he A/D conversi on,

and the Timer1 counter will be reset to zero. Ti mer1 is

reset to au tomati cally rep eat th e A/D ac quisi tion p eriod

with minim al software overhea d (moving the ADRES to

the desired location). The appropriate analog input

channel must b e selecte d and the mi nimum ac quisitio n

done before the “special event trigger” sets the

GO/DONE bit (start s a conversi on).

If the A/D module is not enabled (ADON is cleared),

then the “special event trigger” will be ignored by the

A/D module, but will still reset the Timer1 counter.

TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH A/D

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC

(ADCS1:ADCS0 = 11). To perform an A/D

conversion in SLEEP, ensure the SLEEP

instruction immediately follows the

instruction that sets the GO/DONE bit.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

0Bh,8Bh

10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON 0000 00-0 0000 00-0

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000

85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.

PIC16F72

DS39597B-page 58  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. DS39597B-page 59

PIC16F72

11.0 SPECIAL FEATURES OF THE

CPU

These d evices have a host of features intended to max-

imize system reliability, minimize cost through elimina-

tion of external components, provide power saving

Operating modes and offer code protection:

•Oscillato r Selection

•RESET

- Pow er- on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

•Interrupts

•Watchdog Timer (WDT)

•SLEEP

•Code Protection

•ID Locations

•In-Circuit Serial Programming

These devices have a Watchdog Timer, which can be

enabled or dis abled using a con figurat ion bi t. It runs of f

its own RC oscillator for added reliability.

There are two timers that offer necessary delays on

power-up. One is the Oscillator Start-up Timer (OST),

intended to keep the chip in RESET until the crystal

oscillator is stable. The other is the Power-up Timer

(PWRT), which provides a fixed delay of 72 ms (nomi-

nal) on pow er-up on ly. It is designed to keep th e par t in

RESET while the power supply stabilizes, and is

enabled or disabled using a configuration bit. With

these two timers on-chip, most applications need no

external RESET circuitry.

SLEEP mode is designed to offer a very low current

Power-down mode. The user can wake-up from

SLEEP through external RESET, Watchdog Timer

Wake-up, or through an interrupt.

Several oscillator options are also made available to

allow the part to fit the application. The RC oscillator

option saves system cost while the LP crystal option

saves power. Configuration bits are used to select the

desired oscillator mode.

Additional information on special features is available

in the PICmicro™ Mid-Range Reference Manual

(DS33023).

11.1 Configuration Bits

The configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’), to select vari-

ous device configurations. These bits are mapped in

program memory location 2007h.

The user will note that address 2007h is beyond the

user program memory space, which can be accessed

only during programming.

PIC16F72

DS39597B-page 60  2002 Microchip Technology Inc.

U-1 U-1 U-1 U-1 U-1 U-1 U-1 u-1 U-1 u-1 u-1 u-1 u-1 u-1

———————BOREN —CP PWRTEN WDTEN F0SC1 F0SC0

bit13 bit0

bit 13-7 Unimplemented: Read as ‘1’

bit 6 BOREN: Brown-out Reset Enable bit(2)

1 = BOR enabled

0 = BOR disabled

bit 5 Unimplemented: Read as ‘1’

bit 4 CP: FLASH Program Memory Code Protection bit

1 = Code protection off

0 = All memory locations code protected

bit 3 PWRTEN: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 2 WDTEN: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0 FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh.

2: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of

the value of bit PWRTEN. Ensure the Power-up Timer is enabled any time Brown-out

Reset is enabled.

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’

- n = Value when device is unprogrammed u = Unchanged from programmed state

 2002 Microchip Technology Inc. DS39597B-page 61

PIC16F72

11.2 Oscillator Configurations

11.2.1 OSCILLATOR TYPES

The PIC16F72 can be operated in four different Oscil-

lator modes. The user can program two configuration

bits (FOSC1 and FOSC0) to select one of these four

modes:

•LP Low Power Crystal

•XT Crystal/Resonator

•HS High Speed Crystal/Resonator

•RC Resistor/Capacitor

11.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In XT, LP or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKI and OSC2/CLKO pins

to establish oscillation (Figure 11-1). The PIC16F72

oscill ato r design require s the use of a p a r al lel cut cry s-

ta l. Use of a series c ut crys tal ma y give a frequency out

of the cry stal manuf acturers specifications. When in HS

mode, the device can accept an external clock source

to drive the OSC1/CLKI pin (Figure 11-2). See

Figure 14-1 or Figure 14-2 (depending on the part

number and VDD range) for valid external clock

frequencies.

FIGURE 11-1: CRY STAL/CERAMIC

RESONATOR OPERATION

(HS, XT OR LP

OSC CONFIGURATION)

FIGURE 11-2: EXTERNAL CLOCK INPUT

OPERATION (HS OSC

CONFIGURATION)

TABLE 11-1: CERAMIC RESONATORS

(FOR DESIGN

GUIDANCE ONLY)

Note 1: See Table 11-1 and Table 11-2 for typical

values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cu t crystals.

3: RF varies with the crystal chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

SLEEP

logic

PIC16F72

RS(2)

internal

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

56 pF

47 pF

33 pF

56 pF

47 pF

33 pF

HS 8.0 MHz

16.0 MHz 27 pF

22 pF 27 pF

22 pF

Capacitor values are for design guidance only.

These capacitors were tested with the resonators

listed below for basic start-up and operation. These

values were not optimized.

Dif ferent cap acitor values may be required to prod uce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes at the bottom of page 62 for additional

information.

OSC1

OSC2

Open

Clock from

Ext. Sy stem PIC16F72

(HS Mode)

PIC16F72

DS39597B-page 62  2002 Microchip Technology Inc.

TABLE 11-2: CAPACITOR SELECTION FOR

CRYST AL OSCILLATOR (FOR

DESIGN GUIDANCE ONLY)

11.2.3 RC OSCILLATOR

For timing insensitive applications, the “RC” device

option offers ad diti ona l cos t savings. The RC oscil lator

frequenc y is a fun ction of the sup pl y vo ltage, the re sis -

tor (REXT) and capacitor (CEXT) values, and the opera t-

ing temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to take into account

variation due to tolerance of external R and C com-

ponents used. Figure 11-3 shows how the R/C

combination is connected to the PIC16F72.

FIGURE 11-3: RC OSCILLATOR MODE

11.3 RESET

The PIC16F72 differentiates between various kinds of

RESET:

•Power-on Reset (POR)

•MCLR Reset during normal operation

•MCLR Reset during SLEEP

•WDT Reset (during normal operation)

•WDT Wake-up (during SLEEP)

•Brown-out Reset (BOR)

Some registers are not affected in any RESET condi-

tion. Their status is unknown on POR and unchanged

in any othe r RESET. Most other reg isters are reset to a

“RESET state” on Power-on Reset (POR), on the

MCLR and WDT Reset, on MCLR Reset during

SLEEP, and Brown-out Reset (BOR). They are not

affected by a WDT Wake-up, which is viewed as the

resumption of normal operation. The TO and PD bits

are set or cleared differently in different RESET situa-

tions, as indicated in Table 1 1- 4. These bit s are used in

software to determine the nature of the RESET. See

Table 11-6 for a full description of RESET states of all

registers.

A simplifie d block diagram of the on-chip RESET ci rcuit

is sh own in Figure 11 -4.

Osc Type Crystal

Freq

Typical Cap acitor V alues

Tested:

C1 C2

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 56 pF 56 pF

1 MHz 15 pF 15 pF

4 MHz 15 pF 15 pF

HS 4 MHz 15 pF 15 pF

8 MHz 15 pF 15 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed

below for basic start-up and operation. These values

were not optimized.

Dif ferent capa citor values may be require d to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes following this table for additional

information.

Note 1: Hi gher capacit ance incr eases the st ability

of oscillator, but also increases the

start - up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appro-

priate values of external com ponent s.

3: Rs may be required in HS mode, as well

as XT mode, to av oid ov erdrivi ng crys tal s

with low drive level specification.

4: Always veri fy os ci lla tor pe rform an ce ov er

the VDD and temperature range that is

expected for the application.

OSC2/CLKO

CEXT

REXT

PIC16F72

OSC1

FOSC/4

Internal

Clock

VDD

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20 pF

 2002 Microchip Technology Inc. DS39597B-page 63

PIC16F72

FIGURE 11-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

11.4 MCLR

PIC16F72 device has a noise filter in the MCLR Reset

path. The filter will detect and ignore small pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The behavior of the ESD protection on the MCLR pin

has been altered from previous devices of this family.

Voltages appli ed to t he pin th at exce ed it s spe cific ation

can resul t in both MCLR an d excessi ve current beyon d

the device specification during the ESD event. For this

reason, Microchip recommends that the MCLR pin no

longer be tied directly to VDD. The use of an

RC network, as shown in Figure 11-5, is suggested.

FIGURE 11-5: RECOMMENDED MCLR

CIRCUIT

External

RESET

MCLR

VDD

OSC1

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip

RC OSC

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST

Enable PWRT

SLEEP

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

Brown-out

Reset BOREN

(1)

0.1 µF

1 kΩ (or greater)

(optional, not critical)

VDD

MCLR

PIC16F72

DS39597B-page 64  2002 Microchip Technology Inc.

11.5 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.2V - 1.7V). To

take advantage of the POR, tie the MCLR pin to VDD,

as described in Section 11.4. A maximum rise time for

VDD is specified. See Section 14.0, Electrical

Characteristics for details.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, fre quency, temperature ,...) m ust be m et to ensu re

operation. If these conditions are not met, the device

must be held in RESET until the operating conditions

are met. For more information, see Application Note,

AN607- Power-up Troubl e Shoot ing (DS00607).

11.6 Power-up Timer (PWRT)

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up only from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is kept in RESET as long as the PWRT is active.

The PWR T’s time de lay allows VDD to rise to an accept-

able level. A configuration bit is provided to enable/

disable the PWRT.

The pow er-up time dela y will vary from chip to chip due

to VDD, temperature and process variation. See DC

parameters for details (TPWRT, parameter #33).

11.7 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycles (from OSC1 input) delay after the

PWRT delay is over (if enabled). This helps to ensure

that the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

11.8 Brown-out Reset (BOR)

The configuration bit, BOREN, can enable or disable

the Brown-out Reset circuit. If VDD falls below VBOR

(parameter D005, about 4V) for longer than TBOR

(param eter #3 5, abou t 100 µs), the bro wn-out s ituation

will reset the device. If VDD falls below VBOR for less

than TBOR, a RESET may not occur.

Once the brown-out occurs, the device will remain in

Brown-out Reset until VDD rises above VBOR. The

Power-up Timer then keeps the device in RESET for

TPWRT (param eter #33, abou t 72 ms). If VDD should fall

below VBOR during TPWRT, the Brown-out Reset pro-

cess wi ll res tart when VDD rises above VBOR, with the

Power-up Timer Reset. The Power-up Timer is always

enabled when the Brown-out Reset circuit is enabled,

regardless of the state of the PWRT configuration bit.

11.9 Time-out Sequence

On power-up, the time-out sequence is as follows: the

PWRT delay starts (if enabled) when a POR occurs.

Then, OST start s c oun tin g 102 4 os ci ll ator cycles whe n

PWRT ends (LP, XT, HS). When the OST ends, the

device comes out of RESET.

If MCLR is kept low long enough, all delays will expire.

Bringing MCLR high will begin execution immediately.

This is useful for testing purposes or to synchronize

more than one PIC 16F72 device operat ing in parallel.

Table 11-5 shows the RESET conditions for the

STATUS, PCON and PC registers, while Table 11-6

shows the RESET conditions for all the registers.

11.10 Power Control/ Status Register

(PCON)

The Power Control/Status Register, PCON, has two

bits to indicate the type of RESET that last occurred.

Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is

unknown on a Power-on Reset. It must then be set by

the user and checked on subsequent RESETS to see

if bit BOR cleared, indicating a Brown-out Reset

occurred. When the Brown-out Reset is disabled, the

state of the BOR bit is unpredictable.

Bit1 is POR (Power-on Reset S tatus bit). It is cleared on

a Power-on Reset and unaffected otherwise. The user

must set this bit following a Power-on Reset.

 2002 Microchip Technology Inc. DS39597B-page 65

PIC16F72

TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS

TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE

TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS

Oscillator Co nfigu ration Power-up Brown-out Wake-up from

SLEEP

PWRTEN = 0 PWRTEN = 1

XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC

RC 72 ms —72 ms —

POR

(PCON<1>) BOR

(PCON<0>) TO

(STATUS<4>) PD

(STATUS<3>) Significance

0x 1 1Power-on Reset

0x 0 xIllegal, TO is set on POR

0x x 0Illegal, PD is set on POR

u0 1 1Brown-out Reset

uu 0 1WDT Reset

uu 0 0WDT Wake-up

uu u uMCLR Reset during normal operation

uu 1 0MCLR Reset during SLEEP or interrupt wake-up from

SLEEP

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 000h 000u uuuu ---- --uu

MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu

WDT Reset 000h 0000 1uuu ---- --uu

WDT Wake-up PC + 1 uuu0 0uuu ---- --uu

Brown-out Reset 000h 0001 1uuu ---- --u0

Interrupt Wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

PIC16F72

DS39597B-page 66  2002 Microchip Technology Inc.

TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Brown-out Reset MCLR Reset,

WDT Reset Wake-up via WDT or

Interrupt

Wxxxx xxxx uuuu uuuu uuuu uuuu

INDF N/A N/A N/A

TMR0 xxxx xxxx uuuu uuuu uuuu uuuu

PCL 0000h 0000h PC + 1(2)

STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3)

FSR xxxx xxxx uuuu uuuu uuuu uuuu

PORTA --0x 0000 --0u 0000 --uu uuuu

PORTB xxxx xxxx uuuu uuuu uuuu uuuu

PORTC xxxx xxxx uuuu uuuu uuuu uuuu

PCLATH ---0 0000 ---0 0000 ---u uuuu

INTCON 0000 000x 0000 000u uuuu uuuu(1)

PIR1 -0-- 0000 -0-- 0000 -u-- uuuu(1)

TMR1L xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H xxxx xxxx uuuu uuuu uuuu uuuu

T1CON --00 0000 --uu uuuu --uu uuuu

TMR2 0000 0000 0000 0000 uuuu uuuu

T2CON -000 0000 -000 0000 -uuu uuuu

SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu

SSPCON 0000 0000 0000 0000 uuuu uuuu

CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON --00 0000 --00 0000 --uu uuuu

ADRES xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 0000 00-0 0000 00-0 uuuu uu-u

OPTION 1111 1111 1111 1111 uuuu uuuu

TRISA --11 1111 --11 1111 --uu uuuu

TRISB 1111 1111 1111 1111 uuuu uuuu

TRISC 1111 1111 1111 1111 uuuu uuuu

PIE1 -0-- 0000 -0-- 0000 -u-- uuuu

PCON ---- --qq ---- --uu ---- --uu

PR2 1111 1111 1111 1111 1111 1111

SSPADD 0000 0000 0000 0000 uuuu uuuu

SSPSTAT --00 0000 --00 0000 --uu uuuu

ADCON1 ---- -000 ---- -000 ---- -uuu

PMDATL 0--- 0000 0--- 0000 u--- uuuu

PMADRL xxxx xxxx uuuu uuuu uuuu uuuu

PMDATH xxxx xxxx uuuu uuuu uuuu uuuu

PMADRH xxxx xxxx uuuu uuuu uuuu uuuu

PMCON1 1--- ---0 1--- ---0 1--- ---u

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition,

r = reserved, maintain clear.

Note 1: One or more bits in INTCON, PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 11-5 for RESET value for specific condition.

 2002 Microchip Technology Inc. DS39597B-page 67

PIC16F72

FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH

PULL-UP RESISTOR)

FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH

RC NETWORK): CASE 1

FIGURE 11-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH

RC NETWORK): CASE 2

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

PIC16F72

DS39597B-page 68  2002 Microchip Technology Inc.

FIGURE 11-9: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)

11.11 Interrupts

The PIC16 F72 has up to eight sou rces of interrupt. The

interrupt control register (INTCON) records individual

interrupt requests in flag bits. It also has individual and

global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all unmasked interrupts, or disables (if

cleared ) all i nterrupt s. W hen bit GIE i s enab led, a nd an

interrupt’s flag bit and mask bit are s et, the int errupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt bits are set,

regardless of the status of the GIE bit. The GIE bit is

cleared on RESET.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enabl es inte rrupts.

The RB0/INT pin interrupt, the RB port chang e interrupt

and the TMR 0 over flo w interru pt f lag s are co nt a ine d in

the INTCON register.

The peripheral interrupt flags are contained in the

Special Function Register, PIR1. The corresponding

interrupt enable bits are contained in Special Function

is co ntained in Special F unction Register IN TCON.

When an interrupt is serviced, the GIE bit is cleared to

disable any further interrupt, the return address is

pushed onto the stack, and the PC is loaded with

0004h. Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the i nterr upt flag bits. T he inte rrupt flag bi t(s) mu st be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs, relative to

the current Q cycle. The latency is the same for one or

two cycle ins tructions. Individual interrupt flag bits are

set, regardless of the status of their corresponding

mask bit, PEIE bit, or the GIE bit.

FIGURE 11-10: INTERRUP T LOGIC

VDD

MCLR

INTERNAL POR

PWRT TIME-O UT

OST TIME-OUT

INTERNAL RESET

0V 1V

TPWRT

TOST

Note: Indiv idual interrupt fl ag bits are s et, regard-

less of the status of their corresponding

mask bit, or the GIE bit.

ADIF

ADIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

TMR0IF

TMR0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

 2002 Microchip Technology Inc. DS39597B-page 69

PIC16F72

11.11.1 INT INTERRUPT

External in terrupt on the RB0/INT pin is edge trigg ered,

either rising, if bit INTEDG (OPTION<6>) is set, or fall-

ing, if the INTEDG bit is clear. When a valid edge

appears on the RB0/INT pin, flag bit INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the Interrupt Service

Routin e before re-enablin g this interrupt. The INT int er-

rupt can wake-up the processor from SLEEP, if bit INTE

was set prior to going into SLEEP. The status of global

interrupt enable bit GIE decides whether or not the

processor branches to the interrupt vector following

wake-up. See Section 11.14 for details on SLEEP

mode.

11.11.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

flag bit TMR0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit

TMR0IE (INTCON<5>) (see Section 5.0).

11.11.3 PORTB INTCON CHANGE

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<4>) (see

Section 3.2).

11.12 Context Saving During Inte rrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, user s may wish to save key r eg-

isters during an interrupt (i.e., W, STATUS registers).

This w ill have to be im plemented in softwa re, as sho wn

in Example 11-1.

For the PIC16F72 device, the register W_TEMP must

be defined in both banks 0 and 1 and must be defined

at the same offset from the bank base address (i.e., if

W_TEMP is defined at 20h in bank 0, it must also be

defined a t A0h in bank 1). The re gister STA TUS_TEMP

is on ly defined in bank 0.

EXAMPLE 11-1: SAVING STATUS, W AND PCLATH REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register

SWAPF STATUS,W ;Swap status to be saved into W

CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0

MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register

:(ISR) ;Insert user code here

SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS ;Move W into STATUS register

SWAPF W_TEMP,F ;Swap W_TEMP

SWAPF W_TEMP,W ;Swap W_TEMP into W

PIC16F72

DS39597B-page 70  2002 Microchip Technology Inc.

11.13 Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC

oscillator that does not require any external compo-

nent s. T his RC oscilla tor is s ep arate from the R C osci l-

lator of the OSC1/CLKI pin. That means that the WDT

will run, even if the clock on the OSC1/CLKI and OSC2/

CLKO pins of the device has been stopped, for

exampl e, by ex ecu tion of a SLEEP instruction.

During n ormal operati on, a WDT ti me-out genera tes a

device RESET (W atchdog T imer Reset). If the device is

in SLEE P mo de, a W DT t ime- ou t cause s t he de vice t o

wake-up and continue with normal operation (Watchdog

Timer W ake-up). The TO bit in the STATUS register will

be cleared upon a Watchdog T imer time-out.

The WDT can be permanently disabled by clearing

configuration bit WDTEN (see Section 11.1).

WDT time-out period values may be found in the Elec-

trical Specifications section under parameter #31. Val-

ues for the WDT prescaler (actually a postscaler, but

shared with the Timer0 prescaler) may be assigned

using the OPTION register.

FIGURE 11-11: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 11-7: SUMMARY OF WATCHDOG TI MER REGISTERS

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and the postscaler, if

assigned to the WDT, and prevent it from

timing out and generating a device

RESET condition .

2: When a CLRWDT instruction is executed

and the pre scaler is assi gned to the WDT,

the prescaler count will be cleared, but

the pr es ca ler ass ig nm ent is no t c han ged.

From TMR0 Clock Source

(Figure 5-1)

To TMR0 (Figure 5-1)

Postscaler

WDT Timer

WDT

Enable Bit

PSA

8 - to - 1 MUX PS2:PS0

MUX PSA

WDT

Time-out

Note: PSA and PS2:PS 0 are bits in the OPTION register.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Config. bits (1) BOREN(1) —CP PWRTEN(1) WDTEN FOSC1 FOSC0

81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog T i mer.

Note 1: See Register 11-1 for operation of these bits.

 2002 Microchip Technology Inc. DS39597B-page 71

PIC16F72

11.14 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keep s runni ng, the PD bit (STATUS<3>) is clea red , th e

TO (STATUS<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For lo west curr ent con sum pti on in this mo de, plac e all

I/O pins at either VDD or VSS, ensure no external cir-

cuitr y is dr awing cu rrent from th e I/O pi n, powe r-dow n

the A/D and disable external clocks. Pull all I/O pins

that are hi-impedance inputs, high or low externally, to

avoid s witchi ng curre nts caus ed by fl oating input s. Th e

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should also be considered.

The MCLR pin must be at a logic high level (VIHMC).

11.14.1 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin.

2. Watchdog Timer wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change or a

peripheral interrupt.

External MCLR Reset will cause a device RESET. All

other events are considered a continuation of program

execut ion and ca us e a " wak e-up". The TO and PD bits

in the STATUS register can be used to determine the

cause of the de vice RESET. The PD bit, which is se t on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared if a WDT time-out occurred and caused

wake-up.

The follo wing periph eral interrupt s can wake the device

from SLEEP:

1. TMR1 interrup t. T imer1 m ust be ope rating as an

asynchronous counter.

2. CCP Capture mode interrupt.

3. Special event trigger (Timer1 in Asynchronous

mode using an external clock).

4. SSP (START/STO P) bit detect interrupt.

5. SSP transmit or receive in Slave mode

(SPI/I2C).

6. A/D conversion (when A/D clock source is RC).

Other peripherals cannot generate interrupts since

during SLEEP, no on-chip clocks are present.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up thro ugh an interrupt eve nt, the co rres pon din g

interrupt enable bit must be set (enabled). Wake-up

occurs regardless of the state of the GIE bit. If the GIE

bit is clear (disabled), the device continues execution at

the ins truction a fter the SLEEP i nstructio n. If the GI E bit

is set (enabled), the device executes the instruction

after the SLEEP instruction and then branches to the

interrupt address (0004h). In cases where the execu-

tion of the instruction following SLEEP is not desirable,

the use r should hav e a NOP after the SLEEP instruction.

11.14.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and inte rrupt fla g bit s et, one of the fo llow ing wil l occur:

•If the interrupt occurs before the execution of a

SLEEP instru ct ion , the SLEEP instruction will com-

plete as a NOP. Therefore, the WDT and WDT

pos tscaler will not be cleared, the TO bit will not

be set and PD bits will not be cle are d.

•If the interrupt occurs during or after the execu-

tion of a SLEEP instruction, the device will imme-

diately wake-up from SLEE P. T he SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

pos tscaler will be cleared, the TO bit will be set

and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP ins truc tion exe cuted, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instruction

should be executed before a SLEEP instru ction.

PIC16F72

DS39597B-page 72  2002 Microchip Technology Inc.

FIGURE 11-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT

11.15 Program Verification/

Code Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for verifi cation purposes.

11.16 ID Locations

Four memory locations (2000h - 2003h) are desig nated

as ID locations, where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are read-

able and writable during program/verify. It is recom-

mended that only the four Least Significant bits of the

ID location are used.

11.17 In-Circuit Serial Programming

PIC16F72 microcontrollers can be serially programmed

while in the e nd applicat ion cir cuit. This is si mply don e

with two lines for clock and data and three other lines for

power, ground, and the programming voltage (see

Figure 11-13 for an example). This allows customers to

manufacture boards with unprogrammed devices, and

then program the microcontroller just before shipping

the produ ct. This al so allows the most recent firmware

or a custom firmware to be programmed.

For general information of serial programming, please

refer to the In-Circuit Serial Programming™ (ICSP™)

Guide (DS3 0277). Fo r specific deta ils on programm ing

commands and operations for the PIC16F72 devices,

please refer to the latest version of the PIC16F72

FLASH Program Memory Programming Specification

(DS39588).

FIGURE 11-13: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKO(4)

INT pin

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Lat ency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024 TOSC (drawing not to scale) This delay will not be there for RC Osc mode.

3: GIE = ‘1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine.

If GIE = ‘0', execution will continue in-line.

4: CLKO is not available in these Osc modes, but shown here for timing reference.

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16F72

VDD

VSS

MCLR/VPP

RB6

RB7

+5V

VPP

CLK

Data I/O

VDD

* * *

* Isolation devices (as required).

 2002 Microchip Technology Inc. DS39597B-page 73

PIC16F72

12.0 INSTRUCTION SET SUMMARY

Each PIC 16F7 2 inst ruction is a 14-bi t wo rd div ided into

an OPCO DE that specif ies the instruct ion type and one

or more operands that further specify the operation of

the ins truc tio n. The PIC16 F72 instru cti on se t s um mar y

in Table 12-2 list s byte-oriented, bit-oriented, and lit-

eral and control operations. Table 12-1 shows the

opcode field descriptions.

For byte-oriented in stru ction s, ‘f’ represents a file reg-

ister designator and ‘d’ represents a destination desig-

nator. The file register designator specifies which file

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W regis ter . If ‘d’ is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

design ator which selec t s the nu mb er o f th e bi t a f fected

by the op eration, whil e ‘f’ represe nt s the num be r of th e

file in which the bit is located.

For literal and control operations, ‘k’ represents an

eight or eleven-bit constant or literal value.

TABLE 12-1: OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped

into three basi c categories :

•Byte-oriented operations

•Bit-oriented operations

•Literal and cont rol operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this case, the execution takes two instruction cycles,

with the s econ d cy cle exec ute d as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an osc illator frequency of 4 M Hz, th e normal instruc tion

execut ion time is 1 µs . If a conditio nal test is true, or th e

program counter is changed as a result of an

instruction, the instruction execution time is 2 µs.

Table 12-2 lists the instructions recognized by the

MPASMTM assembler.

Figure 12-1 shows the general formats that the

instructions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signifies a hexadecimal digit.

FIGURE 12-1: GENERAL FORMAT FOR

INSTRUCTIONS

A description of each instruction is available in the

PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023).

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

xDon’t care location (= 0 or 1).

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

dDestination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

PC Program Counter

TO Time-out bit

PD Power-down bit

Byte-oriented file register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE # )

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0

OPCODE b (BIT # ) f (FIL E #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (literal )

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit imm ediate value

General

CALL and GOTO instructions only

PIC16F72

DS39597B-page 74  2002 Microchip Technology Inc.

TABLE 12-2: PIC16F72 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Mov e W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Wat chdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into S tandby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on

the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023).

 2002 Microchip Technology Inc. DS39597B-page 75

PIC16F72

12.1 Instruction Descripti ons

ADDLW Add Literal and W

Syntax: [ label ] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → (W)

Status Affected: C, DC, Z

Description: The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the W

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (destination)

Status Affected: C, DC, Z

Desc ription: Add the conten ts of the W regis ter

with register ‘f’. If ‘d’ = ‘0’, the

result is stored in the W registe r . I f

‘d’ = ‘1’, the result is stored back

in register ‘f’.

ANDLW AND Literal with W

Syntax: [ label ] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (destination)

Status Affe cte d: Z

Description: AND the W register with register

‘f’. If ‘d’ = ‘0’, the result is st ored in

the W register. If ‘d’ = ‘1’, the

result is stored back in regist er ‘f’.

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affe cte d: None

Description: Bit ‘b’ in register ‘f’ is cleared.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affe cte d: None

Description: Bit ‘b’ in register ‘f’ is set.

PIC16F72

DS39597B-page 76  2002 Microchip Technology Inc.

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Descript ion: If bit ‘b’ in register ‘f’ = ‘0’, the next

instructi on is exec uted .

If bit ‘b’ = ‘1’, then the next instruc-

tion is dis ca r de d a nd a NOP is exe-

cuted inste ad, maki ng thi s a 2 TCY

instruction.

BTFSC Bit Test, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Descript ion: If bit ‘b’ in regi ster ‘f’ = ‘1’, the next

instruction is executed.

If bit ‘b’ in regi ste r ‘f’ = ‘0’, th e n ex t

instruction is discarded, and a NOP

is exec ute d ins te ad, m ak in g thi s a

2 TCY instruction.

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 2047

Operation: (PC) + 1 → TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return

address (PC+1) is pushed onto

the stack. The eleven-bit immedi-

ate a ddress is loade d into P C bit s

<10:0>. The upper bits of the PC

are load ed from PCLA TH. CALL is

a two-cycle instruction.

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

Status Affe cte d: Z

Description: The contents of register ‘f’ are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affe cte d: Z

Description: W register is cleared. Zero bit (Z)

is se t.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affe cte d: TO, PD

Description: CLRWDT instruction resets the

W atchdog T imer . It also reset s the

prescaler of the WDT. Status bits

TO and PD are set.

 2002 Microchip Technology Inc. DS39597B-page 77

PIC16F72

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (destination)

Status Affected: Z

Description: The contents of register ‘f’ are

complemented. If ‘d’ = ‘0’, the

result is stor ed in W. If ‘d’ = ‘1’, the

result is stored back in register ‘f’.

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination)

Status Affected: Z

Description: Decrement register ‘f’. If ‘d’ = ‘0’,

the result is stored in the W

stored back in register ‘f’.

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination);

skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are

decrem ented. If ‘d’ = ‘0’, the res ult

is placed in the W register. If

‘d’=‘1’, the result is placed back

in register ‘f’.

If the result is ‘1’, the next instruc-

tion is e xec ut ed. If the resu lt i s ‘0’,

then a NOP is executed instead,

making it a 2 TCY instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Status Affe cte d: None

Description: GOTO is an unconditional branch.

The e lev en -bit im me dia t e v alu e i s

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a

two-cycle instruction .

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination)

Status Affe cte d: Z

Description: The contents of register ‘f’ are

incremented. If ‘d’ = ‘0’, the result

is placed in the W register. If

‘d’=‘1’, the result is placed back

in register ‘f’.

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination),

skip if result = 0

Status Affe cted: None

Description: The contents of register ‘f’ are

incremented. If ‘d’ = ‘0’, the r esult

is placed in the W register. If

‘d’=‘1’, the result is placed back

in regist er ‘f’.

If the result is ‘1’, the next instruc-

tion is exe cu ted . If the res ul t i s ‘0’,

a NOP is e xecuted i nstead, ma king

it a 2 TCY instruction.

PIC16F72

DS39597B-page 78  2002 Microchip Technology Inc.

IORLW Inclusive OR Literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

Status Affected: Z

Desc ription: The contents of the W regis ter are

OR’d with the eight-bit literal ‘k’.

The result is placed in the W

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (destination)

Status Affected: Z

Description: Inclusive OR the W register with

placed in the W regi ster . If ‘d’ = ‘1’,

the result is placed back in

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (destination )

Status Affected: Z

Description: The contents of register ‘f’ are

moved t o a destination dependant

upon the st a tus of ‘d’. If ‘d’ = ‘0’,

the destination is W register. If

‘d’=‘1’, the destination is file reg-

ister ‘f’ itself. ‘d’ = ‘1’ is useful to

test a file register, since status

flag Z is affected.

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affe cte d: None

Description: The eight-bit literal ‘k’ is loaded

into W register. The don’t cares

will assemble as ‘0’s.

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 127

Operation: (W) → (f)

Status Affe cte d: None

Description: Move data from W register to

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

Status Affe cte d: None

Description: No operation.

 2002 Microchip Technology Inc. DS39597B-page 79

PIC16F72

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Status Affected: None

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Description: The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Description: Return from subrouti ne. The stack

is POPed an d t he top o f th e s t a ck

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affe cte d: C

Description: The contents of register ‘f’ are

rotated one bit to the left through

the Carry Flag. If ‘d’ = ‘0’, the

result is placed in the W register.

If ‘d’ = ‘1’, the result is stored

back in register ‘f’.

RRF Rot ate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affe cte d: C

Description: The contents of register ‘f’ are

rotate d one bit to the righ t through

the Carry Flag. If ‘d’ = ‘0’, the

result is placed in the W register.

If ‘d’ = ‘1’, th e result is p laced back

in register ‘f’.

SLEEP

Syntax: [ label ]SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

Status Affe cte d: TO , PD

Description: The power-down status bit, PD is

cleared. Time-out status bit, TO

is set. Watchdog Timer and its

prescaler are cleare d.

The proc essor is put i nto SLEEP

mode with the os cillator stopped.

PIC16F72

DS39597B-page 80  2002 Microchip Technology Inc.

SUBLW Subtract W from Literal

Syntax: [ label ] SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status Affected: C, DC, Z

Desc ript ion : The W register is subtracte d (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W regi ster.

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (destination)

Status Affected: C, DC, Z

Description: Subtract (2’s complement method)

W register from register ‘f’. If

‘d’=‘0’, the result is sto red in the W

stored back in register ‘f’.

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of

‘d’=‘0’, the result is placed in W

placed in regi ste r ‘f’.

XORLW Exclusive OR Literal with W

Syntax: [ label ]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affe cte d: Z

Description: The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (destination)

Status Affe cte d: Z

Description: Exclusive OR the contents of the

W register with register ‘f’. If

‘d’=‘0’, the result is stored in the

W register. If ‘d’ = ‘1’, the result is

stored back in register ‘f’.

 2002 Microchip Technology Inc. DS39597B-page 81

PIC16F72

13.0 DEVELOPMENT SUPPORT

The PICmicro® microcontrollers are supported with a

full ran ge of hardware a nd softwa re develo pment to ols:

•Integrated Development Environment

- MPLAB® IDE Software

•Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C17 and MPLAB C18 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

•Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- ICEPIC™ In-Circuit Emulator

•In-Circuit Debugger

- MPLAB ICD

•Device Programmers

-PRO MATE

® II Universa l Devi ce Pr o gr a mm er

- PICSTART® Plus Entry-Level Development

Programmer

•Low Cost Demonstration Boards

- PICDEMTM 1 Demonstration Board

- PICDEM 2 Demonstration Board

- PICDEM 3 Demons trati on Boar d

- PICDEM 17 Demonstration Board

-K

EELOQ® Demonstration Board

13.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. The MPLAB IDE is a Windows®-based

application that contains:

•An interface to debugging t ools

- simulator

- programmer (so ld sep ara tely )

- em ulator (sold separately)

- in-circuit debugger (sold separately)

•A full-featured editor

•A project manager

•Customizable toolbar and key mapping

•A status bar

•On-line help

The MPLAB IDE allows you to:

•Edit your source files (eithe r assembly o r ‘C’)

•One touch assemble (or compile) and download

to PICmicro emulator and simulator tools (auto-

matically updates all project information)

•Debug us ing :

- source file s

- absolute li sting fi le

- machine code

The ability to use MPLAB IDE with multiple debugging

tools allows users to easily switch from the cost-

effective simulator to a full-featured emulator with

minimal retraining.

13.2 MPASM Assembler

The MPASM assembler is a full-featured universal

macro assembler for all PICmicro MCU’s.

The MPASM assembler has a command line interface

and a Windows shell. It can be used as a stand-alone

application on a Windows 3.x or greater system, or it

can be us ed through MPLAB ID E. The MP ASM assem-

bler generates relocatable object files for the MPLINK

object linker, Intel® standard HEX files, MAP files to

detail memory usage and symbol reference, an abso-

lute LST file that contains source lines and generated

machine code, and a COD file for debugging.

The MPASM assembler features include:

•Integration into MPLAB IDE projects.

•User-defined macros to streamline assembly

code.

•Conditional assembly for multi-purpose source

files.

•Directives that allow complete control over the

assembly p rocess.

13.3 MPLAB C17 and MPLAB C18

C Compilers

The MPLAB C1 7 and MP LAB C18 Code De vel op me nt

Systems are complete ANSI ‘C’ compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microc ontrollers, re spectively. Thes e compiler s provide

powerful integration capabilities and ease of use not

found with other compilers.

For easier source level debugging, the compilers pro-

vide symbol information that is compatible with the

MPLAB IDE memory display.

PIC16F72

DS39597B-page 82  2002 Microchip Technology Inc.

13.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can also

link relocatable objects from pre-compiled libraries,

using directives from a linker script.

The MPLIB object librarian is a librarian for pre-

compiled code to be used with the MPLINK object

linker. When a routine from a library is called from

another source file, only the modules that contain that

routine w ill be linked in with the ap plicatio n. This allo ws

large libraries to be used efficiently in many different

applications. The MPLIB object librarian manages the

creation and modification of library files.

The MPLINK object linker features include:

•Integration with MPASM assembler and MPLAB

C17 and MPLAB C18 C compilers.

•Allows a ll m emo ry are as t o be defined as se ctio ns

to provide l ink -time flex ibi lity.

The MPLIB object librarian features include:

•Easier linking because single libraries can be

included instead of many smaller files.

•Helps keep code maintainable by grouping

related modules together.

•Allows libraries to be created and modules to be

added, listed, replaced, deleted or extracted.

13.5 MPLAB SIM Software Simulator

The MPLAB SIM sof tware simula tor allows code deve l-

opment in a PC-hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user-defined ke y press, to an y of the pins. The

execution can be performed in single step, execute

until break, or trace mode.

The MPLAB SIM simulator fully supports symbolic debug-

ging using the MPLAB C17 and the MPLAB C18 C com-

pilers and the MP ASM assembler. The software simulator

offers the flexibility to develop and debug code outside of

the laborat ory envir onment, making it an excelle nt multi-

project software development tool.

13.6 MPLAB ICE High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB ICE universal in-circuit emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PICmicro

microcontrollers (MCUs). Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment (IDE),

which allows editi ng, buildin g, downlo ading and so urce

debugging from a single environment.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

featur es. Interchangea ble processo r modules al low the

system to be easily reconfigured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmic ro mi cro con trol le rs.

The MPLAB ICE in-circuit emulator system has been

designed as a real-time emulation system, with

advanced features that are generally found on more

expensive development tools. The PC platform and

Microsoft® Windows environment were chosen to best

make these features available to you, the end user.

13.7 ICEPIC In-Circuit Emulator

The ICEPIC low cost, in-circuit emulator is a solution

for the Microchip Technology PIC16C5X, PIC16C6X,

PIC16C7X and PIC16CXXX families of 8-bit One-

T ime-Programmable (OTP) microcontrollers. The mod-

ular sy stem can su pport dif feren t subset s of PIC16 C5X

or PIC16CXXX products through the use of inter-

changeable personality modules, or daughter boards.

The emulator is capable of emulating without target

applic atio n circ ui try bei ng pres en t.

 2002 Microchip Technology Inc. DS39597B-page 83

PIC16F72

13.8 MPLAB ICD In-Circuit Debugger

Microchip’s In-Circuit Debugger , MPLAB ICD, is a pow-

erful, low cost, run-time development tool. This tool is

based o n the F LASH PICmicro MCUs an d can be used

to devel op for this and other PICmicro mic rocontrollers.

The MPLAB IC D u tili ze s th e in -circuit d ebu ggi ng c apa-

bility built into the FLASH devices. This feature, along

with Microchip’s I n-Circuit Se rial Prog rammingTM proto-

col, offers cost-effective in-circuit FLASH debugging

from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by watch-

ing variables, si ngl e-s tep pin g and setting brea k poi nt s .

Runni ng at full sp eed enab les tes ting hardwa re in real-

time.

13.9 PRO MATE II Universal Device

Programmer

The PRO MATE II universal device programmer is a

full-featured programmer, capable of operating in

stand-alone mode, as well as PC-hosted mode. The

PRO MATE II device programmer is CE compliant.

The PRO MATE II device programmer has program-

mable VDD and VPP supplies, which allow it to verify

programmed memory at VDD min and VDD max for max-

imum reliability. It has an LCD display for instructions

and error messages, keys to enter commands and a

modular detachable socket assembly to support various

package types. In stand-alone mode, the PRO MATE II

device programmer can read, verify, or program

PICmicro devices. It can also set code protection in this

mode.

13.10 PICSTART Plus Entry Level

Development Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient.

The PICSTART Plus development programmer sup-

ports all PICmicro devices with up to 40 pins. Larger pin

count devices, such as the PIC16C92X and

PIC17C76 X, may be suppor ted with an adap ter socket.

The PICSTART Plus development programmer is CE

compliant.

13.11 PICDEM 1 Low Cost PICmicro

Demonstration Board

The PICDEM 1 demonstration board is a simple board

which demonstrates the capabilities of several of

Microchip’s mic rocon trollers . The micro contro llers sup-

ported are: PIC16C5X (PIC16C54 to PIC16C58A),

PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,

PIC17C42, PIC17C43 and PIC17C44. All necessary

hardware and software is included to run basic demo

programs. The user can program the sample microcon-

trollers provided with the PICDEM 1 demonstration

board on a PRO MATE II device programmer, or a

PICSTART Plus development programmer, and easily

test firmware. The user can also connect the

PICDEM 1 demonstration board to the MPLAB ICE in-

circuit emulato r and do wnload the firmware to the emu-

lator for testing. A prototype area is available for the

user to build some additional hardware and connect it

to the microcontroller socket(s). Some of the features

include an RS-232 interface, a potentiometer for simu-

lated analog input, push button switches and eight

LEDs connected to PORTB.

13.12 PICDEM 2 Low Cost PIC16CXX

Demonstration Board

The PICDEM 2 demonstration board is a simple dem-

onstration board that supports the PIC16C62,

PIC16C64, PIC16C65, PIC16C73 and PIC16C74

microcontrollers. All the necessary hardware and soft-

ware is included to run the basic demonstration pro-

grams. The user can program the sample

microcontrollers provided with the PICDEM 2 demon-

stration board on a PRO MATE II device programmer,

or a PICSTART Plus development programmer, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may a lso be used with the PICDEM 2 demonstra tion

board to test firmware. A prototype area has been pro-

vided to the user for adding additional hardware and

connecting it to the microcontroller socket(s). Some of

the features include a RS-232 interface, push button

switches , a poten tiomet er for simula ted anal og inpu t, a

serial EEPROM to d emonstrate u sage o f the I2CTM bus

and separate headers for connection to an LCD

module and a keypad.

PIC16F72

DS39597B-page 84  2002 Microchip Technology Inc.

13.13 PICDEM 3 Low Cost PIC16CXXX

Demonstration Board

The PICDEM 3 demonstration board is a simple dem-

onstration board that supports the PIC16C923 and

PIC16C924 in the PLCC package. It will also support

future 44-p in PLCC micro controlle rs with an LCD Mo d-

ule. All the necessary hardware and software is

includ ed to r un the basic dem onstrat ion pro grams . The

user can program the sample microcontrollers pro-

vided with the PICDEM 3 demonstration board on a

PRO MATE II device programmer , o r a PICST AR T Plus

development programmer with an adapter socket, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may a lso be used with the PICDEM 3 demon stration

board to test firmware. A prototype area has been pro-

vided t o the use r for ad ding hardwa re and con necting it

to the microcontroller socket(s). Some of the features

include a RS-232 interface, push button switches, a

potentiometer for simulated analog input, a thermistor

and separate headers for connection to an external

LCD module and a keypad. Also provided on the

PICDEM 3 demonstration board is a LCD panel, with 4

commo ns and 1 2 segment s , tha t is capable of d isp lay-

ing time, temperature and day of the week. The

PICDEM 3 d emons tration board pr ovi des an add itiona l

RS-232 interface and Windows software for showing

the demul tiplexed LC D signals on a PC. A simp le serial

interface allows the user to construct a hardware

demultip lexer for the LCD signals.

13.14 PICDEM 17 Demonstration Board

The P ICDEM 17 de mo ns t rat i on bo a rd is an ev al u at i on

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. All neces-

sary hard ware is inc luded to ru n basic d emo progra ms,

which are supplied on a 3.5-inch disk. A programmed

sample is included and the user may erase it and

program it with the other sample programs using the

PRO MATE II device programmer, or the PICSTART

Plus development programmer, and easily debug and

test the sample code. In addition, the PICDEM 17 dem-

onstratio n board supports download ing of programs to

and executing out of external FLASH memory on board.

The PICDEM 17 demonstration board is also usable

with the MPLAB ICE in-circuit emulator, or the

PICMAST ER emulator and al l of the sample progr ams

can be run and modified using either emulator . Addition-

ally, a generous prototype area is available for user

hardware.

13.15 KEELOQ Evaluati on and

Programming Tools

KEELOQ evaluation and programming tools support

Microchip’s HCS Secure Data Products. The HCS eval-

uation kit includes a LCD display to show changing

codes, a decoder to decode transmissions and a pro-

gramming interface to program test transmitters.

 2002 Microchip Technology Inc. DS39597B-page 85

PIC16F72

TABLE 13-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12CXXX

PIC14000

PIC16C5X

PIC16C6X

PIC16CXXX

PIC16F62X

PIC16C7X

PIC16C7XX

PIC16C8X/

PIC16F8X

PIC16F8XX

PIC16C9XX

PIC17C4X

PIC17C7XX

PIC18CXX2

PIC18FXXX

24CXX/

25CXX/

93CXX

HCSXXX

MCRFXXX

MCP2510

Soft war e To ol s

MPLAB® Integrated

Development Environment

MPLAB® C17 C Compiler

MPLAB® C18 C Compiler

MPASMTM Assembler/

MPLINKTM Obje ct Lin ke r

Emulators

MPLAB® ICE In-Circuit Emulator

ICEPICTM In-Circuit Emulator

Debugger

MPLAB® ICD In-Circuit

Debugger

Programmers

PICSTART® Plus Entry Level

Devel opment Programmer

PRO MATE® II

Universal Device Programmer

Demo Boards and Eval Kits

PICDEMTM 1 Demonstration

Board

†

PICDEMTM 2 Demonstration

Board

†

PICDEMTM 3 Demonstration

Board

PICDEMTM 14A Demonstration

Board

PICDEMTM 17 Demonstration

Board

KEELOQ® Evaluation Kit

KEELOQ® Transp on d er Kit

microIDTM Programmer’s Kit

125 kHz microIDTM

Developer’s Kit

125 kHz Anticollision microIDTM

Developer’s Kit

13.56 MHz Antic olli sion

microIDTM Developer’s Kit

MCP2510 CAN Developer’s Kit

* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.

** Contact Microchip Technology Inc. for availability date.

†Development tool is available on select devices.

PIC16F72

DS39597B-page 86  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. DS39597B-page 87

PIC16F72

14.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Ambient temperature under bias................................................................................................................ -55 to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) .........................................-0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V

Voltage on MC LR with respect to VSS (Note 2)..............................................................................................0 to +13.5V

Voltage on RA4 with respect to Vss...................................................................................................................0 to +12V

Total power diss ipation (Note 1) ...............................................................................................................................1.0W

Maximum curr ent out of VSS pin ...........................................................................................................................300 mA

Maximum curr ent into VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp cur rent, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin....................................................................................................25 mA

Maximum curr ent sunk by PORTA, PORTB..........................................................................................................200 mA

Maximum current sourced by PORTA, PORTB ....................................................................................................200 mA

Maximum current sunk by PORTC .......................................................................................................................200 mA

Maximum current sourced by PORTC..................................................................................................................200 mA

Note 1: Power di ss ipation is calculate d as fo llows: Pdis = VDD x { IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)

2: Voltage spikes at the MCLR pin may cause unpredictable results. A series resistor of greater than 1 kΩ

should be used to pull MCLR to VDD, rather than tying the pin directly to VDD.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16F72

DS39597B-page 88  2002 Microchip Technology Inc.

FIGURE 14-1: PIC16F72 (INDUSTRIAL, EXTENDED) VOLTAGE-FREQUENCY GRAPH

FIGURE 14-2: PIC16LF72 (INDUSTRIAL) VOLTAGE-FREQUENCY GRAPH

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

20 MHz

5.0V

3.5V

3.0V

2.5V

16 MHz

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

5.0V

3.5V

3.0V

2.5V

FMAX = (12 MHz/V) (VDDAPPMIN - 2.5V) + 4 MHz

Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.

4 MHz 10 MHz

Note 2: FMAX has a maximum frequency of 10 MHz.

 2002 Microchip Technology Inc. DS39597B-page 89

PIC16F72

14.1 DC Characteristics:PIC16F72 (Industrial, Extended)

PIC16LF72 (Industrial)

PIC16LF72

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

PIC16F72

(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ†Max Units Conditions

VDD Supply Voltage

D001 PIC16LF72 2.0

2.5

2.2

—

5.5

A/D not used, -40°C to +85°C

A/D in use, -40°C to +85°C

A/D in use, 0°C to +85°C

D001

D001A PIC16F72 4.0

VBOR*—

—5.5

5.5 V

VAll configura tions

BOR enabled (Note 7)

D002* VDR RAM Data Retention

Voltage (Note 1) —1.5 —V

D003 VPOR VDD Start Voltage to

ensure internal Power-on

Reset signal

—VSS —V See sect ion on Pow er-on Reset for details

D004* SVDD VDD Rise Rate to ensure

internal Power-on Reset

signal

0.05 ——V/m s See secti on on Power-o n Reset for details

D005 VBOR Brown-out Reset Volt ag e 3.65 4.0 4.35 V BOREN bit in configuration word enabled

* These parameters are characterized but not tested.

†Dat a in "Typ" colu mn is at 5V, 25°C unl ess o the rw ise s t ate d. The se p a r am eters a re f or d es ign gu ida nc e o nly

and are not tested .

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supp ly curre nt is mainly a functio n of the ope rating vo lta ge and freq ue ncy. Other factors, su ch as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption. The test conditions for all IDD measurements in active Operation mode

are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from

characterization and is for design guidance only. This is not tested.

6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

PIC16F72

DS39597B-page 90  2002 Microchip Technology Inc.

IDD Supply Current (Notes 2, 5)

D010

D010A

PIC16LF72 —

—

0.4

2.0

µA

XT, RC osc configuration

FOSC = 4 MHz, VDD = 3.0V (Note 4)

LP osc configuration

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

D010

D013

PIC16F72 -

—

0.9

5.2

XT, RC osc configuration

FOSC = 4 MHz, VDD = 5.5V (Note 4)

HS osc configuration

FOSC = 20 MHz, VDD = 5.5V

D015* ∆IBOR Brown-out Reset Current

(Note 6) —25 200 µA BOR enabled, VDD = 5.0V

IPD Power-down Current (Notes 3, 5)

D020

D021 PIC16LF72 —

—2.0

0.1 30

5µA

µAVDD = 3.0V, WDT enabled, -40°C to +85°C

VDD = 3.0V, WDT disabled, -40°C to +85°C

D020

D021 PIC16F72 —5.0

0.1 42

19 µA

µAVDD = 4.0V, WDT enabled, -40°C to +85°C

VDD = 4.0V, WDT disabled, -40°C to +85°C

D023* ∆IBOR Brown-out Reset Current

(Note 6) —25 200 µA BOR enabled, VDD = 5.0V

14.1 DC Characteristics:PIC16F72 (Industrial, Extended)

PIC16LF72 (Industrial) (Continued)

PIC16LF72

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

PIC16F72

(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ†Max Units Conditions

* These parameters are characterized but not tested.

†Dat a in "Typ" co lumn is at 5V, 25°C unl es s o the rw ise s t ate d. These p a ram eters a re for des ign gu ida nc e o nly

and are not tested .

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supp ly curre nt is mainly a functi on of the ope rating vo lta ge and freq uency. Other fac tors, su ch as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption. The test conditions for all IDD measurements in active Operation mode

are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from

characterization and is for design guidance only. This is not tested.

6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

 2002 Microchip Technology Inc. DS39597B-page 91

PIC16F72

14.2 DC Characteristics: PIC16F72 (Industrial, Extended)

PIC16LF72 (Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Operating voltage VDD range as described in DC Specification,

Section 14.1.

Param

No. Sym Characteristic Min Typ†Max Units Conditions

VIL Input Low Voltage

I/O ports

D030 with TTL buffer VSS —0.15 V DD V For entire VDD range

D030A VSS —0.8V V 4.5V ≤ VDD ≤ 5.5V

D031 with Schmitt Trigger buffer VSS —0.2 VDD V

D032 MCLR, OSC1 (in RC mode) VSS —0.2 VDD V

D033 OSC1 (in XT and LP mode) VSS —0.3V V (Note 1)

OSC1 (in HS mode) VSS —0.3 VDD V(Note 1)

VIH Input High Voltage

I/O ports

D040 with TTL buffer 2.0 —VDD V4.5V ≤ VDD ≤ 5.5V

D040A 0.25 VDD + 0.8V —VDD V For entire VDD range

D041 with Schmitt Trigger buffer 0.8 VDD —VDD V For entire VDD range

D042 MCLR 0.8 VDD —VDD V

D042A OSC1 (in XT and LP mode) 1.6V —VDD V(Note 1)

OSC1 (in HS mode) 0.7 VDD —VDD V(Note 1)

D043 OSC1 (in RC mode) 0.9 VDD —VDD V

D070 IPURB PORTB Weak Pull-up Current 50 250 400 µAVDD = 5V, VPIN = VSS

IIL Input Leakage Current (Notes 2, 3)

D060 I/O ports ——±1 µAVss ≤ VPIN ≤ VDD, Pin at

hi-impedance

D061 MCLR, RA4/T0CKI ——±5 µAVss ≤ VPIN ≤ VDD

D063 OSC1 ——±5 µAVss ≤ VPIN ≤ VDD, XT, HS

and LP osc configuration

* These parameters are characterized but not tested.

†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PIC16F72 be driven with external clock in RC mode.

2: The leakage curr ent on the MC LR pin is stro ngly dep endent on the app lied vol tage le vel. The speci fied leve ls

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as current sourced by the pin.

PIC16F72

DS39597B-page 92  2002 Microchip Technology Inc.

VOL Output Low Voltage

D080 I/O ports ——0.6 V IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

D083 OSC2/CLKO (RC osc config) ——0.6 V IOL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

VOH O utput High Voltage

D090 I/O ports (Note 3) VDD - 0.7 —— VIOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

D092 OSC2/CLKO (RC osc config) VDD - 0.7 —— VIOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

D150* VOD Open Drain High Voltage ——12 V RA4 pin

Capacitive Loading Specs on Output Pins

D100 COSC2 OSC2 pin ——15 pF In XT, HS and LP modes

when external clock is used

to drive OSC1

D101 CIO All I/O pins and OSC2

(in RC mode) ——50 pF

D102 CBSCL, SDA in I2C mode ——400 pF

Program FLASH Memory

D130 EPEndurance 100 1000 —E/W 25°C at 5V

D131 VPR VDD for read 2.0 —5.5 V

14.2 DC Characteristics: PIC16F72 (Industrial, Extended)

PIC16LF72 (Industrial) (Continued)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Operating voltage VDD range as described in DC Specification,

Section 14.1.

Param

No. Sym Characteristic Min Typ†Max Units Conditions

* These parameters are characterized but not tested.

†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PIC16F72 be driven with external clock in RC mode.

2: The leakage curr ent on the MC LR pin is stro ngly dep endent on the app lied vol tage le vel. The speci fied leve ls

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as current sourced by the pin.

 2002 Microchip Technology Inc. DS39597B-page 93

PIC16F72

14.3 Timing Parameter Symbology

The timing parameter symbols have been created following one of the following formats:

FIGURE 14-3: LOAD CONDITIONS

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)

TF Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKO rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppercase letters and their meanings:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

I2C only

AA output access High High

BUF Bus free Low Low

TCC:ST (I2C specifications only)

HD Hold SU Setup

DAT DATA input hold STO STOP condition

STA START condition

VDD/2

Pin Pin

VSS VSS

RL= 464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load Condition 1 Load Condition 2

PIC16F72

DS39597B-page 94  2002 Microchip Technology Inc.

FIGURE 14-4: EXTERNAL CLOCK TIMING

TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

23344

Parameter

No. Symbol Characteristic Min Typ†Max Units Conditions

FOSC External CLKI Frequency

(Note 1) DC —1MHzXT Osc mode

DC —20 MHz HS Osc mode

DC —32 kHz LP Os c mo de

Oscillator Frequency

(Note 1) DC —4 MHz RC osc mode

0.1 —4 MHz XT Osc mode

5—

—20

200 MHz

kHz HS Osc mode

LP Osc mode

1TOSC External CLKI Period

(Note 1) 1000 ——ns XT Osc mode

50 ——ns HS Osc mode

5——ms LP Osc mode

Oscillator Period

(Note 1) 250 ——ns RC Osc mode

250 —10,000 ns XT Osc mode

50 —250 ns HS Osc mode

5——ms LP Osc mode

2TCY Instruction Cycle Time

(Note 1) 200 TCY DC ns TCY = 4/FOSC

3TosL,

TosH External Clock in (OSC1)

High or Low Time 500 ——ns XT oscillator

2.5 ——ms LP oscillator

15 ——ns HS oscillator

4TosR,

TosF External Clock in (OSC1)

Rise or Fall Time — —25 ns XT oscillator

— —50 ns LP os cil la tor

——15 ns HS oscillator

†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: Instruction cycle period (TCY) equals four ti mes the i nput osc illator tim e-base pe riod. All s pecified values are

based on charac teri za tio n data for that part ic ula r osci lla tor type under st and ard ope rati ng co ndi tions with

the device executing code. Exceeding these specified limits may result in an unstable oscillator operation

and/or highe r than ex pec te d current consumpti on. All device s are teste d to ope rate at "mi n" va lu es w ith an

external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max" cycle time

limit is "DC" (no clock) for all devices.

 2002 Microchip Technology Inc. DS39597B-page 95

PIC16F72

FIGURE 14-5: CLKO AND I/O TIMING

TABLE 14-2: CLKO AND I/O TIMING REQUIREMENTS

Note: Refer to Figure 14-3 for load conditions.

OSC1

CLKO

I/O Pin

(Input)

I/O Pin

(Output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

12 16

Old Value New Value

Param

No. Symbol Characteristic Min Typ†Max Units Conditions

10* TosH2ckL OSC1↑ to CLKO ↓ —75 200 ns (Note 1)

11* TosH2ckH OSC1↑ to C L KO ↑ —75 200 ns (Note 1)

12* TckR CLKO rise time —35 100 ns (Note 1)

13* Tck F CLKO fall ti m e —35 100 ns (Note 1)

14* TckL2ioV CLKO↓ to Port out v a lid ——0.5 TCY + 20 ns (No te 1)

15* TioV2ckH Port in valid before CLKO↑ TOSC + 200 ——ns (Note 1)

16* TckH2ioI Port in hold after CLKO↑ 0——ns (Note 1)

17* TosH2ioV OSC1↑ (Q 1 cycle) to Port out vali d —100 255 ns

18* TosH2ioI OSC1↑ (Q 2 cycle) to

Port input invalid (I/O in

hold time)

Standard (F)100——ns

Extended (LF)200——ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 ——ns

20* Ti oR Port output rise time St andard (F)—10 40 ns

Extended (LF)——145 ns

21* Ti oF Port output fall time Standard (F)—10 40 ns

Extended (LF)——145 ns

22††*T

INP INT pin high or low time TCY ——ns

23††*T

RBP RB7:RB4 change INT high or low time TCY ——ns

* T hes e parameters are characterized but not tested.

†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are

no t te sted.

†† These parameters are asynchronous events, not related to any internal clock edges.

Note 1: M easurements are taken in RC mode, where CLKO output is 4 x TOSC.

PIC16F72

DS39597B-page 96  2002 Microchip Technology Inc.

FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMI NG

FIGURE 14-7: BROWN-OUT RESET TIMING

TABLE 14-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

Reset

I/O Pins

Note: Refer to Figure 14-3 for load conditions.

VDD VBOR

Parameter No. S ymbo l Characteristic Min Typ†Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 ——µsVDD = 5V, -40°C to +85°C

31* TWDT Watchdog Timer Time-out Period

(No Prescaler) 71833msVDD = 5V, -40°C to +85°C

32 TOST Osc illation Start-up Timer Period —1024 TOSC ——TOSC = OSC1 period

33* TPWRT Power-up Timer Period 28 72 132 m s VDD = 5V, -40°C to +85°C

34 TIOZ I/O Hi-impedance from MCLR Low

or Watchdog Timer Reset ——2.1 µs

35 TBOR Brown-out Reset Pulse Width 100 ——µsVDD ≤ VBOR (D005)

* These parameter s are characterized but not tested.

†Data in "Typ" co lumn is at 5V, 25°C u nless otherwise stat ed. These parameters are for design guidance only and are not te ste d.

 2002 Microchip Technology Inc. DS39597B-page 97

PIC16F72

FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 14-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Symbol Characteristic Min Typ†Max Units Conditions

40* T t 0H T0CKI High Pulse Width No Pres caler 0.5 TCY + 20 ——ns Must also meet

parame ter 4 2

With Prescaler 10 ——ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 ——ns Must also meet

parame ter 4 2

With Prescaler 10 ——ns

42* Tt0P T0CKI Period No Prescaler TCY + 40 ——ns

With Prescaler Greater of:

20 or TCY + 40

——ns N = prescale value

(2, 4, ..., 256)

45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5 TCY + 20 ——ns Must also meet

parame ter 4 7

Synchronous,

Prescaler = 2,4,8 Standard(F)15——ns

Extended(LF)25——ns

Asynchronous Standard(F)30——ns

Extended(LF)50——ns

46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5 TCY + 20 ——ns Must also meet

parame ter 4 7

Synchronous,

Prescaler = 2,4,8 Standard(F)15——ns

Extended(LF)25——ns

Asynchronous Standard(F)30——ns

Extended(LF)50——ns

47* Tt1P T1CKI Input

Period Synchronous Standard(F) Greater of:

30 or TCY + 40

——ns N = prescale value

(1, 2, 4, 8)

Extended(LF) Greater of:

50 or TCY + 40

N = prescale value

(1, 2, 4, 8)

Asynchronous Standard(F)60——ns

Extended(LF) 100 ——ns

Ft1 Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz

48 TCKEZtmr1 Delay from Ext ernal Clock Edge to Timer Increment 2 TOSC —7 TOSC —

* T hes e parameters are characterized but not tested.

†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are

no t te sted.

Note: Refer to Figure 14-3 for load conditions.

RA4/T0CKI

RC0/T1OSO/T1CKI

TMR0 o r

TMR1

PIC16F72

DS39597B-page 98  2002 Microchip Technology Inc.

FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 )

TABLE 14-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)

Note: Refer to Figure 14-3 for load conditions.

RC2/CCP1

(Capture Mode)

50 51

53 54

RC2/CCP1

(Compare or PWM Mode)

Param

No. Symbol Characteristic Min Typ†Max Units Conditions

50* TccL CCP1 input low

time No Prescaler 0.5 TCY + 20 ——ns

With Prescaler Standard(F)10——ns

Extended(LF)20——ns

51* TccH CCP1 input high

time No Prescaler 0.5 TCY + 20 ——ns

With Prescaler Standard(F)10——ns

Extended(LF)20——ns

52* Tc cP CCP1 inpu t per iod 3 TCY + 40

N——ns N = prescale

value (1,4 or 16)

53* TccR CCP1 output rise time Standard(F)—10 25 ns

Extended(LF)—25 50 ns

54* TccF CCP1 output fall time Standard(F)—10 25 ns

Extended(LF)—25 45 ns

* These parameters are characterized but not tested.

†Data in "Typ" column is at 5V, 25°C unless other wise stat ed. Thes e para meters are for desi gn guida nce onl y

and are not tested.

 2002 Microchip Technology Inc. DS39597B-page 99

PIC16F72

FIGURE 14-10: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

FIGURE 14-11: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76

MSb LSb

Bit6 - - - - - -1

MSb In LSb In

Bit6 - - - -1

Note: Refer to Figure 14-3 for load conditions.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb

MSb In

Bit6 - - - - - -1

LSb In

Bit6 - - - -1

LSb

Note: Refer to Figure 14-3 for load conditions.

PIC16F72

DS39597B-page 100  2002 Microchip Technology Inc.

FIGURE 14-12: SPI SLAVE MODE TIMING (CKE = 0)

FIGURE 14-13: SPI SLAVE MODE TIMING (CKE = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76 77

MSb LSb

Bit6 - - - - - -1

MSb In Bit6 - - - -1 LSb In

Note: Refer to Figure 14-3 for load conditions.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

SDI

75, 76

MSb Bit6 - - - - - -1 LSb

MSb In Bit6 - - - -1 LSb In

Note: Refer to Figure 14-3 for load conditions.

 2002 Microchip Technology Inc. DS39597B-page 101

PIC16F72

TABLE 14-6: SPI MODE REQUIREMENTS

FIGURE 14-14 : I2C BUS START/STOP BITS TIMING

Param

No. Symbol Characteristic Min Typ†Max Units Conditions

70* TssL2scH,

TssL2scL SS↓ to SCK↓ or SCK↑ input TCY ——ns

71* TscH SCK input high time (Slave mode) TCY + 20 ——ns

72* TscL SCK input low time (Slave mode) TCY + 20 ——ns

73* TdiV2scH,

TdiV2scL Setup time of SDI data input to SCK edge 100 ——ns

74* TscH2diL,

TscL2diL Hold time of SDI data input to SCK edge 100 ——ns

75* TdoR SDO data output ris e time S tandard(F)

Extended(LF)—

—10

25 25

50 ns

76* TdoF SDO data output fall time —10 25 ns

77* TssH2doZ SS↑ to SDO output hi-impedance 10 —50 ns

78* TscR SCK output rise time

(Master mo de) Standard(F)

Extended(LF)—

—10

25 25

50 ns

79* TscF SCK output fall time (Master mode) —10 25 ns

80* TscH2doV,

TscL2doV SDO dat a outp ut val id after

SCK edge Standard(F)

Extended(LF)—

——

—50

145 ns

81* TdoV2scH,

TdoV2scL SDO data output setup to SCK edge TCY ——ns

82* TssL2doV SDO data output valid after SS↓ edge ——50 ns

83* TscH2ssH,

TscL2ssH SS ↑ after SCK edge 1.5 TCY + 40 ——ns

* These parameters are characterized but not tested.

†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note: Refer to Figure 14-3 for load conditions.

SCL

SDA

START

Condition STOP

Condition

PIC16F72

DS39597B-page 102  2002 Microchip Technology Inc.

TABLE 14-7: I2C BUS START/STOP BITS REQUIREMENT S

FIGURE 14-15 : I2C BUS DATA TIMING

Param

No. Symbol Characteristic Min Typ Max Units Conditions

90* TSU:STA START condition 100 kHz mode 4700 —— ns Only relevant for Repeated

START condition

Setu p time 400 kHz mode 600 ——

91* THD:STA START condition 100 kHz mode 4000 —— ns After this period, the first clock

pulse is gen erated

Hold time 400 kHz mode 600 ——

92* TSU:STO STOP condition 100 kHz mode 4700 —— ns

Setu p time 400 kHz mode 600 ——

93 THD:STO STOP condition 100 kHz mode 4000 —— ns

Hold time 400 kHz mode 600 ——

* These parameters are characterized but not tested.

Note: Refer to Figure 14-3 for load conditions.

91 92

100 101

103

106 107

109 109 110

102

SCL

SDA

Out

 2002 Microchip Technology Inc. DS39597B-page 103

PIC16F72

TABLE 14-8: I2C BUS DATA REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

100* THIGH Clock High Time 100 kHz mode 4.0 —µs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 —µs Device must operate at a

minimum of 10 MHz

SSP Module 1.5 TCY —

101* TLOW Clock Low Time 100 kHz mode 4.7 —µs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 —µs Device must operate at a

minimum of 10 MHz

SSP Module 1.5 TCY —

102* TRSDA and SCL Rise

Time 100 kHz mode —1000 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 - 400 pF

103* TFSDA and SCL Fall

Time 100 kHz mode —300 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 - 400 pF

90* TSU:STA START Condition

Setup Time 100 kHz mode 4.7 —µs O nly relevant for

Repeated START

condition

400 kHz mode 0.6 —µs

91* THD:STA START Condition

Hold Time 100 kHz mode 4.0 —µs After this period, the first

clock pulse is generated

400 kHz mode 0.6 —µs

106* THD:DAT Data Input Hold

Time 100 kHz mode 0 —ns

400 kHz mode 0 0.9 µs

107* TSU:DAT Data Input Setup

Time 100 kHz mode 250 —ns (Note 2)

400 kHz mode 100 —ns

92* TSU:STO STOP Condition

Setup Time 100 kHz mode 4.7 —µs

400 kHz mode 0.6 —µs

109* TAA Output Valid from

Clock 100 kHz mode —3500 ns (Note 1)

400 kHz mode ——ns

110* TBUF Bus Free Time 100 kHz mode 4.7 —µs Tim e the bus must b e free

before a new transmission

can start

400 kHz mode 1.3 —µs

CBBus Capacitive Loading — 400 pF

* These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A Fast mode (400 kHz) I2C bus devic e c an be used in a Standard mode (100 kHz) I 2C bus s ys tem , b ut the

requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LO W p erio d of th e SC L si gna l. If s uch a dev ic e do es stret ch th e LOW pe riod of the SCL sig nal ,

it must outp ut the nex t da ta bit to the SDA line TR max.+TSU:DAT = 1000 + 250 = 125 0 ns (acc ord ing to the

Standard mode I2C bus specification), bef ore the SCL line is released.

PIC16F72

DS39597B-page 104  2002 Microchip Technology Inc.

TABLE 14-9: A/D CONVERTER CHARACTERISTICS:PIC16F72 (INDUSTRIAL)

PIC16LF72 (INDUSTRIAL)

Param

No. Sym Characteristic Min Typ†Max Units Conditions

A01 NRResolution PIC16F72 ——8 bits bit VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

PIC16LF72 ——8 bits bit VREF = VDD = 2.2V

A02 EABS Total A bsolute Error ——< ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A03 EIL Integral Linearity Error ——< ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A04 EDL Dif fere nti al Lin eari ty Error ——< ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A05 EFS Full Scale Error ——< ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A06 EOFF Offset Error ——< ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A10 —Monotonicity (N ote 3) —guaranteed ——VSS ≤ VAIN ≤ VREF

A20 VREF Reference Voltage 2.5

2.2 —

—VDD+0.3

VDD+0.3 V

V-40°C to +85°C

0°C to +85°C

A25 VAIN Analog Input Voltage VSS - 0.3 —VREF + 0.3 V

A30 ZAIN Recommended Impedance of

Analog Vo ltage Source ——10.0 kΩ

A40 IAD A/D Conversion

Current (VDD)PIC16F72 —180 —µA Average current

consum pti on when A/D

is on (Note 1).

PIC16LF72 —90 —µA

A50 IREF VREF input current (Note 2) N/A

——

—± 5

500 µA

µADuring VAIN acquisition.

During A/D Conversion

cycle.

* These parameters are characterized but not tested.

†Dat a in “Typ” column is at 5V, 25°C unles s otherw ise s tat ed. The se p arame ters ar e fo r desig n guid ance only

and are not tested.

Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current

spec includes any such leakage from the A/D module.

2: VREF current is from the RA3 pin or the VDD pin, whichever is select ed as a reference inp ut.

3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

 2002 Microchip Technology Inc. DS39597B-page 105

PIC16F72

FIGURE 14-16: A/D CONVE RSION TIMING

TABLE 14-10: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2)(1)

7 6543210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 TCY

134

Param

No. Sym Characteristic Min Typ†Max Units Conditions

130 TAD A/D Clock Period PIC16F72 1.6 ——µsTOSC based, VREF ≥ 3.0V

PIC16LF72 2.0 ——µsT

OSC based,

2.0V ≤ VREF ≤ 5.5V

PIC16F72 2.0 4.0 6.0 µs A/D RC mode

PIC16LF72 3.0 6.0 9.0 µs A/D RC mode

131 TCNV Conversion Time (not including S/H time)

(Note 1) 9—9TAD

132 TACQ Acquisition Time 5* ——µs The minimum time is the

amplifier settling time. This

may be us ed if the “new”

input voltage has not

changed by more than 1 LSb

(i.e., 20.0 mV @ 5.12V) from

the last sampled voltage (as

stated on CHOLD).

134 TGO Q4 to A/D Clock Start —TOSC/2 ——If the A/D clock source is

selected as RC, a time of T CY

is added before the A/D

clock starts. This allows the

SLEEP instr uction to be

executed.

* These parameters are characterized but not tested.

†Dat a i n “Typ” column is at 5V , 25°C unless oth erwise st ated. These p arameters are for desig n guidanc e only

and are not tested.

Note 1: ADR ES register may be read on the following TCY cycle.

PIC16F72

DS39597B-page 106  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. DS39597B-page 107

PIC16F72

15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

“T ypical” represent s the mean of the distribution at 25°C. “Maximum” or “minimum” represent s (mean + 3σ) or (mean - 3σ)

respectively, where σ is a standard deviation, ov er the whole temperature range .

FIGURE 15-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)

FIGURE 15-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics liste d herein are

not teste d or gu aranteed. In s ome gra phs or table s, th e da t a pre se nte d ma y be out sid e the sp eci f ie d op er-

ating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

4 6 8 10 12 14 16 18 20

FOSC (M Hz)

(mA)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ 25°C

Maximu m: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

4 6 8 10 12 14 16 18 20

FOSC (MH z )

(mA)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

PIC16F72

DS39597B-page 108  2002 Microchip Technology Inc.

FIGURE 15-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE)

FIGURE 15-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

FOSC (MHz)

(mA)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

FOSC (MHz)

(mA)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to +125°C)

Mini mum: me an – 3σ (-40°C to +125°C)

 2002 Microchip Technology Inc. DS39597B-page 109

PIC16F72

FIGURE 15-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE)

FIGURE 15-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)

30 50 6040 70 80 90 100

IDD (

FOSC (kHz )

3.5V

3.0V

2.0V

5.5V

5.0V

4.5V

4.0V

2.5V

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3 σ (-40°C to +125°C)

2030 50 6040 70 80 90 100

IDD (

FOSC (kHz )

100

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

PIC16F72

DS39597B-page 110  2002 Microchip Technology Inc.

FIGURE 15-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R

(RC MODE, C = 20 pF, 25°C)

FIGURE 15-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R

(RC MODE, C = 100 pF, 25°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Freq (MHz)

10 kΩ

100 kΩ

Operation above 4 MHz is not recomende d

0.0

1.0

2.0

3.0

4.0

5.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V )

Freq (MHz)

5.1 kΩ

10 kΩ

100 kΩ

Operation above 4 MHz is not recomended

 2002 Microchip Technology Inc. DS39597B-page 111

PIC16F72

FIGURE 15-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R

(RC MODE, C = 300 pF, 25°C)

FIGURE 15-10 : IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

100

150

200

250

300

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Freq (kHz)

3.3 kΩ

5.1 kΩ

10 kΩ

100 kΩ

0.01

0.1

100

2.02.53.03.54.04.55.05.5

VDD (V)

(uA)

Max 125°C

Max 85°C

Typ 25°C

Typical: statistical mean @ 25°C

Maximu m: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

PIC16F72

DS39597B-page 112  2002 Microchip Technology Inc.

FIGURE 15-11: ∆IBOR vs. VDD OVER TEMPERATURE

FIGURE 15-12: TYPICAL AND MAXIMUM ∆IWDT vs. VDD OVER TEMPERATURE

100

1,000

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

Device in

RESET

Device in

SLEEP

Indeterminant

State

Max (125˚C)

Typ (25˚C)

Max (125˚C)

Typ (25˚C)

Typical: statistical mean @ 25°C

Maxi mum: me an + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

Note: Device current in RESET

depends on Oscillator mode,

frequency and circuit.

IDD (

0.1

100

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

Max (125˚C)

Typ (25˚C)

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

∆

IWDT (

 2002 Microchip Technology Inc. DS39597B-page 113

PIC16F72

FIGURE 15-13: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C)

FIGURE 15-14: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C)

2.02.53.03.54.04.55.05.5

VDD (V)

WDT Period (ms)

Max

(125°C)

Typ

(25°C)

Min

(-40°C)

Typical: statistical mean @ 25°C

Maxi mum: me an + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

2.02.53.03.54.04.55.05.5

VDD (V)

WDT Period (ms)

125°C

85°C

25°C

-40°C

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to +125°C)

Mini mum: me an – 3σ (-40°C to +125°C)

PIC16F72

DS39597B-page 114  2002 Microchip Technology Inc.

FIGURE 15-15: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C)

FIGURE 15-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 5 10 15 20 25

IOH (-mA)

(V)

Max

Typ (25°C)

Min

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 5 10 15 20 25

IOH (-mA)

(V)

Max

Typ (25°C)

Min

Typical: statistical mean @ 25°C

Maximu m: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

 2002 Microchip Technology Inc. DS39597B-page 115

PIC16F72

FIGURE 15-17: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C)

FIGURE 15-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 5 10 15 20 25

IOL (-mA)

(V)

Max (125°C)

Max (85°C)

Typ (25°C)

Min (-40°C)

Typical: statistical mean @ 25°C

Maxi mum: me an + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 5 10 15 20 25

IOL (-mA)

(V)

Max (125°C)

Max (85°C)

Typ (25°C)

Min (-40°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

PIC16F72

DS39597B-page 116  2002 Microchip Technology Inc.

FIGURE 15-19: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO +125°C)

FIGURE 15-20: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C)

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

(V)

VTH Max (-40°C)

VTH Min (125°C)

VTH Typ (25°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

(V)

VIH Max (125°C)

VIH Min (-40°C)

VIL Max (-40°C)

VIL Min (125°C)

Typical: statistical mean @ 25°C

Maximu m: mean + 3σ (-40°C to +125°C)

Minimum: mean – 3σ (-40°C to +125°C)

 2002 Microchip Technology Inc. DS39597B-page 117

PIC16F72

16.0 PACKAGE MARKING INFORMATION

28-Lead SOIC

YYWWNNN

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead PDIP (Skinny DIP) Example

XXXXXXXXXXXXXXXXX

0217017

PIC16F72-I/SP

0210017

PIC16F72-I/SO

28-Lead SSOP

YYWWNNN

XXXXXXXXXXXX

Example

0220017

PIC16F72

28-Lead QFN Example

XXXXXXXX

YYWWNNN

PIC16F72

-I/ML

0210017

-I/SS

Legend: XX...X Customer specific information*

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week c ode (week of Ja nuary 1 is week ‘01’)

NNN Alphanumeric traceability code

Note: In the even t the full Mic rochip part number c annot be marked on one line, it wil l

be carried over to the nex t lin e thu s l imi tin g the num be r of av ail abl e ch arac te rs

for customer specific information.

*Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

PIC16F72

DS39597B-page 118  2002 Microchip Technology Inc.

28-Lead Skinny Plasti c Dual In-line (SP) – 300 mil (PDIP)

1510515105

Mold Draft Angle Bottom 1510515105

Mold Draft Angle Top 10.928.898.13.430.350.320

Overall Row Spacing §0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008

Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125A2Molded P acka ge Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units

Notes:

JEDEC Equivalent: MO-095

Drawing No. C04-070

* Controlling Parameter

Dimension D and E1 do not include mo ld flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254 mm ) per s ide.

§ Significant Characteristic

 2002 Microchip Technology Inc. DS39597B-page 119

PIC16F72

28-Lead Plastic Small Outline (SO) –Wide, 300 mil (SOIC)

Foot Angle Top φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff §2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimensi on Lim its MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

§ Significant Characteristic

PIC16F72

DS39597B-page 120  2002 Microchip Technology Inc.

28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-150

Drawing No. C04-073

10501050Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840

Foot Angle 0.250.180.10.010.007.004

Lead Thickness 0.940.750.56.037.030.022LFoot Length 10.3410.2010.06.407.402.396DOvera l l Length 5.385.255.11.212.207.201E1Molded Package Width 8.107.857.59.319.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff §1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits

§ Significant Characteristic

 2002 Microchip Technology Inc. DS39597B-page 121

PIC16F72

28-Lead Plasti c Quad Flat No Leads Package (ML) 6x6 mm Body (QFN)

Lead Width

* Controlling Parameter

Notes:

Mold Draft Angle Top

.009

.011 .014 0.23

0.28 0.35

Pitch

Number of Pins

Overall Width

Standoff

Molded Package Length

Overall Length

Molded Package Width

Molded Package Thickness

Overall Height

MAX

Units

Dimension Limits

A.026

.236 BSC

.000

.226 BSC

INCHES

.026 BSC

MIN 28

NOM MAX

0.65

.031

.002 0.00

6.00 BSC

5.75 BSC

MILLIMETERS*

.039

MIN 28

0.65 BSC

NOM

0.80

0.05

1.00

EXPOSED

METAL

PADS

BOTTOM VIEW

.008 REF.Base Thickness A3 0.20 REF.

TOP VI EW

0.85.033

.0004 0.01

.236 BSC

.226 BSC 6.00 BSC

5.75 BSC

Lead Length

Tie Bar Width L .020.024.0300.500.600.75

R .005.007.0100.130.170.23

T ie Bar Length Q.012 .016 .026 0.30 0.40 0.65

Chamfer CH .009.017.0240.240.420.60

CH x 45

Exposed Pa d Width

Exposed Pa d Len gth .140 .146 .152 3.55 3.70 3.85

.140 .146 .152 3.55 3.70 3.85

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC equivalent: pending

Drawing No. C04-114

PIC16F72

DS39597B-page 122  2002 Microchip Technology Inc.

28-Lead Plasti c Quad Flat No Leads Package (ML) 6x6 mm Body (QFN) (Continued)

Pad Width

*Controlling Parameter

Drawing No. C04-2114

B .009 .011 .014 0.23 0.28 0.35

Pitch MAX

Units

Dimension Limits

INCHES

.026 BSC

MIN NOM MAX

MILLIMETERS*

MIN 0.65 BSC

NOM

Pad Length

Pad to Solder Mask L .020 .024 .030 0.50 0.60 0.75

M .005 .006 0.13 0.15

M B

PACKAGE

EDGE

SOLDER

MASK

 2002 Microchip Technology Inc. DS39597B-page 123

PIC16F72

APPENDIX A: REVISION HISTORY

APPENDIX B: CONVERSION CONSIDERATIONS

Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table B-1.

TABLE B-1: CONVERSION CONSIDERATIONS

Version Date Revision Desc ri ption

A April 2002 This is a ne w dat a sheet. Howeve r , t his devi ce is s imilar to the PIC16C 72 devi ce

found in the PIC16C7X Data Sheet (DS30390), the PIC16C72A Data Sheet

(DS35008) or the PIC16F872 device (DS30221).

B May 2002 Final data sheet. Includes device characterization data. Minor typographic

revisions throughout.

Characteristic PIC16C72/72A PIC16F872 PIC16F72

Pins 28 28 28

Timers 3 3 3

Interrupts 8 10 8

Communication Basic SSP/SSP

(SPI, I2C Slave) MSSP

(SPI, I2C Master/Slave) SSP

(SPI, I2C Slave)

Frequency 20 MHz 20 MHz 20 MHz

A/D 8-bit, 5 Channels 10-bit, 5 Channels 8-bit, 5 Channels

CCP 1 1 1

Program Memory 2K EPROM 2K FLASH

(1,000 E/W cycles) 2K F LASH

(1000 E/W cycles)

RAM 128 bytes 128 bytes 128 bytes

EEPROM Data None 64 bytes None

Other —In-Circuit Debugger,

Low Voltage Program ming —

PIC16F72

DS39597B-page 124  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. DS39597B-page 125

PIC16F72

INDEX

A/D Acquisition Requirements ..................................... .... ..56

ADCON0 Register.......................................................53

ADCON1 Register.......................................................53

ADIF bit....................... ...... ...... ................. ....... ...... ......54

ADRES Register.........................................................53

Analog-to-Digital Converter.........................................53

Associ a te d Re g i sters.... ...... ....... ...... ................. ...... ....57

Configuring Analog Port Pins......................................56

Configuring the Interrupt.............................................54

Configuring the Module...............................................54

Conversi o n Clo ck...... ...... ...... ....... ...... ...... ....... ...... ......56

Conversions................................................................56

Converter Characteristics .........................................104

Effects of a RESET.....................................................57

Internal Sampling Switch (Rss) Impedance... .............56

Operation During SLEEP............................................57

Source Impedance.................. ......... .... .... .... ........... ....56

Use of the the CCP Trigger .........................................57

Absolute Maximum Ratings ................................................87

ACK.....................................................................................49

ADCON0 GO/DONE bit......................................................54

ADRES Register.............................................................9, 54

Application Notes

AN546 (Using the Analog-to-Digital Converter)..........53

AN552 (Implementing Wake-up on

Key Strokes Using PIC16F7X)...............................23

AN556 (Implementing a Table Read)..........................19

AN578 (Use of the SSP Module in the

I2C Multi-Master Environment) ...............................43

AN607 (Power-up Trouble Shooting)..........................64

Assembler

MPASM Assembler.....................................................81

BF .......................................................................................44

Block Diagrams

A/D..............................................................................55

Analog Input Model.....................................................55

Capture Mode Operation ....................... .... .. ..... .... .. .. ..38

Compare Mode Operation ................... .... .. .. ....... .. .... ..39

In-Circuit Serial Programming Connections................72

Inter rupt Logic......... ...... ...... ....... ...... ................. ...... ....68

On-Chip Rese t Circuit......... ............. ...... ...... ....... ........63

PIC16F72......................................................................5

PORTC .......................................................................25

PWM...........................................................................41

RA3:RA0 and RA5 Port Pins ......................................21

RA4/T0CKI Pin. ....... ...... ...... ....... ...... ...... ...... ....... ...... ..21

RB3:RB0 Port Pins ............. ....... ...... ...... ...... ............. ..23

RB7:RB4 Port Pins ............. ....... ...... ...... ...... ............. ..23

Recommended MCLR Circuit.... ...... ...... ...... ....... ...... ..63

SSP in I2C Mode.........................................................48

SSP in SPI Mode........................................................46

Timer0/WDT Prescaler.......... ....... ...... ................. ...... ..29

Timer1.........................................................................32

Timer2.........................................................................35

Watchdog Timer (WDT) ..............................................70

BOR. See Brown-out Reset

Brown-out Reset (BOR)....................................59, 62, 65, 66

Buffe r Full Status bi t, BF............. ....... ................ ....... ...... ....44

Capture/Compare/PWM ..................................................... 37

Associated Registers with PWM and Timer2.............. 42

Associated Registers, Capture, Compare

and Timer1............................................................. 40

Capture

CCP1IF............................................................... 38

CCPR1 ............................................................... 38

CCPR1H:CCPR1L.............................................. 38

Capture Mod e................. ................. ....... ...... ...... ........ 38

CCP Mode Timer Resources.................................... .. 37

CCP Pin Configuration ......................................... 38, 39

CCP Presca le r................... ...... ...... ...... ....... ...... ...... .... 38

CCPR1L Regist e r....... ....... ...... ...... ...... ....... ...... ...... .... 37

Compar e Mod e............. ....... ...... ...... ....... ...... ...... ...... .. 39

PWM Mode..... ...... ................. ...... ...... ................. ...... .. 41

PWM, Example Frequencies/Resolutions.................. 42

Softwar e In terrupt....... ....... ...... ...... ...... ....... ................ 38

Softwar e In terrupt Mode...... ...... ...... ................. ...... .... 39

Special Event Trigger and A/D Conversions .............. 39

Special Event Trigger Output of CCP1....................... 39

Timer1 Mode Selection.................. .. .... ......... .... .... 38, 39

CCPR1H Register................. ....... ...... ............. ...... ...... ...... .. 37

CCPxM0 bit......................................................................... 37

CCPxM1 bit......................................................................... 37

CCPxM2 bit......................................................................... 37

CCPxM3 bit......................................................................... 37

CCPxX bit........................................................................... 37

CCPxY bit........................................................................... 37

CKE .................................................................................... 44

CKP .................................................................................... 45

Clock Polarity Select bit, CKP............................................. 45

Code Examples

Changing Between Capture Prescalers ..................... 38

FLASH Program Read............... ................. ...... ...... .... 28

Indirect Addressing..................................................... 19

Initializing PORTA....................................................... 21

Initializing PORTB ...................................................... 23

Initializing PORTC...................................................... 25

Saving STATUS, W and PCLATH

Registers in RAM ................................................... 69

Code Protection............................................................ 59, 72

Configuration Bits ............................................................... 59

Configuration Word............................................................. 60

Conversi on Cons id e ration s. ....... ...... ...... ...... ....... ...... ...... .. 123

D/A...................................................................................... 44

Data Memory

General Purpose Register File............................. .... .... 7

Special Function Registers........................................... 9

Data/Address bit, D/A......................................................... 44

DC and AC Characteristics

Graphs and Tables ................................................... 107

DC Characteristics.............................................................. 89

Development Support......................................................... 81

Device Overview ................................................................... 5

Direct Add ressing....... ...... ...... ....... ...... ...... ....... ...... ............ 20

Electrical Characteristics.................................................... 87

Errata.................................................................................... 3

PIC16F72

DS39597B-page 126  2002 Microchip Technology Inc.

FLASH Program Memory

Associ a te d Re g i sters........ ...... ...... ................. ...... .......28

Operation During Code Protect...................................28

Reading.......................................................................28

FSR Register...................................................................9, 10

I/O Ports......................... ................. ...... ................. ...... .......21

PORTA........................................................................21

PORTB........................................................................23

PORTC........................................................................25

I2CAssoc i a te d Re g i sters........ ...... ...... ................. ...... .......51

Master Mode...............................................................51

Mode Selection ...........................................................48

Multi-Master Mode ......................................................51

SCL and SDA pins......................................................48

Slave Mode.................................................................48

ICEPIC In -Circuit Em ulator ................... ................. ...... .......82

ID Locations........................................................................72

In-Circuit Serial Programming (ICSP).................................72

INDF Register .....................................................................10

Indirect Addressing.............................................................20

FSR Register ..............................................................19

INDF Register.............................................................19

Instruction Format...............................................................73

Instruction Set.....................................................................73

ADDLW .......................................................................75

ADDWF.......................................................................75

ANDLW .......................................................................75

ANDWF.......................................................................75

BCF.............................................................................75

BSF.............................................................................75

BTFSC ........................................................................76

BTFSS ........................................................................76

CALL...........................................................................76

CLRF...........................................................................76

CLRW..........................................................................76

CLRWDT.....................................................................76

COMF .........................................................................77

DECF ..........................................................................77

DECFSZ......................................................................77

GOTO..........................................................................77

INCF............................................................................77

INCFSZ.......................................................................77

IORLW.........................................................................78

IORWF........................................................................78

MOVF..........................................................................78

MOVLW.......................................................................78

MOVWF ......................................................................78

NOP............................................................................78

RETFIE .......................................................................79

RETLW........................................................................79

RETURN.....................................................................79

RLF .............................................................................79

RRF.............................................................................79

SLEEP ........................................................................79

SUBLW........................................................................80

SUBWF.......................................................................80

Summary Table............. ...... ...... ...... ....... ................. ....74

SWAPF .......................................................................80

XORLW.......................................................................80

XORWF.......................................................................80

INT In t e rr up t (RB0/INT) . See Interrupt Sources

INTCON Register

GIE bit............ ....... ................ ................. ................. .... 14

INTE bit....................... ................. ...... ................. ........ 14

INTF bit.... ...... ................. ...... ................. ...... ....... ........ 14

RBIF bit........ ...... ....... ...... ...... ................. ...... ....... ...... ..14

TMR0IE bit.................................................................. 14

Internal Sampling Switch (Rss) Impedance........................ 56

Interrupt Sources.......................................................... 59, 68

RB0/INT Pin, External................................................. 69

TMR0 Overflow........................................................... 69

Interrupts

RB7:RB4 Port Change....................... .. .... .... ....... .. .... .. 23

Synchronous Serial Port Interrupt............................... 16

Interrupts, Context Saving During....................................... 69

Interrupts, Enable Bits

Global Interrupt Enable (GIE bit) .......................... 14, 68

Interrupt-on-Change (RB7:RB4)

Enable (RBIE bit)................................................... 69

RB0/INT Enable (INTE bit) ......................................... 14

TMR0 Overflow Enable (TMR0IE bit)......................... 14

Interrupts, Flag bits

Interrupt-on-Change (RB7:RB4) Flag

(RBIF b i t) ..................... ................. ................. ........ 14

Interrupt-on-Change (RB7:RB4) Flag

(RBIF b i t) ..................... ................. ................. ..14, 69

RB0/INT Flag (INTF bit).............................................. 14

TMR0 Overflow Flag (TMR0I F bi t)........... ....... ...... ...... 69

KEELOQ Evaluation and Programming Tools...................... 84

Loading of PC....................... .... .... ......... .. .... .... .... ......... .. .... 18

Master Clear (MCLR)

MCLR Reset, Normal Operation..................... 62, 65, 66

MCLR Reset, SLEEP............ ....... ...... ............. 62, 65, 66

Operation and ESD Protection ................................... 63

Memory

Data Mem o ry..... ....... ...... ................. ...... ...... ....... ...... .... 7

Program Memory.......................................................... 7

MPLAB C17 and MPLAB C18 C Compilers ....................... 81

MPLAB ICD In-Circuit Debugger ........................................ 83

MPLAB ICE High Performance Universal

In-Circu it Emulator wit h MPLA B IDE.................. ...... .... 82

MPLAB Integrated Development

Environ ment Softwa re........ ................. ...... ....... ............ 81

MPLINK Object Linker/MPLIB Object Librarian.................. 82

On-Line Support ................. .. .... .... .. ....... .... .... .. .... ....... .... .. 131

OPCODE Field Desc r i p tions....... ....... ...... ...... ...... ............. .. 73

OPTION_REG Register

INTEDG bit........... ...... ...... ................. ...... ....... ............ 13

PS2:PS0 bits............................................................... 13

PSA bit........................................................................ 13

RBPU bit............ ....... ...... ...... ................. ...... ....... ........ 13

T0CS bit...................................................................... 13

T0SE bit......... ....... ...... ...... ...... ................. ....... ............ 13

 2002 Microchip Technology Inc. DS39597B-page 127

PIC16F72

Oscillator Configuration.................................................59, 61

Crystal Oscillator/Ceramic Resonators.......................61

HS.........................................................................61, 65

LP..........................................................................61, 65

RC...................................................................6 1, 62, 65

XT .........................................................................61, 65

Oscillat o r, WDT.... ............. ...... ...... ....... ............ ....... ...... ......70

P..........................................................................................44

Package Marking Information ...........................................117

PCFG0 bit.......... ...... ....... ................ ....... ................. ...... ......54

PCFG1 bit.......... ...... ....... ................ ....... ................. ...... ......54

PCFG2 bit.......... ...... ....... ................ ....... ................. ...... ......54

PCL Register.............................................................9, 10, 18

PCLATH Register .....................................................9, 10, 18

PCON Register...................................................................64

POR bit .......................................................................17

PICDEM 1 Low Cost PICmicro

Demonstration Board....................................................83

PICDEM 17 Demonstr a tion Board......... ...... ...... ....... ..........84

PICDEM 2 Low Cost PIC16CXX

Demonstration Board....................................................83

PICDEM 3 Low Cost PIC16CXXX

Demonstration Board....................................................84

PICSTART Plus Ent ry Level

Development Programmer ...........................................83

Pin Functions

MCLR/VPP.....................................................................6

OSC1/CLKI...................................................................6

OSC2/CLKO .................................................................6

RA0/AN0.......................................................................6

RA1/AN1.......................................................................6

RA2/AN2.......................................................................6

RA3/AN3/VREF..............................................................6

RA4/T0CKI....................................................................6

RA5/AN4/SS.................................................................6

RB0/INT........................................................................6

RB1...............................................................................6

RB2...............................................................................6

RB3...............................................................................6

RB4...............................................................................6

RB5...............................................................................6

RB6/PGC......................................................................6

RB7/PGD......................................................................6

RC0/T1OSO/T1CKI ......................................................6

RC1/T1OSI ...................................................................6

RC2/CCP1....................................................................6

RC3/SCK/SCL ..............................................................6

RC4/SDI/SDA ...............................................................6

RC5/SDO......................................................................6

RC6...............................................................................6

RC7...............................................................................6

VDD ...............................................................................6

VSS................................................................................6

Pinout Descriptions

PIC16F72......................................................................6

POP ....................................................................................19

POR. See Power-on Reset

PORTA

Associ a te d Re g i sters.... ...... ....... ...... ................. ...... ....22

Functions ....................................................................22

PORTA Register................................................................... 9

PORTB

Associ a te d Re g i sters......... ...... ...... ...... ....... ................ 24

Functions.................................................................... 24

Pull-up Enable (RBPU bit).......................................... 13

RB0/INT Edge Select (INTEDG bit)............................ 13

RB0/INT Pin, External ................................................ 69

RB7:RB4 Interrupt-on-Change Flag (RBIF bit)........... 14

RB7:RB4 Interrupt-on-Change................................. .. 69

RB7:RB4 Interrupt-on-Change Enable

(RBIE b i t)... ...... ................................................ ...... 69

RB7:RB4 Interrupt-on-Change Flag

(RBIF b i t)...................................... ................. .. 14, 69

PORTB Register................................................................... 9

PORTC

Associ a te d Re g i sters......... ...... ...... ...... ....... ................ 26

Functions.................................................................... 26

PORTC Register................................................................... 9

Postscaler, WDT

Assignment (PSA Bit)................ ................. ................ 1 3

Rate Select (PS2:PS0 bits) ........................................ 13

Power-down Mode. See SLEEP

Power-on Reset (POR)............................... 59, 62, 64, 65, 66

Brown-o u t Re set (BOR)............... ...... ....... ...... ...... ...... 64

Oscillator Start-up T imer (OST)....... ..................... 59, 64

POR Status (POR bit)........ ...... ...... ...... ....... ................ 17

Power Control/Sta tu s Regis te r (P CON)...... ............ .... 64

Power-down (PD bit) .................................................. 62

Power-up Timer (PWRT)...................................... 59, 64

Time-out (TO bit) .................................................. 12, 62

Time-out Sequence .................................................... 64

PR2 Register...................................................................... 35

Prescaler, Timer0

Assignment (PSA bit) ........ ...... ...... ...... ................. ...... 1 3

Rate Select (PS2:PS0 bits) ........................................ 13

PRO MATE II Univer sal De vice Programm e r................. .... 83

Product Identification System........................................... 133

Program Counter

RESET Conditions. ..................................................... 65

Program Mem ory

Paging ........................................................................ 19

Program Mem ory Map and Stack......................................... 7

Program Verification........................................................... 72

PUSH.................................................................................. 19

R/W..................................................................................... 44

R/W bit................................................................................ 49

RBIF bit........ ...... ....... ...... ................. ...... ...... ....... ................ 23

Read/Write bit Information, R/W......................................... 44

Reader Response............................................................. 132

Reading Program Memory. ................................................. 27

PMADR....................................................................... 27

PMCON1 Register.... ...... ....... ...... ...... ....... ...... ...... ...... 2 7

Receive Ove rflow Indica to r bit, SSPOV............ ...... ...... ...... 45

PIC16F72

DS39597B-page 128  2002 Microchip Technology Inc.

Registers.............................................................................36

ADCON0 (A/D Control 0)............................................53

ADCON1 (A/D Control 1)............................................54

CCPCON1 (Capture/Compare/PWM Control 1) .........37

Initialization Conditions (table)............. ............ ....... ....66

INTCON (Interrupt Control).........................................14

OPTION ......................................................................13

PCON (Power Control) ...............................................17

PIE1 (Peripheral Interrupt Enable 1)...........................15

PIR1 (Peripheral Interrupt Flag 1)...................... .........16

PMCON1 ( P ro g r am Me mory C o n trol 1 ).. ...... ...... ..... .. .27

SSPCON (Sync Serial Port Control)...........................45

SSPSTAT (Synchronous Serial Port Status). ..............44

STATUS ......................................................................12

Summary.......................................................................9

T1CON (Timer 1 Control)......... ...... ....... ...... ...... ....... ....31

RESET..........................................................................59, 62

Brown-out Reset (BOR). See Brown-out Reset (BOR)

MCLR RESET. See MCLR

Power-on Reset (POR). See Power-on Reset (POR)

RESET Conditions for All Registers............................66

RESET Conditions for PCON Register.......................65

RESET Conditions for Program Counter ....................65

RESET Conditions for STATUS Register............. .......65

WDT Reset. See Wat chdog Timer (WDT)

Revision History................................................................123

RP0, RP1 bit .... ...... ...... ................. ...... ....... ...... ................. ....7

S..........................................................................................44

Sales and Support.............................................................133

Slave Mode

SCL.............................................................................48

SDA.............................................................................48

SLEEP.....................................................................5 9, 62, 71

SMP ....................................................................................44

Softwa re Simulato r ( MP L AB SIM)... ...... ................. ...... .......82

Special Event Trigger..........................................................57

Speci a l Features of the CPU................... ....... ...... ...... ....... ..59

Special Function Registers

PMADRH ....................................................................27

PMADRL.....................................................................27

PMCON1.....................................................................27

PMDATH.....................................................................27

PMDATL......................................................................27

SPI Associated Re g i sters........ ...... ................. ...... ...... .......46

SPI Clock Edge Select bit, CKE..........................................44

SPI Da ta Input Sa mple Ph a se Se l e ct bit, SM P. ...... .. ..... .. .. .44

SPI Mode

Serial Clock.................................................................43

Serial Data In ..............................................................43

Serial Data Out............................................................43

Slave Select................................................................43

SSP ACK.............................................................................48

Addressing..................................................................48

BF bit........ ...... ................. ...... ...... ................. ...... .........48

I2C Mode Operation....................................................48

R/W bit........................................................................49

Reception....................................................................49

SCL Clock Input..........................................................48

SSPOV bit...................................................................48

Transmission...............................................................49

SSPADD Regist e r.... ....... ...... ...... ....... ...... ...... ................. .... 10

SSPEN................................................................................ 45

SSPIF ................................................................................. 16

SSPM3:SSPM0 .................................................................. 45

SSPOV ............................................................................... 45

SSPSTAT Regi ster................. ...... ....... ................ ....... ...... ..10

Stack................................................................................... 19

Overflows.................................................................... 19

Underflow ................................................................... 19

START bit, S....................................................................... 44

STATUS Register

DC bit .......................................................................... 12

IRP bit.............. . ...... ...... ...... ................. ................. ...... 12

PD bit.......................................................................... 62

TO bit.................................................................... 12, 62

STOP bit, P......................................................................... 44

Synchronous Serial Port (SSP) .......................................... 43

Overview..................................................................... 43

SPI Mode.................................................................... 43

Synchronous Serial Port Enable bit, SSPEN...................... 45

Synchronous Serial Port Interrupt....................................... 16

Synchronous Serial Port Mode Select bits,

SSPM3:SSPM0............................................................ 45

T2CKPS0 bit....................................................................... 36

T2CKPS1 bit....................................................................... 36

T2CON (Timer2 Con trol) .............. ....... ...... ...... ....... ............ 36

TAD...................................................................................... 56

Timer0................................................................................. 29

Clock Source Edge Select (T0SE bit)......................... 13

Cloc k So urce Se l e ct (T 0 C S bit).. ...... .. ...... .. ..... .. ...... .. . 13

External Clock............................................................. 30

Interrupt ...................................................................... 29

Operation.................................................................... 29

Overflow Enable (TMR0IE bit)............................ .. .... ..14

Overflow Fla g (T MR0 IF bit) ........... ...... ...... ....... .......... 69

Overflow In terrupt........... ................. ...... ...... ....... ...... ..69

Prescaler .................................................................... 30

T0CKI ......................................................................... 30

Timer1

Associ a te d Re g i sters............ ....... ...... ...... ....... ...... ...... 34

Asynchronous Counter Mode..................................... 33

Capacitor Selection..................................................... 33

Counter Operation................ .. ....... .. .. .. .... .. .. ....... .. .. .... 32

Interrupt ...................................................................... 33

Operation in Timer Mode............................................ 32

Oscillator..................................................................... 33

Prescaler .................................................................... 34

Resettin g TMR1H, TMR1L Regi st e r Pair.................... 34

Resetting Using a CCP Trigger Output....................... 33

Synchronized Counter Mode...................................... 32

Timer2................................................................................. 35

Interrupt ...................................................................... 35

Operation.................................................................... 35

Output......................................................................... 35

Prescaler, Postscaler.................................................. 35

 2002 Microchip Technology Inc. DS39597B-page 129

PIC16F72

Timing Diagrams

A/D Conversion..... ...... ...... ...... ....... ...... ...... ....... ...... ..105

Brown-out Reset.........................................................96

Capture/Compar e /PWM (CCP1).... ............ ....... ...... ....98

CLKO and I/O .............................................................95

External Clock.............................................................94

I2C Bus Data.............................................................102

I2C Bus START/STOP bits........................................101

I2C Recepti o n (7 - bit Addres s).................. ....... ...... ......50

I2C Transmi s si o n ( 7 -b i t Add re s s)...... ...... ...... ..... ...... ...50

RESET, Watchdog Timer, Oscillator Start-up Timer

and Power-up Timer.............................. ......... .... ....96

Slow Rise Time (MCLR Tied to VDD Through

RC Network)...........................................................68

SPI Master Mode........................................................47

SPI Mast e r Mode (CKE = 0, SMP = 0) .......................99

SPI Mast e r Mode (CKE = 1, SMP = 1) .......................99

SPI Slave Mode (CKE = 0).................................47, 100

SPI Slave Mode (CKE = 1).................................47, 100

Time-out Sequence on Power-up (MCLR Tied to

VDD Through Pull-up Resistor)..................... .... .. .. ..67

Time-out Sequence on Power-up (MCLR Tied to

VDD Through RC Network): Case 1.......................67

Time-out Sequence on Power-up (MCLR Tied to

VDD Through RC Network): Case 2.......................67

Timer0 and Timer1 External Clock............. ......... .... ....97

Wake-up from SLEEP through Interrupt .....................72

Timing Pa rameter Symbology....... ................. ................. ....93

TMR1H Register...................................................................9

TMR1L Register....................................................................9

TMR2 Register......................................................................9

TMR2ON bit........................................................................36

TOUTPS0 bit.......................................................................36

TOUTPS1 bit.......................................................................36

TOUTPS2 bit.......................................................................36

TOUTPS3 bit.......................................................................36

TRISA Register.............................................................10, 21

TRISB Register.............................................................10, 23

TRISC Register...... ....... ...... ...... ...... ....... ...... .................10, 25

UA....................................................................................... 44

Update Address bit, UA........ ....... .. .... .. .. .... .. ....... .. .. .... .. .. .... 44

Wake-up from SLEEP................................................... 59, 71

Interrupts .............................................................. 65, 66

MCLR Reset................. ....... ................ ....... ...... ...... .... 66

WDT Reset........... ...... ....... ...... ...... ...... ....... ...... .......... 66

Watchdog Timer (WDT)................... .... .... .. ......... .. .... .... 59, 70

Associ a te d Re g i sters......... ...... ...... ...... ....... ................ 70

Enable (WDTEN bit)................................................... 70

Postscaler. See Postscaler, WDT

Programming Considera tions.... ...... ....... ...... ...... ...... .. 70

RC Oscillator .............................................................. 70

Time-out Period.......................................................... 70

WDT Reset, Normal Operation....................... 62, 65, 66

WDT Reset, SLE EP .......... ...... ...... ...... ....... .... 62, 65, 66

WCOL................................................................................. 45

Write Colli sion Detect bit, WCOL........................ ...... .......... 45

WWW, On-Line Support....................................................... 3

PIC16F72

DS39597B-page 130  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. DS39597B-page 131

PIC16F72

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web (WWW) site.

The web site is used b y Micr ochip as a me ans to mak e

files and information easily available to customers. To

view t he site, the user must have acce ss to the In ternet

and a web browser, such as Netscape or Microsoft

Explorer. Files are also available for FTP download

from our FTP site.

Connecting to the Microc hip Inter net W eb Site

The Microchip web site is available by using your

fa vo rite Internet browser to attach to:

www.microchip.com

The file transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest Devel-

opment Tools, Data Sheets, Application Notes, User’s

Guides, Articles and Sample Programs. A variety of

Microchip specific business information is also avail-

able, including listings of Microchip sales offices, dis-

tributors and factory representatives. Other data

available for consideration is:

•Latest Microchip Press Releases

•Technical Support Section with Frequently Asked

Questions

•Design Tips

•Device Errata

•Job Postin gs

•Microchi p Cons ultant Program Member Listing

•Links to other useful web sites related to

Microchip Products

•Confere nces for prod ucts, Dev elopment Systems,

technical information and more

•Listing of seminars and events

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can receive any currently available upgrade kits.The

Hot Line Numbers are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-792-7302 for the rest of the world.

013001

PIC16F72

DS39597B-page 132  2002 Microchip Technology Inc.

READER RESPONSE

It is ou r intentio n to pro vi de you with the bes t do cu me ntation po ss ib le to ens ure suc c es sful use of your Mic roc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , a nd ways i n which o ur docum entat ion

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products ?

To: Technical Publications Manager

RE: Reader Response Total Pages Sent

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature N umber:

Questions:

FAX: (______) _________ - _________

DS39597B

PIC16F72

 2002 Microchip Technology Inc. DS39597B-page 133

PIC16F72

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

* JW Devices are UV eras able and can be programmed to any device configuration. JW D evices mee t the electrical requirement of

each oscillator type.

Sales and Support

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Devi ce PIC16F72: Standard VDD range

PIC16F72T: (Tape and Reel)

PIC16LF72: Extended VDD range

Temperature Range - = 0°C to +70°C

I= -40°C to +85°C

Package SO = SOIC

SS = SSOP

ML = QFN

P=PDIP

Pattern QTP, SQTP, ROM Code (factory specified) or

Special Requirements. Blank for OTP and

Windowed devices.

Examples:

a) PIC16F72-04I/SO = Industrial Temp.,

SOIC package, normal VDD limits

b) PIC16LF72-20I/SS = Industrial Temp.,

SSOP package, extended VDD limits

c) PIC16F72-20I/ML = Industrial Temp.,

QFN package, normal VDD limits

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microc hip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

DS39597B-page 134  2002 Microchip Technology Inc.

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05/16/02

WORLDWIDE SALES AND SERVICE