Document Number : MC34713
Rev. 5.0, 12/2008
Freescale Semiconductor
Advance Information
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-8. All rights reserved.
5.0 A 1.0 MHz Fully Integrated
Single Switch-Mode Power
Supply
The 34713 is a highly integrated, space efficient, low cost, single
synchronous buck switching regulator with integrated N-channel
power MOSFETs. It is a high performance point-of-load (PoL) power
supply with the ability to track an external reference voltage in
different configurations.
Its high effici en t 5. 0 A continuous output current capability
combined with its voltage tracking/sequencing ability and tight output
regulation, makes it ideal as a single power supply.
The 34713 offers the designer the flexibi lity of many control,
supervisory, and protection functions to allow for easy implementation
of complex designs. It is housed in a Pb-free, thermally enhanced,
and space-efficient 24-Pin Exposed Pad QFN.
Features
•50 mΩ integrated N-channel power MOSFETs
• Input voltage operating range from 3.0 to 6.0 V
•±1% accurate outp ut voltage, ranging from 0.7 to 3.6 V
• Voltage tracking capability in different configurations.
• Programmable switching frequency range from 200 kHz to
1.0 MHz with a default of 1.0 MHz
• Programmable soft start timing
• Over-current limit and short-circuit protection
• Thermal shutdown
• Output over-voltage and under-voltage detection
• Active low power good ou tput signal
• Active low shutdown input
• Pb-free packaging designate d by suffix code EP.
Figure 1. 34713 Simplified Application Diagra m
SWITCH-MODE POWER SUPPLY
EP SUFFIX
98ARL10577D
24-PIN QFN
34713
ORDERING INFORMATION
Device Temperature
Range (TA)Package
MC34713EP/R2 -40 to 85°C 24 QFN
VIN
VREFIN
PGND
VDDI
FREQ
ILIM
GND
PVIN
BOOT
SW
INV
COMP
VOUT
PG
SD
34713
VIN
VOUT
VMASTER
(3.0 TO 6.0 V) VIN
MICROCONTROLLER
DSP,
FPGA,
ASIC
Analog Integrated Circuit Device Data
2Freescale Semiconductor
34713
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Figure 2. 34713 Simplified Internal Block Diagram
+
–
+
–
Thermal
Monitoring
System
Reset
M1
Discharge
ILIMIT
System
Control
Internal
Voltage
Regulator
VDDI
M2
M3
M4
M5
VBG
Reference
Selection
Ramp
Generator
VBG
VDDI
Bandgap
Regulator
Discharge
Error
Amplifier
PWM
Comparator
Prog Soft Start
ISENSE ILIMIT
Prog Frequency
Oscillator
Current
Monitoring
Buck
Control
Logic Gate
Driver
FSW ISENSE
VIN VBOOT
SD
VIN
BOOT
PVIN
SW
PGND
COMP
INV
VOUT
GND
VREFIN
VDDI
ILIM
FREQ
PG
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
34713
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 34713 Pin Conne ctions
Table 1. 34713 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number Pin Name Pin Function Formal Name Definition
1GND Ground Signal Ground Analog signal ground of IC
2FREQ Passive Frequency Adjustment Buck converter switching frequency adjustment pin
3ILIM Input Soft Start Soft Start adjustment
4PG Output Power Good Active-low (open drain) power-good status reporting pin
5, 8 NC None No Connect No internal connections to these pins. Recommend attaching a 0.1 µF
capacitor from pin 8 to GND.
6SD Input Shutdown Shutdown mode input control pin
7VREFIN Input Voltage Tracking
Reference Input Voltage Tracking Reference voltage input
9COMP Passive Compensation Buck converter external compensation network pin
10 INV Input Error Amplifier
Inverting Input Buck converter error amplifier inverting input pin
11 VOUT Output Output Voltage
Discharge FET Discharge FET drain connection (connect to buck converter output
capacitors)
12,13,14 PGND Ground Power Ground Ground return for buck converter and discharge FET
15,16,17 SW Output Switching Node Buck converter power switching node
18,19,20 PVIN Supply Power-Circuit Supply
Input Buck converter main supply voltage input
21 BOOT Passive Bootstrap Bootstrap switching node (connect to bootstrap capacitor)
22,23 VIN Supply Logic-Circuit Supply
Input Logic circuits supply voltage input
24 VDDI Passive Internal Voltage
Regulator Internal Vdd Regulator (connect filter capacitor to this pin)
GND
FREQ
ILIM
PG
NC
SD
VREFIN
COMP
INV
VOUT
PGND
SW
PVIN
BOOT
VIN
VDDI
NC
PGND
PGND
SW
SW
PVIN
PVIN
VIN
Transparent
Top View
1
2
3
4
5
6
78 9 10 11 12
13
14
15
16
17
18
1920
2122
2324
PIN 25
Analog Integrated Circuit Device Data
4Freescale Semiconductor
34713
PIN CONNECTIONS
25 GND Ground Thermal Pad Thermal pad for heat transfer. Connect the thermal pad to the analog
ground and the ground plane for heat sinking.
Table 1. 34713 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number Pin Name Pin Function Formal Name Definition
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
34713
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
ELECTRICAL RATINGS
Input Supply Voltage (VIN) Pin VIN -0.3 to 7.0 V
High Side MOSFET Drain Voltage (PVIN) Pin PVIN -0.3 to 7.0 V
Switching Node (SW) Pin VSW -0.3 to 7.0 V
BOOT Pin (Referenced to SW Pin) VBOOT - VSW -0.3 to 7.0 V
PG, VOUT,and SD Pins --0.3 to 7.0 V
VDDI, FREQ, ILIM, INV, COMP, and VREFIN Pins --0.3 to 3.0 V
Continuous Output Current(1) IOUT +5.0 A
ESD Voltage(2)
Human Body Model
Machine Model (MM)
Charge Device Model
VESD1
VESD2
VESD3
±2000
±200
±750
V
THERMAL RATINGS
Operating Ambient Temperature(3) TA-40 to 85 °C
Storage Temperature TSTG -65 to +150 °C
Peak Package Reflow Temperature During Reflow(4),(5) TPPRT Note 5 °C
Maximum Junction Temperature TJ(MAX) +150 °C
Power Dissipation (TA = 85°C)(6) PD2.9 W
Notes
1. Continuous output current capability so long as TJ is ≤ TJ(MAX).
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM)
(CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
3. The limiting factor is junction temperature, taking into account power dissipation, th ermal resistance, and heatsinking.
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
6. Maximum power dissipation at indicated ambient temperature
Analog Integrated Circuit Device Data
6Freescale Semiconductor
34713
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
THERMAL RESISTANCE(7)
Thermal Resistance, Junction to Ambient, Single-layer Board (1s)(8) RθJA 139 °C/W
Thermal Resistance, Junction to Ambient, Four-layer Board (2s2p)(9) RθJMA 43 °C/W
Thermal Resistance, Junction to Board(10) RθJB 22 °C/W
Notes
7. The PVIN, SW, and PGND pins comprise the main heat conduction paths.
8. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
9. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are no thermal vias connecting the package to the two planes in the
board.
10. Thermal resistance between the device and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
34713
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C und er nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
IC INPUT SUPPLY VOLTAGE (VIN)
Input Supply Voltage Operating Range VIN 3.0 -6.0 V
Input DC Supply Current(11)
Normal Mode: SD = 1, Unloaded Outputs IIN - - 25 mA
Input DC Supply Current(11)
Shutdown Mode, SD = 0 IINOFF - - 100 µA
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)
Internal Supply Voltage Range VDDI 2.35 2.5 2.65 V
BUCK CONVERTER (PVIN, SW, PGND, BOOT, INV, COMP, ILIM)
High Side MOSFET Drain Voltage Range PVIN 2.5 -6.0 V
Output Voltage Adjustment Range(12),(13) VOUT 0.7 -3.6 V
Output Voltage Accuracy(12),(14) --1.0 -1.0 %
Line Regulation(12)
Normal Operation, VIN = 3.0 to 6.0 V, IOUT = +5.0 A REGLN -1.0 -1.0 %
Load Regulation(12)
Normal Operation, IOUT = 0.0 to 5.0 A REGLD -1.0 -1.0 %
Error Amplifier Common Mode Voltage Range(12),(13) VREF 0.0 -1.35 V
Output Under-voltage Threshold VUVR -8.0 --1.5 %
Output Over-voltage Threshold VOVR 1.5 -8.0 %
Continuous Output Current IOUT - - 5.0 A
Over-current Limit ILIM -6.5 - A
Soft start Adjusting reference Voltage Range VILIM 1.25 - VDDI V
Short-circuit Current Limit ISHORT -8.5 - A
High Side N-CH Power MOSFET (M3) RDS(ON)(12)
IOUT = 1.0 A, VBOOT - VSW = 3.3 V RDS(ON)HS 10 -50 mΩ
Low Side N-CH Power MOSFET (M4) RDS(ON)(12)
IOUT = 1.0 A, VIN = 3.3 V RDS(ON)LS 10 -50 mΩ
Notes
11. Section “MODES OF OPERATION”, page 13 has a detailed description of the different operating modes of the 34713
12. Design information only, this parameter is not production tested.
13. The ±1% accuracy is only guaranteed for VEFOUT greater then or equal 0.7 V at room temperature.
14. Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended
Analog Integrated Circuit Device Data
8Freescale Semiconductor
34713
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
M2 RDS(ON)
VIN = 3.3 V, M2 is on RDS(ON)M2 1.5 -4.0 Ω
SW Leakage Current (Standby and Shutdown modes) ISW -10 -10 µA
PVIN Pin Leakage Current
Shutdown Mode IPVIN -10 -10 µA
INV Pin Leakage Current IINV -1.0 -1.0 µA
Error Amplifier DC Gain(15) AEA -150 -dB
Error Amplifier Unit Gain Bandwidth(15) UGBWEA -3.0 -MHz
Error Amplifier Slew Rate(15) SREA -7.0 -V/µs
Error Amplifier Input Offset(15) OFFSETEA -3.0 03.0 mV
Thermal Shutdown Threshold(15) TSDFET -170 -°C
Thermal Shutdown Hysteresis(15) TSDHYFET -25 -°C
OSCILLATOR (FREQ)
Oscillator Frequency Adjusting Reference Voltage Range VFREQ 0.0 - VDDI V
TRACKING (VREFIN, VOUT)
VREFIN External Reference Voltage Range(15) VREFIN 0.0 -1.35 V
VOUT Total Discharge Resistance(15) RTDR(M5) -50 -Ω
CONTROL AND SUPERVISORY (SD, PG)
SD High Level Input Voltage VSDHI 2.0 - - V
SD Low Level Input Voltage VSDLO - - 0.4 V
SD Pin Internal Pull-up Resistor(15) RSDUP 1.0 -2.0 MΩ
PG Low Level Output Voltage
IPG = 3.0 mA VPGLO - - 0.4 V
PG Pin Leakage Current
M1 is off, Pulled up to VIN IPGLKG -1.0 -1.0 µA
Notes
15. Design information only, this parameter is not production tested.
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typ ical
values noted reflect the approximate parameter means at TA = 25°C und er nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
34713
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C und er nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
BUCK CONVERTER (PVIN, SW, PGND, BOOT)
Switching Node (SW) Rise Time(16)
(PVIN = 3.3 V, IOUT = 5.0 A) tRISE -14 -ns
Switching Node (SW) Fall Time(16)
(PVIN = 3.3 V, IOUT = 5.0 A) tFALL -20 -ns
Minimum OFF Time tOFFMIN -150 -ns
Minimum ON Time tONMIN - 0(17) -ns
Soft Start Duration (Normal Mode) ILIM= 1.25 - 1.49 V
1.50 - 1.81 V
1.82 - 2.13 V
2.14 - 2.50 V
tSS
-
-
-
-
3.2
1.6
0.8
0.4
-
-
-
-
ms
Over-current Limit Timer tLIM -10 -ms
Over-current Limit Retry Time-out Period tTIMEOUT 80 -120 ms
Output Under-voltage/Over-voltage Filter Delay Timer tFILTER 5.0 -25 µs
OSCILLATOR (FREQ)
Oscillator Default Switching Frequency
Oscillator Frequency tolerance is ±10% (FREQ = GND) fSW -1.0 -MHz
Oscillator Switching Frequency Range fSW 200 -1000 KHz
CONTROL AND SUPERVISORY (SD, PG)
PG Reset Delay tPGRESET 8.0 -12 ms
Thermal Shutdown Retry Timeout Period(16) tTIMEOUT 80 -120 ms
Notes
16. Design information only, this parameter is not production tested.
17. The regulator has the ability to enter into pulse skip mode when the inductor current ripple reaches the threshold for the LS zero detect,
which has a typical value of 500 mA.
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
34713
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
Advanced microprocessor-based systems require
compact, efficient, and accurate point-of-load (PoL) power
supplies. These PoL supply high current and fast transient
response capability while maintaini ng regulation accuracy.
Voltage monitoring (power sequencing) and increased
operating frequency are also key fea tu r es for PoL power
supplies.
PoL power supplies are non-isolated DC to DC converters
that are physically located near their load (on the same
printed circuit board) and take their input supply from an
intermediate bus. Their close proximity to the load allows for
higher efficiency, localized protection, and minimum
distribution losses. Their compact design and low
component-count also reduces overall system cost.
The 34713 is a PoL single-output power supply that
embodies an integrated solution that’s both highly cost-
effective and reliable. It utilizes a voltage-mode synchronous
buck switching converter topology with integrated low
RDS(ON) (50 mΩ) N-channel power MOSFETs for high-
efficiency operation. It provides an output voltage with an
accuracy of less than ±2.0%, capable of supplying up to 5.0 A
of continuous current. Its power sequencing/tracking abilities
makes it ideal for systems with multiple related supply rails. It
has an adjustable switching frequency, thus permitting
greater design flexibility and optimization over a wide range
of operating conditions, and can operate at up to 1.0 MHz to
significantly reduce the external components size and cost. It
also features an over-current limit control, and protects
against output over-voltage, under-voltage, and over-
temperature conditions. It also protects the system from
short-circuit events and incorporates a power-good output
signal to alert the host MCU should a fault occur.
Operation can be enabled or disabled by controlling the
SD pin, which offers power sequencing capabilities.
By monolithically integrating the control and supervisory
circuitry along with power-FETs, the 34713 offers a complete,
compact, cost-effective, and simple solution to satisfy the
PoL needs of today’s systems.
FUNCTIONAL PIN DESCRIPTION
REFERENCE VOLTAGE INPUT (VREFIN)
The 34713 will track the voltage applied at this pin.
FREQUENCY ADJUSTMENT INPUT (FREQ)
The buck converter switching frequency can be adjusted
by connecting this pin to an external resistor divider between
VDDI and GND pins. The default switching frequency (FREQ
pin connected to ground, GND) is set at 1.0 MHz.
SOFT START ADJUSTMENT INPUT (ILIM)
Soft start timing can be adjusted by applying an external
voltage between 1.25 V and VDDI on this pin.
SIGNAL GROUND (GND)
Analog ground of the IC. Internal analog signals are
referenced to this pin voltage.
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)
This is the output of the internal bias voltage regulator.
Connect a 1.0 µF, 6.0 V low ESR ceramic filter capacitor
between this pin and the GND pin. Filtering any spikes on this
output is essential to the internal circuitry stable operation.
OUTPUT VOLTAGE DISCHARGE PATH (VOUT)
Output voltage of the Buck Converter is connected to this
pin. it only serves as the output discharge path once the SD
signal is asserted.
ERROR AMPLIFIER INVERTING INPUT (INV)
Buck converter error amplifier inverting input. Connect the
output voltage feedback network to this pin.
COMPENSATION INPUT (COMP)
Buck converter external compensation network connects
to this pin. Use a type III compensation network.
INPUT SUPPLY VOLTAGE (VIN)
IC power supply input voltage. Input filtering is required for
the device to operate properly.
POWER GROUND (PGND)
Buck converter and discharge MOSFET power ground. It
is the source of the buck converter low side power MOSFET.
SWITCHING NODE (SW)
Buck converter switching node. This pin is connected to
the output inductor.
POWER INPUT VOLTAGE (PVIN)
Buck converter power input voltage. This is the drain of the
buck converter high side power MOSFET.
BOOTSTRAP INPUT (BOOT)
Bootstrap capacitor input pin. Connect a capacitor (as
discussed on page 18) betwee n this pin and the SW pin to
Analog Integrated Circuit Device Data
Freescale Semiconductor 11
34713
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
enhance the gate of the high side Power MOSFET durin g
switching.
SHUTDOWN INPUT (SD)
If this pin is tied to the GND pin, the device will be in
Shutdown mode. If left unconnected or tied to the VIN pin, the
device will be in Normal mode. The pin has an internal pull-
up of 1.5 MΩ.
POWER GOOD OUTPUT SIGNAL (PG)
This is an active low open drain output that is used to
report the status of the device to a host. This output activates
after a successful power up sequence and stays active as
long as the device is in normal operation and is not
experiencing any faults. This output activates after a 10 ms
delay and must be pulled up by an external resistor to a
supply voltage (e.g., VIN).
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 4. 34713 Block Diagram
INTERNAL BIAS CIRCUITS
This block contains all circuits that provide the necessary
supply voltages and bias currents for the internal circuitry. It
consists of:
• Internal voltage supply regulator: This regulator
supplies the VDDI voltage that is used to drive the digital/
analog internal circuits. It is equipped with a Power-On-
Reset (POR) circuit that watches for the right regulation
levels. External filtering is needed on the VDDI pin. This
block will turn off during the shutdown mode.
• Internal bandgap reference voltage: This supplies the
reference voltage to some of the internal circuitry.
• Bias circuit: This block generates the bias currents
necessary to run all of the blocks in the IC.
SYSTEM CONTROL AND LOGIC
This block is th e brain of the IC where the device
processes data and reacts to it. Based on the status of the SD
pin, the system control reacts accordingly and orders the
device into the right status. It also takes inputs from all of the
monitoring/protection circuits and initiates power up or power
down commands. It communicates with the buck converter to
manage the switching operation and protects it ag ainst any
faults.
OSCILLATOR
This block generates the clock cycles necessary to run the
IC digital blocks. It also generates the buck converter
switching frequency. The switching frequency has a default
value of 1.0 MHz and can be programmed by connecting a
resistor divider to the FREQ pin, between VDDI and GND
pins (See Figure 1).
PROTECTION FUNCTIONS
This block contains the following circu its:
• Over-current limit and short-circuit detection: This block
monitors the output of the buck converter for over
current conditions and short-circuit events and alerts
the system control for further command.
• Thermal limit detection: This block monitors the
temperature of the device for overheating events. If the
temperature rises above the thermal shutdown
MC34713 - Functional Block Diagram
Internal Bias Circuits System Control and Logic Oscillator
Protection Functions Control and
Supervisory Functions Tracking and Sequencing
Buck Converter
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
34713
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
threshold, this block will alert the system control for
further commands.
• Output over-voltage and under-voltage monitoring: This
block monitors the buck conve rter output voltage to
ensure it is within regulation boundaries. If not, this
block alerts the system control for further commands.
CONTROL AND SUPERVISORY FUNCTIONS
This block is used to interface with an outside host. It
contains the following circuits:
• Shutdown control input: An outside host can put the
34713 device into shutdown mode by sending a logic
“0” to the SD pin.
• Power good output signal PG: The 34713 can
communicate to an external host that a fault has
occurred by releasing the drive on the PG pin high,
allowing the signal/pin to be pulled high by the external
pull-up resistor.
TRACKING AND SEQUENCING
This block allows the output of the 34713 to track the
voltage applied at the VREFIN pin in differen t tracking
configurations. This will be discussed in further details later in
this document. For power down during a shutdown mode, the
34713 uses internal discharge MOSFET (Figure 2) to
discharge the output. The discharge MOSFET is only active
during shutdown mode. Using this block along with
controlling the SD pin can offer the user power sequencing
capabilities by controlling when to turn the 34713 output on or
off.
BUCK CONVERTER
This block provides the main function of the 34713: DC to
DC conversion from an un-regulated input voltage to a
regulated output voltage used by the loads for reliable
operation. The buck converter is a high performance, fixed
frequency (externally adjustable), synchronous buck PWM
voltage-mode control. It drives integrated 50 mΩ N-channel
power MOSFETs saving board space and enhancing
efficiency. The switching regulator output voltage is
adjustable with an accuracy of less than ±2% to meet today’s
requirements. Its output has the ability to track the voltage
applied at the VREFIN pin. The regulator' s voltage control
loop is compensated using a type III compensation network,
with external components to allow for optimizing the loop
compensation, for a wide range of operating conditions . A
typical bootstrap circuit with an internal PMOS switch is used
to provide the voltage necessary to properly enhance the
high side MOSFET gate.
The 34713 has the ability to supply up to 5.0 A of
continuous current, making it suitable for many high current
applications.
Analog Integrated Circuit Device Data
Freescale Semiconductor 13
34713
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 5. Operation Modes Diagram
MODES OF OPERATION
The 34713 has two primary modes of operation :
Normal Mode
In normal mode, all functions and outputs are fully
operational. To be in this mode, the VIN needs to be within its
operating range, Shutdown input is high, and no faults are
present. This mode consumes the most amount of power.
Shutdown Mode
In this mode, activated by pulling the SD pin low, the chip
is in a shutdown state and the output is disabled and
discharged. In this mode, the 34713 consume s the least
amount of power since almost all of the internal blo cks are
disabled.
START-UP SEQUENCE
When power is first applied, the 34713 checks the status
of the SD pin. If the device is in a shutdown mode, no block
will power up and the output will not attempt to ramp. Once
the SD pin is released to enable the device, the VDDI internal
supply voltage and the bias currents are established and the
internal VDDI POR signal is also released. The rest of the
internal blocks will be enabled and the buck converter
switching frequency and so ft start values are determined by
reading the FREQ and ILIM pins respectively. A soft start
cycle is then initiated to ramp up the output of the buck
converter. The buck converter error amplifier uses the
voltage on the VREFIN pin as its reference voltage until
VREFIN is equal to 0.7 V, then the error amplifi e r de fa ults to
the internal 0.7 V reference voltage. This method helps
achieve multiple tracking configu rations as will be explained
later in this document.
Soft start is used to prevent the output voltage from
overshooting during startup. At initial startup, the output
capacitor is at zero volts; VOUT = 0 V. Therefore, the voltage
across the inductor will be PVIN during the capacitor charge
phase which will create a very sharp di/dt ramp. Allowing the
inductor current to rise too high can result in a large
difference between the charging current and the actual load
current that can result in an undesired voltage spike once the
capacitor is fully charged. The soft start is active each time
the IC goes out of standby or shutdown mode, pow er is
recycled, or after a fault retry.
After a successful start-up cycle where the device is
enabled, no faults have occurred, and the output voltage has
reached its regulation point, the 34713 pulls the power good
Normal
V
TT
= ON
PG = 0
Shutdown
V
OUT
= Discharge
V
REF
= Discharge
PG = 1
V
IN
< 3.0 V
I
OUT
>=I
SHORT
I
OUT1
>=I
LIM1
For>=10 ms
T
J
>= 170
°C
V
OUT
>V
OV
3.0 V<=V
IN
<=6.0 V
T
J
<=145
°C
TIMEOUT Expired TIMEOUT
Expired
V
OUT
<V
OV
Over-voltage
V
OUT
=ON
PG = 1
Thermal Shutdown
V
OUT
=OFF
PG = 1
Under-voltage
V
OUT
=ON
PG = 1
Short-circuit
V
OUT
=OFF
PG = 1
Over-current
V
OUT
=OFF
PG = 1
Power Off
V
OUT
=OFF
PG = 1
V
REF
=OFF
SD = 0
SD = 1
V
REF
=ON
V
REF
=OFF
V
REF
=ON
V
REF
=ON V
REF
=OFF
V
REF
=ON
V
OUT
<V
UV
TIMEOUT
Expired
V
OUT
>V
UV
Analog Integrated Circuit Device Data
14 Freescale Semiconductor
34713
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
output signal low after a 10 ms reset delay, to indicate to the
host that the device is in normal operation.
PROTECTION AND DIAGNOSTIC FEATURES
The 34713 monitors the appl ication for several fault
conditions to protect the load from overstress. The reaction of
the IC to these faults ranges from turning off the outpu ts to
just alerting the host that something is wrong. In the following
paragraphs, each fault condition is explained:
Output Over-voltage
An over-voltage condition occurs once the output voltage
goes higher than the rising over-voltage threshold (VOVR). In
this case, the power good output signal is pulled high, alerting
the host that a fault is present, but the output will stay active.
To avoid erroneous over-voltage cond itions, a 20 µs filter is
implemented. The buck converter will use its feedback loop
to attempt to correct the fault. Once the output voltage falls
below the falling over-voltage threshold (VOVF), the fault is
cleared and the power good output signal is pulled low, the
device is back in normal operation.
Output Under-voltag e
An under-voltage condition occurs once the output voltage
falls below the falling under-voltage threshold (VUVF). In this
case, the power good output signal is pulled high, alerting the
host that a fault is present, but the output will stay active. To
avoid erroneous under-voltage conditions, a 20 µs fi lter is
implemented. The buck converter will use its feedback loop
to attempt to correct the fault. Once the output voltage rises
above the rising under-voltage threshold (VUVR), the fault is
cleared and the power good output signal is pulled low, the
device is back in normal operation.
Output Over-current
This block detects over-current in the Power MOSFETs of
the buck converter. It is comprised of a sense MOSFET and
a comparator. The sense MOSFET acts as a current
detecting device by sampling a ratio of the load current. That
sample is compared via the comparator with an internal
reference to determine if the output is in over-current or not.
If the peak current in the output inductor reaches the over
current limit (ILIM), the converter will start a cycle-by-cycle
operation to limit the current, and a 10 ms over-current limit
timer (tLIM) starts. The converter will stay in this mode of
operation until one of the followi ng occurs:
• The current is reduced back to the normal level before
tLIM expires, and in this case normal operation is
regained.
•t
LIM expires without regaining normal operation, at
which point the device turns off the output and the
power good output signal is pulled high. At the end of a
time-out period of 100 ms (tTIMEOUT), the device will
attempt another soft start cycle.
• The device reaches the thermal shutdown limit (TSDFET)
and turns off the output. The power good output signal
is pulled high.
• The output current keeps increasing until it reaches the
short circuit current limit (ISHORT). See below for more
details.
Short-circuit Current Limit
This block uses the same current detection mechanism as
the over-current limit detection block. If the load current
reaches the ISHORT value, the device reacts by shutting down
the output immediately. This is necessary to prevent damage
in case of a permanent short-circuit. Then, at the end of a
timeout period of 100 ms (tTIMEOUT), the device will attempt
another soft start cycle.
Thermal Shutdown
Thermal limit detection block monitors the temperature of
the device and protects against excessive heating . If the
temperature reaches the thermal shutdown threshold
(TSDFET), the converter output switches off and the power
good output signal indicates a fault by pulling high. The
device will stay in this state until the temperature has
decreased by the hysteresis value and then After a timeout
period (TTIMEOUT) of 100 ms, the device will retry
automatically and the output will go through a soft start cycle.
If successful normal operation is regained, the power good
output signal is asserted low to indicate that.
Analog Integrated Circuit Device Data
Freescale Semiconductor 15
34713
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Figure 6. Typical App lic a tio ns
SGND
ILIM
NC
GND
VOUT
VREFIN
NC
SD
COMP
INV
VOUT
GND
SW
SW
PVIN
PVIN
PVIN
PVIN
PVIN
BOOT
VDDI
VIN
VIN
0.1
μF
C14
VDDI
INV
COMP
0.1
μF
C15
BOOT
x
R10
VIN
FREQ
ILIM
FREQ
0.1
μF
C12 0.1
μF
C11
PG
SD
MC34713
1
2
3
5
6
7891011
13
12
14
17
18
192021222324
415
16
C18
0.02 pF
R15
15 k
C19
1.9 nF R2
12.7 k
C20
0.910 nF
R14
300
R1
20 k
COMP
VOUT
INV
Compensation Network
Buck Converter
VOUT
C8
100
μF
C7
100
μF
C6
100
μF
R3
4.7_nopop
C9
1n
F_nopop
D3
PMEG2010EA
_nopop
L1
1.5
μH
SW VOUT1VOUT2
0.1
μF
C13
VREFIN
GND GND
SW SW
SW
PG
10 k
R13
10 k_nopop
R12
10 k_nopop
R11
10 k
J2
J3
PVIN
VIN
GND
3
2
1
3
2
1
GND
VOUT
VMASTER
I/O Signals
R16
4.7_nopop
VMASTER
VREFIN
R8
10 k
R9
10 k
VMASTER
R7
1k
D1
LED
VIN
LED
PGOOD LED
STBY_nopop
PVIN
VMASTER
LED
VREFIN
PG
SD
J1
SD CON10A
1
1
12
2
2
34
56
78
910
Jumpers
x
PVIN
C1
0.1
μ
FC2
1
.0 μ
FC3
100
μ
FC4
100
μ
FC5
100
μ
F
PVIN Capacitors
VIN C17
10
μF
C16
0.1
μF
VIN Capacitors
VDDI
R5
POT_50 k_nopop R6
POT_50 k_nopop
ILIM FREQ
Optional nopop
SW
Analog Integrated Circuit Device Data
16 Freescale Semiconductor
34713
TYPICAL APPLICATIONS
COMPONENT SELECTION
SWITCHING FREQUENCY SELECTION
The switching frequency defaults to a value of 1.0 MHz
when the FREQ pin is grounded, and 200 kHz when the
FREQ pin is connected to VDDI. Intermediate switching
frequencies can be obtained by connecting an external
resistor divider to the FREQ pin. The table below shows the
resulting switching frequency versus FREQ pin voltage .
Table 5. Switching Freq uency Adjustment
Figure 7. Resistor Divider for Frequency Adjustment
SELECTION OF THE INDUCTOR
Inductor calculation is straight forw ard, being
where,
Maximum OFF time percentage
Switching period.
Drain – to – source resistance of FET
Winding resistance of Inductor
Output current ripple.
OUTPUT FILTER CAPACITOR
For the output capacitor, the following considerations are
more important than the actual capacitance value, the
physical size, the ESR and the voltage rating:
Transient Response percentage, TR_%
(Use a recommended value of 2 to 4% to assure a good
transient response.)
Maximum Transient Voltage, TR_v_dip = Vo*TR_%
Maximum current step,
Inductor Current rise time,
where,
D_max = Maximum ON time percentage.
IO = Rated output current.
Vin_min = Minimum input voltage at PVIN
As a result, it is possib l e to calc ul a te
FREQUENCY VOLTAGE APPLIED TO PIN FREQ
200 2.341 – 2.500
253 2.185 - 2.340
307 2.029 - 2.184
360 1.873 - 2.028
413 1.717 – 1.872
466 1.561 – 1.716
520 1.405 - 1.560
573 1.249 - 1.404
627 1.093 - 1.248
680 0.936 - 1.092
733 0.781 - 0.936
787 0.625 - 0.780
840 0.469 - 0.624
893 0.313 - 0.468
947 0.157 - 0.312
1000 0.000 - 0.156
RFQH
RFQL
VDDI
FREQ
GND
Analog Integrated Circuit Device Data
Freescale Semiconductor 17
34713
TYPICAL APPLICATIONS
In order to find the maximum allowed ESR,
The effects of the ESR is often neglected by the designers
and may present a hidden danger to the ultimate supply
stability. Poor quality capacitors have widely disparate ESR
value, which can make the closed loop respon se
inconsistent.
Figure 8. Transient Parameters
TYPE III COMPENSATION NETWORK
Power supplies are desired to offer accurate and tight
regulation output voltages. To accomplish this requires a high
DC gain. But with high gain comes the possibility of instability .
The purpose of adding compensation to the internal error
amplifier is to counteract some of the gains and phases
contained in the control-to-output transfer function that could
jeopardized the stability of the power supply. The Type III
compensation network used for 34713 comprise s two poles
(one integrator and one high frequency pol e to cancel the
zero generated from the ESR of the output capacitor) and two
zeros to cancel the two poles generated from the LC filter as
shown in Figure 9.
Figure 9. Type III Compensatio n Netw ork
Consider the crossover frequency, FCROSS, o f the open lo op
gain at one-tenth of the switching frequency, FSW.
Then,
where RO is a user selected resistor. Knowing the LC
frequency, it can be obtained the values of RF and CS:
This gives as a result,
Calculate Rs by placing the Pole 1 at the ESR zero
frequency:
Io
Worst case
assumption
Current
response
dt_I_rise
Io_step
+
–
+
–
F
SW Gate
Driver
PWM
Comparitor
V
REFIN
Ramp
Generator Error
Amplifier
SW
VOUT
INV
COMP
L
R
S
C
S
R
O
C
O
C
X
R
F
C
F
BOOT
C
BOOT
R
B
V
DDI Reference
Selection
Bandgap
Regulator
34713
VOVREF RO
RB
------- 1+
⎝⎠
⎛⎞
=
⇒
FCROSS 10
2πROCF
•
----------------------------
=
CF10
2πROFCROSS
•
---------------------------------------
=
&
Analog Integrated Circuit Device Data
18 Freescale Semiconductor
34713
TYPICAL APPLICATIONS
Equating the Pole 2 to 5 times the Crossover Frequency to
achieve a faster response and a proper phase margin,
BOOTSTRAP CAPACITOR
The bootstrap capacitor is needed to supply the gate
voltage for the high side MOSFET. This N-Channel MOSFET
needs a voltage difference between its gate and source to be
able to turn on. The high side MOSFET source is the SW
node, so it is not ground and it is floating and moving in
voltage, so we cannot just apply a voltage directly to the gate
of the high side that is referenced to ground, we need a
voltage referenced to the SW node. That is why the bootstrap
capacitor is needed for. This capacitor charges during the
high side off time, since the low side will be on during that
time, so the SW node and the bottom of the bootstrap
capacitor will be connected to ground and the top of the
capacitor will be connected to a voltage source, so the
capacitor will charge up to that voltage source (say 5.0 V).
Now when the low side MOSFET switches off and the high
side MOSFET switches on, the SW nodes rises up to Vin,
and the voltage on the boot pin will be Vcap + Vin. So the gate
of the high side will have Vcap across it and it will be able to
stay enhanced. A 0.1 μF capacitor is a good value for this
bootstrap element.
LAYOUT GUIDELINES
The layout of any switching regulator requires careful
consideration. First, there are high di/dt signals present, and
the traces carrying these signals need to be kept as short and
as wide as possible to minimize the trace inductance, and
therefore reduce the voltage spikes they can create. To do
this, an understanding of the major current carrying loops is
important. See Figure 10. These loops, and their associated
components, should be placed in such a way as to minimize
the loop size to prevent coupling to other parts of the circuit.
Also, the current carrying power traces and their associated
return traces should run adjacent to one another, to minimize
the amount of noise coupling. If sensitive traces must cross
the current carrying traces, they should be made
perpendicular to one another to reduce field interaction.
Second, small signal components which connect to
sensitive nodes need consideration. The critical small signal
components are the ones associated with the feedba ck
circuit. The high impedance input of the error amp is
especially sensitive to noise, and the feedback and
compensation components should be placed as far from the
switch node, and as close to the input of the error amplifier as
possible. Other critical small signal components include the
bypass capacitors for VIN, VREFIN, and VDDI. Locate the
bypass capacitors as close to the pin as possible.
The use of a multi-layer printed circuit board is
recommended. Dedicate one laye r, usually the layer under
the top layer, as a ground plane. Make all critical component
ground connections with vias to this layer. Make sure that the
power ground, PGND, is connected directly to the ground
plane and not routed through the thermal pad or analog
ground. Dedicate another laye r as a power plane and split
this plane into local areas for common voltage nets.
The IC input supply (VIN) should be connected with a
dedicated trace to the input supply. This will help prevent
noise from the Buck Regulator's power inpu t (PVIN) from
injecting switching noise into the IC’s analog circuitry.
In order to effectively transfer heat from the top layer to the
ground plane and other layers of the printed circuit board,
thermal vias need to be used in the thermal pad design. It is
recommended that 5 to 9 vias be spaced evenly and have a
finished diameter of 0.3 mm.
⇒
5F•CROSS FP2 1
2πRFCFCX
CFCX
+
---------------------
•
-----------------------------------------
==
⇒
Analog Integrated Circuit Device Data
Freescale Semiconductor 19
34713
TYPICAL APPLICATIONS
Figure 10. Cu rre nt Loops
SOFT START SELECTION
Table 6 shows the voltage that should be applied to the
terminal ILIM to get the desired configuration of the soft start
timing.
VIN1
BUCK
CO NV ERTER 1
H
S
SD Loop
Current
SD ON
Loop C urrent
HS O N
VIN 2 and 3
B UCK CONVE R TER
2 and 3
HS
LS Loop
Current
LS ON
Loop C urrent
HS O N
SW1 S W 2 and 3
GND 2 and 3
Buck Converter
PGND
SW
PVIN
Table 6. ILIM Table
Soft Start (ms) Voltage Applied to ILIM
3.2 1.25 - 1.49
1.6 1.50 - 1.81
0.8 1.82 - 2.13
0.4 2.14 - 2.50
Analog Integrated Circuit Device Data
20 Freescale Semiconductor
34713
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
EP SUFFIX
24-PIN
98ARL10577D
ISSUE B
Analog Integrated Circuit Device Data
Freescale Semiconductor 21
34713
PACKAGING
PACKAGING DIMENSIONS
EP SUFFIX
24-PIN
98ARL10577D
ISSUE B
Analog Integrated Circuit Device Data
22 Freescale Semiconductor
34713
REVISION HISTORY
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES
1.0 2/2006 • Pre-release version
• Implemented Revision History page
2.0 11/2006 • Initial release
• Converted format from Market Assessment to Product Preview
• Major updates to the data, form, and style
3.0 2/2007 • Major updates to the data, form, and style
4.0 5/2007 • Changed Feature fom 2% to 1%, relabeled to include soft start
• Changed 34713 Simplified Application Diagram
• Made change to 34713 Simplified Internal Block Diagram
• Removed Machine Model in Maximum Ratings
• Changed Input DC Supply Current(11) Normal mode and Input DC Supply Current(11) Shutdown
mode
• Changed Output Voltage Accuracy(12),(14)
• Changed Soft start Adjusting reference Voltage Range and Short-circuit Current Limit
• Changed High Side N-CH Power MOSFET (M3) RDS(ON)(12) and Low Side N-CH Power MOSFET
(M4) RDS(ON)(12)
• Changed M2 RDS(ON) and PVIN Pin Leakage Current
• Changed SD Pin Internal Pull-up Resistor(15)
• Changed Changed Soft Start Duration (Normal Mode)
• Changed Over-current Limit Retry Time-out Period and Output Under-voltage/Over-voltage Filter
Delay Timer
• Changed PG Reset Delay and Thermal Shutdown Retry Timeout Period(16)
• Changed definition for Soft Start Adjustment input (ILIM)
• Changed drawings in Typical Applications
• Changed drawing in Type III Compensation Network
• Changed table for Soft Start Selection
• Removed PC34713EP/R2 from the ordering information and added MC34713EP/R2
• Changed the data sheet status to Advance Information
5.0 1/2008 • Made changes to Switching Node (SW) Pin, BOOT Pin (Referenced to SW Pin), Output Under-
voltage Threshold, Output Over-voltage Threshold, High Side N-CH Power MOSFET (M3)
RDS(ON)(12), Low Side N-CH Power MOSFET (M4) RDS(ON)(12), Charge Device Model
• Added Machine Model (MM), SW Leakage Current (Standby and Shutdown modes), Error Amplifier
DC Gain(15), Error Amplifier Unit Gain Bandwidth(15), Error Amplifier Slew Rate(15), Error Amplifier
Input Offset(15), High Side MOSFET Drain Voltage (PVIN) Pin
• Added pin 25 to Figure 3 and the 34713 Pin Definitions
• Added the section Layout Guidelines
MC34713
Rev. 5.0
12/2008
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