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General Description
The MAX1080/MAX1081 10-bit analog-to-digital convert-
ers (ADCs) combine an 8-channel analog-input multiplex-
er, high-bandwidth track/hold (T/H), and serial interface
with high conversion speed and low power consumption.
The MAX1080 operates from a single +4.5V to +5.5V sup-
ply; the MAX1081 operates from a single +2.7V to +3.6V
supply. Both devices’ analog inputs are software config-
urable for unipolar/bipolar and single-ended/pseudo-dif-
ferential operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1080/
MAX1081 use an external serial-interface clock to perform
successive-approximation analog-to-digital conversions.
The devices feature an internal +2.5V reference and a ref-
erence-buffer amplifier with a ±1.5% voltage-adjustment
range. An external reference with a 1V to VDD1 range may
also be used.
The MAX1080/MAX1081 provide a hard-wired SHDN pin
and four software-selectable power modes (normal opera-
tion, reduced power (REDP), fast power-down (FASTPD),
and full power-down (FULLPD)). These devices can be
programmed to automatically shut down at the end of a
conversion or to operate with reduced power. When using
the power-down modes, accessing the serial interface
automatically powers up the devices, and the quick turn-
on time allows them to be shut down between all conver-
sions. This technique can cut supply current below 100mA
at lower sampling rates.
The MAX1080/MAX1081 are available in a 20-pin TSSOP
package. These devices are higher-speed versions of the
MAX148/MAX149. For more information, refer to the
respective data sheet.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
Features
8-Channel Single-Ended or 4-Channel
Pseudo-Differential Inputs
Internal Multiplexer and Track/Hold
Single-Supply Operation
+4.5V to +5.5V (MAX1080)
+2.7V to +3.6V (MAX1081)
Internal +2.5V Reference
400ksps Sampling Rate (MAX1080)
Low Power: 2.5mA (400ksps)
1.3mA (REDP)
0.9mA (FASTPD)
2µA (FULLPD)
SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial Interface
Software-Configurable Unipolar or Bipolar Inputs
20-Pin TSSOP Package
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
________________________________________________________________ Maxim Integrated Products 1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TSSOP
VDD1
VDD2
DIN
SSTRB
DOUT
GND
REFADJ
REF
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX1080
MAX1081
SHDN
CS
SCLK
19-1685; Rev 0; 5/00
PART
MAX1080ACUP
MAX1080BCUP
MAX1080AEUP -40°C to +85°C
0°C to +70°C
0°C to +70°C
TEMP.
RANGE
PIN-
PACKAGE
20 TSSOP
20 TSSOP
20 TSSOP
Typical Operating Circuit appears at end of data sheet.
Pin Configuration
INL
(LSB)
±1/2
±1
±1/2
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
Ordering Information
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—MAX1080
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD_ to GND .............................................................. -0.3V to 6V
VDD1 to VDD2 ......................................................... -0.3V to 0.3V
CH0–CH7, COM to GND.......................... -0.3V to (VDD1 + 0.3V)
REF, REFADJ to GND .............................. -0.3V to (VDD1 + 0.3V)
Digital Inputs to GND................................................. -0.3V to 6V
Digital Outputs to GND ............................ -0.3V to (VDD2 + 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 7.0mW/°C above +70°C) ........ 559mW
Operating Temperature Ranges
MAX108_ _CUP ................................................. 0°C to +70°C
MAX108_ _EUP............................................... -40°C to +85°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
MAX1080A
SINAD > 58dB
-3dB point
fIN = 200kHz, VIN = 2.5Vp-p
fIN1 = 99kHz, fIN2 =102kHz
MAX1080B
No missing codes over temperature
Up to the 5th harmonic
CONDITIONS
MHz
0.5 6.4
fSCLK
Serial Clock Frequency
ps
<50
Aperture Jitter
ns
10
Aperture Delay
ns
468
tACQ
Track/Hold Acquisition Time
µs
2.5
tCONV
Conversion Time (Note 5)
kHz
350
Full-Linear Bandwidth
MHz
6
Full-Power Bandwidth
dB
-78
Channel-to-Channel Crosstalk
(Note 4)
dB
76
IMDIntermodulation Distortion
dB
70
SFDRSpurious-Free Dynamic Range
dB
-70
THDTotal Harmonic Distortion
LSB
±0.5
INLRelative Accuracy (Note 2)
Bits
10
Resolution
dB
60
SINAD
Signal-to-Noise plus Distortion
Ratio
LSB
±0.1
Channel-to-Channel Offset-Error
Matching
ppm/°C
±0.8
Gain-Error Temperature
Coefficient
±1.0
LSB
±1.0
DNLDifferential Nonlinearity
LSB
±3.0
Offset Error
LSB
±3.0
Gain Error (Note 3)
UNITSMIN TYP MAXSYMBOLPARAMETER
%
40 60
Duty Cycle
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)
DC ACCURACY (Note 1)
CONVERSION RATE
mA
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—MAX1080 (continued)
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
To power down the internal reference
For small adjustments, from 1.22V
0 to 1mA output load
On/off leakage current, VCH_ = 0 or VDD1
TA= +25°C
Bipolar, VCOM or VCH_ = VREF/2, referenced
to COM or CH_
Unipolar, VCOM = 0
V/V
+2.05
Buffer Voltage Gain
V
1.4 VDD1 - 1.0
REFADJ Buffer Disable
Threshold
mV
±100
REFADJ Input Range
V
1.22
REFADJ Output Voltage
µF
0.01 10
Capacitive Bypass at REFADJ
µF
4.7 10
Capacitive Bypass at REF
mV/mA
0.1 2.0
Load Regulation (Note 7)
ppm/°C
±15
TC VREF
REF Output Temperature
Coefficient
mA
30
REF Short-Circuit Current
V
2.480 2.500 2.520
VREF
REF Output Voltage
pF18Input Capacitance
µA
±0.001 ±1
Multiplexer Leakage Current
±VREF/2 V
VREF
VCH_
Input Voltage Range, Single
Ended and Differential (Note 6)
VIN = 0 or VDD2
In power-down mode, fSCLK = 0
VREF = 2.500V, fSCLK = 0
VREF = 2.500V, fSCLK = 6.4MHz
(Note 8)
pFCIN
Input Capacitance
µA±1IIN
Input Leakage
V0.2VHYST
Input Hysteresis
V0.8VINL
Input Low Voltage
V3.0VINH
Input High Voltage
5
320 µA
200 350
REF Input Current
V
1.0 VDD1 +
50mV
REF Input Voltage Range
ISINK = 5mA V0.4VOL
Output Voltage Low
15
ISOURCE = 1mA V4VOH
Output Voltage High
CS = 5V µA±10IL
Three-State Leakage Current
CS = 5V pF15COUT
Three-State Output Capacitance
ANALOG INPUTS (CH7–CH0, COM)
EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF)
INTERNAL REFERENCE
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS (DOUT, SSTRB)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
4 _______________________________________________________________________________________
VDD1 =
VDD2 =
5.5V
VDD1 = VDD2 = 5V ±10%, midscale input
CONDITIONS
mA
2.5 4.0
IVDD1+
IVDD2
Supply Current
V4.5 5.5
VDD1,
VDD2
Positive Supply Voltage
(Note 9)
1.3 2.0
0.9 1.5
µA
210
mV±0.5 ±2.0PSRPower-Supply Rejection
UNITSMIN TYP MAXSYMBOLPARAMETER
Normal operating mode (Note 10)
Reduced-power mode (Note 11)
Fast power-down mode (Note 11)
Full power-down mode (Note 11)
ELECTRICAL CHARACTERISTICS—MAX1080 (continued)
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS—MAX1081
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1081A
SINAD > 58dB
-3dB point
fIN = 150kHz, VIN = 2.5Vp-p
fIN1 = 73kHz, fIN2 = 77kHz
MAX1081B
No missing codes over temperature
Up to the 5th harmonic
CONDITIONS
kHz
250
Full-Linear Bandwidth
MHz
3
Full-Power Bandwidth
dB
-78
Channel-to-Channel Crosstalk
(Note 4)
dB
76
IMDIntermodulation Distortion
dB
70
SFDRSpurious-Free Dynamic Range
dB
-70
THDTotal Harmonic Distortion
LSB
±0.5
INLRelative Accuracy (Note 2)
Bits
10
Resolution
dB
60
SINAD
Signal-to-Noise plus Distortion
Ratio
LSB
±0.2
Channel-to-Channel Offset-Error
Matching
ppm/°C
±1.6
Gain-Error Temperature
Coefficient
±1.0
LSB
±1.0
DNLDifferential Nonlinearity
LSB
±3.0
Offset Error
LSB
±3.0
Gain Error (Note 3)
UNITSMIN TYP MAXSYMBOLPARAMETER
POWER SUPPLY
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS—MAX1081 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Normal operating mode
Normal operating mode
Normal operating mode
CONDITIONS
MHz
0.5 4.8
fSCLK
Serial Clock Frequency
ps
<50
Aperture Jitter
ns
10
Aperture Delay
ns
625
tACQ
Track/Hold Acquisition Time
µs
3.3
tCONV
Conversion Time (Note 5)
UNITSMIN TYP MAXSYMBOLPARAMETER
To power down the internal reference
For small adjustments, from 1.22V
0 to 0.75mA output load
On/off leakage current, VCH_ = 0 or VDD1
TA= +25°C
Bipolar, VCOM or VCH_ = VREF/2,
referenced to COM or CH_
Unipolar, VCOM = 0
V/V
2.05
Buffer Voltage Gain
V
1.4 VDD1 - 1
REFADJ Buffer Disable
Threshold
mV
±100
REFADJ Input Range
V
1.22
REFADJ Output Voltage
µF
0.01 10
Capacitive Bypass at REFADJ
µF
4.7 10
Capacitive Bypass at REF
mV/mA
0.1 2.0
Load Regulation (Note 7)
ppm/°C
±15
TC VREF
REF Output Temperature
Coefficient
mA
15
REF Short-Circuit Current
V
2.480 2.500 2.520
VREF
REF Output Voltage
pF18Input Capacitance
µA
±0.001 ±1
Multiplexer Leakage Current
±VREF/2
%
40 60
Duty Cycle
V
VREF
VCH_
Input Voltage Range, Single
Ended and Differential (Note 6)
VIN = 0 or VDD2
In power-down mode, fSCLK = 0
VREF = 2.500V, fSCLK = 0
VREF = 2.500V, fSCLK = 4.8MHz
(Note 8)
pF
15
CIN
Input Capacitance
µA
±1
IIN
Input Leakage
V
0.2
VHYST
Input Hysteresis
V
0.8
VINL
Input Low Voltage
V
2.0
VINH
Input High Voltage
5
REF Input Current 320 µA
200 350
V
1.0 VDD1 +
50mV
REF Input Voltage Range
V/V
+2.05
Buffer Voltage Gain
CONVERSION RATE
ANALOG INPUTS (CH7–CH0, COM)
INTERNAL REFERENCE
EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF)
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
6 _______________________________________________________________________________________
VDD1 =
VDD2 =
3.6V
ISOURCE = 0.5mA
VDD1 = VDD2 = 2.7V to 3.6V, midscale input
CONDITIONS
mA
2.5 3.5
IVDD1+
IVDD2
Supply Current
V2.7 3.6
VDD1,
VDD2
VVDD2 - 0.5VVOH
Output Voltage High
Positive Supply Voltage
(Note 9)
1.3 2.0
Normal operating mode (Note 10)
Reduced-power mode (Note 11)
0.9 1.5
Fast power-down mode (Note 11)
Full power-down mode (Note 11) µA
210
mV±0.5 ±2.0PSRPower-Supply Rejection
UNITSMIN TYP MAXSYMBOLPARAMETER
ISINK = 5mA V0.4VOL
Output Voltage Low
CS = 3V µA±10IL
Three-State Leakage Current
CS = 3V pF15COUT
Three-State Output Capacitance
ELECTRICAL CHARACTERISTICS—MAX1081 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS–MAX1080
(Figures 1, 2, 6, 7; VDD1 = VDD2 = +4.5V to +5.5V, TA= TMIN to TMAX, unless otherwise noted.)
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CONDITIONS
ns
100
tCSW
CS Pulse Width High
ns
65
tSTE
CS Fall to SSTRB Enable
ns
65
tDOE
CS Fall to DOUT Enable
ns
10 65
tSTD
CS Rise to SSTRB Disable
ns
10 65
tDOD
CS Rise to DOUT Disable
ns
80
tSTV
SCLK Rise to SSTRB Valid
ns
80
tDOV
SCLK Rise to DOUT Valid
ns
62
tCL
SCLK Pulse Width Low
ns
62
tCH
ns
156
tCP
SCLK Period
SCLK Pulse Width High
ns
10 20
tSTH
SCLK Rise to SSTRB Hold
ns
10 20
tDOH
SCLK Rise to DOUT Hold
ns
35
tCS1
CS Rise to SCLK Rise Ignore
ns
35
tCSO
SCLK Rise to CS Fall Ignore
ns
35
tDS
DIN to SCLK Setup
ns
0
tDH
DIN to SCLK Hold
ns
35
tCSS
CS Fall to SCLK Rise Setup
ns
0
tCSH
SCLK Rise to CS Rise Hold
UNITSMIN TYP MAXSYMBOLPARAMETER
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER SUPPLY
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 7
TIMING CHARACTERISTICS—MAX1081
(Figures 1, 2, 6, 7; VDD1 = VDD2 = +2.7V to +3.6V, TA= TMIN to TMAX, unless otherwise noted.)
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CONDITIONS
ns
100
tCSW
CS Pulse Width High
ns
85
tSTE
CS Fall to SSTRB Enable
ns
85
tDOE
CS Fall to DOUT Enable
ns
13 85
tSTD
CS Rise to SSTRB Disable
ns
13 85
tDOD
CS Rise to DOUT Disable
ns
100
tSTV
SCLK Rise to SSTRB Valid
ns
100
tDOV
SCLK Rise to DOUT Valid
ns
83
tCL
SCLK Pulse Width Low
ns
83
tCH
ns
208
tCP
SCLK Period
SCLK Pulse Width High
ns
13 20
tSTH
SCLK Rise to SSTRB Hold
ns
13 20
tDOH
SCLK Rise to DOUT Hold
ns
45
tCS1
CS Rise to SCLK Rise Ignore
ns
45
tCSO
SCLK Rise to CS Fall ignore
ns
45
tDS
DIN to SCLK Setup
ns
0
tDH
DIN to SCLK Hold
ns
45
tCSS
CS Fall to SCLK Rise Setup
ns
0
tCSH
SCLK Rise to CS Rise Hold
UNITSMIN TYP MAXSYMBOLPARAMETER
Note 1: Tested at VDD1 = VDD2 = VDD(MIN), COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled.
Note 4: Ground the “on” channel; sine wave is applied to all “off” channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs (CH7–CH0 and COM) is from GND to VDD1.
Note 7: External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is the
result of production test limitations.
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9: Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) to VDD1(MAX) = VDD2(MIN). For operations beyond
this range, see Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 10: AIN= midscale. Unipolar mode. MAX1080 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz, 0 to 5V.
MAX1081 tested with same loads, fSCLK = 4.8MHz, 0 to 3V.
Note 11: SCLK = DIN = GND, CS = VDD1.
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
8 _______________________________________________________________________________________
Typical Operating Characteristics
(MAX1080: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1081: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)
-0.04
-0.08
0
0.08
0.12
0400200 600 800 1000
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1080/1-01
DIGITAL OUTPUT CODE
INL (LSB)
1200
0.04
-0.05
-0.10
0
0.05
0.10
0 400
200 600 800 1000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1080/1-02
DIGITAL OUTPUT CODE
DNL (LSB)
1200
-0.15
0.15
3.5
3.0
2.5
2.0
1.5
2.5 4.03.0 3.5 4.5 5.0 5.5
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (CONVERTING)
MAX1080/1-03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
2.0
2.4
2.2
2.8
2.6
3.0
3.2
-40 20 40-20 0 60 80 100
SUPPLY CURRENT vs. TEMPERATURE
MAX1080/1-04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1081
MAX1080
NORMAL OPERATION (PD1 = PD0 = 1)
REDP (PD1 = 1, PD0 = 0)
FASTPD (PD1 = 0, PD0 = 1)
0
0.5
1.5
1.0
2.0
2.5
2.5 3.53.0 4.0 4.5 5.0 5.5
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (STATIC)
MAX1080/1-05
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
0
0.5
1.5
1.0
2.0
2.5
-40 0-20 20 40 60 80 100
SUPPLY CURRENT vs. TEMPERATURE
(STATIC)
MAX1080/1-06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1080 (PD1 = 1, PD0 = 1)
MAX1080 (PD1 = 1, PD0 = 0)
MAX1080 (PD1 = 0, PD0 = 1)
MAX1081 (PD1 = 1, PD0 = 1)
MAX1081 (PD1 = 1, PD0 = 0)
MAX1081 (PD1 = 0, PD0 = 1)
0
0.5
1.5
1.0
2.0
2.5
2.5 3.53.0 4.0 4.5 5.0 5.5
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1080/1-07
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
(PD1 = PD0 = 0)
0
0.5
1.5
1.0
2.0
2.5
-40 0-20 20 40 60 80 100
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1080/1-08
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
MAX1081
MAX1080
(PD1 = PD0 = 0)
2.4995
2.4997
2.5001
2.4999
2.5003
2.5005
2.5 3.53.0 4.0 4.5 5.0 5.5
REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1080/1-09
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 9
2.4988
2.4992
2.4990
2.4996
2.4994
2.5000
2.4998
2.5002
-40 0 20-20 40 60 80 100
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1080/1-10
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX1081
MAX1080
-0.50
-0.25
0
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1080/1-11
VDD (V)
OFFSET ERROR (LSB)
2.7 3.33.0 3.6
-0.50
-0.25
0
-40 10-15 35 60 85
OFFSET ERROR vs. TEMPERATURE
MAX1080/1-12
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-0.75
-0.25
-0.50
0
0.25
2.7 3.33.0 3.6
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1080/1-13
VDD (V)
GAIN ERROR (LSB)
-0.50
-0.25
0
MAX1081
GAIN ERROR vs. TEMPERATURE
MAX1080/1-14
TEMPERATURE (°C)
GAIN ERROR (LSB)
-40 10-15 35 60 85
Typical Operating Characteristics (continued)
(MAX1080: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1081: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
10 ______________________________________________________________________________________
Pin Description
Positive Supply VoltageVDD2
19
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to
VDD1.
REFADJ12
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-
ance when CS is high.
SSTRB15
Serial Data Input. Data is clocked in at SCLK’s rising edge.DIN16
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
and SSTRB are high impedance.
CS
17
Serial Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty
cycle must be 40% to 60%.)
SCLK18
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode, the reference buffer provides a 2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
VDD1.
REF11
Analog and Digital GroundGND13
Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
DOUT14
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA
(typ).
SHDN
10
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
COM9
PIN
Sampling Analog InputsCH0–CH71–8
FUNCTIONNAME
VDD2
6k
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
6k
DOUT
a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL
VDD2
6k
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
6k
DOUT
a) VOH to High-Z b) VOL to High-Z
Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time
Positive Supply VoltageVDD1
20
Detailed Description
The MAX1080/MAX1081 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 10-bit digital out-
put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia-
gram of the MAX1080/MAX1081.
Pseudo-Differential Input
The equivalent circuit of Figure 4 shows the MAX1080/
MAX1081s’ input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched-
capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 1 and 2.
The MAX1080/MAX1081 input configuration is pseudo-
differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation-
ship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a
sinusoidal signal at IN-, the input voltage is determined
by:
The maximum voltage variation is determined by:
A 2.6Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / fSCLK). When a DC refer-
ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
CHOLD as a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLD from IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to VDD1/2 within the limits of 10-bit resolu-
tion. This action is equivalent to transferring a
12pF [(VIN+ - VIN-)] charge from CHOLD to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
max d
dt V2f
1LSB
t
V
2t
IN IN CONV
REF
10 CONV
νπ
=
()
≤=
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
______________________________________________________________________________________ 11
INPUT
SHIFT
REGISTER CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+1.22V
REFERENCE
T/H
ANALOG
INPUT
MUX
10 + 2-BIT
SAR ADC
IN
DOUT
SSTRB
VDD1
VDD2
GND
SCLK
DIN
COM
REFADJ
REF
OUT
REF
CLOCK
+2.500V
17k
10
11
12
9
14
15
16
17
18
CH6 7
CH7 8
CH4 5
CH5 6
CH1 2
CH2 3
CH3 4
CH0 1
MAX1080
MAX1081
CS
SHDN
20
19
13
2.05
A
Figure 3. Functional Diagram
CHOLD
12pF
RIN
800
HOLD
INPUT
MUX
CSWITCH*
*INCLUDES ALL INPUT PARASITICS
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
CH0
REF
GND
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
ZERO
VDD1/2
COMPARATOR
CAPACITIVE
DAC
6pF
TRACK
Figure 4. Equivalent Input Circuit
νπ
IN IN
V sin(2 ft)
−−
=
()
Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
00 0 +
00 1 +
01 0 +
01 1 +–
10 0 +
10 1 +
11 0 +
11 1 +
Table 2. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
00 0 +
00 1 +
01 0 +
01 1 +–
10 0 +
10 1 +
11 0 +
11 1 –+
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
12 ______________________________________________________________________________________
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter con-
verts the “+” input. If the converter is set up for differen-
tial inputs, the difference of
[(
IN+) - (IN-)
]
is converted.
At the end of the conversion, the positive input con-
nects back to IN+ and CHOLD charges to the input sig-
nal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. It is calculated by the following equa-
tion:
tACQ = 7 (RS+ RIN) 12pF
where RIN = 800, RS= the source impedance of the
input signal, and tACQ is never less than 468ns
(MAX1080) or 625ns (MAX1081). Note that source
impedances below 4kdo not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input tracking circuitry has a 6MHz
(MAX1080) or 3MHz (MAX1081) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, anti-
alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog input
to VDD1 and GND, allow the channel input pins to swing
from GND - 0.3V to VDD1 + 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD1 by more than 50mV or be
lower than GND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not allow the input current to exceed 2mA.
Quick Look
To quickly evaluate the MAX1080/MAX1081s’ analog per-
formance, use the circuit of Figure 5. The devices require
a control byte to be written to DIN before each conver-
sion. Connecting DIN to VDD2 feeds in control bytes of
$FF (HEX), which trigger single-ended unipolar conver-
sions on CH7 without powering down between conver-
sions. The SSTRB output pulses high for one clock
period before the MSB of the conversion result is shift-
ed out of DOUT. Varying the analog input to CH7 will
alter the sequence of bits from DOUT. A total of 16
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs typically occur 20ns
after the rising edge of SCLK.
Starting a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1080/MAX1081s’ internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 3 shows the control-byte format.
The MAX1080/MAX1081 are compatible with SPI/
QSPI and MICROWIRE devices. For SPI, select the cor-
rect clock polarity and sampling edge in the SPI control
registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at
the same time. Using the Typical Operating Circuit, the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to clock
out the conversion result). See Figure 17 for MAX1080/
MAX1081 QSPI connections.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 500kHz to 6.4MHz (MAX1080) or
4.8MHz (MAX1081):
1) Set up the control byte and call it TB1. TB1 should
be of the format: 1XXXXXXX binary, where the Xs
denote the particular channel, selected conversion
mode, and power mode.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB3.
6) Pull CS high.
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
______________________________________________________________________________________ 13
10µF0.1µF
2.5V
VDD1
VDD2
GND
COM
CS
SCLK
DIN
DOUT
SSTRB
SHDN
VDD2
VDD2
0.01µF
0.01µF
CH7
REFADJ
REF
4.7µF
0 TO
+2.500V
ANALOG
INPUT
OSCILLOSCOPE
CH1 CH2 CH3 CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $3FF (HEX)
MAX1080
MAX1081
+3V OR +5V
EXTERNAL CLOCK
SCLK
SSTRB
DOUT*
Figure 5. Quick-Look Circuit
MAX1080/MAX1081
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with three leading zeros, two sub-LSB bits, and one
trailing zero. The total conversion time is a function of
the serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar input mode, the output is two’s
complement (Figure 15). Data is clocked out on the ris-
ing edge of SCLK in MSB-first format.
Serial Clock
The external clock not only shifts data in and out but
also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the
next 12 SCLK rising edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 7 shows the detailed serial-interface
timings.
The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
Data Framing
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after VDD1 and VDD2
are applied.
OR
The first high bit clocked into DIN after bit 4 of a con-
version in progress is clocked onto the DOUT pin.
Once a start bit has been recognized, the current conver-
sion may only be terminated by pulling SHDN low.
The fastest the MAX1080/MAX1081 can run with CS held
low between conversions is 16 clocks per conversion.
Figure 8 shows the serial-interface timing necessary to
perform a conversion every 16 SCLK cycles. If CS is tied
low and SCLK is continuous, guarantee a start bit by first
clocking in 16 zeros.
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
14 ______________________________________________________________________________________
BIT NAME DESCRIPTION
7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.
6 SEL2 These three bits select which of the eight channels are used for the conversion (Tables 1 and 2).
5 SEL1
4 SEL0
3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0 to VREF can be converted; in bipolar mode, the differential signal can
range from -VREF/2 to +VREF/2.
2 SGL/DIF 1 = single ended, 0 = pseudo-differential. Selects single-ended or pseudo-differential conver-
sions. In single-ended mode, input signal voltages are referred to COM. In pseudo-differential
mode, the voltage difference between two channels is measured (Tables 1 and 2).
1 PD1 Select operating mode.
0(LSB) PD0 PD1 PD0 Mode
0 0 Full power-down
0 1 Fast power-down
1 0 Reduced power
1 1 Normal operation
Table 3. Control-Byte Format
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(MSB) (LSB)
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
______________________________________________________________________________________ 15
___________Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1080/MAX1081 in normal operating mode, ready to
convert with SSTRB = low. The MAX1080/MAX1081
require 10µs to reset after the power supplies stabilize;
no conversions should be initiated during this time. If
CS is low, the first logical 1 on DIN is interpreted as a
start bit. Until a conversion takes place, DOUT shifts out
zeros. Additionally, wait for the reference to stabilize
when using the internal reference.
Power Modes
You can save power by placing the converter in one of
two low-current operating modes or in full power-down
between conversions. Select the power mode through
bit 1 and bit 0 of the DIN control byte (Tables 3 and 4),
or force the converter into hardware shutdown by dri-
ving SHDN to GND.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
progress. In software power-down mode, the serial
interface remains active while waiting for a new control
byte to start conversion and switch to full-power mode.
Once the conversion is completed, the device goes into
the programmed power mode until a new control byte
is written.
The power-up delay is dependent on the power-down
state. Software low-power modes will be able to start
conversion immediately when running at decreased
clock rates (see Power-Down Sequencing). During
power-on reset, when exiting software full power-down
mode, or when exiting hardware shutdown, the device
goes immediately into full-power mode and is ready to
convert after 2µs when using an external reference.
When using the internal reference, wait for the typical
power-up delay from a full power-down (software or
hardware) as shown in Figure 9.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. When software power-down is
asserted, the ADC completes the conversion in
progress and powers down into the specified low-qui-
escent-current state (2µA, 0.9mA, or 1.3mA).
The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1080/MAX1081 into its full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 = 1,
a 0.9mA power-down resumes after one conversion.
Table 4 details the four power modes with the corre-
sponding supply current and operating sections. For
data rates achievable in software power-down modes,
see Power-Down Sequencing.
ACQUISITION
IDLE
CS
SCLK
DIN
SSTRB
DOUT
tACQ
IDLECONVERSION
RB3RB2
RB1
SEL
2
1
START
4 891216 2024
SEL
1
SEL
0
UNI/
BIP
SGL/
DIF PD1 PD0
B9 B8 B7 B6 B5
B4
B3 B2 B1 B0 S1 S0
HIGH-Z
HIGH-Z HIGH-Z
HIGH-Z
Figure 6. Single-Conversion Timing
MAX1080/MAX1081
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is terminated immediately. When returning
to normal operation from SHDN with an external refer-
ence, the MAX1080/MAX1081 can be considered fully
powered up within 2µs of actively pulling SHDN high.
When using the internal reference, the conversion
should be initiated only after the reference has settled;
its recovery time is dependent on the external bypass
capacitors and shutdown duration.
Power-Down Sequencing
The MAX1080/MAX1081 automatic power-down modes
can save considerable power when operating at less
than maximum sample rates. Figures 10 and 11 show
the average supply current as a function of the sam-
pling rate.
Using Full Power-Down Mode
Full power-down mode (FULLPD) achieves the lowest
power consumption, up to 1000 conversions per chan-
nel per second. Figure 10a shows the MAX1081’s
power consumption for one- or eight-channel conver-
sions utilizing full power-down mode (PD1 = PD0 = 0),
with the internal reference and the maximum clock
speed. A 0.01µF bypass capacitor at REFADJ forms an
RC filter with the internal 17kreference resistor, with a
200µs time constant. To achieve full 10-bit accuracy,
seven time constants or 1.4ms are required after
power-up if the bypass capacitor is fully discharged
between conversions. Waiting this 1.4ms duration in
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
16 ______________________________________________________________________________________
PD1/PD0 MODE CONVERTING
(mA)
AFTER
CONVERSION INPUT COMPARATOR REFERENCE
00 Full Power-Down
(FULLPD) 2.5 2µA Off Off
01 Fast Power-Down
(FASTPD) 2.5 0.9mA Reduced Power On
10 Reduced-Power
Mode (REDP) 2.5 1.3mA Reduced Power On
11 Normal Operating 2.5 2.0mA Full Power On
CIRCUIT SECTIONS*TOTAL SUPPLY CURRENT
Table 4. Software-Controlled Power Modes
*Circuit operation between conversions; during conversion all circuits are fully powered up.
SCLK
DIN
DOUT
SSTRB
tCSS tCH
tCSO tCL
tDH
tDS
tDOE
tSTE
tCSW
tCP tCSH
tCS1
tSTD
tDOD
tDOV
tDOH
tSTV
tSTH
CS
Figure 7. Detailed Serial-Interface Timing
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
______________________________________________________________________________________ 17
SCLK
11 15885812 12 1216 16 1 516
B4B9S0B4B9S0
DIN
SSTRB
DOUT
CS
CONTROL BYTE 0SSSCONTROL BYTE 1
CONVERSION RESULT 1CONVERSION RESULT 0
CONTROL BYTE 2 S ETC.
B4B9
HIGH-Z
HIGH-Z
Figure 8. Continuous 16-Clock/Conversion Timing
0
0.50
0.25
1.00
0.75
1.25
1.50
0.0001 0.010.001 0.1 1 10
TIME IN SHUTDOWN (s)
REFERENCE POWER-UP DELAY (ms)
MAX1081, VDD1 = VDD2 = 3.0V
CLOAD = 20pF
CODE = 1010100000
1000
100
10
1
0.1 101 100 1k 10k
SAMPLING RATE (sps)
SUPPLY CURRENT (µA)
8 CHANNELS
1 CHANNEL
10,000
1000
10
100
1
1 10010 1k 10k 100k
SAMPLING RATE (sps)
SUPPLY CURRENT (µA)
MAX1081, VDD1 = VDD2 = 3.0V
CLOAD = 20pF
CODE = 1010100000
8 CHANNELS
1 CHANNEL
Figure 9. Reference Power-Up Delay vs. Time in Shutdown
Figure 10a. Average Supply Current vs. Sampling Rate (sps)
Using FULLPD and Internal Reference
Figure 10b. Average Supply Current vs. Sampling Rate (sps)
Using FULLPD and External Reference
2.5
2.0
1.0
1.5
0.5
0150 250
100
50 200 300 350
SAMPLING RATE (sps)
SUPPLY CURRENT (mA)
MAX1081, VDD1= VDD2 = 3.0V
CLOAD = 20pF
CODE = 1010100000
REDP
FASTPD
NORMAL OPERATION
Figure 11. Average Supply Current vs. Sampling Rate (sps) Using
FASTPD, REDP, Normal Operation, and Internal Reference
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
18 ______________________________________________________________________________________
Figure 12a. Full Power-Down Timing
REFADJ 1.22V 1.22V
0V
2.5mA 2.5mA
1.3mA OR 0.9mA
DIN
IVDD1 + IVDD2
REF
FULLPD REDP
WAIT 1.4ms (7 x RC)
FULLPD
10011
γ = RC = 17kx 0.01µF
DUMMY CONVERSION
1
1000
2.5V
2.5mA
0V 0mA
2.5V
0V
Figure 12b. FASTPD and REDP Timing
2.5V (ALWAYS ON)
2.5mA 2.5mA
DIN
IVDD1 + IVDD2
REF
REDP REDP FASTPD
11011
1001
2.5mA
0.9mA 0.9mA 1.3mA
fast power-down (FASTPD) or reduced-power (REDP)
mode instead of in full power-up can further reduce
power consumption. This is achieved by using the
sequence shown in Figure 12a.
Figure 10b shows the MAX1081’s power consumption
for one- or eight-channel conversions utilizing FULLPD
mode (PD1 = PD0 = 0), an external reference, and the
maximum clock speed. One dummy conversion to
power up the device is needed, but no wait time is nec-
essary to start the second conversion, thereby achiev-
ing lower power consumption at up to half the full
sampling rate.
Using Fast Power-Down and Reduced Power Modes
FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sam-
pling rate. Figure 11 shows the MAX1081’s power con-
sumption in FASTPD mode (PD1 = 0, PD0 = 1), REDP
mode (PD1 = 1, PD0 = 0), and for comparison, normal
operating mode (PD1 = 1, PD0 = 1). The figure shows
power consumption using the specified power-down
mode, with the internal reference and conversion con-
trolled at the maximum clock speed. The clock speed
in FASTPD or REDP should be limited to 4.8MHz for the
MAX1080/MAX1081. FULLPD mode may provide
increased power savings in applications where the
MAX1080/MAX1081 are inactive for long periods of
time, but intermittent bursts of high-speed conversions
are required. Figure 12b shows FASTPD and REDP tim-
ing.
Internal and External References
The MAX1080/MAX1081 can be used with an internal
or external reference. An external reference can be
connected directly at REF or at the REFADJ pin.
An internal buffer is designed to provide 2.5V at
REF for the MAX1080/MAX1081. The internally trimmed
1.22V reference is buffered with a 2.05V/V gain.
Internal Reference
The MAX1080/MAX1081s’ full-scale range with the inter-
nal reference is 2.5V with unipolar inputs and ±1.25V
with bipolar inputs. The internal reference voltage is
adjustable by ±100mV with the circuit in Figure 13.