Low Cost Instrumentation Amplifier
Data Sheet
AD622
Rev. E
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights
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FEATURES
Easy to use
Low cost solution
Higher performance than two or three op amp design
Unity gain with no external resistor
Optional gains with one external resistor
(Gain range: 2 to 1000)
Wide power supply range: ±2.6 V to ±15 V
Available in 8-lead PDIP and 8-lead SOIC_N packages
Low power, 1.5 mA maximum supply current
DC performance
0.15% gain accuracy: G = 1
125 µV maximum input offset voltage
1.0 µV/°C maximum input offset drift
5 nA maximum input bias current
66 dB minimum common-mode rejection ratio: G = 1
Noise
12 nV/√Hz @ 1 kHz input voltage noise
0.60 µV p-p noise: 0.1 Hz to 10 Hz, G = 10
AC characteristics
800 kHz bandwidth: G = 10
10 µs settling time to 0.1% @ G = 1 to 100
1.2 V/µs slew rate
APPLICATIONS
Transducer interface
Low cost thermocouple amplifier
Industrial process controls
Difference amplifier
Low cost data acquisition
PIN CONFIGURATION
R
G1
–IN
2
+IN
3
–V
S4
R
G
8
+V
S
7
OUTPUT
6
REF
5
AD622
00777-001
Figure 1. 8-Lead PDIP and 8-Lead SOIC_N
(N and R Suffixes)
GENERAL DESCRIPTION
The AD622 is a low cost, moderately accurate instrumentation
amplifier in the traditional pin configuration that requires only
one external resistor to set any gain between 2 and 1000. For a
gain of 1, no external resistor is required. The AD622 is a
complete difference or subtractor amplifier system that also
provides superior linearity and common-mode rejection by
incorporating precision laser-trimmed resistors.
The AD622 replaces low cost, discrete, two or three op amp
instrumentation amplifier designs and offers good common-
mode rejection, superior linearity, temperature stability,
reliability, power, and board area consumption. The low cost of
the AD622 eliminates the need to design discrete
instrumentation amplifiers to meet stringent cost targets. While
providing a lower cost solution, it also provides performance
and space improvements.
Table 1. Next Generation Upgrades for AD622
Part Comment
AD8221
Better specs at lower price
AD8222
Dual channel or differential out
AD8226
Low power, wide input range
AD8220
JFET input
AD8228
Best gain accuracy
AD8295
+2 precision op amps or differential out
AD8421
Low noise, better specs
AD622 Data Sheet
Rev. E | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation .........................................................................9
Make vs. Buy: A Typical Application Error Budget ..................9
Gain Selection ................................................................................. 11
Input and Output Offset Voltage .............................................. 11
Reference Terminal .................................................................... 11
Input Protection ......................................................................... 11
RF Interference ........................................................................... 12
Ground Returns for Input Bias Currents ................................ 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 14
REVISION HISTORY
6/12—Rev. D to Rev. E
Changes to General Description Section; Added Table 1 ........... 1
Changes to Theory of Operation Section and Figure 16 ............. 9
Changes to Table 5 .......................................................................... 10
Changes to Input Selection Section; Deleted Large Input
Voltages at Large Gains Section; Added Figure 18, Renumbered
Sequentially ..................................................................................... 11
Changes to Ordering Guide .......................................................... 14
8/07—Re v. C to Rev. D
Updated Format .................................................................. Universal
Added Thermal Resistance Section ............................................... 5
Added Figure 16 ................................................................................ 9
Added Large Input Voltages at Large Gains Section ................. 11
Replaced RF Interference Section ................................................ 11
Deleted Grounding Section .......................................................... 10
Deleted Figure 16 ............................................................................ 10
Changes to Ground Returns for Input Bias Currents Section .. 12
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
4/99—Re v. B to Rev. C
8/98—Re v. A to Rev. B
2/97—Re v. 0 to Re v. A
1/96—Revision 0: Initial Version
Data Sheet AD622
Rev. E | Page 3 of 16
SPECIFICATIONS
TA = 25°C, VS = ±15 V, and RL = 2 kΩ typical, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
GAIN G = 1 + (50.5 k/RG)
Gain Range
1
1000
Gain Error1 VOUT = ±10 V
G = 1 0.05 0.15 %
G = 10 0.2 0.50 %
G = 100 0.2 0.50 %
G = 1000
0.2
0.50
%
Nonlinearity VOUT = ±10 V
G = 1 to 1000 RL = 10 kΩ 10 ppm
G = 1 to 100 RL = 2 kΩ 10 ppm
Gain vs. Temperature Gain = 1 10 ppm/°C
Gain > 11 −50 ppm/°C
VOLTAGE OFFSET Total RTI Error = VOSI + VOSO/G
Input Offset, VOSI VS = ±5 V to ±15 V 60 125 µV
Average Temperature Coefficient VS = ±5 V to ±15 V 1.0 µV/°C
Output Offset, V
OSO
V
S
= ±5 V to ±15 V
600
1500
µV
Average Temperature Coefficient VS = ±5 V to ±15 V 15 µV/°C
Offset Referred to Input vs. Supply (PSR) VS = ±5 V to ±15 V
G = 1 80 100 dB
G = 10 95 120 dB
G = 100
110
140
dB
G = 1000 110 140 dB
INPUT CURRENT
Input Bias Current
2.0
5.0
nA
Average Temperature Coefficient 3.0 pA/°C
Input Offset Current 0.7 2.5 nA
Average Temperature Coefficient 2.0 pA/°C
INPUT
Input Impedance
Differential 10||2 G Ω||pF
Common Mode 10||2 GΩ||pF
Input Voltage Range2
V
S
= ±2.6 V to ±5 V
−V
S
+ 1.9
+V
S
– 1.2
V
Over Temperature −VS + 2.1 +VS – 1.3 V
VS = ±5 V to ±18 V −VS + 1.9 +VS – 1.4 V
Over Temperature −VS + 2.1 +VS – 1.4 V
Common-Mode Rejection Ratio
DC to 60 Hz with 1 kΩ Source Imbalance
VCM = 0 V to ±10 V
G = 1
66
78
dB
G = 10 86 98 dB
G = 100 103 118 dB
G = 1000 103 118 dB
OUTPUT
Output Swing RL = 10 kΩ
VS = ±2.6 V to ±5 V −VS + 1.1 +VS – 1.2 V
Over Temperature −VS + 1.4 +VS – 1.3 V
VS = ±5 V to ±18 V −VS + 1.2 +VS – 1.4 V
Over Temperature −VS + 1.6 +VS – 1.5 V
Short Current Circuit ±18 mA
AD622 Data Sheet
Rev. E | Page 4 of 16
Parameter Conditions Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 1000 kHz
G = 10 800 kHz
G = 100
120
kHz
G = 1000 12 kHz
Slew Rate 1.2 V/µs
Settling Time to 0.1% 10 V step
G = 1 to 100 10 µs
NOISE
Voltage Noise, 1 kHz Total RTI Noise = √(e2ni) + (eno∕G)2
Input Voltage Noise, eni 12 nV/√Hz
Output Voltage Noise, eno 72 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 4.0 µV p-p
G = 10 0.6 µV p-p
G = 100 0.3 µV p-p
Current Noise f = 1 kHz 100 fA/√Hz
0.1 Hz to 10 Hz
10
pA p-p
REFERENCE INPUT
RIN 20 kΩ
I
IN
V
IN+
, V
REF
= 0
50
60
µA
Voltage Range −VS + 1.6 +VS – 1.6 V
Gain to Output 1 ± 0.0015
POWER SUPPLY
Operating Range3 ±2.6 ±18 V
Quiescent Current VS = ±2.6 V to ±18 V 0.9 1.3 mA
Over Temperature 1.1 1.5 mA
TEMPERATURE RANGE
For Specified Performance −40 to +85 °C
1 Does not include effects of External Resistor RG.
2 One input grounded, G = 1.
3 Defined as the same supply range that is used to specify PSR.
Data Sheet AD622
Rev. E | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation1 650 mW
Input Voltage (Common Mode) ±VS
Differential Input Voltage2 ±25 V
Output Short Circuit Duration Indefinite
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec)
300°C
1 Specification is for device in free air; see Table 4.
2 May be further restricted for gains greater than 14. See the Input Protection
section for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the device in free air.
Table 4. Thermal Resistance
Package Type θJA Unit
8-Lead PDIP (N-8) 95 °C/W
8-Lead SOIC_N (R-8) 155 °C/W
ESD CAUTION
AD622 Data Sheet
Rev. E | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.
50
40
30
20
10
0
–1.2 –0.8 –0.4 00.4 0.8 1.2
PERCE NTAGE OF UNIT S
OUTPUT OFFSET VOLTAGE (mV)
SAMPLE SIZE = 191
00777-002
Figure 2. Typical Distribution of Output Offset Voltage
50
40
30
20
10
060 80 100 120 140
PERCE NTAGE OF UNIT S
COM M ON-MODE RE JE CTI ON RAT IO ( dB)
SAMPLE SIZE = 383
00777-003
Figure 3. Typical Distribution of Common-Mode Rejection
2.0
1.5
1.0
0.5
00 54321
INPUT OFFSET VOLTAGE (µV)
WARM-UP TIME (Minu tes)
00777-004
Figure 4. Change in Input Offset Voltage vs. Warm-Up Time
1000
100
10
11100k10k1k10010
VOLTAGE NOISE (nV/ Hz)
FRE QUENCY ( Hz )
GAIN = 1
GAIN = 1000
BW LIMIT
GAIN = 10
GAIN = 100, 1000
00777-005
Figure 5. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000)
1000
100
10 1100010010
CURRENT NOIS E ( f A/ Hz)
FRE QUENCY ( Hz )
00777-006
Figure 6. Current Noise Spectral Density vs. Frequency
140
120
100
80
60
40
20
0
0.1 1M100k10k1k100101
CMR (dB)
FRE QUENCY ( Hz )
G = 1000
G = 100
G = 10
G = 1
00777-007
Figure 7. CMR vs. Frequency, RTI, 0 kΩ to 1 kΩ Source Imbalance
Data Sheet AD622
Rev. E | Page 7 of 16
0.1
POSIT I VE PSR (dB)
180
140
160
120
100
80
60
40
20 1M100k10k1k100101FREQ UE NCY ( Hz )
G = 1000
G = 100
G = 10
G = 1
00777-008
Figure 8. Positive PSR vs. Frequency, RTI (G = 1 to 1000)
0.1 1M100k10k1k100101
NEGATIVE PSR (dB)
FRE QUENCY ( Hz )
G = 1000
G = 100
G = 10
G = 1
180
140
160
120
100
80
60
40
20
00777-009
Figure 9. Negative PSR vs. Frequency, RTI (G = 1 to 1000)
100 10M1M100k
10k
0.1
1
10
100
1000
1k
GAIN (V/V)
FRE QUENCY ( Hz )
00777-010
Figure 10. Gain vs. Frequency
10 10k1k100
0
10
30
20
OUTPUT VOLTAGE SWING (V p-p)
LOAD RESISTANCE (Ω)
00777-011
VS = ±15V
G = 10
Figure 11. Output Voltage Swing vs. Load Resistance
02010 155
0
20
15
5
10
SETTLING TIME (µs)
OUTPUT STEP SI Z E (V)
TO 0.1%
00777-012
Figure 12. Settling Time vs. Step Size (G = 1)
1100010010
1
10
1000
100
SETTLING TIME (µs)
GAIN
00777-013
Figure 13. Settling Time to 0.1% vs. Gain, for a 10 V Step
AD622 Data Sheet
Rev. E | Page 8 of 16
100
90
10
0%
Ø
10µV 2V
00777-014
Figure 14. Gain Nonlinearity, G = 1, RL = 10 kΩ (20 µV = 2 ppm)
AD622
2
1
8
34
5
6
7
+VS
–VS
51.1Ω
511Ω
5.62kΩ
G = 1
G = 10G = 100
G = 1000
11kΩ
0.1% 1kΩ
0.1% 100Ω
0.1%
100kΩ
0.1%
INPUT
20V p - p VOUT
10kΩ
0.01% 1kΩ
POT 10kΩ
0.1%
00777-015
Figure 15. Settling Time Test Circuit
Data Sheet AD622
Rev. E | Page 9 of 16
THEORY OF OPERATION
The AD622 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp approach. Absolute
value trimming allows the user to program gain accurately (to
0.5% at G = 1000) with only one resistor. Monolithic construction
and laser wafer trimming allow the tight matching and tracking
of circuit components, thus insuring AD622 performance.
Input Transistor Q1 and Input Transistor Q2 provide a single
differential-pair bipolar input for high precision (see Figure 16).
Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop
maintains constant collector current of the Q1 and Q2 input
devices, thereby impressing the input voltage across External
Gain-Setting Resistor RG. This creates a differential gain from the
inputs to the A1 and A2 outputs given by G = (R1 + R2)/RG + 1.
Unity-Gain Subtractor A3 removes any common-mode signal,
yielding a single-ended output referred to the REF pin potential.
00777-022
V
B
–V
S
A1 A2
A
3
C2
R
G
R1 R2
GAIN
SENSE GAIN
SENSE
10kΩ
10kΩ
I2
I1
10kΩ
REF
10kΩ
+IN
– INR4
400Ω
OUTPUT
C1
Q2
Q1
R3
400Ω
+V
S
+V
S
+V
S
20µA20µA
Figure 16. Simplified Schematic of the AD622
The value of RG also determines the transconductance of the
preamp stage. As RG is reduced for larger gains, the trans-
conductance increases asymptotically to that of the input
transistors. This has the following three important advantages:
• Open-loop gain is boosted for increasing programmed
gain, thus reducing gain-related errors.
• The gain-bandwidth product (determined by C1, C2, and
the preamp transconductance) increases with programmed
gain, thus optimizing frequency response.
• The input voltage noise is reduced to a value of 12 nV/√Hz,
determined mainly by the collector current and base
resistance of the input devices.
The internal gain resistors, R1 and R2, are trimmed to an
absolute value of 25.25 kΩ, allowing the gain to be programmed
accurately with a single external resistor.
MAKE vs. BUY: A TYPICAL APPLICATION ERROR
BUDGET
The AD622 offers cost and performance advantages over
discrete two op amp instrumentation amplifier designs along
with smaller size and fewer components. In a typical application
shown in Figure 17, a gain of 10 is required to receive and
amplify a 0 to 20 mA signal from the AD694 current transmitter.
The current is converted to a voltage in a 50 Ω shunt. In
applications where transmission is over long distances, line
impedance can be significant so that differential voltage
measurement is essential. Where there is no connection
between the ground returns of transmitter and receiver, there
must be a dc path from each input to ground, implemented in
this case using two 1 kΩ resistors. The error budget detailed in
Table 5 shows how to calculate the effect of various error
sources on circuit accuracy.
AD694
0 TO 20mA
TRANSMITTER
R
L2
10Ω
R
L2
10Ω
0 TO 20mA 50Ω
0 TO 20 mA CURRENT LOOP
WITH 50Ω SHUNT IMPEDANCE
R
G
5.62kΩ
1kΩ
1kΩ REF
AD622
AD622 MO NOLITHIC INSTRUMENTAT ION
AMPLIFIER, G = 9.986 HOMEBREW IN-AMP, G = 10
1kΩ
1kΩ
1/2
LT1013 1/2
LT1013
9kΩ* 1kΩ* 1kΩ* 9kΩ*
–
+
V
IN
*0.1% RE S IST OR MATCH, 50pp m/° C TRACKING
00777-016
Figure 17. Make vs. Buy
AD622 Data Sheet
Rev. E | Page 10 of 16
The AD622 provides greater accuracy at lower cost. The higher
cost of the homebrew circuit is dominated in this case by the
matched resistor network. One could also realize a homebrew
design using cheaper discrete resistors that are either trimmed
or hand selected to give high common-mode rejection. This
level of common-mode rejection, however, degrades significantly
over temperature due to the drift mismatch of the discrete
resistors.
Note that for the homebrew circuit, the LT1013 specification for
noise has been multiplied by √2. This is because a two op amp
type instrumentation amplifier has two op amps at its inputs,
both contributing to the overall noise.
Table 5. Make vs. Buy Error Budget
Error Source AD622 Circuit Calculation Homebrew Circuit Calculation
Total Error in ppm
Relative to 1 V FS
AD622 Homebrew
ABSOLUTE ACCURACY at TA = 25°C
Total RTI Offset Voltage, µV 125 µV + 1500 µV/10 800 µV × 2 275 1600
Input Offset Current, nA 2.5 nA × 1 kΩ 15 nA × 1 kΩ 2.5 15
CMR, dB 86 dB
→
50 ppm × 0.5 V (0.1% Match × 0.5 V)/10 V 25 50
Total Absolute Error 302.5 1665
DRIFT TO 85°C
Gain Drift, ppm/°C (50 ppm + 5 ppm) × 60°C (50 ppm)/°C × 60°C 3300 3000
Total RTI Offset Voltage, µV/°C (1 µV/°C + 15 µV/°C /10) × 60°C 9 µV/°C × 2 × 60°C 150 1080
Input Offset Current, pA/°C 2 pA/°C × 1 kΩ × 60°C 155 pA/°C × 1 kΩ × 60°C 0.12 9.3
Total Drift Error 3450.12 4089.3
RESOLUTION
Gain Nonlinearity, ppm of Full Scale 10 ppm 20 ppm 10 20
Typ 0.1 Hz to 10 Hz Voltage Noise, µV p-p
0.6 µV p-p
0.55 µV p-p × √2
0.6
0.778
Total Resolution Error 10.6 20.778
Grand Total Error 3763 5775
Data Sheet AD622
Rev. E | Page 11 of 16
GAIN SELECTION
The AD622 gain is resistor programmed by RG or, more
precisely, by whatever impedance appears between Pin 1 and
Pin 8. The AD622 is designed to offer gains as close as possible
to popular integer values using standard 1% resistors. Table 6
shows required values of RG for various gains. Note that for
G = 1, the RG pins are unconnected (RG = ∞). For any arbitrary
gain, RG can be calculated by using the formula
1
k5.50
−
Ω
=
G
R
G
To minimize gain error, avoid high parasitic resistance in series
with RG. To minimize gain drift, RG should have a low temperature
coefficient less than 10 ppm/°C for the best performance.
Table 6. Required Values of Gain Resistors
Desired
Gain 1% Std Table Value of RG, Ω
Calculated
Gain
2 51.1 k 1.988
5 12.7 k 4.976
10 5.62 k 9.986
20
2.67 k
19.91
33 1.58 k 32.96
40 1.3 k 39.85
50 1.02 k 50.50
65 787 65.17
100 511 99.83
200
255
199.0
500 102 496.1
1000 51.1 989.3
INPUT AND OUTPUT OFFSET VOLTAGE
The low errors of the AD622 are attributable to two sources:
input and output errors. The output error is divided by G when
referred to the input. In practice, the input errors dominate at
high gains and the output errors dominate at low gains. The
total VOS for a given gain is calculated as follows:
Total Error RTI = input error + (output error/G)
Total Error RTO = (input error × G) + output error
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage
and is especially useful when the load does not share a precise
ground with the rest of the system. The reference terminal provides
a direct means of injecting a precise offset to the output, with an
allowable range of 2 V within the supply voltages. Parasitic
resistance should be kept to a minimum for optimum CMR.
INPUT PROTECTION
The AD622 safely withstands an input current of ±60 mA for
several hours at room temperature. This is true for all gains and
power on and off, which is useful if the signal source and amplifier
are powered separately. For longer time periods, the input
current should not exceed 6 mA.
For input voltages beyond the supplies, a protection resistor should
be placed in series with each input to limit the current to 6 mA.
These can be the same resistors as those used in the RFI filter.
High values of resistance can impact the noise and AC CMRR
performance of the system. Low leakage diodes (such as the
BAV199) can be placed at the inputs to reduce the required
protection resistance.
00777-023
AD622
R
REF
R
+SUPPLY
–SUPPLY
V
OUT
+IN
–IN
Figure 18. Diode Protection for Voltages Beyond Supply
AD622 Data Sheet
Rev. E | Page 12 of 16
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
may appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass, RC network placed at the input
of the instrumentation amplifier, as shown in Figure 19. In
addition, this RC input network also provides additional input
overload protection (see the Input Protection section).
R
G
REF
V
OUT
+IN
–IN
AD622
+
0.1µF 10µF
+
0.1µF 10µF
+V
S
–V
S
C
C
1nF
C
D
47nF
C
C
1nF
R
4.02kΩ
R
4.02kΩ
00777-017
Figure 19. RFI Suppression Circuit for AD622 Series In-Amps
The filter limits the input signal bandwidth to the following
cutoff frequencies:
)(22
1
C
D
DIFF CCR
FilterFreq +π
=
C
CM RC
FilterFreq π
=2
1
where CD ≥ 10CC.
Figure 19 shows an example where the differential filter
frequency is approximately 400 Hz, and the common-mode
filter frequency is approximately 40 kHz. With this differential
filter in place and operating at gain of 1000, the typical dc offset
shift over a frequency range of 1 Hz to 20 MHz is less than 1.5 µV
RTI, and the RF signal rejection of the circuit is better than
71 dB. At a gain of 100, the dc offset shift is well below 1 mV
RTI, and RF rejection is greater than 70 dB.
The input resistors should be selected to be high enough to
isolate the sensor from the CC and C D capacitors but low
enough not to influence system noise. Mismatch between
R × CC at the positive input and R × CC at the negative input
degrades the CMRR of the AD622. Therefore, the CC capacitors
should be high precision types such as NPO/COG ceramics.
The tolerance of the CD capacitor is less critical.
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the
input transistors of an amplifier. There must be a direct return
path for these currents; therefore, when amplifying floating
input sources such as transformers or ac-coupled sources, there
must be a dc path from each input to ground as shown in
Figure 20, Figure 21, and Figure 22. Refer to the Designer’s
Guide to Instrumentation Amplifiers (free from Analog Devices,
Inc.) for more information regarding in-amp applications.
AD622
2
1
8
34
5
6
7
+VS
–VS
RGVOUT
LOAD
–IN
+IN REF
TO POWER
SUPPLY
GROUND
00777-018
Figure 20. Ground Returns for Bias Currents with Transformer Coupled Inputs
AD622
2
1
8
34
5
6
7
+V
S
–V
S
R
G
V
OUT
LOAD
–IN
+IN REF
TO POWER
SUPPLY
GROUND
00777-019
Figure 21. Ground Returns for Bias Currents with Thermocouple Inputs
AD622
2
1
8
34
5
6
7
+V
S
–V
S
R
G
V
OUT
LOAD
–IN
+IN REF
TO POWER
SUPPLY
GROUND
100kΩ 100kΩ
00777-020
Figure 22. Ground Returns for Bias Currents with AC-Coupled Inputs
Data Sheet AD622
Rev. E | Page 13 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MS - 001
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OF F I NCH E QUIVALENTS FOR
REF E RE NCE ONLY AND ARE NO T APPROPRIATE FOR USE IN DESIGN.
CORNE R LEADS MAY BE CONF IG URE D AS WHO LE OR HALF L E ADS .
070606-A
0.022 ( 0.56)
0.018 ( 0.46)
0.014 ( 0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 ( 5.33)
MAX
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2.92)
0.070 ( 1.78)
0.060 ( 1.52)
0.045 ( 1.14)
8
14
5
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.100 ( 2.54)
BSC
0.400 ( 10.16)
0.365 ( 9.27)
0.355 ( 9.02)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
0.015 ( 0.38)
GAUGE
PLANE
0.005 ( 0.13)
MIN
Figure 23. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONSARE IN MILLI M E TERS ; INCH DI M E NS IONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REF E RE NCE ONLY AND ARE NO T APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JE DE C S TANDARDS MS - 012- AA
012407-A
0.25 ( 0.0098)
0.17 ( 0.0067)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.50 ( 0.0196)
0.25 ( 0.0099) 45°
8°
0°
1.75 ( 0.0688)
1.35 ( 0.0532)
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 ( 0.1574)
3.80 ( 0.1497)
1.27 ( 0.0500)
BSC
6.20 ( 0.2441)
5.80 ( 0.2284)
0.51 ( 0.0201)
0.31 ( 0.0122)
COPLANARITY
0.10
Figure 24. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
AD622 Data Sheet
Rev. E | Page 14 of 16
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
AD622ANZ −40°C to +85°C 8-Lead PDIP N-8
AD622AR
–40°C to +85°C
8-Lead SOIC_N
R-8
AD622AR-REEL –40°C to +85°C 8-Lead SOIC_N R-8
AD622AR-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8
AD622ARZ –40°C to +85°C 8-Lead SOIC_N R-8
AD622ARZ-RL –40°C to +85°C 8-Lead SOIC_N R-8
AD622ARZ-R7 –40°C to +85°C 8-Lead SOIC_N R-8
1 Z = RoHS Compliant Part.
Data Sheet AD622
Rev. E | Page 15 of 16
NOTES
