MOTOROLA SEMICONDUCTOR a TECHNICAL DATA Wideband Linear Four-Quadrant Multiplier The MC1495/1595 is designed for use where the output is a linear product of two input voltages. Maximum versatility is assured by allowing the user to select the level shift method. Typical applications include: multiply, divide, square root*, mean square, phase detector, frequency doubler, balanced modulator/demoduiator, and electronic gain control. Wide Bandwidth Excellent Linearity: 2% max Error on X input, 4% max Error on Y Input (MC 1495) 1% max Error on X Input, 2% max Error on Y Input (MC 1595) @ Adjustable Scale Factor, K Excellent Temperature Stability @ Wide Input Voltage Range: + 10 V @ +15 V Operation *When used with an operational amplifier. MC1495 MC1595 LINEAR FOUR-QUADRANT MULTIPLIER SILICON MONOLITHIC INTEGRATED CIRCUIT D SUFFIX PLASTIC PACKAGE @B CASE 751A 1 (SO-14) 1 L SUFFIX CERAMIC PACKAGE CASE 632 Figure 1. Multiplier Transfer Characteristic 10 8.0 6.0 AN? 40 N 20 w?* 0 -2.0 -4.0 ~6.0 -8.0 1049 N Vo, OUTPUT VOLTAGE (V} A\,, GAIN (dB) a ~8=.0 -60 -40 -20 0 20 40 Vy, INPUT VOLTAGE (V} 6.0 80 Figure 3. Circuit Schematic 44 Output (KXY) Q5 Q6)71_Q7 08 8 9 X Input Y Input 4 12 npu won wor Figure 2. Transconductance Bandwidth 10 f, FREQUENCY (MHz) 100 1000 ORDERING INFORMATION Ambient Device Temperature Range Package MC1495D SO-14 0 to +70C MC1595D MC1495L Ceramic DIP 55 to +125C MC1595L MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-26MC1495, MC1595 ELECTRICAL CHARACTERISTICS (+V =+32 V ,-V =-15 V, Ta = +25C, Ig = 143 = 1.0 mA, Rx = Ry = 15 kQ, Ri = 11 kQ, unless otherwise noted.) Characteristics Figure | Symbol Min Typ Max Unit Linearity (Output Error in percent of full scale) 5 % Ta = + 25C -10 < Vy < +10 (Vy = +10 V) MC1495 ERX +1.0 +2.0 MC1595 _ +0.5 +1.0 10 < Vy < +10 (Vx = #10 V) MC 1495 ERY +2.0 +4.0 MC1595 _ +1.0 +2.0 Ta = 0 to +70C -10 < Vx < +10 (Vy = +10 V) MC 1495 ERX +15 _ -10< Vy < +10 (Vx = +10 V) ERY _ +3.0 _ Ta =55 to +125C MC1595 10 < Vx < +10 (Vy =+10 V) ErRx _ +0.75 _ 10 < Vy <410 (Vx = +10 V) ERy $1.5 _ Square Mode Error (Accuracy in percent of full scale after 5 Esq % Offset and Scale Factor adjustment) Ta = +25C MC1495 +0.75 _ MC1595 _ 0.5 _ Ta = 0 to +70C MC1495 _- +1.0 _ Ta =55 to +125C MC1595 _ 40.75 _ le F Adj | _ K _ 0.1 _ Scale Factor (Adjustable) ( . RL 13 Rx Ry Input Resistance MC1495 7 Rinx _ 30 _ MQ (f = 20 Hz) MC1595 35 MC1495 RinY 20 MC1595 _ 35 Differential Output Resistance (f = 20 Hz) 8 Ro _ 300 _ kQ Input Bias Current 6 pA MC1495 | _ 2.0 12 Ig +l Iq +1 bx iby = (9412), iby = ila + Ie) MC1595 2.0 8.0 2 2 MC1495 Iby 2.0 12 MC1595 _ 2.0 8.0 Input Offset Current 6 HA {Ig - 14a MC1495 lliox! ~ 0.4 2.0 MC1595 _ 0.2 1.0 114 Ig| MC1495 ilioyl 0.4 2.0 MC 1595 _ 0.2 1.0 Average Temperature Coefficient of Input Offset Current 6 [TCliol nArc (Ta = 0 to + 70C) MC1495 _ 2.5 _ (Ta =55 to +125C MC1595 _ 2.5 Output Offset Current MC1495 6 llool 20 100 LA Iha- lo} MC 1595 10 50 Average Temperature Coefficient of Output Offset Current 6 ITCiool nArC (Ta = 0 to + 70C) MC 1495 _ 20 _ (Ta =55 to + 125C) MC1595 _ 20 _ Frequency Response 9,10 3.0 dB Bandwidth, Ry = 11 kQ BW(3dB) _ 3.0 MHz 3.0 dB Bandwidth, RL = 50 Q (Transconductance Bandwidth) TBW(3dB) _ 80 _ MHz 3 Relative Phase Shift Between Vx and Vy S _ 750 _ kHz 1% Absolute Error Due to Input-Output Phase Shift fo _ 30 _ kHz Common Mode Input Swing MC1495 1 CMV +10.5 +12 _ Vde (Either Input) MC1595 411.5 +13 _ Common Mode Gain MC1495 aml ACM 40 -50 _ dB (Either Input) MC1595 50 60 _ Common Mode Quiescent 12 Vo1 _ 2i _ Vde Output Voltage Voe2 _ 21 _ Differential Output Voltage Swing Capability 9 Vo _ +14 Vok Power Supply Sensitivity 12 St _ 5.0 _ mvV/V s- = 10 _ Power Supply Current 12 \7 _ 6.0 7.0 mA DC Power Dissipation 12 Pp _ 135 170 mw MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-27MC1495, MC1595 MAXIMUM RATINGS (Ta = +25C, unless otherwise noted.) Rating Symbol Value Unit Applied Voltage AV 30 Vde (V2-V4, V14-V1, Vi-Vg, Vi-V12, V1-Va, V1-Vg, V12-V7, Vg-V7, Ve-V7, V4-V7) Differential input Signal Vi2-Vo +(6+143 Rx) Vde V4-Vg +(6+lg Ry) Maximum Bias Current \3 10 mA Higa 10 Power Dissipation (Package Limitation) O Suffix, Plastic Package Pp 862 mw Derate above Ta = +25C 145 mwrc J Suffix, Ceramic Package Pp 750 mw Derate above Ta = +25C 5.0 C/W Operating Temperature Range TA C MC 1495 0 to +70 MC1595 -55 to +125 Storage Temperature Range Tstg -65 to +150 C Figure 4. Linearity (Using Null Technique) OAR AE Ry = 27k Ry =7.5k = 3.0k 10k Vy 10k 10k: Ww 7s 6 bi bi Es : \ = - 4 Vs Vix 1k x + MC1495 + 5 + 9 TT 10k 8 14 - 12 63 67 413 Offset Adjust 13k 12k See Figure 13 Scale Factor + Adjust FE OME NOTE: Adjust Scale Factor Adjust for a null in Ve. This schematic for illustrative purposes only, not specified for test conditions. Figure 5. Linearity (Using X-Y Plotter Technique) Ry = 15k Ry = 15k 32V ren 5h ao dio Ou A , ies 43 1 94k 0.1uF ye | aa ve 5 Ruy = 11k: = 8 MC 1495 rs + XY . o_o Plotter - Piotter Oftset Adjust | Y Ry = 11k Vo yinput | Plotter | XInput (See Figures 13 and 14) 12 14 t 4 1 99 fg tg 12 RB r R43 = 13.7k 5.0k 4 Factor O.tuF Adjust ~15V MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-28MC1495, MC1595 Figure 6. input and Output Current +32V Ry = 15k Ry = 15k , bs 6b bio = \4 9 ip 8 MC1495 7 ig 12 = Ip 3 7 ap nF 1 48 12k = ig = 1.0mA Scale 5.0k Factor Adjust = -15V Figure 8. Output Resistance Ry = 15k Ry = 15k nav }-Ow 0 9 1* e9 2 Ry = 11k MC1495 Figure 10. Bandwidth (Ri = 50 Q) Ry =510 Ry =510 +15V 4 95 69 910 O11 @in = 1.0 V{rms) >of ein MC1495 io == CL <3.0pF 13 K= 40 137k & > : & Scale Factor 5.0k = Adjust 1 if Figure 7. Input Resistance 2 = 1.0 V (rms) Ry = 15k Ry = 15k +32V 20 Hz 1.0M 4 5 6 10 "1, 94k e ~) 10M = 9 2 tk i 4 @ 8 MC1495 e 12 14 11k ~ 10M 3 7 13 10M 312k 13.75k + = = O4pF 5.0K | - a, O.iuF Rinx = Riny=R |g, -? | = Figure 9. Bandwidth (Ri. = 11k) Ry =15k Ry = 15k +32V 4 5 6 10 O11 ein = 1.0 V(rms) Oo 1 9.ik ein 9 2 11k tO L 6-6 MC1495 8 14 11k + OV 12 13 = = 3 7 ar 0.1pF 12k R13 I 13.7k Te, + 0.1pF a Scale pe o5.0k | Toh | == CL <30pF Factor = Adjust =f - -15V Figure 11. Common Mode Gain and Common Mode Input Swing 15k 18k +32V (= 262) 4 25 8) 910 Ott, + 9 _ 6 50 8 - MC1495 -O = 4 3 50 CMVy 12k94 (f= 20 Hz) '1.0mA 5 Ok Vo O.4pF { 1.0mA 1 = 20 log O- Aco = 20log CMVy Vo or 20 log CMV MOTOROLA LINEAR/INTERFACE ICs DEVICE DATAMC1495, MC1595 Figure 12. Power Supply Sensitivity +32V +32V 6.2V J 13 13,7k O.1MF Vo2 Voi 7 O.1MF -V gy - Wor -Yoal Figure 13. Offset Adjust Circuit To Pin & Y Offset Adjust Pot #1 o> 15V| 32V| [| tox 224) or Equivalent -15V AV+ g.- Wor - Yoo)! TS AVE Figure 14. Offset Adjust Circuit (Alternate) yt [, 5.1V lq. Lm ToPin8 = Pot #1 Pot #2 To Pin 12 Y Offset 10k +* X Offset Adjust Adjust rL 32 5.AV | Lp [2.0K[ 5.14} a -15V 10k 2.0k yt | R Pot #2 To Pin 12 10keae- X Offset Adjust 2.0k i -15V MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-30Erx Epy LINEARITY (%) ERROR, PERCENT OF FULL SCALE (%) 0.8 0.6 0.4 0.2 MC1495, MC1595 Figure 15. Linearity versus Temperature Figure 16. Scale Factor versus Temperature 0.110 oc (0.105 N e 2 K Adjusted to 0.100 at 25C 4 0.100 % PL 0.095 rr -55 -25 0 25 50 75 ~~ 100 125 -55 -25 0 25 50 75 100125 Ta, AMBIENT TEMPERATURE (C) Ta , AMBIENT TEMPERATURE (C) Figure 17. Error Contributed by Figure 18. Error Contributed by Input Differential Amplifier input Differential Amplifier Vy = Vy = + 10 V Max Vy = Vy =+5.0 V Max Ig = lhg = 1.0 mAde z 13 = 143 = 1.0 mAdc 8 \ a => nw wm o b = Ww oO oc Ww a foal ] 2 ac Ww 0 10 12 14 16 18 20 4.0 6.0 8.0 10 12 14 Ry of Ry (kQ2) Ry or Ry (k 9) Figure 19. Maximum Allowable input Voltage versus Voltage at Pin 1 or Pin 7 = = = 2 = a = Minimum -" = > 5 -~ = Recommended 2.0 40 6.0 8.0 10 M4] or [Vzl (VY) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-31MC1495, MC1595 OPERATION AND APPLICATIONS INFORMATION THEORY OF OPERATION The MC1495 is a monolithic, four-quadrant multiplier which operates on the principle of variable transconductance. A detailed theory of operation is covered in Application Note AN489, Analysis and Basic Operation of the MC1595. The result of this analysis is that the differential output current of the multiplier is given by: 2VxVy RxRy!3 where, lA and Ig are the currents into Pins 14 and 2, respectively, and Vx and Vy are the X and Y input voitages at the multiplier input terminals. la-lp=Al= DESIGN CONSIDERATIONS General The MC 1495 permits the designer to tailor the multiplier to a specific application by proper selection of external components. External components may be selected to optimize a given parameter (e.g. bandwidth) which may in turn restrict another parameter (e.g. maximum output voltage swing). Each important parameter is discussed in detail in the following paragraphs. Linearity, Output Error, Ernx or Eny Linearity error is defined as the maximum deviation of output voltage from a straight line transfer function. It is expressed as error in percent of full scale (see figure below). For example, if the maximum deviation, VE(max), is +100 mV and the full scale output is 10 V, then the percentage error is: ER= Ve(max) 100 = 100 10-3 e 100 = +1.0%. Vo(max) 10 Linearity error may be measured by either of the following methods: 1. Using an X-Y plotter with the circuit shown in Figure 5, obtain plots for X and Y similar to the one shown above. 2. Use the circuit of Figure 4. This method nulls the level shifted output of the multiplier with the original input. The peak output of the null operational amplifier will be equal to the error voltage, VE (max)- One source of linearity error can arise from large signal nonlinearity in the X and Y input differential amplifiers. To avoid introducing error from this source, the emitter degeneration resistors Rx and Ry must be chosen large enough so that nonlinear base-emitter voltage variation can be ignored. Figures 17 and 18 show the error expected from this source as a function of the values of Rx and Ry with an operating current of 1.0 mA in each side of the differential amplifiers (i.e. |g =113 = 1.0 mA). 3 dB Bandwidth and Phase Shift Bandwidth is primarily determined by the load resistors and the stray multiplier output capacitance and/or the operational amplifier used to level shift the output. If wideband operation is desired, low value load resistors and/or a wideband operational amplifier should be used. Stray output capac- itance will depend to a large extent on circuit layout. Phase shift in the multiplier circuit results from two sources: phase shift common to both X and Y channels (due to the load resistor-output capacitance pole mentioned above) and relative phase shift between X and Y channels (due to differences in transadmittance in the X and Y channels). If the input to output phase shift is only 0.6, the output product of two sine waves will exhibit a vector error of 1%. A 3 relative phase shift between Vx and Vy results in a vector error of 5%. Maximum Input Voltage Vx(max), VY(max) input voltages must be such that: Vx(max) <!13 Ry Vy(max) <I3g Ry Exceeding this value will drive one side of the input amplifier to cutoff and cause nonlinear operation. Current 1g and 113 are chosen at a convenient value (observing power dissipation limitation) between 0.5 mA and 2.0 mA, approximately 1.0 mA. Then Rx and Ry can be determined by considering the input signal handling requirements. For Vx(max) = VY(max) = 10 V; JO0V_ Rx = RY > iG mA 10 kQ. . 2Vx VY The equation la Ig = Ax Ry 13 is derived from Ia Ip = ___.__2Vx VY (Rx + 2K ) (RY + 2KT 1, ql13 ql3 with the assumption Rx >> 2KT and Ry >> 2kT . qli3 ql3 At Ta = +25C and 143 = 13 = 1.0 mA, 2kT _ 2kT p59 qi3 qig Therefore, with Rx = Ry = 10 kQ the above assumption is valid. Reference to Figure 19 will indicate limitations of VX(max)orVY(max)duetoV 4 andV7.Exceedingtheselimitswill cause saturation or cutoff of the input transistors. See Step 4 of General Design Procedure for further details. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-32MC1495, MC1595 Maximum Output Voltage Swing The maximum output voltage swing is dependent upon the factors mentioned below and upon the particular circuit being considered. For Figure 20 the maximum output swing is dependent upon V+ for positive swing and upon the voltage at Pin 1 for negative swing. The potential at Pin 1 determines the quiescent level for transistors Q5, Qg, Q7 and Qg. This potential should be related so that negative swing at Pins 2 or 14 does not saturate those transistors. See General Design Procedure for further information regarding selection of these potentials. Figure 20. Basic Multiplier Ifan operational amplifier is used for level shift, as shown in Figure 21, the output swing (of the multiplier) is greatly reduced. See Section 3 for further details. GENERAL DESIGN PROCEDURE Selection of component values is best demonstrated by the following example. Assume resistive dividers are used at the X and Y-inputs to limit the maximum multiplier input to + 5.0 V [Vx = Vy(max)] for a + 10 V input [Vx = Vy(max)] (see Figure 21). If an overall scale factor of 1/10 is desired, Vx Vy7_ (2Vx) (2Vy)_ then, Vo = 10. 7 10 Therefore, K = 4/10 for the multiplier (excluding the divider network). = 4/10 Vx Vy vt . : Step 1. The fist step is to select current !3 and current 143. Ry R R R There are no restrictions on the selection of either of these wv 2 wh t currents except the power dissipation of the device. Ig and l13 g Or ty 75 Psyt 5 AL will normally be 1.0 mA or 2.0 mA. Further, Ig does not have to eo-} + + +@ be equal to !13, and there is normally no need to make them 12 i i e 5]. 14 Vo different. For this example, let a MC1495 -}-o_4+* Ig =143=1.0 mA. 8 oe o - Vo = K Vy Vy 3 13 7 aR fh, K= L Ry Ry Ig Rg Rig = = V- Figure 21. Multiplier with Operational Amplifier Level Shift -t8v - 15V Rx Ry 10k 10k tok 4 106 11 5 06 Vy + v 1K $Y t MC1495 10k 9 Vy + Vj 10k x3 ' 8 Ig. R ns po Output * | a Adjust Y Offset X Offset ~ fa Adjust Py Adjust ~10V < Vy < H10V Adjust = we -10V < Vy < H10V 2.0k y= 1 20k +H15V @w y ~15V 10 sw Ww 5 MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-33MC1495, MC1595 To set currents |3 and 143 to the desired value, it is only necessary to connect a resistor between Pin 13 and ground, and between Pin 3 and ground. From the schematic shown in Figure 3, it can be seen that the resistor values necessary are given by: \V-|-0.7 V R13 + 500 Q = ___ 8 hg V-|-0.7 V R3 + 500 2 San eae Let V- = -15 V, then R13 + 500 =!43V or R13 = 13.8 kQ 1.0mA Let R13 = 12 kQ. Similarly, Rg = 13.8 kQ, let Rg = 15 kQ However, for applications which require an accurate scale factor, the adjustment of Rg and consequently, 13, offers a convenient method of making a final trim of the scale factor. For this reason, as shown in Figure 21, resistor R3 is shown as a fixed resistor in series with a potentiometer. For applications not requiring an exact scale factor (balanced modulator, frequency doubler, AGC amplifier, etc.) Pins 3 and 13 can be connected together and a single resistor from Pin 3 to ground can be used. In this case, the single resistor would have a value of 1/2 the above calculated value for R13. Step 2. The next step is to select Rx and Ry. To insure that the input transistors will always be active, the following conditions should be met: Vy Vx A<113 <13 , Ry Rx A good rule of thumb is to make IgRy 2 1.5 Vy(max) and 143RX21.5Vx(max). Thelarger the IgRy and|13Rx productin relation to Vy and Vy respectively, the more accurate the multiplier will be (see Figures 17 and 18). Let Rx = Ry = 10 kQ, then IgRy =10V l#3Rx =10V since VX(max) = Vy(max) = 5.0 V, the value of Rx=Ry=10 kQ is Sufficient. Step 3. Now that Rx, Ry and I3 have been chosen, Ri_ can be determined: 2RE 4 Ke . (2) (RL) 4 Rx Ry lg 10 OF (10 k) (10 k) (1.0mA) 10 Thus Ry = 20 kQ. Step 4. To determine what power supply voltage is necessary for this application, attention must be given to the circuit schematic shown in Figure 3. From the circuit schematic it can be seen that in order to maintain transistors Qy,Q2, Q3 and Qq inanactive region when the maximum input voltages are applied (Vx = Vy = 10 V or Vx = 5.0 V, Vy = 5.0 V), their respective collector voltage should be at least a few tenths of a volt higher than the maximum input voltage. It should also be noticed that the collector voltage of transistors Q3 and Qg is at a potential which is two diode-drops below the voltage at Pin 1. Thus, the voltage at Pin 1 should be about 2.0 V higher than the maximum input voitage. Therefore, to handle +5.0 V at the inputs, the voltage at Pin 1 must be at least +7.0 V. Let V1 = 9.0 Vdc. Since the current flowing into Pin 1 is always equal to 2l3, the voitage at Pin 1 can be set by placing a resistor (R71) from Pin 1 to the positive supply: _ VvR-V4 21g Let V+ =15V, then Ry = 12V-9.0V (2) (1.0 mA) Ry =3.0kQ. Note that the voltage at the base of transistors Q5, Qg, Q7 and Qg is one diode-drop below the voltage at Pin 1. Thus, in order that these transistors stay active, the voltage at Pins 2 and 14 should be approximately halfway between the voltage at Pin 1 and the positive supply voltage. For this example, the voltage at Pins 2 and 14 should be approximately 11 V. Step 5. For DC applications, such as the multiply, divide and square-root functions, itis usually desirable to convert the differential output to a single-ended output voltage referenced to ground. The circuit shown in Figure 22 performs this function. Itcan be shown that the output voltage of this circuit is given by: Vo = (l2-114) RL . 2lx ly 2VxVy And since la Ip = lo -l44 = Ig. ~ IgRxRy 2RL Vx Vy then Vo = GR PX where, Vx Vy is the voltage at the input to the voltage dividers. Figure 22. Level Shift Circuit yt > co Ro lp Ve eV, V44 9 id uF RL MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-34MC1495, MC1595 The choice of an operational amplifier for this application should have low bias currents, low offset current, and a high common mode input voltage range as well as a high common mode rejection ratio. The MC1456, and MC1741C operational amplifiers meet these requirements. Referring to Figure 21, the level shift components will be determined. When Vx = Vy = 0, the currents lo and I} 4 will be equal to 13. In Step 3, RL was found to be 20 kQ and in Step 4, V2 and V14 were found to be approximately 11 V. From this information Ro can be found easily from the following equation (neglecting the operational amplifiers bias current): V2 V+ -Vo ~f J lyga 2 RLt 13 Ro : 11V 16bV-11V And for this example, 30 kat 1.0 mA= Ro Solving for Ra: Ro = 2.6 kQ, thus, select Ro = 3.0 kQ For Ro = 3.0 kQ, the voltage at Pins 2 and 14 is calculated to be: Vo =Vi4= 10.4 V. The linearity of this circuit (Figure 21) is likely to be as good or better than the circuit of Figure 5. Further improvements are possible as shown in Figure 23 where Ry has been increased substantially to improve the Y linearity, and Rx decreased somewhat so as not to materially affect the X linearity. This avoids increasing RL significantly in order to maintain a K of 0.1. The versatility of the MC 1495 aliows the user to to optimize its performance for various input and output signal levels. OFFSET AND SCALE FACTOR ADJUSTMENT Offset Voltages Within the monolithic multiplier (Figure 3) transistor base- emitter junctions are typically matched within 1.0 mV and resistors are typically matched within 2%. Even with this careful matching, an output error can occur. This output error is comprised of X-input offset voltage, Y-input offset voltage, and output offset voltage. These errors can be adjusted to zero with the techniques shown in Figure 21. Offset terms can be shown analytically by the transfer function: Vo = KIVx + Viox + Vx(off)] [Vy + Vioy t Vy(offylt Voo (1) Where: K scale factor Vy = x input voltage Vy = y input voltage Viox = x input offset voltage Vioy = y" input offset voltage Vx(off) = x input offset adjust voltage Vy(off) = y input offset adjust voltage Yoo = output offset voltage. Figure 23. Multiplier with Improved Linearity ~15V - 1V +15V 7.5k 27k 1% = 4: 109.119 95 06 97 vy + 10k -Vy Vy H10V I MC1495 re oe 10k 9 Vyr + 10k 3 13 8 + 13k 12k 5.0k 10k Output Scale = Offset Factor Adjust Adjust = Y Offset X Offset Adjust Adjust 20k 15k 15k +15V. Lp To -15v 20k 2.0k pm MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-35MC1495, MC1595 X, and Output Offset Voltages Output Vv Output Yo Offset OY Otte! | W t V. \_| x N / / \ A X Offset Y Offset aa For most DC applications, all three offset adjust potentiometers (P1, P2, P4) will be necessary. One or more offset adjust potentiometers can be eliminated for AC applications (see Figures 28, 29, 30, 31). If well regulated supply voltages are available, the offset adjust circuit of Figure 13 is recommended. Otherwise, the circuit of Figure 14 will greatly reduce the sensitivity to power supply changes. Scale Factor The scale factor K is set by P3 (Figure 21). P3 varies |3 which inversely controls the scale factor K. It should be noted that current |3 is one-half the current through R1. Rj sets the bias level for Q5, Qg, Q7, and Qg (see Figure 3). Therefore, to be sure that these devices remain active under all conditions of input and output swing, care should be exercised in adjusting P3 over wide voltage ranges (see General Design Procedure). Adjustment Procedures The following adjustment procedure should be used to null the offsets and set the scale factor for the multiply mode of operation, (see Figure 21). 1. X-Input Offset (a) Connect oscillator (1.0 kHz, 5.0 Vp-p sinewave) to the Y-input (Pin 4). (b) Connect X-input (Pin 9) to ground. (c) Adjust X offset potentiometer (P2) for an AC null at the output. 2. Y-Input Offset (a) Connect oscillator (1.0 kHz, 5.0 Vp-p sinewave) to the X-input (Pin 9). (b) Connect Y-input (Pin 4) to ground. (c) Adjust Y offset potentiometer (P41) for an AC null at the output. 3. Output Offset (a) Connect both X and Y-inputs to ground. (b) Adjust output offset potentiometer (P4) until the output voltage (Vo) is 0 Vdc. 4. Scale Factor (a) Apply +10 Vdc to both the X and Y-inputs. (b) Adjust P3 to achieve + 10 V at the output. 5. Repeat steps 1 through 4 as necessary. The ability to accurately adjust the MC1495 depends upon the characteristics of potentiometers P 1 through Py. Multi-turn, infinite resolution potentiometers with low temperature coefficients are recommended. DC APPLICATIONS Muitiply The circuit shown in Figure 21 may be used to multiply signals from DC to 100 kHz. Input levels to the actual multiplier are 5.0 V (max). With resistive voltage dividers the maximum could be very large however, for this application two-to-one dividers have been used so that the maximum input level is 10 V. The maximum output level has also been designed for 10 V (max). Squaring Circuit If the two inputs are tied together, the resultant function is squaring; thatis Vo = KV2 where Kis the scale factor. Note that all error terms can be eliminated with only three adjustment potentiometers, thus eliminating one of the input offset adjustments. Procedures for nulling with adjustments are given as follows: A. AC Procedure: 1. Connect oscillator (1.0 KHz, 15 Vp-p) to input. 2. Monitor output at 2.0 kHz with tuned voltmeter and adjust P3 for desired gain. (Be sure to peak response of the voltmeter.) 3. Tune voltmeter to 1.0 kHz and adjust Pj fora minimum output voltage. 4. Ground input and adjust P4 (output offset) for 0 Vdc output. 5. Repeat steps 1 through 4 as necessary. B. DC Procedure: 1. Set Vx = Vy =0 V and adjust P4 (output offset potentiometer) such that Vo = 0 Vde 2. Set Vx = Vy = 1.0 V and adjust Pj (Y-input offset potentiometer) such that the output voltage is + 0.100 V. 3. Set Vx = Vy = 10 Vde and adjust P3 such that the output voltage is + 10 V. 4. Set Vx = Vy =-10 Vdc. Repeat steps 1 through 3 as necessary. Figure 24. Basic Divide Circuit KV Vy oe Vy MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-36MC1495, MC1595 Divide Circuit Consider the circuit shown in Figure 24 in which the multiplier is placed in the feedback path of an operational amplifier. For this configuration, the operational amplifier will maintain a virtual ground at the inverting (-) input. Assuming that the bias current of the operational amplifier is negligible, then 14 = lg and, KVxVy _ -V2 ' Ris RR (1) : -R1 Vz Solving for Vy, Vy = - olving for Vy, Vy RK VX (2) -VZ ifRisR2, Vy =* 3 Y= kvy (3) -VZ #Ri=KR2, Vy=4 (4) Hence, the output voltage is the ratio of Vz to Vx and provides a divide function. This analysis is, of course, the ideal condition. If the multiplier error is taken into account, the output voltage is found to be: a {et Nz AE Y="1R2K] Vx* KVx (5) where AE is the error voltage at the output of the multiplier. From this equation, it is seen that divide accuracy is strongly dependent upon the accuracy at which the multiplier can be set, particularly at small values of Vy. For example, assume that R1 = R2, and K = 1/10. For these conditions the output of the divide circuit is given by: -10Vz 10A4E Ve Vx * Vx (6) From Equation 6, it is seen that only when Vx = 10 Vis the error voltage of the divide circuit as low as the error of the multiply circuit. For example, when Vx is smail, (0.1 V) the error voltage of the divide circuit can be expected to be a hundred times the error of the basic multiplier circuit. In terms of percentage error, percentage error = "F x 100% actual or from Equation (5), AE PEp = Re = ile (7) lw x Vx From Equation 7, the percentage error is inversely related to voltage V7 (i.e., for increasing values of Vz, the percentage error decreases). A circuit that performs the divide function is shown in Figure 25. Two things should be emphasized concerning Figure 25. 1. The input voltage (Vx) must be greater than zero and must be positive. This insures that the current out of Pin 2 of the multiplier will always be in a direction compatible with the polarity of Vz. 2. Pin 2 and 14 of the multiplier have been interchanged in respect to the operational amplifiers input terminals. in this instance, Figure 25 differs from the circuit connection shown in Figure 21; necessitated to insure negative feedback around the loop. A suggested adjustment procedure for the divide circuit. 1. Set Vz = 0 V and adjust the output offset potentiometer (Pq) until the output voltage (Vo) remains at some (not necessarily zero) constant value as Vy is varied between +1.0 V and +10 V. 2. Keep Vz at 0 V, set Vx at +10 V and adjust the Y input offset potentiometer (Pj) until Vo = 0 V. 3. Let Vx = V7 and adjust the X-input offset potentiometer (P2) until the output voltage remains at some (not necessarily 10 V) constant value as V7 = Vx is varied between +1.0 and +10 V. 4. Keep Vx = V7 and adjust the scale factor potentiometer (P3) until the average value of Vois10 V as V7=Vy-is varied between +1.0 V and +10 V. 5. Repeat steps 1 through 4 as necessary to achieve optimum performance. Figure 25. Divide Circuit ~18V ~ 15V @ +15V Rx Ry 10k ak aah 3.9k 109 11 5 607 $1 4m 4 10k 1 M1495 ** Vo -10Vz 10k -_* vy g + + L 8 Vo = Vy 10k 3 13 8 12 = 13k @ V7 12k 5.0k P. To Offset . Output scale $9) = Adjust 50k Offset O<Vyr<H10V hast = (See Figure 13) [Adjust WOVEVZ<+10V MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-37MC1495, MC1595 Figure 26. Basic Square Root Circuit KVo?2 + Ot cra9s * Vo KV? =-V2 or Wz vos Ory K Square Root Aspecial case of the divide circuit in which the two inputs to the multiplier are connected together is the square root function as indicated in Figure 26. This circuit may suffer from latch-up problems similar to those of the divide circuit. Note that only one polarity of input is allowed and diode clamping (see Figure 27) protects against accidental latch-up. This circuit also may be adjusted in the closed-loop mode as follows: 1. Set Vz to -0.01 V and adjust P4 (output offset) for Vo = +0.316 V, being careful to approach the output from the positive side to preclude the effect of the output diode clamping. 2. Set Vz to -0.9 V and adjust Po (X adjust) for Vo = +3.0 V. 3. Set Vz to -10 V and adjust P3 (scale factor adjust) for VQ = +10 V. 4. Steps 1 through 3 may be repeated as necessary to achieve desired accuracy. AC APPLICATIONS The applications that follow demonstrate the versatility of the monolithic multiplier. If a potted multiplier is used for these cases, the results generally would not be as good because the potted units have circuits that, although they optimize DC multiplication operation, can hinder AC applications. Frequency doubling often is done with a diode where the fundamental plus a series of harmonics are generated. However, extensive filtering is required to obtain the desired harmonic, and the second harmonic obtained under this technique usually is small in magnitude and requires amplification. When a multiplier is used to double frequency the second harmonic is obtained directly, except for a DC term, which can be removed with AC coupling. o = KE2 cos2 ant eo = Kee (1 + cos 2t). A potted multiplier can be used to obtain the double frequency component, but frequency would be limited by its internal level-shift amplififer. {n the monolithic units, the amplifier is omitted. In atypical doubler circuit, conventional + 15 V supplies are used. An input dynamic range of 5.0 V peak-to-peak is allowed. The circuit generates wave-forms that are double frequency; less than 1% distortion is encountered without filtering. The configuration has been successfully used in excess of 200 kHz; reducing the scale factor by decreasing the load resistors can further expand the bandwidth. Figure 29 represents an application for the monolithic multiplier as a balanced modulator. Here, the audio input signal is 1.6 kHz and the carrier is 40 kHz. Figure 27. Square Root Circuit ~ 15V - 15V 4 @ +15V Rx Ry 10k 10k 10k 4 10> 119 95 06 97 + oe V MC1495 0 _ 9 Vo= V10\z| + + 10k 343 8 ep L 13k ok + 1k SK V7 5.0k AL P3 To Offset 5.0k Output Scale = Adjust Offset -10<V2<40V Factor _[_ (See Figure 13) Adjust Adjust = = MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-38MC1495, MC1595 Figure 28. Frequency Doubler The defining equation for balanced modulation is ay rx Yoo 15V K(Emcos mt) (Ec cos wet) = ea KEc Em [ COS (Wg + Wm)t + COS (We Wm) t] sb 6b dio bn 4 ee where ac is the carrier frequency, @m is the modulator E cos wt o frequency and K is the multiplier gain constant. {<50Vp9) _ oT Mci495 AC coupling at the output eliminates the need for level Offset. Y 8 Ry translation or an operational amplifier; a higher operating Adjust 2 14 3.3K frequency results. A problem common to communications is to extract the { 30 13 7 im intelligence from single-sideband received signal. The ssb ~ Select signal is of the form: ak 1.0K eo= 5 cos 2 at @sgb = A COS (We + Om) t T and if multiplied by the appropriate carrier waveform, cos wet, - -18V &ssbcarrier -K [cos (20 + tm)t + COs (we) tJ. When two equal cosine waves are applied to X and Y. the result If the frequency of the band-limited carrier signal (w) is is a wave shape of twice the input frequency. For this example . . : : the input was a 10 kHz signal, output was 20 kHz. ascertained in advance, the designer can insert a low pass filter and obtain the (AK/2) (cosmct) term with ease. He/she also can use an operational amplifier for a combination level shift-active filter, as an external component. But in potted multipliers, even if the frequency range can be covered, the Figure 29. Balanced Modulator operational amplifier is inside and not accessible, so the user must accept the jevel shifting provided, and still add a low (A) pass filter. Ry Rx +15V Amplitude Modulation 82k 8.2k The multiplier performs amplitude modulation, similar to balanced modulation, when a DC term is added to the modulating signal with the Y-offset adjust potentiometer (see Figure 30). Here, the identity is: 4 ey = Ecos a pteO-] 9 ex = Ecos a,teo- 8 MC1495 oftset Y- F Em(1 +m cos wmt) Ec cos wet = KEmEccos wet + Adjust y 12 *_ KEmEcm 30 13 7 1 a [ COS(@ + Wm)t + COS (We Mm) t] *Select . o where m indicates the degrees of modulation. Since m is 6.8k mT adjustable, via potentiometer Py, 100% modulation is = possible. Without extensive tweaking, 96% modulation may = be obtained where wc and wm are the same as in the balanced modulator example. Linear Gain Control To obtain linear gain control, the designer can feed to one of the two MC1495 inputs a signal that will vary the units gain. The following example demonstrates the feasibility of this application. Suppose a 200 kHz sinewave, 1.0 V peak-to-peak, is the signal to which a gain control will be added. The dynamic range of the control voltage Vc is 0 V to +1.0 V. These must be ascertained and the proper values of Rx and Ry can be selected for optimum performance. For the 200 kHz operating frequency, load resistors of 100 Q were chosen to broaden the operating bandwidth of the multiplier, but gain was sacrificed. It may be made up with an amplifier operating at the appropriate frequency (see Figure 31). MOTOROLA LINEARANTERFACE ICs DEVICE DATA 11-39MC1495, MC1595 Figure 30. Amplitude Modulation Ry Rx 8.2k 8.2k sb ob So bn Voc = +15V 4 ey = Ecos apt eO-7 9 ey = Ecos Opt eo- y 8 MC1495 % Modulation Adjust. #0 x 12 14 Offset Adjust @O- 3 13 7 T ct ey, ey < 5.0 Vp-p *Select : 0 68k> 1.0uF T -15V Riu 3.3k The signal is applied to the units Y-input. Since the total input range is limited to 1.0 Vp-p, a 2.0 V swing, a current source of 2.0 mA and an Ry value of 1.0 kQ is chosen. This takes best advantage of the dynamic range and insures linear operation in the Y-channel. Since the X-input varies between 0 and +1.0 V, the current source selected was 1.0 mA, and the Rx value chosen was 2.0kQ. This also insures linear operation over the X-input dynamic range. Choosing RL = 100 assures wide bandwidth operation. Hence, the scale factor for this configuration is: RL ~ Rx Ry Ig 100 _ (2 k) (1 k) (2 10+3) v4 K ai yt = 70 V The 2 in the numerator of the equation is missing in this scale factor expression because the output is single-ended and AC coupled. Figure 31. Linear Gain Control +12V 2.0k 1.0k q 105 118 Io bs Y 1 15k Vin + Lo Le 51 Voth x MC1495 | 2 100 | Cc + 1 9 = O.1NF k 40 Offset 7 YI. 100 Adjust 8 X 2 = 3 13 2.0mAy 3.0k 11k Ok 5.0 Ps 1287 Vin= 1.0Vp-p 200 kHz 1.0 f- a O75 F = S 0.5 0.25 F Amplifier Vv Ay = 40 0 0 po. i 1 1 L 0 0.2 #04 06 08 10 12 Vaec ) NOTE: Linear gain control of a 1.0 Vp.p signal is performed with a 0 V to 1.0 V control voltage. If Vc is 0.5 V the output will be 0.5 Vp-p. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 11-40