August 1998
NDT3055L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
Absolute Maximum Ratings TA = 25oC unless otherwise noted
Symbol Parameter NDT3055L Units
VDSS Drain-Source Voltage 60 V
VGSS Gate-Source Voltage - Continuous ±20 V
IDMaximum Drain Current - Continuous (Note 1a) 4A
- Pulsed 25
PDMaximum Power Dissipation (Note 1a)3W
(Note 1b) 1.3
(Note 1c)1.1
TJ,TSTG Operating and Storage Temperature Range -65 to 150 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
NDT3055L Rev.A1
4 A, 60 V. RDS(ON) = 0.100 @ VGS = 10 V,
RDS(ON) = 0.120 @ VGS = 4.5 V.
Low drive requirements allowing operation directly from logic
drivers. VGS(TH) < 2V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
SOIC-16
SuperSOTTM-3 SuperSOTTM-8 SO-8 SOT-223
SuperSOTTM-6
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance and provide superior
switching performance, and withstand high energy pulse
in the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such as
DC motor control and DC/DC conversion where fast
switching, low in-line power loss, and resistance to
transients are needed.
D
DS
G
D
S
G
G
D
S
D
SOT-223 G
D
S
SOT-223*
(J23Z)
© 1998 Fairchild Semiconductor Corporation
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V
BVDSS/TJBreakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 o C55 mV/o C
IDSS Zero Gate Voltage Drain Current VDS = 60 V, VGS = 0 V 1µA
TJ =125°C 50 µA
IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS = 0 V -100 nA
ON CHARACTERISTICS (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 11.6 2V
VGS(th)/TJGate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC-4 mV /oC
RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 4 A0.07 0.1
TJ =125°C 0.125 0.18
VGS = 4.5 V, ID = 3.7 A0.103 0.12
ID(ON) On-State Drain Current VGS = 5 , VDS = 10 V 10 A
gFS Forward Transconductance VDS = 5 V, ID = 4 A 7S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = 25, VGS = 0 V,
f = 1.0 MHz 345 pF
Coss Output Capacitance 110 pF
Crss Reverse Transfer Capacitance 30 pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on)Turn - On Delay Time VDD = 25, ID = 1 A,
VGS = 10 V, RGEN = 6 5 20 ns
trTurn - On Rise Time 7.5 20 ns
tD(off) Turn - Off Delay Time 20 50 ns
tfTurn - Off Fall Time 7 20 ns
QgTotal Gate Charge VDS = 40 V, ID = 4 A,
VGS = 10 V 13 20 nC
Qgs Gate-Source Charge 1.7 nC
Qgd Gate-Drain Charge 3.2 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
ISMaximum Continuous Drain-Source Diode Forward Current 2.5 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.5 A (Note 2)0.8 1.2 V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is
guaranteed by design while RθCA is determined by the user's board design.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
NDT3055L Rev.A1
a. 42oC/W when mounted on a 1 in2 pad of
2oz Cu. b. 95oC/W when mounted on a 0.066 in2
pad of 2oz Cu. c. 110oC/W when mounted on a 0.00123
in2 pad of 2oz Cu.
NDT3055L Rev.A1
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
Figure 3. On-Resistance Variation
with Temperature.
Figure 5. Transfer Characteristics.
Figure 4. On-Resistance Variation with
Gate-to- Source Voltage.
012345
0
5
10
15
20
25
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
V =10V
GS
3.5V
5.0V
4.5V
4.0V
DS
D
6.0V
3.0V
0 5 10 15 20 25
0.8
1
1.2
1.4
1.6
1.8
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 4.0V
GS
10V
4.5V
D
6.0V
8.0V
5.0V
R , NORMALIZED
DS(ON)
Figure 6. Body Diode Forward Voltage
Variation with Current and
Temperature.
246810
0
0.04
0.08
0.12
0.16
0.2
0.24
0.28
V , GATE TO SOURCE VOLTAGE (V)
GS
R , ON-RESISTANCE (OHM)
DS(ON)
25°C
I = 2A
D
T = 125°C
A
11.5 22.5 33.5 44.5 5
0
2
4
6
8
10
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = 5V
DS
GS
D
T = -55°C
J125°C
25°C
00.2 0.4 0.6 0.8 11.2 1.4
0.0001
0.001
0.01
0.1
1
10
30
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125°C
A
25°C
-55°C
V = 0V
GS
SD
S
-50 -25 025 50 75 100 125 150
0.6
0.8
1
1.2
1.4
1.6
1.8
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
V = 10 V
GS
I = 4.0 A
D
R , NORMALIZED
DS(ON)
NDT3055L Rev.A1
Figure 10. Single Pulse Maximum Power
Dissipation.
Figure 8. Capacitance Characteristics.
Figure 7. Gate Charge Characteristics.
Figure 9. Maximum Safe Operating Area.
Typical Electrical Characteristics (continued)
0.0001 0.001 0.01 0.1 110 100 300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t / t
1 2
R (t) = r(t) * R
R = 110 °C/W
T - T = P * R (t)
A
J
P(pk)
t
1 t
2
θJA
θJA
θJA
θJA
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1c.
Transient thermal response will change depending on the circuit board design.
0.1 0.3 1 4 10 30 60
10
20
50
100
200
500
1000
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0V
GS
C
oss
C
rss
0246810 12 14
0
2
4
6
8
10
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 4A
DV = 10V
DS 30V
40V
0.1 0.2 0.5 1 2 5 10 30 60 100
0.01
0.03
0.1
0.3
1
3
10
50
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
1s
100ms
10s
10ms
RDS(ON) LIMIT
1ms
DC
V = 10V
SINGLE PULSE
R = 110 C/W
T = 25°C
GS
A
θJA o
100us
0.001 0.01 0.1 110 100 300
0
20
40
60
80
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =110°C/W
T = 25°C
θJA
A
TRADEMARKS
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS P ATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TinyLogic™
UHC™
VCX™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8