Hot Swap Smart Fuse NCP81295, NCP81296 The NCP81295 and NCP81296 are 50 A, electronically re-settable, in-line fuses for use in 12 V, high current applications such as servers, storage and base stations. The NCP81295/6 offers a very low 0.65 mW integrated MOSFET to reduce solution size and minimize power loss. It also integrates a highly accurate current sensor for monitoring and overload protection. www.onsemi.com Power Features * * * * Control Features * * * * Enable Input Optional Enable-controlled Output Pulldown when Disabled Programmable Soft-Start Programmable, Multi-level Current Limit Reporting Features * * * * MARKING DIAGRAM Co-packaged Power Switch, Hotswap Controller and Current Sense Up to 60 A Peak Current Output, 50 A Continuous Vin Range: 4.5 V to 18 V 0.65 mW, no RSENSE Required Accurate Analog Load Current Monitor Programmable Over Current Alert Output Analog Temperature Output Status Fault OK Output 1 NCP8129x AWLYYWWG G 1 32 LQFN32 5x5, 0.5P CASE 487AA NCP8129x = Specific Device Code x = 5 or 6 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package = (may or may not be present) (Note: Microdot may be in either location) Other Features 26 25 27 28 29 30 31 32 PINOUT 1 24 23 2 3 NCP81295/6 22 4 (TOP VIEW) 21 20 5 33 VIN 6 19 16 15 14 13 17 12 18 8 11 7 9 * * 5 mm x 5 mm QFN32 Package Operating Temperature: -40C to 125C Can be Paralleled for Higher Current Applications Built-in Insertion Delay for Hotswap Applications NCP81295: Latch off for Following Protection Features NCP81296: Auto-Retry Mode for Following Protection Features Current-limit after Delay Fast Short-circuit Protection Over-Temperature Shutdown Excessive Soft-start Duration Internal Switch Fault Diagnostics Low-power Auxiliary Output Voltage 10 * * * * * For more details see Figure 1. ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. (c) Semiconductor Components Industries, LLC, 2017 April, 2020 - Rev. 12 1 Publication Order Number: NCP81295/D VOUT32 VOUT31 VOUT30 VOUT29 VOUT28 VOUT27 VOUT26 VOUT25 32 31 30 29 28 27 26 25 NCP81295, NCP81296 NC4 1 24 CLREF NC5 2 23 CS D_OC 3 22 IMON 21 VDD 20 GND NCP81295 /6 ON 4 GOK 5 NC1 6 19 SS VINF 7 18 VTEMP NC2 8 17 GATE (TOP VIEW) 11 12 13 14 15 16 VIN12 VIN13 VIN14 VIN15 VIN16 10 VIN10 VIN11 9 VIN9 33 VIN Figure 1. Pin Configuration Ordering Information Table 1. AVAILABLE DEVICES Device Package Shipping NCP81295MNTXG QFN32 2500 / Tape & Reel NCP81296MNTXG QFN32 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 2 NCP81295, NCP81296 System VIN VIN VINF VDD GOK D_OC ON Fuse-protected System VIN VOUT NCP81295/ 6 VTEMP IMON CS GATE SS CLREF GND Figure 2. Typical Application Main System Power Main Efuse Input Voltage Main System Main Efuse E-Fuse Control/ Monitor E-Fuse Control/ Monitor PMBSUS Control and Monitor mController E-Fuse IMON Standby System Power Standby Efuse E-Fuse Control/ Monitor Figure 3. Typical Application Diagram www.onsemi.com 3 Standby System NCP81295, NCP81296 System VIN VIN mController FAULT IN VDD GOK OVERCURRENT IN D_OC ENABLE OUT NCP81295 ON TEMP MONITOR A/D IN VOUT GATE VTEMP CURRENT MONITOR A/D IN VINF IMON CURRENT LIMIT D/A OUT SS CLREF CS GND VIN VINF VDD GOK D_OC NCP81295 ON VOUT GATE VTEMP IMON SS CLREF VIN NCP81295 ON VOUT GATE VTEMP IMON CLREF VINF VDD GOK D_OC CS GND SS GND CS Figure 4. Application Schematic - Parallel Fuse Operation with Controller www.onsemi.com 4 Fuse-protected System VIN NCP81295, NCP81296 System VIN VIN mController GOK FAULT IN VDD GATE D_OC OVERCURRENT IN VINF ON NCP81295/6 ENABLE OUT TEMP MONITOR A/D IN VTEMP VOUT CURRENT LIMIT D/A OUT CLREF CS IMON SS CURRENT MONITOR A/D IN Fuse Protected System VIN GND Figure 5. Application Schematic - Single EFuse with Controller System VIN VIN VINF GOK VDD GATE D_OC ON NCP81295/6 VOUT VTEMP CLREF CS IMON SS Fuse Protected System VIN GND Figure 6. Application Schematic - Stand-alone Single EFuse www.onsemi.com 5 NCP81295, NCP81296 System VIN VIN VINF VDD GOK D_OC NCP81295 ON VOUT GATE VTEMP IMON Fuse-protected System VIN SS CLREF CS GND VIN VINF VDD GOK D_OC NCP81295 ON VOUT GATE VTEMP IMON SS CLREF VIN NCP81295 ON VOUT GATE VTEMP IMON CLREF VINF VDD GOK D_OC CS GND SS GND CS Figure 7. Application Schematic - Stand-alone Parallel EFuse www.onsemi.com 6 NCP81295, NCP81296 VIN 9-16 SENSEFET 1:5000 VINF 7 5V LDO VDD 21 CHARGE PUMP VINF+2XVDD VOUT > 90 % VIN VOUT > 80 % VIN OUTPUT MONITOR VOUT > 70 % VIN VOUT > 40 % VIN 25-32 -32 VOUT 500 EN VDD VDD_UVR PD 5 mA 19 SS ISC 5mA ON 4 22 IMON A IMON VDD VOUT>90%VIN VOUT>70%VIN DRAIN MON GATE MON 23 CS A CS VDD 10 mA OVERCURRENT TIMER VSWON 24 CLREF 3 D_OC VCL_MAX VSWOFF VDD LOGIC DIE TEMP MONITOR VCL_HI VCL_LO VOUT>80%VIN VOC_TH(85% CLREF) VOUT>40%VIN 5 GOK VTEMP 18 50 mA GND 20 Figure 8. Block Diagram www.onsemi.com 7 NCP81295, NCP81296 Table 2. PIN DESCRIPTION Pin No. Symbol 1 NC4 No electrical connection internally. May connect to any potential Description 2 NC5 No electrical connection internally. May connect to any potential 3 D_OC 4 ON 5 GOK OK status indicator output (open drain). Low indicates that the NCP81295 was turned off by a fault. 6 NC1 Test pin. Do not connect to this pin. Leave floating 7 VINF Control circuit power supply input. Connect to VIN pins through an RC filter. (1 W / 0.1 mF) 8 NC2 Internal FET sense pin. Do not connect to this pin. Leave floating 9 VIN09 Input of high current output switch 10 VIN10 Input of high current output switch 11 VIN11 Input of high current output switch 12 VIN12 Input of high current output switch 13 VIN13 Input of high current output switch 14 VIN14 Input of high current output switch 15 VIN15 Input of high current output switch 16 VIN16 Input of high current output switch 17 GATE Internal FET gate pin. Connect to the cathode of an anode grounded diode such as BAS16P2T5G. A 4.7 nF ceramic capacitor is reserved between this pin and GND for NCP81295 to mitigate the oscillation risk when small amount of output capacitance (< 100 mF) or long input/output cable (large LIN / LOUT) happens. 18 VTEMP Overcurrent indicator output (open drain). Low indicates the NCP81295 is limiting current. The D_OC output does not report current limiting during soft-start. Enable input and output pulldown resistance control. Analog temperature monitor output. 19 SS 20 GND Soft Start time programming pin. Connect a capacitor to this pin to set the softstart time. Ground 21 VDD Linear regulator output 22 IMON Analog current monitor output 23 CS 24 CLREF 25 VOUT25 Output of high current output switch 26 VOUT26 Output of high current output switch 27 VOUT27 Output of high current output switch 28 VOUT28 Output of high current output switch 29 VOUT29 Output of high current output switch 30 VOUT30 Output of high current output switch 31 VOUT31 Output of high current output switch 32 VOUT32 Output of high current output switch 33 VIN33 Current sense feedback output (current). Scaling the voltage developed at this pin with a resistor to ground makes this also an input for several current limiting functions and overcurrent indicator D_OC. Current limit setpoint input for normal operation (after soft-start). Input of high current output switch www.onsemi.com 8 NCP81295, NCP81296 Table 3. MAXIMUM RATINGS Symbol Min Max Unit Pin Voltage Range (Note 1) Vout enabled Rating VINx, VINF -0.3 20 V Pin Voltage Range (Note 1) Vout disabled (Note 2) VINx, VINF -0.3 30 V Pin Voltage Range (Note 1) VOUTx -0.3 -1(<500 ms) 20 V Pin Voltage Range (Note 1) VDD -0.3 6.0 V Pin Voltage Range (Note 3) All Other Pins -0.3 VDD + 0.3 V 150 C 150 C Operating Junction Temperature TJ(max) Storage Temperature Range TSTG -55 Lead Temperature Soldering Reflow (SMD Styles Only), Pb-Free Versions (Note 4) TSLD 260 C Electrostatic Discharge - Charged Device Model ESDCDM 2.0 kV Electrostatic Discharge - Human Body Model ESDHBM 2.5 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. All signals referenced to GND unless noted otherwise. 2. Vout disable is the state of output OFF when internal FET has turned off by disable ON or FAULTs protection. 3. Pin ratings referenced to VDD apply with VDD at any voltage within the VDD Pin Voltage Range. 4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D Table 4. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Resistance, Junction-to-Ambient (Note 5) RJA 30 C/W Thermal Resistance, Junction-to-Top-Case RJCT 50 C/W Thermal Resistance, Junction-to-Bottom-Case RJCB 1.5 C/W Thermal Resistance, Junction-to-Board (Note 6) RJB 1.5 C/W RJC 1.5 C/W Thermal Resistance, Junction-to-Case (Note 7) mm2, 5. RqJA is obtained by simulating the device mounted on a 500 1-oz Cu pad on a 80 mm x 80 mm, 1.6 mm thick 8-layer FR4 board. 6. RqJB value based on hottest board temperature within 1 mm of the package. 7. RqJC RqJCT // RqJCB (Two-Resistor Compact Thermal Model, JESD15-3). Table 5. RECOMMENDED OPERATING RANGES Parameter Symbol Min Max Unit 4.5 18 V IAVE 50 A Peak Output Current IPEAK 60 A VDD Output Load Capacitance Range CVDD 2.2 10 mF VIN, VINF Pin Voltage Range Maximum Continuous Output Current VTEMP Output Load Capacitance Range CVTEMP 0.1 Softstart Duration TSS 10 100 ms CS Load Resistance Range RCS 1.8 4 kW CLREF Voltage Range VCLREF 0.2 1.4 V Operating Junction Temperature TJ(OP) -40 125 C mF Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 9 NCP81295, NCP81296 Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, VON = 3.3 V, CVINF = 0.1 mF, CVDD = 4.7 mF, CVTEMP = 0.1 mF, RVTEMP = 1 kW, CSS = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range -40C TA = TJ 125C unless noted otherwise, and are guaranteed by design and characterization through statistical correlation. Parameter Symbol Test Conditions Min Typ Max Units 3.23 5.0 mA 5.0 mA 4.0 mA 4.0 mA 5.3 V 30 mA VINF INPUT Quiescent Current VON > 1.4 V, no load VON > 1.4 V, fault VON < 0.8 V 2.38 VON < 0.8 V, VINF = 16 V VDD REGULATOR VDD Output Voltage VDD_NL IVDD = 0 mA, VINF = 6 V VDD Load Capability IDDLOAD VINF = 5.5 V VDD Current Limit IDD_CL VDD Dropout Voltage VINF = 12 V and VINF = 6 V 4.7 50 IVDD = 25 mA, VINF = 4.5 V 5.09 70 mA 85 200 mV UVLO threshold - rising VDD_UVR 4.1 4.3 4.5 V UVLO threshold - falling VDD_UVF 3.8 4.0 4.2 V 4.0 5.0 6.0 mA ON INPUT Bias Current ION From pin into a 0 V or 1.5 V source Switch ON Threshold VSWON 1.33 1.4 1.47 V Switch OFF/ Pulldown Upper Threshold VSWOFF 1.13 1.2 1.27 V Pulldown Lower Threshold VPDOFF 0.8 Switch ON Delay Timer tON From ON transitioning above VSWON to SS start Switch OFF Delay Time (Note 8) tOFF From ON transitioning below VSWOFF to GATE pulldown 1.7 ms Max pullup voltage of current source 3.0 V From ON transitioning into the range between VSWOFF and VPDOFF 2.0 ms 0.77 kW ON Current Source Clamp Voltage VON_CLMP Load Pulldown Delay Timer tPD_DEL Output Pulldown Resistance RPD VOUT = 12 V, PD mode = 1 ISS From pin into a 0 V or 1 V source 0.6 1.0 V 2.5 ms SS PIN Bias Current Gain to VOUT SS Pulldown Voltage AVSS VOL_SS 0.1 mA into pin during ON delay 4.62 5.15 5.62 mA 9.6 10 10.4 V/V 22 mV GOK OUTPUT Output Low Voltage VOL_GOK IGOK = 1 mA 0.1 V Off-state Leakage Current ILK_GOK VGOK= 5 V 1.0 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 8. Guaranteed by design or characterization data. Not tested in production. www.onsemi.com 10 NCP81295, NCP81296 Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, VON = 3.3 V, CVINF = 0.1 mF, CVDD = 4.7 mF, CVTEMP = 0.1 mF, RVTEMP = 1 kW, CSS = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range -40C TA = TJ 125C unless noted otherwise, and are guaranteed by design and characterization through statistical correlation. Parameter Symbol Test Conditions Min Typ Max Units IMON/CS OUTPUT IMON or CS Current (single EFuse) Based on 10 mA/A+5 mA IIMON/ICS Accuracy (single EFuse) TJ = 0 to 85C TJ = 0 to 85C IMON or CS Current Source Clamp Voltage VIM_CLMP/ VCS_CLMP Pre-Biased Offset Current Load for Auto-Zero Op-Amp IAZ_BIAS IOUT = 5 A (Note 8) 55 mA IOUT = 10 A (Note 8) 105 mA IOUT = 25 A (Note 8) 255 mA IOUT = 50 A (Note 8) 505 mA IOUT = 5 A (Note 8) -6 +6 % IOUT = 10 A (Note 8) -4 +4 % IOUT = 25 A (Note 8) -4 +4 % IOUT = 50 A (Note 8) -4 +4 % Max pullup voltage of current source 3.0 V 5.0 mA CURRENT LIMIT & CLREF PIN Current Limit Voltage VCL_TH If VCS > VCL_TH current limiting regulation occurs via gate 95 98 101 %VCLREF Current Limit Enact Offset Voltage VENACT 0.2 V < VCLREF < 1.4 V -70 -24 12 mV Current Limit Clamp Voltage VCL_LO VOUT < 40% VIN, VCLREF > 0.15 V 135 152 165 mV VCL_HI 40% VIN < VOUT < 80% VIN VCLREF > 0.5 V 480 504 520 mV Max Current Limit Reference Voltage VCL_MX VOUT > 80% VIN, VCLREF > 1.6 V 1.55 1.6 1.65 V Response Time (Note 8) tCL_REG VCS > VCLREF until current limiting 10.4 mA CLREF Bias Current CLREF Current Source Clamp Voltage FET Turn-off Timer ICL VCL_CLMP tCL_LA From pin into a 1.2 V source 200 9.6 10 ms Max pullup voltage of current source 3.0 V Delay between current limit detection and FET turn-off (GOK = 0) 250 ms D_OC OUTPUT Overcurrent Threshold VOC_TH If VCS > VOC_TH D_OC pin pulls low Output Low Voltage VOL_DOC IDOC = 1 mA 83 86 90 %VCLREF 0.1 V Off-state Leakage Current ILK_DOC VDOC= 5 V - 1.0 mA Delay (rising) (Note 8) VCS < limit until D_OC rising - 1.0 ms Delay (falling) (Note 8) VCS > limit until D_OC falling - 1.0 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 8. Guaranteed by design or characterization data. Not tested in production. www.onsemi.com 11 NCP81295, NCP81296 Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, VON = 3.3 V, CVINF = 0.1 mF, CVDD = 4.7 mF, CVTEMP = 0.1 mF, RVTEMP = 1 kW, CSS = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range -40C TA = TJ 125C unless noted otherwise, and are guaranteed by design and characterization through statistical correlation. Parameter Symbol Test Conditions Min Typ Max Units SHORT CIRCUIT PROTECTION Current Threshold (Note 8) ISC Response Time (Note 8) tSC NCP81295 100 A NCP81296 80 A From IOUT > ILIMSC until gate pulldown 500 ns VVTEMP25 At 25C 450 mV Gain (Note 8) AVTEMP 0C 10 mV/C Load Capability RVTEMP At 25C 1 kW Pulldown Current IVTEMP At 25C 50 mA TTSD GOK pulls dow 140 C On Resistance RDSon TJ = 25C 0.65 Off-state leakage current IDSoff VIN = 16 V, VON < 1.2 V, TJ = 25C VTEMP OUTPUT Bias Voltage TJ 125C THERMAL SHUTDOWN Temperature Shutdown (Note 8) OUTPUT SWITCH (FET) 1.0 mW 1.0 mA FAULT detection VDS Short Threshold VDS_TH Startup postponed if VOUT > VDS_TH at VON > VSWON transition 88.8 %VIN VDS Short OK Threshold VDS_OK Startup resumed if VOUT < VDS_OK anytime after postponed 68.6 %VIN VGD Short Threshold VDG_TH Startup postponed if VG > VDG_TH at VON > VSWON transition 3.1 V VGD Short OK Threshold VDG_OK Startup resumed if VG < VDG_OK anytime after postponed 3.0 V VG_TH Latch/Restart if VGD < VG_TH after tSSF_END or tGATE_FLT 5.4 V VG Low Threshold VOUT Low Threshold VOUTL_TH Latch/Restart if VOUT < VOUTL_TH after tSSF_END 90 %VIN Gate Fault Timer (Note 8) tGATE_FLT Time from VGD < VG_TH transition after tSSF_END completed 200 ms Startup Timer Failsafe (Note 8) tSSF_END Time from VON > VSWON transition, Max programmable softstart time 200 ms Delay from power-down to retry of startup 1000 ms AUTO-RETRY (NCP81296) Auto-Retry Delay tDLY_RETRY Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 8. Guaranteed by design or characterization data. Not tested in production. www.onsemi.com 12 NCP81295, NCP81296 TYPICAL CHARACTERISTICS 600 600 500 500 400 400 Imon (mA) Ics (mA) Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, RCLREF = 121 kW, RIMON = 2 kW 300 200 200 100 100 0 0 10 20 30 40 50 0 60 20 30 40 50 Figure 9. Ics vs. Load Current Figure 10. Imon vs. Load Current 60 600 50 A 50 A 500 400 Imon (mA) 400 Ics (mA) 10 LOAD CURRENT (A) 500 30 A 300 200 100 0 -50 0 LOAD CURRENT (A) 600 30 A 300 200 100 -25 0 25 50 75 100 125 0 -50 150 -25 0 25 50 75 100 TEMPERATURE (C) TEMPERATURE (C) Figure 11. Ics vs. Temperature Figure 12. Imon vs. Temperature 1.0 1600 0.9 1400 0.8 125 150 1200 Vtemp (mV) 0.7 RDS(on) (mW) 300 0.6 0.5 0.4 0.3 1000 800 600 400 0.2 0.1 0 -60 -40 -20 200 0 20 40 60 80 100 120 140 0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) TEMPERATURE (C) Figure 13. Output Switch RDS(on) @ 22 A vs. Temperature Figure 14. Vtemp vs. Temperature (no load) www.onsemi.com 13 NCP81295, NCP81296 TYPICAL CHARACTERISTICS Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, RCLREF = 121 kW, RIMON = 2 kW 2500 -1 2000 POWER LOSS (mW) OFF-STATE LEAKAGE (mA) 0 -2 -3 -4 1500 Power Loss 1000 500 -5 -6 -60 -40 -20 0 40 20 60 80 0 100 120 140 0 10 30 20 50 40 TEMPERATURE (C) OUTPUT CURRENT (A) Figure 15. Output Switch Off-state Leakage vs. Temperature Figure 16. Power Loss vs. Load Current 60 ID, DRAIN CURRENT (A) 1000 100 100 ms 250 ms 10 1 ms 1 0.1 0.01 10 ms 100 ms 1s RDS(ON) Limit Single Pulse RqJA = 24.8 C/W TA = 25C 0.1 10 s Dotted Lines: Measured SOA Solid Lines: Calculated SOA 10 1 20 VDS, DRAIN-SOURCE VOLTAGE (V) Figure 17. Internal FET's Safe Operating Area (SOA) 10k 200 POWER (W) 250 POWER (W) 100k 1k TA = 25C 100 1 0.00001 0.0001 0.001 0.01 0.1 100 TA = 25C 50 TA = 85C 10 150 TA = 85C 1.0 10 100 0 0.01 1k 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.1 PULSE WIDTH (s) PULSE WIDTH (s) Figure 18. Single Pulse Power Rating (10 ms - 1000 s, Junction-to-Ambient, Note 4) Figure 19. Single Pulse Power Rating (10 ms - 100 ms, Junction-to-Ambient, Note 4) www.onsemi.com 14 NCP81295, NCP81296 TYPICAL CHARACTERISTICS Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, RCLREF = 121 kW, RIMON = 2 kW Figure 20. Start Up by VIN (Iout = 0 A) Figure 21. Shut Down by VIN (Iout = 0 A) Figure 22. Start Up by VIN (Iout = 15 A) Figure 23. Shut Down by VIN (Iout = 15 A) Figure 24. Start Up by EN (Iout = 0 A) Figure 25. Shut Down by EN (Iout = 0 A) www.onsemi.com 15 NCP81295, NCP81296 TYPICAL CHARACTERISTICS Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, RCLREF = 121 kW, RIMON = 2 kW Figure 26. Start Up by EN (Iout = 15 A) Figure 27. Shut Down by EN (Iout = 15 A) Figure 28. Short Circuit during Normal Operation (Iout = 0 A) Figure 29. Short Circuit during Normal Operation (Iout = 50 A) Figure 30. Short FET's Gate During Normal Operation (Iout = 2.5 A) Figure 31. DOC Index for Current Limit during Normal Operation (Iout = 51.8 A) www.onsemi.com 16 NCP81295, NCP81296 TYPICAL CHARACTERISTICS Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, RCLREF = 121 kW, RIMON = 2 kW Figure 32. OCP during Normal Operation(Iout=60.2A) Figure 33. OCP during Power Up by Enable www.onsemi.com 17 NCP81295, NCP81296 General Information The NCP81295/6 is an N-channel MOSFET co-packaged with a smart hotswap controller. It is suited for high-side current limiting and fusing in hot-swap applications. It can be used either alone, or in a paralell configuration for higher current applications. VDD Output (Auxiliary Regulated Supply) An internal linear regulator draws current from the VINF pin to produce and regulate voltage at the VDD pin. This auxiliary output supply is current-limited to IDD_CL. A ceramic capacitor in the range of 2.2 mF to 10 mF must be placed between the VDD and GND pins, as close to the NCP81295/6 as possible. The voltage difference between VIN and VINF pin voltage should be within 0.4 V for better CS/IMON performance. Small time constant R/C filter such as 1 W/0.1 mF on the VINF pin is recommended. tSS (ms) CSS (nF) tSS (ms) CSS (nF) 10 47 60 270 20 82 70 330 30 120 80 330 40 180 90 470 50 220 100 470 The maximum load capacitor value NCP81295/6 can power up depends on the device soft-start time. When VIN = 12 V, RCS = 2 kW, RLOAD = 2.4 W, their relationship for different paralleled operations are shown as below chart (above line device shuts down safely due to protection, below line device powers up successfully without trigger protection): ON Input (Device Enable) When the ON pin voltage (VON) is higher than VSWON, and no undervoltage (UVLO) or output switch faults are present, the output switch turns on. When VON is lower than VSWOFF, the output switch is off. If VON is between VPDOFF and VSWOFF for longer than tPD_DEL, the output switches off, and a pulldown resistance to ground, of RPD, is applied to VOUT. In other words, there is behavior as follows: * When VON < 0.8 V, FET turns off. * When 0.8 V < VON < 1.2 V, VOUT will discharge with 15 mA. * When VON > 1.2 V, FET turns on. For standalone applications, the ON pin sources current ION, which can be used to delay output switch turn-on for some time after the appearance of input voltage by connecting a capacitor from the ON pin to ground. A bi-level control signal driving to ground can be biased up with a resistive divider to produce ON input levels between VPDOFF < VON < VSWON and VON > VSWON in order to always apply the output pulldown when the output switch is off. GOK Output (Gate OK) The GOK pin is an open-drain output that is pulled low to report the fault under the following conditions: * VDD voltage is below UVLO voltage at any time. * VON disabled and VDS_OK is false (indicates a short from VIN to VOUT). * VON disabled and VDG_OK is false (indicates a short from GATE to VIN). * VON enabled and VSS_OK is false at tSSF_END (indicates VOUT < 90% after soft-start completes - FET latches off for NCP81295/auto-retries for NCP81296). * VON enabled and VG is below VG_TH at tSSF_END (indicates leakage on GATE in startup - FET latches off for NCP81295/auto-retries for NCP81296). * VON enabled and VG is below VG_TH after tGATE_FLT (indicates leakage on GATE during normal operation - FET latches off for NCP81295/auto-retries for NCP81296). * VON enabled and a current-limiting condition lasts longer than tOC_LA (FET latches off for NCP81295/auto-retries for NCP81296). SS Output (Soft-Start) When the output switch first turns on, it does so in a controlled manner. The output voltage (VOUT) follows the voltage at the SS pin, produced by current ISS into a capacitor from SS to ground. The duration of soft-start can be programmed by selection of the capacitor value. In parallel fuse applications, the SS pins of all fuses should be shorted together to one shared SS capacitor. Internal soft-start load balancing circuity will ensure the soft-start current is shared between paralleled devices, so as not to stress one device more than another or hit a soft start-current limit. The soft-start capacitor value can be calculated by: CSS = (tSS * ISS * AVSS)/VIN (where tSS is the target soft-start time). The recommended range of tSS is 10 - 100 ms (see Table 5). The typical CSS values for different tSS are listed below: www.onsemi.com 18 NCP81295, NCP81296 * VON enabled and device temperature is above TTSD During startup (VON > VSWON for less than tSS_END), the current limit reference voltage is clamped according to the following: * When VOUT < 40% of VIN, VCL_TH = VCL_LO or VCLREF (whichever is lower). * When VOUT is between 40% and 80% of VIN, VCL_TH = VCL_HI or VCLREF (whichever is lower). * When VOUT exceeds 80% of VIN, VCL_TH = VCL_MX or VCLREF (whichever is lower). (indicates an over-temperature is detected - FET latches off for NCP81295/auto-retries for NCP81296). Usually GOK can't be used as power good to indicate the output voltage is in the normal range. Bringing VDD below the UVLO voltage is required to release a latching condition. IMON Output (Current Monitor) The IMON pin sources a current that is AIMON (10 mA/A) times the VOUT output current and plus IAZ_BIAS. A resistor connected from the IMON pin to ground can be used to monitor current information as a voltage up to VIM_CLMP. A capacitor of any value in parallel with the IMON resistor can be used to low-pass filter the IMON signal without affecting any internal operation of the device. If a current limiting condition exists anytime for a continuous duration > tCL_LA, then the device latches off (NCP81295) or restarts (NCP81296). The CS pin must have no capacitive loading other than parasitic device/board capacitance to function correctly. The recommended range of RCS is 1.8 - 4 kW (see Table 5). CLREF Pin (Current Limit and Over-Current Reference) CS AMP OFFSET BIAS The CLREF pin voltage determines the current-limit regulation point and over-current indication point via its interaction with the CS pin voltage. The CLREF voltage can be applied by an external source, such as a hot-swap controller or D-to-A converter, or developed across a programming resistor to ground by the CLREF bias current, ICL. The recommended range of CLREF voltage is 0.2 - 1.4 V (see Table 5). NCP81295/6 use an auto-zero Op-Amp with low input offset to sense current in FET with high-accuracy, and an pre-biased offset current load, IAZ_BIAS is need for this Op-Amp to always keep it to maintain this low input offset (<100 mV). The internal IMON and CS current source follow below relationship: CS Input/Output (Current Set) I OUT + )V OC_TH ENACT R CS * I AZ_BIAS 10 m I OUT + I OUT + )V CL_TH ENACT R CS * I AZ_BIAS 10 m I MON * I AZ_BIAS 10 m (eq. 4) For typical 5 mA IAZ_BIAS, there has 0.5 A positive off-set in IOUT sense. D_OC Output (Over-current Indicator) The D_OC pin is an open-drain output that indicates when an over-current condition exists after soft-start is complete. When the voltage on the CS pin is higher than VOC_TH, D_OC is pulled low. If output current drops below VOC_TH, the D_OC pin is released and gets pulled high by an external pullup resistor. VTEMP Output (Temperature Indicator) VTEMP is a voltage output proportional to device temperature, with an offset voltage. The VTEMP output can source much more current than it can sink, so that if multiple VTEMP outputs are connected together, the voltage of all VTEMP outputs will be driven to the voltage produced by the hottest NCP81295/6. A 100 nF capacitor or greater must be connected from the VTEMP pin to ground. (eq. 1) The VOC_TH trip point is based on a percentage of VCLREF (86%). During normal operation (VON > VSWON for longer than tSS_END), if the voltage on the CS pin is above VCL_TH (VCL_TH is clamped at VCL_MX if VCL_TH > VCL_MX), then the gate voltage of the FET is modulated to limit current into the output based on the following formula: V (eq. 3) and The CS pin is both an input and an output. The CS pin sources a current that is ACS (10 mA/A) times the VOUT current and plus IAZ_BIAS. This produces a voltage on the CS pin that is the product of the CS pin current and an external CS pin resistance to ground. The voltage generated on VCS determines the D_OC over-current indicator trip point and the current-limit regulation point, via its interaction with the voltage on CLREF pin. When the voltage on the CS pin is higher than VOC_TH , D_OC is pulled low. If the CS pin voltage drops below VOC_TH, the D_OC pin is released to and gets pulled high by the external pullup resistor. D_OC transitions based on the following formula: V I CS * I AZ_BIAS 10 m I OUT + (eq. 2) The VCL_TH regulation point is equal to VCLREF. www.onsemi.com 19 NCP81295, NCP81296 * VIN to VOUT short, non-latching/non-auto-retry Auto-Retry Restart (NCP81296) Under certain fault conditions, the FET is turned off and another soft-start procedure takes place. Between the fault and the new soft-start, there is a delay of tDLY_RETRY. The protection features that use this hiccup mode restart are: * Over-Current * Short-Circuit Detection * Over-Temperature * Excessive Soft-Start Duration * Gate Leakage * * Protection Features For the following protection features, the FET either latches off (NCP81295) or the FET turns off and initiates a restart (NCP81296), unless noted otherwise. * Excessive Current Limiting If a current limiting condition exists anytime for a continuous duration > tCL_LA, then the FET latches/restarts. condition. If the device is disabled and VOUT > VDS_TH then GOK is pulled low and the device is prevented from powering up. The device is allowed to power up once VOUT < VDS_OK. GATE to VIN short, non-latching/non-auto-retry condition. If the device is disabled and GATE (Pin 8) > VDG_TH, then GOK is pulled low and device is prevented from powering up. The device allowed to power up once GATE < VDG_OK. GATE leakage - startup. If (GATE - VINF) < VG_TH at tSSF_END, then GOK is pulled low and FET latches/restarts. GATE leakage - normal operation. If (GATE - VINF) < VG_TH for tGATE_FLT time after the soft-start timer completes, then GOK is pulled low and device latches/restarts. FET SOA Limits If VOUT < VOUTL_TH when tSSF_END expires, then the FET latches/restarts. In-built timed current limits and fault-monitoring circuits ensure the copackaged FET is always kept within SOA limits. Short Circuit Detection Multiple Fuse Power Up Excessive Soft-Start Duration When multiple NPC81295 are paralleled together as shown in Figure 4, the NPC81295s will turn on together. Keeping the current through each switch within 1 A (typical) helps to prevent overstress on each switching during soft-start. Due to NCP81296 is featured by Auto-Retry Mode protection, please follow the below reference schematic of NCP81296 for paralleled operation. If switch current exceeds ISC, the device reacts within tSC, and the FET latches/restarts. The short-circuit current monitor is independent of CS, CLREF, IMON and current limit setting (cannot be changed externally). Over-Temperature Shutdown If the FET controller temperature > TTSD, then the FET latches/restarts. FET Fault Detection The device contains various FET monitoring circuits: www.onsemi.com 20 NCP81295, NCP81296 When paralleled multiple NPC81295 encounter fault, the system can recover the E-fuse by resetting their VDD with below buffer and reset circuit. www.onsemi.com 21 NCP81295, NCP81296 22nF 22nF www.onsemi.com 22 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LQFN32 5x5, 0.5P CASE 487AA ISSUE A DATE 03 OCT 2017 1 32 SCALE 2:1 A B D EEE EEE EEE PIN ONE REFERENCE 0.10 C 0.10 C DETAIL A ALTERNATE CONSTRUCTION E EEE EEE CCC TOP VIEW A1 DETAIL B (A3) ALTERNATE CONSTRUCTION A 0.05 C NOTE 4 A1 SIDE VIEW C SEATING PLANE GENERIC MARKING DIAGRAM* L2 K 9 XXXXXXXX XXXXXXXX AWLYYWWG G DETAIL C 17 32X L2 MILLIMETERS MIN MAX 1.20 1.40 --- 0.05 0.20 REF 0.18 0.30 5.00 BSC 3.30 3.50 5.00 BSC 3.30 3.50 0.50 BSC 0.30 0.50 0.13 REF 1 D2 DETAIL A DIM A A1 A3 b D D2 E E2 e L L2 A3 DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L 4 PLACES L E2 DETAIL C 1 XXXXX A WL YY WW G 24 32 25 32X e e/2 BOTTOM VIEW b 0.10 M C A B 0.05 M C NOTE 3 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) RECOMMENDED SOLDERING FOOTPRINT* *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. Some products may not follow the Generic Marking. 5.30 32X 3.60 0.63 3.60 5.30 0.50 PITCH 32X 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON11454G LQFN32, 5x5, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 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