NCP81295, NCP81296
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•VON enabled and device temperature is above TTSD
(indicates an over−temperature is detected − FET
latches off for NCP81295/auto−retries for NCP81296).
Usually GOK can’t be used as power good to indicate the
output voltage is in the normal range. Bringing VDD below
the UVLO voltage is required to release a latching condition.
IMON Output (Current Monitor)
The IMON pin sources a current that is AIMON (10 mA/A)
times the VOUT output current and plus IAZ_BIAS. A resistor
connected from the IMON pin to ground can be used to
monitor current information as a voltage up to VIM_CLMP
. A
capacitor of any value in parallel with the IMON resistor can
be used to low−pass filter the IMON signal without affecting
any internal operation of the device.
CLREF Pin (Current Limit and Over−Current Reference)
The CLREF pin voltage determines the current−limit
regulation point and over−current indication point via its
interaction with the CS pin voltage. The CLREF voltage can
be applied by an external source, such as a hot−swap
controller or D−to−A converter, or developed across a
programming resistor to ground by the CLREF bias current,
ICL. The recommended range of CLREF voltage is 0.2 −
1.4 V (see Table 5).
CS Input/Output (Current Set)
The CS pin is both an input and an output. The CS pin
sources a current that is ACS (10 mA/A) times the VOUT
current and plus IAZ_BIAS. This produces a voltage on the CS
pin that is the product of the CS pin current and an external
CS pin resistance to ground.
The voltage generated on VCS determines the D_OC
over−current indicator trip point and the current−limit
regulation point, via its interaction with the voltage on
CLREF pin.
When the voltage on the CS pin is higher than VOC_TH ,
D_OC is pulled low. If the CS pin voltage drops below
VOC_TH, the D_OC pin is released to and gets pulled high by
the external pullup resistor. D_OC transitions based on the
following formula:
(eq. 1)
IOUT +
VOC_TH)VENACT
RCS
*IAZ_BIAS
10 m
The VOC_TH trip point is based on a percentage of VCLREF
(86%).
During normal operation (VON > VSWON for longer than
tSS_END), if the voltage on the CS pin is above VCL_TH
(VCL_TH is clamped at VCL_MX if VCL_TH > VCL_MX), then
the gate voltage of the FET is modulated to limit current into
the output based on the following formula:
(eq. 2)
IOUT +
VCL_TH)VENACT
RCS
*IAZ_BIAS
10 m
The VCL_TH regulation point is equal to VCLREF.
During startup (VON > VSWON for less than tSS_END), the
current limit reference voltage is clamped according to the
following:
•When VOUT < 40% of VIN, VCL_TH = VCL_LO or
VCLREF (whichever is lower).
•When VOUT is between 40% and 80% of VIN,
VCL_TH = VCL_HI or VCLREF (whichever is lower).
•When VOUT exceeds 80% of VIN, VCL_TH = VCL_MX
or VCLREF (whichever is lower).
If a current limiting condition exists anytime for a
continuous duration > tCL_LA, then the device latches off
(NCP81295) or restarts (NCP81296).
The CS pin must have no capacitive loading other than
parasitic device/board capacitance to function correctly. The
recommended range of RCS is 1.8 − 4kW (see Table 5).
CS AMP OFFSET BIAS
NCP81295/6 use an auto−zero Op−Amp with low input
offset to sense current in FET with high−accuracy, and an
pre−biased offset current load, IAZ_BIAS is need for this
Op−Amp to always keep it to maintain this low input offset
(<100 mV). The internal IMON and CS current source
follow below relationship:
IOUT +
ICS *IAZ_BIAS
10 m(eq. 3)
and
(eq. 4)
IOUT +
IMON *IAZ_BIAS
10 m
For typical 5 mA IAZ_BIAS, there has 0.5 A positive off−set
in IOUT sense.
D_OC Output (Over−current Indicator)
The D_OC pin is an open−drain output that indicates
when an over−current condition exists after soft−start is
complete. When the voltage on the CS pin is higher than
VOC_TH, D_OC is pulled low. If output current drops below
VOC_TH, the D_OC pin is released and gets pulled high by
an external pullup resistor.
VTEMP Output (Temperature Indicator)
VTEMP is a voltage output proportional to device
temperature, with an offset voltage. The VTEMP output can
source much more current than it can sink, so that if multiple
VTEMP outputs are connected together, the voltage of all
VTEMP outputs will be driven to the voltage produced by
the hottest NCP81295/6. A 100 nF capacitor or greater must
be connected from the VTEMP pin to ground.