1
Features
•Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
•Three-wire Serial Interface
•2 MHz Clock Rate (5V) Compatibility
•Self-timed Write Cycle (10 ms max)
•High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
•Automotive Grade, Extended Temperature, and Lead-free/Halogen-free Devices
Available
•8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
Description
The AT93C46A provides 1024 bits of serial electrically-erasable programmable read-
only memory (EEPROM) organized as 64 words of 16 bits each. The device is opti-
mized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential. The AT93C46A is available in space-saving 8-
lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages.
The AT93C46A is enabled through the Chip Select pin (CS) and accessed via a three-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output DO pin. The write cycle is completely self-timed
and no separate erase cycle is required before write. The write cycle is only enabled
when the part is in the erase/write enable state. When CS is brought high following the
initiation of a write cycle, the DO pin outputs the ready/busy status of the part.
The AT93C46A is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configuration
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
Three-wire
Serial EEPROM
1K (64 x 16)
AT93C46A
Rev. 0539J–SEEPR–11/04
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
NC
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
NC
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
NC
GND
8-lead PDIP
8-lead SOIC
8-lead TSSOP
2AT93C46A
0539J–SEEPR–11/04
Figure 1. Block Diagram
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
MEMORY ARRAY
64 X 16
DATA
REGISTER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
ADDRESS
DECODER
3
AT93C46A
0539J–SEEPR–11/04
Note: This parameter is characterized and is not 100% tested.
Note: 1. VIL min and VIH max are reference only and are not tested.
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (DO) 5 pF VOUT = 0V
CIN Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V, (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC Supply Current VCC = 5.0V Read at 1.0 MHz 0.5 2.0 mA
Write at 1.0 MHz 0.5 2.0 mA
ISB1 Standby Current VCC = 1.8V CS = 0V 14.0 20.0 µA
ISB2 Standby Current VCC = 2.7V CS = 0V 14.0 20.0 µA
ISB3 Standby Current VCC = 5.0V CS = 0V 35.0 50.0 µA
IIL Input Leakage VIN = 0V to VCC 0.1 1.0 µA
IOL Output Leakage VIN = 0V to VCC 0.1 1.0 µA
VIL1(1)
VIH1(1)
Input Low Voltage
Input High Voltage 2.7V ≤ VCC ≤ 5.5V −0.6
2.0
0.8
VCC + 1 V
VIL2(1)
VIH2(1)
Input Low Voltage
Input High Voltage 1.8V ≤ VCC ≤ 2.7V −0.6
VCC x 0.7
VCC x 0.3
VCC + 1 V
VOL1
VOH1
Output Low Voltage
Output High Voltage 2.7V ≤ VCC ≤ 5.5V IOL = 2.1 mA 0.4 V
IOH = −0.4 mA 2.4 V
VOL2
VOH2
Output Low Voltage
Output High Voltage 1.8V ≤ VCC ≤ 2.7V IOL = 0.15 mA 0.2 V
IOH = −100 µA VCC − 0.2 V
4AT93C46A
0539J–SEEPR–11/04
Note: 1. This parameter is characterized and is not 100% tested.
Table 4. AC Characteristics
Applicable over recommended operating range from TA = −40°C to + 85°C, VCC = +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
fSK SK Clock Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
2
1
0.25
MHz
tSKH SK High Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tSKL SK Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tCS Minimum CS Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tCSS CS Setup Time Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
50
200
ns
tDIS DI Setup Time Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tCSH CS Hold Time Relative to SK 0 ns
tDIH DI Hold Time Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tPD1 Output Delay to “1” AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tPD0 Output Delay to “0” AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tSV CS to Status Valid AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tDF
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tWP Write Cycle Time 0.1 3 10 ms
Endurance(1) 5.0V, 25°C 1M Write Cycle
5
AT93C46A
0539J–SEEPR–11/04
Functional
Description
The AT93C46A is accessed via a simple and versatile three-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor.
A valid instruction starts with a rising edge of CS
and consists of a start bit (logic
“1”) followed by the appropriate op code and the desired memory address location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 16-bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes
into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before any programming instructions
can be carried out. Please note that once in the EWEN state, programming remains
enabled until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
Erase instruction and address are decoded. The DO pin outputs the ready/busy status
of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be writ-
ten into the specified memory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
ready/busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions.
A
ready/busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle, tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the ready/busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the ready/busy
Table 5. Instruction Set for the AT93C46A
Instruction SB Op Code
Address
Commentsx 16
READ 1 10 A5 − A0Reads data stored in memory, at specified address
EWEN 1 00 11XXXX Write enable must precede all programming modes
ERASE 1 11 A5 − A0Erase memory location An − A0
WRITE 1 01 A5 − A0Writes memory location An − A0
ERAL 1 00 10XXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V
WRAL 1 00 01XXXX Writes all memory locations. Valid only at VCC = 4.5V to 5.5V
EWDS 1 00 00XXXX Disables all programming instructions
6AT93C46A
0539J–SEEPR–11/04
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the Read instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
Timing Diagrams
Figure 2. Synchronous Data Timing
Note: 1. This is the minimum SK period.
µs(1)
Table 6. Organization Key for Timing Diagrams
I/O
AT93C46A
x 16
ANA5
DND15
7
AT93C46A
0539J–SEEPR–11/04
Figure 3. READ Timing
Figure 4. EWEN Timing1
Note: 1. Requires a minimum of nine clock cycles.
Figure 5. EWDS Timing1
Note: 1. Requires a minimum of nine clock cycles.
High Impedance
tCS
CS
11 ...
001
SK
DI
t
CS
CS t
CS
SK
DI 1 0 000 ...
8AT93C46A
0539J–SEEPR–11/04
Figure 6. WRITE Timing
Figure 7. WRAL Timing(1 ),( 2 )
Notes: 1. Valid only at VCC = 4.5V to 5.5V.
2. Requires a minimum of nine clock cycles.
Figure 8. ERASE Timing
SK
CS t
CS
t
WP
11
A
N
D
N
0A0D0
... ...
DI
DO
HIGH IMPEDANCE BUSY READY
CS
SK
DI
DO
HIGH IMPEDANCE BUSY
READY
1 0 0 1 ... DN
tCS
tWP
... D00
SK
1 1 ...1
CS
DI A
N
t
CS
t
SV
t
DF
t
WP
A
N-1
A
N-2
A0
CHECK
STATUS
STANDBY
READY
BUSY
DO
HIGH IMPEDANCE HIGH IMPEDANCE
9
AT93C46A
0539J–SEEPR–11/04
Figure 9. ERAL Timing(1)
Note: 1. Valid only at VCC = 4.5V to 5.5V.
SK
CS
DI 1 1000
DO
HIGH IMPEDANCE HIGH IMPEDANCE
READY
BUSY
CHECK
STATUS
STANDBY
t
WP
t
CS
t
SV
t
DF
10 AT93C46A
0539J–SEEPR–11/04
Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in
Table 3 on page 3
and
Table 4 on page 4
.
Ordering Information
Ordering Code Package Operation Range
AT93C46A-10PI-2.7
AT93C46A-10SI-2.7
AT93C46A-10TI-2.7
8P3
8S1
8A2
Industrial
(−40°C to 85°C)
AT93C46A-10PI-1.8
AT93C46A-10SI-1.8
AT93C46A-10TI-1.8
8P3
8S1
8A2
Industrial
(−40°C to 85°C)
AT93C46A-10PU-2.7
AT93C46A-10PU-1.8
AT93C46A-10SU-2.7
AT93C46A-10SU-1.8
AT93C46A-10TU-2.7
AT93C46A-10TU-1.8
8P3
8P3
8S1
8S1
8A2
8A2
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Small Outline Package (TSSOP)
Options
−2.7 Low Voltage (2.7V to 5.5V)
−1.8 Low Voltage (1.8V to 5.5V)
11
AT93C46A
0539J–SEEPR–11/04
Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
12 AT93C46A
0539J–SEEPR–11/04
8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
10/7/03
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0˚ – 8˚
∅
Top View
End View
Side View
eB
D
A
A1
N
E
1
C
E1
L
13
AT93C46A
0539J–SEEPR–11/04
8A2 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
Printed on recycled paper.
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