www.fairchildsemi.com UC3842/UC3843/UC3844/UC3845 SMPS Controller Features Description * * * * The UC3842/UC3843/UC3844/UC3845 are fixed frequency current-mode PWM controller. They are specially designed for Off - Line and DC-to-DC converter applications with minimum external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier. current sensing comparator, and a high current totempole output Ideally suited for driving a power MOSFET. Protection circuity Includes built in under-voltage lockout and current limiting. TheUC3842 and UC3844 have UVLO thresholds of 16V (on) and 10V (off) The UC3843 and UC3845 are 8.5V (on) and 7.9V (off) The UC3842 and UC3843 can operate within 100% duty cycle. The UC3844and UC3845 can operate with 50% duty cycle. Low Start Up Current Maximum Duty Clamp UVLO With Hysteresis Operating Frequency Up To 500KHz 8-DIP 1 14-SOP 1 Internal Block Diagram Rev. 1.0.0 (c)2001 Fairchild Semiconductor Corporation UC3842/UC3843/UC3844/UC3845 Absolute Maximum Ratings Parameter Symbol Value Unit Supply Voltage VCC 30 V Output Current IO 1 A V(ANA) -0.3 to 6.3 V Error Amp Output Sink Current ISINK (E.A) 10 mA Power Dissipation (TA = 25C) PD 1 W Analog Inputs (Pin 2.3) 2 UC3842/UC3843/UC3844/UC3845 Electrical Characteristics (VCC=15V, RT=10K, CT=3.3nF, TA= 0C to +70C, unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit TJ = 25C, IREF = 1mA 4.90 5.00 5.10 V REFERENCE SECTION Reference Output Voltage VREF Line Regulation VREF 12V VCC 25V - 6 20 mV Load Regulation VREF 1mA IREF 20mA - 6 25 mV ISC TA = 25C - -100 -180 mA f TJ = 25C 47 52 57 KHz 12V VCC 25V - 0.05 1 % VOSC - - 1.6 - VP-P IBIAS - - -0.1 -2 A Short Circuit Output Current OSCILLATOR SECTION Oscillation Frequency Frequency Change with Voltage f/VCC Oscillator Amplitude ERROR AMPLIFIER SECTION Input Bias Current Input Voltage Open Loop Voltage Gain VI(E>A) Vpin1 = 2.5V 2.42 2.50 2.58 V GVO 2V VO 4V 65 90 - dB Power Supply Rejection Ratio PSRR 12V VCC 25V 60 70 - dB Output Sink Current ISINK Vpin2 = 2.7V, Vpin1 = 1.1V 2 7 - mA -0.6 -1.0 - mA Output Source Current ISOURCE Vpin2 = 2.3V, Vpin1 = 5V High Output Voltage VOH Vpin2 = 2.3V, RL = 15K to GND 5 6 - V Low Output Voltage VOL Vpin2 = 2.7V, RL = 15K to Pin 8 - 0.8 1.1 V GV (Note 1 & 2) 2.85 3 3.15 V/V Vpin1 = 5V(Note 1) 0.9 1 1.1 V - 70 - dB - -3 -10 A ISINK = 20mA - 0.08 0.4 V ISINK = 200mA - 1.4 2.2 V CURRENT SENSE SECTION Gain Maximum Input Signal VI(MAX) Power Supply Rejection Ratio PSRR Input Bias Current IBIAS 12V VCC 25V (Note 1) - OUTPUT SECTION Low Output Voltage High Output Voltage VOL VOH ISOURCE = 20mA 13 13.5 - V ISOURCE = 200mA 12 13.0 - V Rise Time tR TJ = 25C, CL= 1nF (Note 3) - 45 150 ns Fall Time tF TJ = 25C, CL= 1nF (Note 3) - 35 150 ns UC3842/UC3844 14.5 16.0 17.5 V UC3843/UC3845 7.8 8.4 9.0 V UC3842/UC3844 8.5 10.0 11.5 V UC3843/UC3844 7.0 7.6 8.2 V UNDER-VOLTAGE LOCKOUT SECTION Start Threshold Min. Operating Voltage (After Turn On) VTH(ST) VOPR(MIN) 3 UC3842/UC3843/UC3844/UC3845 Electrical Characteristics (Continued) (VCC=15V, RT=10K, CT=3.3nF, TA= 0C to +70C, unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit PWM SECTION Max. Duty Cycle D(max) UC3842/UC3843 95 97 100 % D UC3844/UC3845 47 48 50 % Min. Duty Cycle D(MIN) - - - 0 % IST - - 0.45 1 mA - 14 17 mA 30 38 - V TOTAL STANDBY CURRENT Start-Up Current Operating Supply Current Zener Voltage ICC(OPR) VZ Vpin3=Vpin2=ON ICC = 25mA Adjust VCC above the start threshould before setting at 15V Note: 1. Parameter measured at trip point of latch 2. Gain defined as: V pin1 A = ----------------- ,0 Vpin3 0.8V V pin3 3.These parameters, although guaranteed, are not 100 tested in production. UC3842 Figure 1. Open Loop Test Circuit High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5K potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. 4 UC3842/UC3843/UC3844/UC3845 UC3842/44 UC3843/45 Figure 2. Under Voltage Lockout During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with output leakage current. Figure 3. Error Amp Configuration Figure 4. Current Sense Circuit Peak current (IS) is determined by the formula: 1.0V I S ( MAX ) = -----------RS A small RC filter may be required to suppress switch transients. 5 UC3842/UC3843/UC3844/UC3845 Figure 5. Oscillator Waveforms and Maximum Duty Cycle Oscillator timing capacitor, CT, is charged by VREF through RT, and discharged by an internal current source. During the discharge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines both oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas: tc = 0.55 RT CT 0.0063RT - 2.7 t D = R T C T I n ---------------------------------------- 0.0063R T - 4 Frequency, then, is: f=(tc + td)-1 1.8 ForRT > 5K ,f = --------------RT CT Figure 6. Oscillator Dead Time & Frequency Figure 7. Timing Resistance vs Frequency (Deadtime vs CT RT > 5k) Figure 8. Shutdown Techniques 6 UC3842/UC3843/UC3844/UC3845 Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SOR which will be reset by cycling Voc below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset. UC3842/UC3843 Figure 9. Slope Compensation A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes. TEMPERATURE (C) TEMPERATURE (C) Figure 10. TEMPERATURE DRIFT (Vref) Figure 11. TEMPERATURE DRIFT (Ist) TEMPERATURE (C) Figure 12. TEMPERATURE DRIFT (Icc) 7 UC3842/UC3843/UC3844/UC3845 Mechanical Dimensions Package 2.54 0.100 5.08 MAX 0.200 7.62 0.300 3.40 0.20 0.134 0.008 +0.10 0.25 -0.05 +0.004 0~15 8 0.010 -0.002 3.30 0.30 0.130 0.012 0.33 MIN 0.013 0.060 0.004 #5 1.524 0.10 #4 0.018 0.004 #8 9.60 MAX 0.378 #1 9.20 0.20 0.362 0.008 ( 6.40 0.20 0.252 0.008 0.46 0.10 0.79 ) 0.031 8-DIP UC3842/UC3843/UC3844/UC3845 Mechanical Dimensions (Continued) Package 14-SOP MIN #8 0.60 0.20 0.024 0.008 MAX0.10 MAX0.004 1.80 MAX 0.071 5.72 0.225 8 3.95 0.20 0.156 0.008 0~ +0.10 0.20 -0.05 +0.004 0.008 -0.002 6.00 0.30 0.236 0.012 1.27 0.050 #7 +0.10 0.406 -0.05 +0.004 0.016 -0.002 #14 8.70 MAX 0.343 #1 8.56 0.20 0.337 0.008 ( 0.47 ) 0.019 1.55 0.10 0.061 0.004 0.05 0.002 9 UC3842/UC3843/UC3844/UC3845 Ordering Information Product Number Package Operating Temperature UC3842N UC3843N UC3844N 8-DIP UC3845N 0 ~ + 70C UC3842D UC3843D UC3844D 14-SOP UC3845D DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 9/25/01 0.0m 001 Stock#DSxxxxxxxx 2001 Fairchild Semiconductor Corporation