GS8324Z18C-200T - Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

2M x 18, 1M x 36, 512K x 72

36Mb Sync NBT SRAMs

250 MHz–133MHz

2.5 V or 3.3 V VDD

2.5 V or 3.3 V I/O

119- and 209-Pin BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• FT pin for user-configurable flow through or pipeline operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 209-bump BGA package

Functional Description

Applications

The GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die

synchronous SRAM module with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device now

finds application in synchronous SRAM applications, ranging

from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS8324Z18/36/72 operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output power

(VDDQ) pins are used to decouple output noise from the internal

circuits and are 3.3 V and 2.5 V compatible.

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1 tKQ

tCycle 2.3

4.0 2.5

4.4 3.0

5.0 3.5

6.0 3.8

6.6 4.0

7.5 ns

3.3 V Curr (x18)

Curr (x36)

Curr (x72)

365

560

660

335

510

600

305

460

540

265

400

460

245

370

430

215

330

380

2.5 V Curr (x18)

Curr (x36)

Curr (x72)

360

550

640

330

500

590

305

460

530

260

390

450

240

360

420

215

330

370

Flow

Through

2-1-1-1

tKQ

tCycle 6.0

7.0 6.5

7.5 7.5

8.5 8.5

10 10

10 11

15 ns

3.3 V Curr (x18)

Curr (x36)

Curr (x72)

235

300

350

230

300

350

210

270

300

200

270

300

195

270

300

150

200

220

2.5 V Curr (x18)

Curr (x36)

Curr (x72)

235

300

340

230

300

340

210

270

300

200

270

300

195

270

300

145

190

220

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z72B Pad Out

209-Bump BGA—Top View

1234567 8 9 10 11

ADQG5 DQG1 A13 E2 A14 ADV A15 E3 A17 DQB1 DQB5 A

BDQG6 DQG2 BCBGNC WA16 BBBFDQB2 DQB6 B

CDQG7 DQG3 BHBD NC E1 NC BEBADQB3 DQB7 C

DDQG8 DQG4 VSS NC NC GNC NC VSS DQB4 DQB8 D

EDQPG9 DQPC9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPF9 DQPB9 E

FDQC4 DQC8 VSS VSS VSS ZQ VSS VSS VSS DQF8 DQF4 F

GDQC3 DQC7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQF7 DQF3 G

HDQC2 DQC6 VSS VSS VSS MCL VSS VSS VSS DQF6 DQF2 H

JDQC1 DQC5 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQF5 DQF1 J

KNC NC CK NC VSS MCL VSS NC NC NC NC K

LDQH1 DQH5 VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA5 DQA1 L

MDQH2 DQH6 VSS VSS VSS MCL VSS VSS VSS DQA6 DQA2 M

NDQH3 DQH7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQA7 DQA3 N

PDQH4 DQH8 VSS VSS VSS ZZ VSS VSS VSS DQA8 DQA4 P

RDQPD9 DQPH9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPA9 DQPE9 R

TDQD8 DQD4 VSS NC NC LBO PE NC VSS DQE4 DQE8 T

UDQD7 DQD3 NC A12 NC A11 A18 A10 NC DQE3 DQE7 U

VDQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 DQE2 DQE6 V

WDQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK DQE1 DQE5 W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z36C Pad Out

209-Bump BGA—Top View

1234567 8 9 10 11

ANC NC A13 E2 A14 ADV A15 E3 A17 DQB1 DQB5 A

BNC NC BC NC A19 WA16 BBNC DQB2 DQB6 B

CNC NC NC BD NC E1 NC NC BADQB3 DQB7 C

DNC NC VSS NC NC GNC NC VSS DQB4 DQB8 D

ENC DQPC9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ NC DQPB9 E

FDQC4 DQC8 VSS VSS VSS ZQ VSS VSS VSS NC NC F

GDQC3 DQC7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ NC NC G

HDQC2 DQC6 VSS VSS VSS MCL VSS VSS VSS NC NC H

JDQC1 DQC5 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ NC NC J

KNC NC CK NC VSS MCL VSS NC NC NC NC K

LNC NC VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA5 DQA1 L

MNC NC VSS VSS VSS MCL VSS VSS VSS DQA6 DQA2 M

NNC NC VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQA7 DQA3 N

PNC NC VSS VSS VSS ZZ VSS VSS VSS DQA8 DQA4 P

RDQPD9 NC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPA9 NC R

TDQD8 DQD4 VSS NC NC LBO PE NC VSS NC NC T

UDQD7 DQD3 NC A12 NC A11 A18 A10 NC NC NC U

VDQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 NC NC V

WDQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK NC NC W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18C Pad Out

209-Bump BGA—Top View

1234567 8 9 10 11

ANC NC A13 VDD A14 ADV A15 VSS A17 NC NC A

BNC NC BBNC A19 WA16 NC NC NC NC B

CNC NC NC NC NC E1 A20 NC BANC NC C

DNC NC VSS NC NC GNC NC VSS NC NC D

ENC DQPB9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ NC NC E

FDQB4 DQB8 VSS VSS VSS ZQ VSS VSS VSS NC NC F

GDQB3 DQB7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ NC NC G

HDQB2 DQB6 VSS VSS VSS MCL VSS VSS VSS NC NC H

JDQB1 DQB5 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ NC NC J

KNC NC CK NC VSS MCL VSS NC NC NC NC K

LNC NC VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA5 DQA1 L

MNC NC VSS VSS VSS MCL VSS VSS VSS DQA6 DQA2 M

NNC NC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQA7 DQA3 N

PNC NC VSS VSS VSS ZZ VSS VSS VSS DQA8 DQA4 P

RNC NC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPA9 NC R

TNC NC VSS NC NC LBO PE NC VSS NC NC T

UNC NC NC A12 NC A11 A18 A10 NC NC NC U

VNC NC A9 A8 A7 A1 A6 A5 A4 NC NC V

WNC NC TMS TDI A3 A0 A2 TDO TCK NC NC W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18/36/72 209-Bump BGA Pin Description

Pin Location Symbol Type Description

W6, V6 A0, A1IAddress field LSBs and Address Counter Preset Inputs.

W7, W5, V9, V8, V7, V5, V4, V3, U8, U6, U4,

A3, A5, A7, B7, A9, U7 An IAddress Inputs

B5 A19 IAddress Inputs (x36/x18 Versions)

C7 A20 IAddress Inputs (x18 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10

A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1

L1, M1, N1, P1, L2, M2, N2, P2, R2

DQA1–DQA9

DQB1–DQB9

DQC1–DQC9

DQD1–DQD9

DQE1–DQE9

DQF1–DQF9

DQG1–DQG9

DQH1–DQH9

I/O Data Input and Output pins (x72 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10

A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

DQA1–DQA9

DQB1–DQB9

DQC1–DQC9

DQD1–DQD9

I/O Data Input and Output pins (x36 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10

J1, H1, G1, F1, J2, H2, G2, F2, E2 DQA1–DQA9

DQB1–DQB9 I/O Data Input and Output pins (x18 Version)

C9, B8 BA, BBIByte Write Enable for DQA, DQB I/Os; active low

B3, C4 BC,BDIByte Write Enable for DQC, DQD I/Os; active low

(x72/x36 Versions)

C8, B9, B4, C3 BE, BF, BG,BHIByte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

(x72 Version)

B5 NC —No Connect (x72 Version)

C7 NC —No Connect (x72/x36 Versions)

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1

L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,

B4, C3

NC —No Connect (x36/x18 Versions)

B3, C4 NC —No Connect (x18 Version)

C5, D4, D5, D7, D8, K1, K2, K4, K8, K9, K10,

K11, T4, T5, T7, T8, U3, U5, U9 NC —No Connect

K3 CK IClock Input Signal; active high

C6 E1IChip Enable; active low

A8 E3IChip Enable; active low (x72/x36 Versions)

A4 E2IChip Enable; active high (x72/x36 Versions)

D6 GIOutput Enable; active low

A6 ADV IBurst address counter advance enable

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

P6 ZZ ISleep Mode control; active high

L6 FT IFlow Through or Pipeline mode; active low

T6 LBO ILinear Burst Order mode; active low

G6, J6 MCH IMust Connect High

N6 MCH IMust Connect High (x72 and x36 versions)

H6, J6, K6, M6 MCL Must Connect Low

A8, N6 MCL Must Connect Low (x18 version)

B6 WIWrite Enable; active low

T7 PE IParity Bit Enable; active low (High = x16/32 Mode, Low = x18/36

Mode)

F6 ZQ IFLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

W3 TMS IScan Test Mode Select

W4 TDI IScan Test Data In

W8 TDO OScan Test Data Out

W9 TCK IScan Test Clock

A4, N6 VDD ICore power supply (x18 version)

E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,

R6, R7 VDD ICore power supply

D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,

H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,

P4, P5, P7, P8, P9, T3, T9 VSS II/O and Core Ground

E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9,

L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9 VDDQ IOutput driver power supply

GS8324Z18/36/72 209-Bump BGA Pin Description

Pin Location Symbol Type Description

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z36B Pad Out

119-Bump BGA—Top View

1234567

AVDDQ A6 A7 A18 A8 A9 VDDQ A

BNC E2 A4 ADV A15 E3 NC B

C NC A5 A3 VDD A14 A16 NC C

DDQC DQPC VSS ZQ VSS DQPB DQB D

EDQC DQC VSS E1 VSS DQB DQB E

FVDDQ DQC VSS GVSS DQB VDDQ F

GDQC DQC BCA17 BBDQB DQB G

HDQC DQC VSS WVSS DQB DQB H

JVDDQ VDD NC VDD NC VDD VDDQ J

KDQD DQD VSS CK VSS DQA DQA K

LDQD DQD BD NC BADQA DQA L

MVDDQ DQD VSS CKE VSS DQA VDDQ M

NDQD DQD VSS A1 VSS DQA DQA N

PDQD DQPD VSS A0 VSS DQPA DQA P

R NC A2 LBO VDD FT A13 PE R

TNC NC A10 A11 A12 A19 ZZ T

UVDDQ TMS TDI TCK TDO NC VDDQ U

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18B Pad Out

119-Bump BGA—Top View

1234567

AVDDQ A6 A7 A18 A8 A9 VDDQ A

BNC VDD A4 ADV A15 VSS NC B

C NC A5 A3 VDD A14 A16 NC C

DDQB NC VSS ZQ VSS DQPA NC D

ENC DQB VSS E1 VSS NC DQA E

FVDDQ NC VSS GVSS DQA VDDQ F

GNC DQB BBA17 NC NC DQA G

HDQB NC VSS WVSS DQA NC H

JVDDQ VDD NC VDD NC VDD VDDQ J

KNC DQB VSS CK VSS NC DQA K

LDQB NC NC VDD BADQA NC L

MVDDQ DQB VSS CKE VSS NC VDDQ M

NDQB NC VSS A1 VSS DQA NC N

PNC DQPB VSS A0 VSS NC DQA P

R NC A2 LBO VDD FT A13 PE R

TNC A10 A11 A20 A12 A19 ZZ T

UVDDQ TMS TDI TCK TDO NC VDDQ U

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18/36 119-Bump BGA Pin Description

Pin Location Symbol Type Description

P4, N4 A0, A1IAddress field LSBs and Address Counter Preset Inputs

R2, C3, B3, C2, A2, A3, A5, A6, T3,

T5, R6, C5, B5, C6, G4, A4 An IAddress Inputs

T4, T6 An Address Input (x36 Version)

T2 NC —No Connect (x36 Version)

T2, T6, T4 An IAddress Input (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6

H7, G7, E7, D7, H6, G6, F6, E6

H1, G1, E1, D1, H2, G2, F2, E2

K1, L1, N1, P1, K2, L2, M2, N2

DQA1–DQA8

DQB1–DQB8

DQC1–DQC8

DQD1–DQD8

I/O Data Input and Output pins. (x36 Version)

P6, D6, D2, P2 DQA9, DQB9,

DQC9, DQD9 I/O Data Input and Output pins. (x36 Version)

L5, G5, G3, L3 BA, BB, BC, BDIByte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2 DQA1–DQA9

DQB1–DQB9 I/O Data Input and Output pins (x18 Version)

L5, G3 BA, BBIByte Write Enable for DQA, DQB I/Os; active low (x18 Version)

B1, C1, R1, T1, U6, B7, C7, J3, J5 NC —No Connect

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3 NC —No Connect (x18 Version)

L4 NC —No Connect (x36 Version)

K4 CK IClock Input Signal; active high

M4 CKE IClock Enable; active low

H4 WIWrite Enable; active low

E4 E1IChip Enable; active low

B6 E3IChip Enable; active low (x36 version)

B2 E2IChip Enable; active high (x36 version)

F4 GIOutput Enable; active low

B4 ADV IBurst address counter advance enable

T7 ZZ ISleep mode control; active high

R5 FT IFlow Through or Pipeline mode; active low

R3 LBO ILinear Burst Order mode; active low

D4 ZQ IFLXDrive Output Impedance Control (Low = Low Impedance [High Drive],

High = High Impedance [Low Drive])

R7 PE IParity Bit Enable; active low

U2 TMS IScan Test Mode Select

U3 TDI IScan Test Data In

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

U5 TDO OScan Test Data Out

U4 TCK IScan Test Clock

J2, C4, J4, R4, J6 VDD ICore power supply

B2, L4 VDD ICore power supply (x18 version)

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5 VSS II/O and Core Ground

B6 VSS II/O and Core Ground (x18 version)

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7 VDDQ IOutput driver power supply

GS8324Z18/36 119-Bump BGA Pin Description

Pin Location Symbol Type Description

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18/36/72 Block Diagram

A0 A0

A1 D0

D1 Q1

Counter

Load

A0–An

LBO

ADV

ADSC

ADSP

ZZ Power Down

Control

Memory

Array

36 36

DQx0–DQx9

Note: Only x36 version shown for simplicity.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Inputs

TDO TDI TDOTDI

18 I/Os

Die A

x18

16Mb

Die B

x18

16Mb

GS8324Z18 Die Layout

Inputs

TDO TDI TDOTDI

18 I/Os 18 I/Os

Die A

x18

16Mb

Die B

x18

16Mb

GS8324Z36 Die Layout

Inputs

TDO TDI TDOTDI

36 I/Os 36 I/Os

Die A

x36

32Mb

Die B

x36

32Mb

GS8324Z72 Die Layout

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle

read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device

activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable

inputs will deactivate the device.

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three

chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control

logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At

the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.

The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write

cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,

matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At

the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is

required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the

use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after

new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow

Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability

to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late

write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address

and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of

clock.

Function WBABBBCBD

Read HX X X X

Write Byte “a” L L H H H

Write Byte “b” LHLH H

Write Byte “c” LH H LH

Write Byte “d” LHHHL

Write all Bytes L L L L L

Write Abort/NOP LH H H H

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Byte Write Truth Table

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Function GW BW BABBBCBDNotes

Read H H XXXX1

Read HLHHHH1

Write byte a HL L HHH2, 3

Write byte b HLHLH H 2, 3

Write byte c HLH H LH2, 3, 4

Write byte d HLHHHL2, 3, 4

Write all bytes HLLLLL2, 3, 4

Write all bytes LXXXXX

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Synchronous Truth Table (x72 and x36 209-Bump BGA)

Operation Type Address E1E2E3ZZ ADV WBx GCKE CK DQ Notes

Deselect Cycle, Power Down DNone HX X L L X X X LL-H High-Z

Deselect Cycle, Power Down DNone X X HL L X X X LL-H High-Z

Deselect Cycle, Power Down DNone XLXL L X X X LL-H High-Z

Deselect Cycle, Continue DNone XXXLHX X X LL-H High-Z 1

Read Cycle, Begin Burst RExternal LHL L L HXL L L-H Q

Read Cycle, Continue Burst BNext XXXLHX X L L L-H Q1,10

NOP/Read, Begin Burst RExternal LHL L L HXHLL-H High-Z 2

Dummy Read, Continue Burst BNext XXXLHX X HLL-H High-Z 1,2,10

Write Cycle, Begin Burst WExternal LHL L L L L XLL-H D3

Write Cycle, Continue Burst BNext XXXLHXLXLL-H D1,3,10

NOP/Write Abort, Begin Burst WNone LHL L L L HXLL-H High-Z 2,3

Write Abort, Continue Burst BNext XXXLHXHXLL-H High-Z 1,2,3,10

Clock Edge Ignore, Stall Current XXXLX X X X HL-H -4

Sleep Mode None XXXHX X X X X X High-Z

Notes:

1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered into if a

Deselect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin

is sampled low but no Byte Write pins are active, so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write

cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals

are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Synchronous Truth Table (x18 209-Bump BGA and x36/x18 119-Bump BGA)

Operation Type Address E1ZZ ADV WBx GCKE CK DQ Notes

Deselect Cycle, Power Down DNone HL L X X X LL-H High-Z

Deselect Cycle, Power Down DNone XL L X X X LL-H High-Z

Deselect Cycle, Continue DNone XLHX X X LL-H High-Z 1

Read Cycle, Begin Burst RExternal L L L HXL L L-H Q

Read Cycle, Continue Burst BNext XLHX X L L L-H Q1,10

NOP/Read, Begin Burst RExternal L L L HXHLL-H High-Z 2

Dummy Read, Continue Burst BNext XLHX X HLL-H High-Z 1,2,10

Write Cycle, Begin Burst WExternal L L L L L XLL-H D3

Write Cycle, Continue Burst BNext XLHXLXLL-H D1,3,10

NOP/Write Abort, Begin Burst WNone L L L L HXLL-H High-Z 2,3

Write Abort, Continue Burst BNext XLHXHXLL-H High-Z 1,2,3,10

Clock Edge Ignore, Stall Current XLX X X X HL-H -4

Sleep Mode None XHX X X X X X High-Z

Notes:

1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered

into if a Deselect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs

when the W pin is sampled low but no Byte Write pins are active, so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off

during write cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write

cycle, the bus will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/

Write signals are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Deselect

New Read New Write

Burst Read Burst Write

Pipelined and Flow Through Read Write Control State Diagram

Current State (n) Next State (n+1)

Transition

Input Command Code

Key Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

Clock (CK)

Command

Current State Next State

nn+1 n+2 n+3

ƒƒƒ

Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Intermediate Intermediate

Intermediate

Intermediate Intermediate

Intermediate

High Z

(Data In) Data Out

(Q Valid)

High Z

BWB

Pipeline Mode Data I/O State Diagram

Current State (n) Next State (n+2)

Transition

Input Command Code

Key

Transition

Intermediate State (N+1)

Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Clock (CK)

Command

Current State Intermediate

nn+1 n+2 n+3

ƒƒƒ

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Next State

State

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

High Z

(Data In) Data Out

(Q Valid)

High Z

BWB

Current State (n) Next State (n+1)

Transition

Input Command Code

Key Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Flow Through Mode Data I/O State Diagram

Clock (CK)

Command

Current State Next State

nn+1 n+2 n+3

ƒƒƒ

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from

read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address

generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when

driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write

the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into

Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been

accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst

sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables

below for details.

Note:

There are pull-up devices on the ZQ, SCD DP, and FT pins and a pull-down devices on the PE and ZZ pins, so those input pins can

be unconnected and the chip will operate in the default states as specified in the above tables.

Enable/Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,

x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE

deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits

generated and read into the ByteSafe parity circuits.

Mode Pin Functions

Mode Name Pin

Name State Function

Burst Order Control LBO LLinear Burst

HInterleaved Burst

Output Register Control FT LFlow Through

H or NC Pipeline

Power Down Control ZZ L or NC Active

H Standby, IDD = ISB

Parity Enable PE L or NC Activate 9th I/O’s (x18/36 Mode)

HDeactivate 9th I/O’s (x16/32 Mode)

FLXDrive Output Impedance Control ZQ LHigh Drive (Low Impedance)

H or NC Low Drive (High Impedance)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

x16/32/64 Mode (PE = 0) Read Parity Error Output Timing Diagram

Address A Address B Address C Address D Address E Address F

D Out A D Out B D Out C D Out D D Out E

tKQ

tHZ

tKQX

tLZ

Flow Through ModePipelined Mode

D Out A D Out B D Out C D Out D

tKQ

tHZ

tKQX

tLZ

QE Err A

Err A Err C

Err C

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

x18/x36 Mode (PE = 1) Write Parity Error Output Timing Diagram

BPR 1999.05.18

Burst Counter Sequences

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

D In A D In B D In C D In D D In E

tKQ

tHZ

tKQX

tLZ

Flow Through ModePipelined Mode

tKQ

tHZ

tKQX

tLZ

D In A D In B D In C D In D D In E

Err A

Err A Err C

Err C

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal

found on . Not all vendors offer this option, however most mark as VDD or VDDQ on pipelined parts and VSS on flow through

parts. GSI NBT SRAMs are fully compatible with these sockets.

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

VDD Voltage on VDD Pins –0.5 to 4.6 V

VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V

VCK Voltage on Clock Input Pin –0.5 to 6 V

VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V

VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V

IIN Input Current on Any Pin +/–20 mA

IOUT Output Current on Any I/O Pin +/–20 mA

PDPackage Power Dissipation 1.5 W

TSTG Storage Temperature –55 to 125 oC

TBIAS Temperature Under Bias –55 to 125 oC

ZZ tZZR

tZZH

tZZS

Sleep

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V

2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V

3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V

2.5 V VDDQ I/O Supply Voltage VDDQ2 2.4 2.5 2.7 V

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

VDDQ3 Range Logic Levels

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage VIH 1.7 —VDD + 0.3 V1

VDD Input Low Voltage VIL –0.3 —0.8 V1

VDDQ I/O Input High Voltage VIHQ 1.7 —VDDQ + 0.3 V1,3

VDDQ I/O Input Low Voltage VILQ –0.3 —0.8 V1,3

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.

VDDQ2 Range Logic Levels

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V1

VDD Input Low Voltage VIL –0.3 —0.3*VDD V1

VDDQ I/O Input High Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V1,3

VDDQ I/O Input Low Voltage VILQ –0.3 —0.3*VDD V1,3

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Note: These parameters are sample tested.

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-

ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Ambient Temperature (Commercial Range Versions) TA0 25 70 °C2

Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C2

Note:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Capacitance

(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance CIN VIN = 0 V 6.5 7.5 pF

Input/Output Capacitance (x36/x72) CI/O VOUT = 0 V 6 7 pF

Input/Output Capacitance (x18) CI/O VOUT = 0 V 8.5 9.5 pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2

Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2

Junction to Case (TOP) —RΘJC 9°C/W 3

20% tKC

SS – 2.0 V

50%

VSS

VIH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

VDD + 2.0 V

50%

VDD

VIL

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

Output load Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig.

1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ

4. Device is deselected as defined by the Truth Table.

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA

ZZ and PE Input Current IIN1VDD ≥ VIN ≥ VIH

0 V ≤ VIN ≤ VIH

–1 uA

–1 uA 1 uA

100 uA

FT, SCD, ZQ, DP Input Current IIN2VDD ≥ VIN ≥ VIL

0 V ≤ VIN ≤ VIL

–100 uA

–1 uA 1 uA

1 uA

Output Leakage Current (x36/x72) IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA

Output Leakage Current (x18) IOL Output Disable, VOUT = 0 to VDD –2 uA 2 uA

Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —

Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V —

Output Low Voltage VOL IOL = 8 mA —0.4 V

VT = 1.25 V

50Ω30pF*DQ

2.5 V

Output Load 1 Output Load 2

225Ω

5pF*

* Distributed Test Jig Capacitance

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Operating Currents

Notes:

1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.

2. All parameters listed are worst case scenario.

Parameter Test Conditions Mode Symbol

-250 -225 -200 -166 -150 -133

Unit

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

Operating

Current

3.3 V

Device Selected;

All other inputs

≥VIH or ≤ VIL

Output open

(x72)

Pipeline IDD

IDDQ

580

80 560

80 530

70 550

70 480

60 500

60 410

50 430

50 380

50 400

50 340

40 360

40 mA

Flow

Through IDD

IDDQ

310

40 330

40 340

40 330

40 270

30 290

30 270

30 290

30 270

30 290

30 200

20 220

20 mA

(x36)

Pipeline IDD

IDDQ

520

40 540

40 470

40 490

40 430

30 450

30 370

30 390

30 340

30 360

30 310

20 330

20 mA

Flow

Through IDD

IDDQ

280

20 300

20 280

20 300

20 250

20 270

20 350

20 270

20 250

20 270

20 180

20 200

20 mA

(x18)

Pipeline IDD

IDDQ

345

20 360

20 315

20 330

20 290

15 305

15 250

15 265

15 230

15 245

15 205

10 220

10 mA

Flow

Through IDD

IDDQ

200

10 215

10 200

10 215

10 175

10 190

10 175

10 190

10 175

10 190

10 135

10 150

10 mA

Operating

Current

2.5 V

Device Selected;

All other inputs

≥VIH or ≤ VIL

Output open

(x72)

Pipeline IDD

IDDQ

580

60 600

60 530

60 550

60 480

50 500

50 410

40 430

40 380

40 400

40 340

30 360

30 mA

Flow

Through IDD

IDDQ

310

30 330

30 310

30 330

30 270

30 290

30 270

30 290

30 270

30 290

30 200

20 220

20 mA

(x36)

Pipeline IDD

IDDQ

520

30 540

30 470

30 490

30 430

30 450

30 370

20 390

20 340

20 360

20 310

20 330

20 mA

Flow

Through

IDD

IDDQ

280

20 300

20 280

20 300

20 250

20 270

20 250

20 270

20 250

20 270

20 180

10 200

10 mA

(x18)

Pipeline IDD

IDDQ

345

15 360

15 315

15 330

15 290

15 305

15 250

10 265

10 230

10 245

10 205

10 220

10 mA

Flow

Through IDD

IDDQ

200

10 215

10 200

10 215

10 175

10 190

10 175

10 190

10 175

10 190

10 135

5150

5mA

Standby

Current ZZ ≥ VDD – 0.2 V —Pipeline ISB 40 60 40 60 40 60 40 60 40 60 40 60 mA

Flow

Through ISB 40 60 40 60 40 60 40 60 40 60 40 60 mA

Deselect

Current

Device Deselected;

All other inputs

≥ VIH or ≤ VIL

—Pipeline IDD 170 180 160 170 150 160 130 140 120 130 100 110 mA

Flow

Through IDD 120 130 120 130 100 110 100 110 100 110 90 100 mA

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

AC Electrical Characteristics

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Parameter Symbol -250 -225 -200 -166 -150 -133 Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Pipeline

Clock Cycle Time tKC 4.0 —4.4 —5.0 —6.0 —6.7 —7.5 —ns

Clock to Output Valid tKQ —2.3 —2.5 —3.0 —3.4 —3.8 —4.0 ns

Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —1.5 —1.5 —1.5 —ns

Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —1.5 —1.5 —1.5 —ns

Flow

Through

Clock Cycle Time tKC 7.0 —7.5 —8.5 —10.0 —10.0 —15.0 —ns

Clock to Output Valid tKQ —6.0 —6.0 —7.5 —8.5 —10.0 —10.0 ns

Clock to Output Invalid tKQX 3.0 —3.0 —3.0 —3.0 —3.0 —3.0 —ns

Clock to Output in Low-Z tLZ13.0 —3.0 —3.0 —3.0 —3.0 —3.0 —ns

Clock HIGH Time tKH 1.3 —1.3 —1.3 —1.3 —1.5 —1.7 —ns

Clock LOW Time tKL 1.5 —1.5 —1.5 —1.5 —1.7 —2—ns

Clock to Output in

High-Z tHZ11.5 2.3 1.5 2.5 1.5 3.0 1.5 3.5 1.5 3.8 1.5 4.0 ns

G to Output Valid tOE —2.3 —2.5 —3.2 —3.5 —3.8 —4.0 ns

G to output in Low-Z tOLZ10—0—0—0—0—0—ns

G to output in High-Z tOHZ1—2.3 —2.5 —3.0 —3.5 —3.8 —4.0 ns

Setup time tS 1.5 —1.5 —1.5 —1.5 —1.5 —1.5 —ns

Hold time tH 0.5 —0.5 —0.5 —0.5 —0.5 —0.5 —ns

ZZ setup time tZZS25—5—5—5—5—5—ns

ZZ hold time tZZH21—1—1—1—1—1—ns

ZZ recovery tZZR 100 —100 —100 —100 —100 —100 —ns

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Pipeline Mode Read/Write Cycle Timing

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

CKE

ADV

tKH

tKL tKC

A0–An A1

A2 A3

D(A1)

D(A2)

Q(A3) QQ(A6)

DD(A5)

tKQLZ

tKQ tKQHZ

tOEHZ tOELZ

tKQX

tKHQZ

tGLQV

1 2 3 4 5 6 7 8 9 10

COMMAND Write

D(A1) Write

D(A2) BURST

Write

D(A2+1)

Read

Q(A3) Read

Q(A4) BURST

Read

Q(A4+1)

Write

D(A5) Read

Q(A6) Write

D(A7) DESELECT

DON’T CARE UNDEFINED

DQA–DQD

A4 A5 A6 A7

Q(A4)

(A4+1)

(A2+1)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Pipeline Mode No-Op, Stall and Deselect Timing

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

CKE

ADV

A0–An A1 A5

D(A1) Q(A2) Q(A3) Q(A5)

12345 6 78910

COMMAND Write

D(A1) Read

Q(A2) STALL Read

Q(A3) Write

D(A4) STALL NOP Read

Q(A5) CONTINUE

DON’T CARE UNDEFINED

D(A4)

tKHQZ

tKQHZ

DESELECT DESELECT

A2 A3 A4

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Flow Through Mode Read/Write Cycle Timing

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

CKE

ADV

tKH

tKL tKC

A0–An

1 2 345678910

COMMAND Write

D(A1) Write

D(A2) BURST

Write

D(A2+1)

Read

Q(A3) Read

Q(A4) BURST

Read

Q(A4+1)

Write

D(A5) Read

Q(A6) Write

D(A7) DESELECT

DON’T CARE UNDEFINED

A1 A2 A3 A4 A5 A6

D(A1)

D(A2)

Q(A3) QQ(A6)

DD(A5)

tKQLZ

tKQ tKQHZ

tOEHZ tOELZ

tKQX

tKHQZ

tGLQV

Q(A4)

(A4+1)

(A2+1)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Flow Through Mode No-Op, Stall and Deselect Timing

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

CKE

ADV

A0–An

Q(A5)

1 2 345 6 78910

COMMAND Write

D(A1) Read

Q(A2) STALL Read

Q(A3) Write

D(A4) STALL NOP Read

Q(A5) CONTINUE

DON’T CARE UNDEFINED

D(A4)

tKHQZ

tKQHZ

DESELECT DESELECT

D(A1) Q(A2) Q(A3)

A1 A5A2 A3 A4

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

JTAG Port Operation

Due to the fact that this device is built from two die, the two JTAG parts are chained together internally. The following describes

the behavior of each die.

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output

drivers are powered by VDDQ.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

TDI Test Data In In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

TDO Test Data Out Out Output that is active depending on the state of the TAP state machine. Output changes in

response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Instruction Register

ID Code Register

Boundary Scan Register

012

· · · ·

31 30 29

012

· · ·

· · ·· · ·

Bypass Register

TDI TDO

TMS

TCK Test Access Port (TAP) Controller

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

ID Register Contents

Die

Revision

Code Not Used I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1

x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1

x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1

x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1

x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when

the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices

in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-

tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan

Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the

Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it

is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although

allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be

stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be

paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-

DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s.

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle 0

0 0

11 0

1 1 1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input

pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST

command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK

when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,

the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-

ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the

value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID

register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any

time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the

Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFUThese instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

Forces all RAM output drivers to High-Z. 1

RFU 011 Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1

SAMPLE/

PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO. 1

GSI 101 GSI private instruction. 1

RFU 110 Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V1

3.3 V Test Port Input Low Voltage VILJ3 –0.3 0.8 V1

2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V1

2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V1

TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2

TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3

TDO Output Leakage Current IOLJ –1 1 uA 4

Test Port Output High Voltage VOHJ 1.7 —V5, 6

Test Port Output Low Voltage VOLJ —0.4 V5, 7

Test Port Output CMOS High VOHJC VDDQ – 100 mV —V5, 8

Test Port Output CMOS Low VOLJC —100 mV V5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. VILJ ≤ VIN ≤ VDDn

3. 0 V ≤ VIN ≤ VILJn

4. Output Disable, VOUT = 0 to VDDn

5. The TDO output driver is served by the VDDQ supply.

6. IOHJ = –4 mA

7. IOLJ = + 4 mA

8. IOHJC = –100 uA

9. IOHJC = +100 uA

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

JTAG Port AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

VT = 1.25 V

50Ω30pF*

JTAG Port AC Test Load

* Distributed Test Jig Capacitance

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

JTAG Port Timing Diagram

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 —ns

TCK Low to TDO Valid tTKQ —20 ns

TCK High Pulse Width tTKH 20 —ns

TCK Low Pulse Width tTKL 20 —ns

TDI & TMS Set Up Time tTS 10 —ns

TDI & TMS Hold Time tTH 10 —ns

tTKQ

tTS tTH

tTKH tTKL

TCK

TMS

TDI

TDO

tTKC

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Notes:

1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1,

PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1.

2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.

3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control

is effective after JTAG EXTEST instruction is executed.

4. 1 = no connect, internally set to logic value 1

5. 0 = no connect, internally set to logic value 0

6. X = no connect, value is undefined

GS8324Z18/36/72 Boundary Scan Chain Order

Order x72 x36 x18 Bump

x72 x36 x18

1(TBD)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

209 BGA Package Drawing

14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array

Symbol Min Typ Max Units

A1.70 mm

A1 0.40 0.50 0.60 mm

∅b0.50 0.60 0.70 mm

c0.31 0.36 0.38 mm

D21.9 22.0 22.1 mm

D1 18.0 (BSC) mm

E13.9 14.0 14.1 mm

E1 10.0 (BSC) mm

e1.00 (BSC) mm

aaa 0.15 mm

Rev 1.0

∅be

aaa

Bottom View

Side View

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Package Dimensions—119-Pin PBGA

Pin 1

Corner

C T

1234567

Package Dimensions—119-Pin PBGA

Unit: mm

Symbol Description Min. Nom. Max

AWidth 13.9 14.0 14.1

BLength 21.9 22.0 22.1

CPackage Height (including ball) 1.73 1.86 1.99

DBall Size 0.60 0.75 0.90

EBall Height 0.50 0.60 0.70

FPackage Height (excluding balls) 1.16 1.26 1.36

GWidth between Balls 1.27

KPackage Height above board 0.65 0.70 0.75

RWidth of package between balls 7.62

SLength of package between balls 20.32

TVariance of Ball Height 0.15

Bottom View

Top View

Side View

119-Bump BGA Package

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Ordering Information for GSI Synchronous NBT SRAMs

Org Part Number1Type Package Speed2

(MHz/ns) TA3

2M x 18 GS8324Z18B-250 Pipeline/Flow Through 119 BGA 250/6 C

2M x 18 GS8324Z18B-225 Pipeline/Flow Through 119 BGA 225/6.5 C

2M x 18 GS8324Z18B-200 Pipeline/Flow Through 119 BGA 200/7.5 C

2M x 18 GS8324Z18B-166 Pipeline/Flow Through 119 BGA 166/8.5 C

2M x 18 GS8324Z18B-150 Pipeline/Flow Through 119 BGA 150/10 C

2M x 18 GS8324Z18B-133 Pipeline/Flow Through 119 BGA 133/11 C

2M x 18 GS8324Z18C-250 Pipeline/Flow Through 209 BGA 250/6 C

2M x 18 GS8324Z18C-225 Pipeline/Flow Through 209 BGA 225/6.5 C

2M x 18 GS8324Z18C-200 Pipeline/Flow Through 209 BGA 200/7.5 C

2M x 18 GS8324Z18C-166 Pipeline/Flow Through 209 BGA 166/8.5 C

2M x 18 GS8324Z18C-150 Pipeline/Flow Through 209 BGA 150/10 C

2M x 18 GS8324Z18C-133 Pipeline/Flow Through 209 BGA 133/11 C

1M x 36 GS8324Z36B-250 Pipeline/Flow Through 119 BGA 250/6 C

1M x 36 GS8324Z36B-225 Pipeline/Flow Through 119 BGA 225/6.5 C

1M x 36 GS8324Z36B-200 Pipeline/Flow Through 119 BGA 200/7.5 C

1M x 36 GS8324Z36B-166 Pipeline/Flow Through 119 BGA 166/8.5 C

1M x 36 GS8324Z36B-150 Pipeline/Flow Through 119 BGA 150/10 C

1M x 36 GS8324Z36B-133 Pipeline/Flow Through 119 BGA 133/11 C

1M x 36 GS8324Z36C-250 Pipeline/Flow Through 209 BGA 250/6 C

1M x 36 GS8324Z36C-225 Pipeline/Flow Through 209 BGA 225/6.5 C

1M x 36 GS8324Z36C-200 Pipeline/Flow Through 209 BGA 200/7.5 C

1M x 36 GS8324Z36C-166 Pipeline/Flow Through 209 BGA 166/8.5 C

1M x 36 GS8324Z36C-150 Pipeline/Flow Through 209 BGA 150/10 C

1M x 36 GS8324Z36C-133 Pipeline/Flow Through 209 BGA 133/11 C

512K x 72 GS8324Z72C-250 Pipeline/Flow Through 209 BGA 250/6 C

512K x 72 GS8324Z72C-225 Pipeline/Flow Through 209 BGA 225/6.5 C

512K x 72 GS8324Z72C-200 Pipeline/Flow Through 209 BGA 200/7.5 C

512K x 72 GS8324Z72C-166 Pipeline/Flow Through 209 BGA 166/8.5 C

512K x 72 GS8324Z72C-150 Pipeline/Flow Through 209 BGA 150/10 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8324Z18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

512K x 72 GS8324Z72C-133 Pipeline/Flow Through 209 BGA 133/11 C

2M x 18 GS8324Z18B-250I Pipeline/Flow Through 119 BGA 250/6 I

2M x 18 GS8324Z18B-225I Pipeline/Flow Through 119 BGA 225/6.5 I

2M x 18 GS8324Z18B-200I Pipeline/Flow Through 119 BGA 200/7.5 I

2M x 18 GS8324Z18B-166I Pipeline/Flow Through 119 BGA 166/8.5 I

2M x 18 GS8324Z18B-150I Pipeline/Flow Through 119 BGA 150/10 I

2M x 18 GS8324Z18B-133I Pipeline/Flow Through 119 BGA 133/11 I

2M x 18 GS8324Z18C-250I Pipeline/Flow Through 209 BGA 250/6 I

2M x 18 GS8324Z18C-225I Pipeline/Flow Through 209 BGA 225/6.5 I

2M x 18 GS8324Z18C-200I Pipeline/Flow Through 209 BGA 200/7.5 I

2M x 18 GS8324Z18C-166I Pipeline/Flow Through 209 BGA 166/8.5 I

2M x 18 GS8324Z18C-150I Pipeline/Flow Through 209 BGA 150/10 I

2M x 18 GS8324Z18C-133I Pipeline/Flow Through 209 BGA 133/11 I

1M x 36 GS8324Z36B-250I Pipeline/Flow Through 119 BGA 250/6 I

1M x 36 GS8324Z36B-225I Pipeline/Flow Through 119 BGA 225/6.5 I

1M x 36 GS8324Z36B-200I Pipeline/Flow Through 119 BGA 200/7.5 I

1M x 36 GS8324Z36B-166I Pipeline/Flow Through 119 BGA 166/8.5 I

1M x 36 GS8324Z36B-150I Pipeline/Flow Through 119 BGA 150/10 I

1M x 36 GS8324Z36B-133I Pipeline/Flow Through 119 BGA 133/11 I

1M x 36 GS8324Z36C-250I Pipeline/Flow Through 209 BGA 250/6 I

1M x 36 GS8324Z36C-225I Pipeline/Flow Through 209 BGA 225/6.5 I

1M x 36 GS8324Z36C-200I Pipeline/Flow Through 209 BGA 200/7.5 I

1M x 36 GS8324Z36C-166I Pipeline/Flow Through 209 BGA 166/8.5 I

1M x 36 GS8324Z36C-150I Pipeline/Flow Through 209 BGA 150/10 I

1M x 36 GS8324Z36C-133I Pipeline/Flow Through 209 BGA 133/11 I

512K x 72 GS8324Z72C-250I Pipeline/Flow Through 209 BGA 250/6 I

Ordering Information for GSI Synchronous NBT SRAMs (Continued)

Org Part Number1Type Package Speed2

(MHz/ns) TA3

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8324Z18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

512K x 72 GS8324Z72C-225I Pipeline/Flow Through 209 BGA 225/6.5 I

512K x 72 GS8324Z72C-200I Pipeline/Flow Through 209 BGA 200/7.5 I

512K x 72 GS8324Z72C-166I Pipeline/Flow Through 209 BGA 166/8.5 I

512K x 72 GS8324Z72C-150I Pipeline/Flow Through 209 BGA 150/10 I

512K x 72 GS8324Z72C-133I Pipeline/Flow Through 209 BGA 133/11 I

Ordering Information for GSI Synchronous NBT SRAMs (Continued)

Org Part Number1Type Package Speed2

(MHz/ns) TA3

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8324Z18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

36Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New Types of Changes

Format or Content Page;Revisions;Reason

8324Z18_r1 • Creation of new datasheet