FX029J - CML Microcircuits (USA) Inc.

PRODUCT INFORMATION

CML Semiconductor Products

FX029

Features

2 Digitally Contr olled Amplifiers

Gain/Attenuation Range of ±48dB

+ Output Mute, in 2dB Steps

Gain/Attenuation Levels Set by

Serial Interface

Separate Fixed-Gain Uncommitted

Amplifier

5 Volt Low-Po wer Operation

Applications

Cellular and PMR

Communications Systems

Automatic and Manual Test

Equipment

Remote Gain Adjustments

T elephone Audio Settings

Medical Equipment

Audio and Data Gain Setting

Applications

Brief Description

The FX029 single-chip Dual Digitally Controlled

Amplifier Array can replace manual audio-level

controls in most electronic applications including radio

and line communications systems.

The FX029 comprises two digitally controlled gain

and attenuation stages, with each stage having 48

distinct gain steps (range; between -48dB and +48dB

in 2dB steps) plus a MUTE state.

Both gain stages have selectable inputs. This switching

allows for selection of three different input signals

to stage 1 and two to stage 2.

Dual Digitally Controlled

Amplifier Array

Publication D/029/4 November 2003

Provisional Issue

FX029

Fig.1 Functional Block Diagram

Stage 1 also provides output switching.

In addition to the two digitally controlled gain stages,

there is a general purpose, uncommitted inverting

amplifier; the gain of this particular amplifier is

component controlled externally using negative

feedback.

Control of each gain stage section is accomplished

through the serial interface. All switching is

accomplished using controlled rise and fall times,

thereby ensuring no annoying transients (clicks or

pops).

The FX029 requires a single 5 volt supply and is

available in compact cerdip and small outline packages.

21B1A

BIAS

Stage 1

Stage 1 Inputs Stage 2 Inputs

Stage 3 Input

OUTPUTS

Control 1

Gain

BIAS

Gain

SERIAL CLOCK

SERIAL DATA

Control 2

BIAS

Stage 2

IN 2A

IN 1A

IN 2B

IN 1B

IN 3

IN 1C

(UNCOMMITTED)

Stage 3

SERIAL

INTERFACE

STAGE 1

CONTROL

STAGE 2

CONTROL

LOAD/LATCH

Serial Clock: This external clock input is used to “clock in” the control data. See Figure 4 for

timing information. This input has an internal 1MΩ pullup resistor.

Serial Data: Operation of the two amplifier stages (1 and 2) is controlled by the data entered

serially at this pin. The data is entered (bit 13 to bit 0) on the rising edge of the external Serial

Clock. The data format is described in Tables 1-3 and Figure 4.

This input has an internal 1MΩ pullup resistor.

Load/Latch: Governs the loading and execution of the serial control data. During serial data

loading this input should be kept at a logical “1” to ensure that data rippling past the latches

has no effect. When all 14 bits have been loaded this input should be strobed “1” to “0” to “1” to

latch the new data in. Data is executed on the rising edge of this strobe.

IN 1A (Stage 1 Input 1): Analogue Input.

IN 1B (Stage 1 Input 2): Analogue Input.

IN 2A (Stage 2 Input 1): Analogue Input.

IN 2B (Stage 2 Input 2): Analogue Input.

VSS: Negative supply rail (GND).

VBIAS: The output of the on-chip bias circuitry, held at VDD/2.

IN 1C (Stage 1 Input 3): Analogue Input. Normally used for FSK data.

OUT 2 (Stage 2 Output) : Analogue Output.

OUT 1B (Stage 1 Output 2): Analogue Output.

OUT 1A (Stage 1 Output 1): Analogue Output.

OUT 3 (Uncommitted Amplifier Output): Output from the general purpose uncommitted

amplifier.

IN 3 (Uncommitted Amplifier Input): Inverting input to general purpose uncommitted amplifier.

VDD: Positive supply rail. A single +5-volt power supply is required.

Pin Number Function

DW/J

FX029

Application Information

External Components

Fig.2 Recommended External Components

SERIAL CLOCK

IN 1A

IN 1B

IN 2A

IN 2B IN 1C

OUT 2

OUT 1B

OUT 1A

OUT 3

IN 3

BIAS

SERIAL DATA

LOAD/LATCH

FX029

DW/J

SERIAL

CLOCK

SERIAL

DATA

PWL

PWH

LLW

LLD

LLO

LOAD/LATCH

1ST

CLOCK

PULSE

14TH

CLOCK

PULSE

D13 D12 D1

Serial Interface Timing

Component Recommendations

Component Value

C10.1µF

C20.1µF

C30.1µF

C40.1µF

C50.1µF

C6Not Used

C71.0µF

Tolerances 20%

Input capacitors C1 to C5 are only required for ac

input signals; dc input signals do not require these

components.

The gain of the uncommitted stage (3) is set by

external components employed around the input and

output pins (see Specification page).

Application Recommendations

To avoid noise and instability the following practices

are recommended:

(a) Use a clean, well-regulated power supply.

(b) Keep tracks short.

possible.

(d) Analogue tracks should not run parallel to digital

tracks.

(e) A “Ground Plane” connected to V

will assist in

eliminating external pick-up on the channel input

and output pins.

(f) Avoid running high level outputs adjacent to low

level inputs.

(g) The serial clock should not be running

consecutively when not in the process of actually

loading data.

Fig.3 Serial Timing Diagram - see Specification page for timing specifications

Control Data and Timing

The gain and I/O signal path for each section (Channels 1 and 2) is set individually by a 14-bit data word (D0 to

D13). Data is loaded on the rising edge of the Serial Clock. Loaded data is executed on the rising edge of the Load/

Latch pulse.The 14-bit word consists of 1 channel address bit (D7) for selection of the channel to be programmed,

6 bits for setting the amplification/attenuation level (D8-D13), 3 bits for input selection (D4 and D6), and 4 bits for

output settings (D0-D3). This format is illustrated below in Figure 4.

Tables 1-3 show how the data word is used to control channel selection, amplification/attenuation, input selection

and output settings, respectively.

GAIN/ATTENUATION

LEVEL INPUT

SELECT

CHANNEL

ADDRESS

OUTPUT

SETTINGS

D13 D12 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Fig.4 Level-Controlling Data Word Format

D13 D12 D11 D10 D9 D8 Gain

Set (dB)

0 0 0 0 0 0 MUTE

000001 -48

000010 -46

000011 -44

000100 -42

000101 -40

000110 -38

000111 -36

001000 -34

001001 -32

001010 -30

001011 -28

001100 -26

001101 -24

001110 -22

001111 -20

010000 -18

010001 -16

010010 -14

010011 -12

010100 -10

010101 -8

010110 -6

010111 -4

011000 -2

011001 0

Table 1 - Amplification/Attenuation Level

D13 D12 D11 D10 D9 D8 Gain

Set (dB)

011001 0

011010 2

011011 4

011100 6

011101 8

011110 10

011111 12

100000 14

100001 16

100010 18

100011 20

100100 22

100101 24

100110 26

100111 28

101000 30

101001 32

101010 34

101011 36

101100 38

101101 40

101110 42

101111 44

110000 46

110001 48

110010 48

110011 48

D7 Stage D6 D5 D4 Inputs

Selected Selected

0 1 0 0 0 none

1 2 001 1

010 2

0 1 1 1 and 2

100 3

1 0 1 1 and 3

1 1 0 2 and 3

1 1 1 1, 2 and 3

Table 2 Stage and Input Selection

D3 D2 Output D1 D0 Outputs

1B 1A & 2

0 0 high Z 0 0 high Z

0 1 enabled 0 1 enabled

10 V

SS 10 V

11 V

BIAS 11 V

BIAS

Table 3 Stage Output Selection

Specification

Absolute Maximum Ratings

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits

is not implied.

Supply voltage -0.3 to 7.0V

Input voltage at any pin (ref. VSS = 0V) -0.3 to (VDD + 0.3V)

Sink/source current (supply pins) +/- 30mA

(other pins) +/- 20mA

Total device dissipation (DW/J) @ TAMB 25°C 800mW Max.

(D5) @ TAMB 25°C 550mW Max.

Derating (DW/J) 10mW/°C

(D5) 9mW/°C

Operating temperature range: FX029DW/D5/J -40°C to +85°C

Storage temperature range: FX029D5 -40°C to +85°C

FX029DW/J -55°C to +125°C

Operating Characteristics

All device characteristics are measured under the following conditions unless otherwise specified:

VDD = 5.0V, TAMB = 25°C. External components as Figure 2. Audio 0dB ref. = 775mVrms

Characteristics See Note Min. Typ. Max. Unit

Supply Voltage4.55.05.5V

Current(All Stages Operating)-3.0-mA

Digital Inputs 4

Input Logic “1” 3.5 - - V

Input Logic “0” - - 1.5 V

Digital Input Impedances 0.5 1.0 - MΩ

Gain Control Amplifier Stages (Stages 1 and 2)

Bandwidth (-3dB) 1 3.3 - - kHz

Output Impedance - 1.0 2.0 kΩ

Total Harmonic Distortion 2, 5 - 0.35 0.5 %

Interstage Isolation - 60.0 - dB

Gain 46.0 48.0 - dB

Attenuation 46.0 48.0 - dB

Gain/Attenuation Step Size - 2.0 - dB/step

Step Error - - 0.4 dB

Input Impedance 50.0 - - kΩ

Input Referred Offset Voltage (VIOS) - 10.0 - mV

Uncommitted Amplifier (Stage 3)

Bandwidth (-3dB) 3 10.0 - - kHz

Output Impedance - 1.0 2.0 kΩ

Total Harmonic Distortion 3 - 0.35 0.5 %

Open Loop DC Gain - 60 - dB

Timing (See Figure 3)

Serial Clock “High” Pulse Width (tPWH) 250 - - ns

Serial Clock “Low” Pulse Width (tPWL) 250 - - ns

Data Set-up Time (tDS) 150 - - ns

Data Hold Time (tDH) 50.0 - - ns

Load/Latch Delay (tLLD) 200 - - ns

Load/Latch Over-Time (tLLO)--0ns

Load/Latch Pulse Width (tLLW) 150 - - ns

Serial Data Clock Frequency - - 2.0 MHz

Notes

1. Gain set to maximum (+48.0dB).

2. Gain Set 0dB. Input Level 1.0kHz, -3.0dB (549mVrms).

3. Gain externally set to 10.0dB.

4. Serial Clock, Serial Data and Load/Latch inputs.

5. With a 100kΩ load on the relevant output.

Package Outlines

The FX029 is available in the package styles outlined

below. Mechanical package diagrams and

specifications are detailed in Section 10 of the Data

Book.

Pin 1 identification marking is shown on the relevant

diagram and pins on all package styles number

anti-clockwise when viewed from the top.

Handling Precautions

The FX029 is a CMOS LSI circuit which includes input

protection. However precautions should be taken to

prevent static discharges which may cause damage.

CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied

and CML reserves the right at any time without notice to change the said circuitry.

Ordering Information

FX029D5 24-pin plastic S.S.O.P.

FX029DW 16-pin plastic S.O.I.C. (D4)

FX029J 16-pin cerdip (J2)

NOT TO SCALE

Max. Body Length 10.49mm

Max. Body Width 7.59mm

NOT TO SCALE

Max. Body Length 19.48mm

Max. Body Width 7.39mm

FX029DW 16-pin plastic S.O.I.C. (D4) FX029J 16-pin cerdip DIL (J2)

FX029D5 24-Pin Plastic S.S.O.P.

NOT TO SCALE

Max. Body Length 8.33mm

Max. Body Width 5.38mm

CML Product Data

In the process of creating a more global image, the three standard product semiconductor

companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc

(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst

maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)

Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Micro-

circuits.

These companies are all 100% owned operating companies of the CML Microsystems Plc

Group and these changes are purely changes of name and do not change any underlying legal

entities and hence will have no effect on any agreements or contacts currently in force.

CML Microcircuits Product Prefix Codes

Until the latter part of 1996, the differentiator between products manufactured and sold from

MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX

respectively. These products use the same silicon etc. and today still carry the same prefixes.

In the latter part of 1996, both companies adopted the common prefix: CMX.

This notification is relevant product information to which it is attached.

Company contact information is as below:

CML Microcircuits

(UK)Ltd

COMMUNICATION SEMICONDUCTORS

CML Microcircuits

COMMUNICATION SEMICONDUCTORS

CML Microcircuits

(Singapore)PteLtd

COMMUNICATION SEMICONDUCTORS

CML Microcircuits

(USA) Inc.

COMMUNICATION SEMICONDUCTORS

Oval Park, Langford, Maldon,

Essex, CM9 6WG, England

Tel: +44 (0)1621 875500

Fax: +44 (0)1621 875600

uk.sales@cmlmicro.com

www.cmlmicro.com

4800 Bethania Station Road,

Winston-Salem, NC 27105, USA

Tel: +1 336 744 5050,

0800 638 5577

Fax: +1 336 744 5054

us.sales@cmlmicro.com

www.cmlmicro.com

No 2 Kallang Pudding Road, 09-05/

06 Mactech Industrial Building,

Singapore 349307

Tel: +65 7450426

Fax: +65 7452917

sg.sales@cmlmicro.com

www.cmlmicro.com

D/CML (D)/1 February 2002