CAT28F020N-12T - Catalyst Semiconductor, Inc.

I/O0–I/O7

I/O BUFFERS

CE, OE LOGIC SENSE

AMP

DATA

LATCH

ERASE VOLTAGE

SWITCH

PROGRAM VOLTAGE

SWITCH

COMMAND

VOLTAGE VERIFY

SWITCH

ADDRESS LATCH

Y-DECODER

X-DECODER

Y-GATING

2,097,152 BIT

MEMORY

ARRAY

A0–A17

CAT28F020

2 Megabit CMOS Flash Memory

Characteristics subject to change without notice

FEATURES

■Fast read access time: 90/120 ns

■Low power CMOS dissipation:

– Active: 30 mA max (CMOS/TTL levels)

– Standby: 1 mA max (TTL levels)

– Standby: 100 µA max (CMOS levels)

■High speed programming:

– 10 µs per byte

– 4 seconds typical chip program

■0.5 seconds typical chip-erase

■12.0V ± 5% programming and erase voltage

■Commercial, industrial and automotive

temperature ranges

■Stop timer for program/erase

■On-chip address and data latches

■JEDEC standard pinouts:

– 32-pin DIP

– 32-pin PLCC

– 32-pin TSOP (8 x 20)

■100,000 program/erase cycles

■10 year data retention

■Electronic signature

using a two write cycle scheme. Address and Data are

latched to free the I/O bus and address bus during the

write operation.

The CAT28F020 is manufactured using Catalyst’s

advanced CMOS floating gate technology. It is designed

to endure 100,000 program/erase cycles and has a data

retention of 10 years. The device is available in JEDEC

approved 32-pin plastic DIP, 32-pin PLCC or 32-pin

TSOP packages.

DESCRIPTION

The CAT28F020 is a high speed 256K x 8-bit electrically

erasable and reprogrammable Flash memory ideally

suited for applications requiring in-system or after-sale

code updates. Electrical erasure of the full memory

contents is achieved typically within 0.5 second.

It is pin and Read timing compatible with standard

EPROM and E2PROM devices. Programming and

Erase are performed through an operation and verify

algorithm. The instructions are input via the I/O bus,

5115 FHD F02

BLOCK DIAGRAM

Licensed Intel

second source

Doc. No. 1029, Rev. B

CAT28F020

Doc. No. 1029, Rev. B

PIN FUNCTIONS

Pin Name Type Function

A0–A17 Input Address Inputs for

memory addressing

I/O0–I/O7I/O Data Input/Output

CE Input Chip Enable

OE Input Output Enable

WE Input Write Enable

VCC Voltage Supply

VSS Ground

VPP Program/Erase

Voltage Supply

PIN CONFIGURATION

5115 FHD F01

TSOP Package (Standard Pinout) (T)

5115 FHD F14

TSOP Package (Reverse Pinout) (TR)

I/O0

I/O1

I/O2

VSS

I/O6

I/O5

I/O4

I/O3

A10

I/O7

VPP

A16

A15

A12 A13

A11

VCC

A17

A14 A7

I/O013

A14

A13

26 A11

A10

22 I/O7

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

I/O6

14 15 16 17 18 19 20

4321323130

A12

A15

A16

VPP

VCC

A17

A10

I/O7

I/O6

I/O5

I/O4

I/O3

VSS

I/O2

I/O1

I/O0

A12

A15

A16

VPP

VCC

A17

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

VSS

I/O2

I/O1

I/O0

A3A4

A12

A15

A16

VPP

VCC

A17

A14

A13

A11

PLCC Package (N)

DIP Package (P)

CAT28F020

3Doc. No. 1029, Rev. B

CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol Test Conditions Min Typ Max Units

CIN(3) Input Pin Capacitance VIN = 0V 6 pF

COUT(3) Output Pin Capacitance VOUT = 0V 10 pF

CVPP(3) VPP Supply Capacitance VPP = 0V 25 pF

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................... –55°C to +95°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground(1) ........... –2.0V to +VCC + 2.0V

Voltage on Pin A9 with

Respect to Ground(1) ................... –2.0V to +13.5V

VPP with Respect to Ground

during Program/Erase(1) .............. –2.0V to +14.0V

VCC with Respect to Ground(1) ............ –2.0V to +7.0V

Package Power Dissipation

Capability (TA = 25°C) .................................. 1.0 W

Lead Soldering Temperature (10 secs)............ 300°C

Output Short Circuit Current(2) ........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Test Method Min Typ Max Units

NEND(3) Endurance MIL-STD-883, Test Method 1033 100K Cycles/Byte

TDR(3) Data Retention MIL-STD-883, Test Method 1008 10 Years

VZAP(3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts

ILTH(3)(4) Latch-Up JEDEC Standard 17 100 mA

Note:

1. The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.

2. Output shorted for no more than one second. No more than one output shorted at a time.

3. This parameter is tested initially and after a design or process change that affects the parameter.

4. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

CAT28F020

Doc. No. 1029, Rev. B

D.C. OPERATING CHARACTERISTICS

VCC = +5V ±10%, unless otherwise specified. (See Note 2)

Symbol Parameter Test Conditions Min Typ Max Unit

ILI Input Leakage Current VIN = VCC or VSS ±1µA

VCC = 5.5V, OE = VIH

ILO Output Leakage Current VOUT = VCC or VSS,±1µA

VCC = 5.5V, OE = VIH

ISB1 VCC Standby Current CMOS CE = VCC ±0.5V, 100 µA

VCC = 5.5V

ISB2 VCC Standby Current TTL CE = VIH, VCC = 5.5V 1 mA

ICC1 VCC Active Read Current VCC = 5.5V, CE = VIL,30mA

IOUT = 0mA, f = 6 MHz

ICC2(1) VCC Programming Current VCC = 5.5V, 15 mA

Programming in Progress

ICC3(1) VCC Erase Current VCC = 5.5V, 15 mA

Erasure in Progress

ICC4(1) VCC Prog./Erase Verify Current VCC = 5.5V, Program or 15 mA

Erase Verify in Progress

IPPS VPP Standby Current VPP = VPPL ±10 µA

IPP1 VPP Read Current VPP = VPPH 200 µA

IPP2(1) VPP Programming Current VPP = VPPH,30mA

Programming in Progress

IPP3(1) VPP Erase Current VPP = VPPH,30mA

Erasure in Progress

IPP4(1) VPP Prog./Erase Verify Current VPP = VPPH, Program or 5 mA

Erase Verify in Progress

VIL Input Low Level TTL -0.5 0.8 V

VILC Input Low Level CMOS -0.5 0.8 V

VOL Output Low Level IOL = 5.8mA, VCC(2) = 4.5V 0.45 V

VIH Input High Level TTL 2 VCC+0.5 V

VIHC Input High Level CMOS VCC*0.7 VCC+0.5 V

VOH1 Output High Level TTL IOH = -2.5mA, VCC(2) = 4.5V 2.4 V

VOH2 Output High Level CMOS IOH = -400µA, VCC(2) = 4.5V VCC-0.4 V

VID A9 Signature Voltage A9 = VID 11.4 13 V

IID(1) A9 Signature Current A9 = VID 200 µA

VLO VCC Erase/Prog. Lockout Voltage 2.5 V

Note:

1. This parameter is tested initially and after a design or process change that affects the parameter.

2. CAT28F020-90, VCCMIN = 4.75 V.

CAT28F020

5Doc. No. 1029, Rev. B

SUPPLY CHARACTERISTICS

Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)

Testing Load Circuit (example)

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified. (See Note 8)

JEDEC Standard 28F020-90(7) 28F020-12(7)

Symbol Symbol Parameter Min Typ Max Min Typ Max Unit

tAVAV tRC Read Cycle Time 90 120 ns

tELQV tCE CE Access Time 90 120 ns

tAVQV tACC Address Access Time 90 120 ns

tGLQV tOE OE Access Time 35 50 ns

tAXQX tOH Output Hold from Address OE/CE Change 0 0 ns

tGLQX tOLZ(1)(6) OE to Output in Low-Z 0 0 ns

tELQX tLZ(1)(6) CE to Output in Low-Z 0 0 ns

tGHQZ tDF(1)(2) OE High to Output High-Z 30 30 ns

tEHQZ tDF(1)(2) CE High to Output High-Z 40 40 ns

tWHGL(1) - Write Recovery Time Before Read 6 6 µs

1.3V

DEVICE

UNDER

TEST

1N914

3.3K

CL = 100 pF

OUT

CL INCLUDES JIG CAPACITANCE

INPUT PULSE LEVELS REFERENCE POINTS

2.0 V

0.8 V

2.4 V

0.45 V

Note:

1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.

3. Input Rise and Fall Times (10% to 90%) < 10 ns.

4. Input Pulse Levels = 0.45 V and 2.4 V. For High Speed Input Pulse Levels 0.0 V and 3.0 V.

5. Input and Output Timing Reference = 0.8 V and 2.0 V. For High Speed Input and Output Timing Reference = 1.5 V.

6. Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.

7. For load and reference points, see Fig. 1.

8. CAT28F020-90, VCCMIN = 4.75 V.

lobmySretemaraPniMpyTxaMtinU

CCVegatloVylppuSCCV 09-020F8257.45.5V

21-020F825.45.5V

LPPVsnoitarepOdaeRgniruDPPV05.6V

HPPVmargorP/esarE/daeRgniruDPPV4.116.21V

CAT28F020

Doc. No. 1029, Rev. B

ERASE AND PROGRAMMING PERFORMANCE(1)

28F020-90 28F020-12

Parameter Min Typ Max Min Typ Max Unit

Chip Erase Time(3)(5) 0.5 10 0.5 10 sec

Chip Program Time(3)(4) 4 25 4 25 sec

A.C. CHARACTERISTICS, Program/Erase Operation

VCC = +5V ±10%, unless otherwise specified. (See Note 6)

JEDEC

Standard

28F020-90 28F020-12

Symbol Symbol Parameter Min Typ Max Min Typ Max Unit

tAVAV tWC Write Cycle Time 90 120 ns

tAVWL tAS Address Setup Time 0 0 ns

tWLAX tAH Address Hold Time 40 40 ns

tDVWH tDS Data Setup Time 40 40 ns

tWHDX tDH Data Hold Time 10 10 ns

tELWL tCS CE Setup Time 0 0 ns

tWHEH tCH CE Hold Time 0 0 ns

tWLWH tWP WE Pulse Width 40 40 ns

tWHWL tWPH WE High Pulse Width 20 20 ns

tWHWH1(2) - Program Pulse Width 10 10 µs

tWHWH2(2) - Erase Pulse Width 9.5 9.5 ms

tWHGL - Write Recovery Time Before Read 6 6 µs

tGHWL - Read Recovery Time Before Write 0 0 µs

tVPEL -V

PP Setup Time to CE 100 100 ns

Note:

1. Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is switched,

VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.

2. Program and Erase operations are controlled by internal stop timers.

3. ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP.

4. Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/

byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since

most bytes program significantly faster than the worst case byte.

5. Excludes 00H Programming prior to Erasure.

6. CAT28F020-90, VCCMIN = 4.75 V

CAT28F020

7Doc. No. 1029, Rev. B

FUNCTION TABLE(1)

Pins

Mode CE OE WE VPP I/O Notes

Read VIL VIL VIH VPPL DOUT

Output Disable VIL VIH VIH X High-Z

Standby VIH XXV

PPL High-Z

Signature (MFG) VIL VIL VIH X 31H A0 = VIL, A9 = 12V

Signature (Device) VIL VIL VIH X BDH A0 = VIH, A9 = 12V

Program/Erase VIL VIH VIL VPPH DIN See Command Table

Write Cycle VIL VIH VIL VPPH DIN During Write Cycle

Read Cycle VIL VIL VIH VPPH DOUT During Write Cycle

WRITE COMMAND TABLE

Commands are written into the command register in one or two write cycles. The command register can be altered

only when VPP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch

addresses and data required for programming and erase operations.

Pins

First Bus Cycle Second Bus Cycle

Mode Operation Address DIN Operation Address DIN DOUT

Set Read Write X 00H Read AIN DOUT

Read Sig. (MFG) Write X 90H Read 00 31H

Read Sig. (Device) Write X 90H Read 01 BDH

Erase Write X 20H Write X 20H

Erase Verify Write AIN A0H Read X DOUT

Program Write X 40H Write AIN DIN

Program Verify Write X C0H Read X DOUT

Reset Write X FFH Write X FFH

Note:

1. Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, VPPL, VPPH)

CAT28F020

Doc. No. 1029, Rev. B

READ OPERATIONS

Read Mode

A Read operation is performed with both CE and OE low

and with WE high. VPP can be either high or low,

however, if VPP is high, the Set READ command has to

be sent before reading data (see Write Operations). The

data retrieved from the I/O pins reflects the contents of

the memory location corresponding to the state of the 18

address pins. The respective timing waveforms for the

read operation are shown in Figure 3. Refer to the AC

Read characteristics for specific timing parameters.

Signature Mode

The signature mode allows the user to identify the IC

manufacturer and the type of device while the device

resides in the target system. This mode can be activated

in either of two ways; through the conventional method

of applying a high voltage (12V) to address pin A9 or by

sending an instruction to the command register (see

Write Operations).

Figure 3. A.C. Timing for Read Operation

28F020 F05

ADDRESSES

CE (E)

OE (G)

WE (W)

DATA (I/O) HIGH-Z

POWER UP ST ANDBY DEVICE AND

ADDRESS SELECTION OUPUTS

ENABLED DATA VALID STANDBY

ADDRESS STABLE

OUTPUT VALID

tAVQV (tACC)

tELQX (tLZ)

tGLQX (tOLZ)

tGLQV (tOE)

tELQV (tCE)tAXQX (tOH)

tGHQZ (tDF)

tEHQZ (tDF)

tAVAV (tRC)

POWER DOWN

HIGH-Z

tWHGL

The conventional mode is entered as a regular READ

mode by driving the CE and OE pins low (with WE high),

and applying the required high voltage on address pin A9

while all other address lines are held at VIL.

A Read cycle from address 0000H retrieves the binary

code for the IC manufacturer on outputs I/O0 to I/O7:

CATALYST Code = 00110001 (31H)

A Read cycle from address 0001H retrieves the binary

code for the device on outputs I/O0 to I/O7.

28F020 Code = 1011 1101 (BDH)

Standby Mode

With CE at a logic-high level, the CAT28F020 is placed

in a standby mode where most of the device circuitry is

disabled, thereby substantially reducing power con-

sumption. The outputs are placed in a high-impedance

state.

CAT28F020

9Doc. No. 1029, Rev. B

Figure 4. A.C. Timing for Erase Operation

28F020 F11

ADDRESSES

CE (E)

OE (G)

WE (W)

DATA (I/O)

VCC

VPP

tWC tWC tRC

tCS

tCH tCS

tCH tCH tEHQZ

tDF

tGHWL

tWPH tWHWH2 tWHGL

tWP

tDS

HIGH-Z DATA IN

= 20H DATA IN

= A0H VALID

DATA OUT

tDH tWP tDH

tDS tDS

tWP tDH tOLZ

tOE tOH

tLZ

tCE

tVPEL

VPPH

VPPL

5.0V

VCC POWER-UP

& STANDBY SETUP ERASE

COMMAND ERASE

COMMAND ERASING ERASE VERIFY

COMMAND ERASE

VERIFICATION VCC POWER-DOWN/

STANDBY

tAS tAH

DATA IN

= 20H

tWC

WRITE OPERATIONS

The following operations are initiated by observing the

sequence specified in the Write Command Table.

Read Mode

The device can be put into a standard READ mode by

initiating a write cycle with 00H on the data bus. The

subsequent read cycles will be performed similar to a

standard EPROM or E2PROM Read.

Signature Mode

An alternative method for reading device signature (see

Read Operations Signature Mode), is initiated by writing

the code 90H into the command register while keeping

VPP high. A read cycle from address 0000H with CE and

OE low (and WE high) will output the device signature.

CATALYST Code = 00110001 (31H)

A Read cycle from address 0001H retrieves the binary

code for the device on outputs I/O0 to I/O7.

28F020 Code = 1011 1101 (BDH)

Erase Mode

During the first Write cycle, the command 20H is written

into the command register. In order to commence the

erase operation, the identical command of 20H has to be

written again into the register. This two-step process

ensures against accidental erasure of the memory con-

tents. The final erase cycle will be stopped at the rising

edge of WE, at which time the Erase Verify command

(A0H) is sent to the command register. During this cycle,

the address to be verified is sent to the address bus and

latched when WE goes low. An integrated stop timer

allows for automatic timing control over this operation,

eliminating the need for a maximum erase timing speci-

fication. Refer to AC Characteristics (Program/Erase)

for specific timing parameters.

CAT28F020

Doc. No. 1029, Rev. B

Figure 5. Chip Erase Algorithm(1)

5108 FHD F10

Note:

(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.

DATA = 20H

START ERASURE

APPLY VPPH

INITIALIZE

ADDRESS

INITIALIZE

PLSCNT = 0

WRITE ERASE

SETUP COMMAND

WRITE ERASE

COMMAND

TIME OUT 10ms

WRITE ERASE

VERIFY COMMAND

TIME OUT 6µs

READ DATA

FROM DEVICE

DATA =

FFH?

LAST

ADDRESS?

WRITE READ

COMMAND

APPLY VPPL

ERASURE

COMPLETED

APPLY VPPL

ERASE

ERROR

INCREMENT

ADDRESS

INC PLSCNT

= 3000 ?

YES

PROGRAM ALL

BYTES TO 00H STANDBY

VPP RAMPS TO VPPH

(OR VPP HARDWIRED)

BUS

OPERATION COMMAND COMMENTS

READ

STANDBY

WRITE

STANDBY

ERASE

VERIFY

READ

INITIALIZE ADDRESS

ALL BYTES SHALL BE

PROGRAMMED TO 00

BEFORE AN ERASE

OPERATION

PLSCNT = PULSE COUNT

ACTUAL ERASE

NEEDS 10ms PULSE,

DATA = 20H

WAIT

ADDRESS = BYTE T O VERIFY

DATA = 20H;

STOPS ERASE OPERATION

READ BYTE TO

VERIFY ERASURE

DA TA = 00H

RESETS THE REGISTER

FOR READ OPERA TION

VPP RAMPS TO VPPL

(OR VPP HARDWIRED)

WRITE

ERASE

WAIT

COMPARE OUTPUT TO FF

INCREMENT PULSE COUNT

DATA = 20H

DATA=20H

A0H

=1000 ?

CAT28F020

11 Doc. No. 1029, Rev. B

28F020 F07

ADDRESSES

CE (E)

OE (G)

WE (W)

DATA (I/O)

VCC

VPP

tWC tWC tRC

tAS tAH

tCS

tCH tCS

tCH tCH tEHQZ

tDF

tGHWL

tWPH tWHWH1 tWHGL

tWP

tDS

HIGH-Z DATA IN

= 40H DATA IN DATA IN

= C0H VALID

DATA OUT

tDH tWP tDH

tDS tDS

tWP tDH tOLZ

tOE tOH

tLZ

tCE

tVPEL

VPPH

VPPL

5.0V

VCC POWER-UP

& STANDBY SETUP PROGRAM

COMMAND LA TCH ADDRESS

& DATA PROGRAMMING

PROGRAM

VERIFY

COMMAND

PROGRAM

VERIFICATION VCC POWER-DOWN/

STANDBY

Figure 6. A.C. Timing for Programming Operation

Program-Verify Mode

A Program-verify cycle is performed to ensure that all

bits have been correctly programmed following each

byte programming operation. The specific address is

already latched from the write cycle just completed, and

stays latched until the verify is completed. The Program-

verify operation is initiated by writing C0H into the

command register. An internal reference generates the

necessary high voltages so that the user does not need

to modify VCC. Refer to AC Characteristics (Program/

Erase) for specific timing parameters.

Erase-Verify Mode

The Erase-verify operation is performed on every byte

after each erase pulse to verify that the bits have been

erased.

Programming Mode

The programming operation is initiated using the pro-

gramming algorithm of Figure 7. During the first write

cycle, the command 40H is written into the command

the memory location to be programmed is latched on the

falling edge of WE, while the data is latched on the rising

edge of WE. The program operation terminates with the

next rising edge of WE. An integrated stop timer allows

for automatic timing control over this operation, eliminat-

ing the need for a maximum program timing specifica-

tion. Refer to AC Characteristics (Program/Erase) for

specific timing parameters.

CAT28F020

Doc. No. 1029, Rev. B

Figure 7. Programming Algorithm(1)

5108 FHD F06

START

PROGRAMMING

APPLY VPPH

INITIALIZE

ADDRESS

PLSCNT = 0

WRITE SETUP

PROG. COMMAND

WRITE PROG. CMD

ADDR AND DA T A

TIME OUT 10µs

WRITE PROGRAM

VERIFY COMMAND

TIME OUT 6µs

READ DATA

FROM DEVICE

VERIFY

DATA ?

LAST

ADDRESS?

WRITE READ

COMMAND

APPLY VPPL

PROGRAMMING

COMPLETED

APPLY VPPL

PROGRAM

ERROR

INCREMENT

ADDRESS

INC

PLSCNT

= 25 ?

YES

STANDBY

WRITE

SETUP

VPP RAMPS TO VPPH

(OR VPP HARDWIRED)

BUS

OPERATION COMMAND COMMENTS

1ST WRITE

CYCLE

2ND WRITE

CYCLE

1ST WRITE

CYCLE

READ

STANDBY

1ST WRITE

CYCLE

STANDBY

PROGRAM

VERIFY

READ

INITIALIZE ADDRESS

INITIALIZE PULSE COUNT

PLSCNT = PULSE COUNT

DATA = 40H

V ALID ADDRESS AND DA TA

WAIT

READ BYTE TO VERIFY

PROGRAMMING

COMPARE DATA OUTPUT

TO DATA EXPECTED

DA TA = 00H

SETS THE REGISTER FOR

READ OPERA TION

VPP RAMPS TO VPPL

(OR VPP HARDWIRED)

WAIT

DATA = C0H

Note:

(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.

CAT28F020

13 Doc. No. 1029, Rev. B

Figure 8. Alternate A.C. Timing for Program Operation

28F020 F09

POWER SUPPLY DECOUPLING

To reduce the effect of transient power supply voltage

spikes, it is good practice to use a 0.1µF ceramic

capacitor between VCC and VSS and VPP and VSS. These

high-frequency capacitors should be placed as close as

possible to the device for optimum decoupling.

Abort/Reset

An Abort/Reset command is available to allow the user

to safely abort an erase or program sequence. Two

consecutive program cycles with FFH on the data bus

will abort an erase or a program operation. The abort/

reset operation can interrupt at any time in a program or

erase operation and the device is reset to the Read

Mode.

POWER UP/DOWN PROTECTION

The CAT28F020 offers protection against inadvertent

programming during VPP and VCC power transitions.

When powering up the device there is no power-on

sequencing necessary. In other words, VPP and VCC

may power up in any order. Additionally VPP may be

hardwired to VPPH independent of the state of VCC and

any power up/down cycling. The internal command

power up.

ADDRESSES

28F020 F09

WE (W)

OE (G)

CE (E)

DATA (I/O)

VCC

VPP

tWC tWC tRC

tAVEL tELAX

tWLEL

tWLEL tEHQZ

tDF

tGHEL tEHEL tEHEH tEHGL

tELEH

HIGH-Z DATA IN

= 40H DATA IN DATA IN

= C0H VALID

DATA OUT

tEHDX

tOLZ

tOE tOH

tLZ

tCE

tVPEL

VPPH

VPPL

5.0V

VCC POWER-UP

& STANDBY SETUP PROGRAM

COMMAND LA TCH ADDRESS

& DATA PROGRAMMING

PROGRAM

VERIFY

COMMAND

PROGRAM

VERIFICATION VCC POWER-DOWN/

STANDBY

tWLEL

tEHWH

tEHWH tEHWH

tELEH

tDVEH tDVEH tDVEH

tEHDX

CAT28F020

Doc. No. 1029, Rev. B

ALTERNATE CECE

CECE

CE-CONTROLLED WRITES

JEDEC Standard 28F020-90 28F020-12

Symbol Symbol Parameter Min Typ Max Min Typ Max Unit

tAVAV tWC Write Cycle Time 90 120 ns

tAVEL tAS Address Setup Time 0 0 ns

tELAX tAH Address Hold Time 40 4 0 ns

tDVEH tDS Data Setup Time 40 40 ns

tEHDX tDH Data Hold Time 10 10 ns

tEHGL — Write Recovery Time Before Read 6 6 µs

tGHEL — Read Recovery Time Before Write 0 0 µs

tWLEL tWS WE Setup Time Before CE 00 ns

tEHWH —WE Hold Time After CE 00 ns

tELEH tCP Write Pulse Width 40 40 ns

tEHEL tCPH Write Pulse Width High 20 20 ns

tVPEL —V

PP Setup Time to CE Low 100 100 ns

ORDERING INFORMATION

28F020 F12

Note:

(1) The device used in the above example is a CAT28F020NI-12T (PLCC, Industrial Temperature, 120 ns access time, Tape & Reel).

* -40˚ to +125˚ is available upon request.

Prefix Device # Suffix

28F020 N I T

Product

Number Tape & Reel

T: 500/Reel

Package

N: PLCC

P: PDIP

T: TSOP (8mmx20mm)

TR: TSOP (Reverse Pinout)

-12CAT

Optional

Company ID

Temperature Range

Blank = Commercial (0˚C to +70˚C)

I = Industrial (-40˚C to +85˚C)

A = Automotive (-40˚C to +105˚C)*

Speed

90: 90ns

12: 120ns

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

www.catalyst-semiconductor.com

Publication #: 1029

Revison: B

Issue date: 2/10/04

Type: Final

Copyrights, Trademarks and Patents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ™ AE2 ™

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

REVISION HISTORY

Date Rev. Reason

5/1/2002 A Initial issue

2/10/2004 B Change VCCMIN for CAT28F020-90 to 4.75 V from

4.5 V