MT9VDDT3272PHY-265XX - Micron Technology, Inc.

‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

pdf: 09005aef808ffe58, source: 09005aef808ffdc7

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE‡

DDR SDRAM

SMALL-OUTLINE DIMM

MT9VDDT1672PH(I) – 128MB,

MT9VDDT3272PH(I) – 256MB,

MT9VDDT6472PH(I) – 512MB,

MT9VDDT12872PH(I) – 1GB (ADVANCE

‡

)

For the lastest data sheet, please refer to the Micron



Web site: www.micron.com/products/modules

Features

• 200-pin, small-outline, dual in-line memory

module (SODIMM)

• Supports ECC error detection and correction

• Fast data transfer rates: PC2100 and PC2700

• Utilizes 266 MT/s and 333 MT/s DDR SDRAM

components

• 128MB (16 Meg x 72); 256MB (32 Meg x 72); 512MB

(64 Meg x 72); 1GB (128 Meg x 72)

•V

DD = VDDQ = +2.5V

•V

DDSPD = +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Four internal device banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.625µs (128MB), 7.8125µs (256MB, 512MB, 1GB)

maximum average periodic refresh interval

• Serial Presence Detect (SPD) with EEPROM

• Programmable READ CAS latency

• Bidirectional data strobe (DQS) transmitted/re-

ceived with data—i.e., source-synchronous data

capture

• Differential clock inputs CK and CK#

•Gold edge contacts

Figure 1: 200-Pin SODIMM (MO-224)

NOTE: 1. Consult Micron for product availability; indus-

trial temperature option available in -265 speed

only.

2. CL = Device CAS (READ) Latency.

OPTIONS MARKING

• Operating Temperature Range

Commercial (0°C ≤ TA ≤ +70°C) None

Industrial (-40°C ≤ TA ≤ +85°C) I1

•Package

200-pin SODIMM (standard) G

200-pin SODIMM (lead-free) Y1

• Memory Clock, Speed, CAS Latency2

6ns (267 MHz), 333 MT/s, CL = 2.5 -335

7.5ns (133 MHz), 266 MT/s, CL = 2 -2621

7.5ns (133 MHz), 266 MT/s, CL = 2 -26A1

7.5ns (133 MHz), 266 MT/s, CL = 2.5 -265

•PCB

1.25in. (31.75mm)

Low Profile: 1.25in. (31.75mm)

Table 1: Address Table

128MB 256MB 512MB 1GB

Refresh Count 4K 8K 8K 8K

Row Addressing 4K (A0–A11) 8K (A0–A12) 8K (A0–A12) 16K (A0–A13)

DeviceBankAddressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Base Device Configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8)

Column Addressing 1K (A0–A9) 1K (A0–A9) 1K (A0–A9, A11) 2K (A0–A9, A11)

Module Rank Addressing 1 (S0#) 1 (S0#) 1 (S0# 1 (S0#)

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for

current revision codes. Example: MT9VDDT3272PHG-265A1.

Table 2: Part Numbers and Timing Parameters

PART NUMBER MODULE

DENSITY

CONFIGURATION

MODULE

BANDWIDTH

MEMORY CLOCK/

DATA RATE

CLOCK LATENCY

(CL - tRCD - tRP)

MT9VDDT1672PHG-335_ 128MB 16 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3

MT9VDDT1672PHY-335_ 128MB 16 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3

MT9VDDT1672PHG-262_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2

MT9VDDT1672PHY-262_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2

MT9VDDT1672PHG-26A_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3

MT9VDDT1672PHY-26A_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3

MT9VDDT1672PH(I)G-265_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3

MT9VDDT1672PH(I)Y-265_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3

MT9VDDT3272PHG-335_ 256MB 32 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3

MT9VDDT3272PHY-335_ 256MB 32 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3

MT9VDDT3272PHG-262_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2

MT9VDDT3272PHY-262_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2

MT9VDDT3272PHG-26A_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3

MT9VDDT3272PHY-26A_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3

MT9VDDT3272PH(I)G-265_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3

MT9VDDT3272PH(I)Y-265_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3

MT9VDDT6472PHG-335_ 512MB 64 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3

MT9VDDT6472PHY-335_ 512MB 64 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3

MT9VDDT6472PHG-262_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2

MT9VDDT6472PHY-262_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2

MT9VDDT6472PHG-26A_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3

MT9VDDT6472PHY-26A_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3

MT9VDDT6472PH(I)G-265_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3

MT9VDDT6472PH(I)Y-265_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3

MT9VDDT12872PHG-335_ 1GB 128 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3

MT9VDDT12872PHY-335_ 1GB 128 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3

MT9VDDT12872PH

G-262_

1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2

MT9VDDT12872PH

Y-262_

1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2

MT9VDDT12872PH

G-26A_

1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3

MT9VDDT12872PH

Y-26A_

1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3

MT9VDDT12872PH(I)G

-265_

1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3

MT9VDDT12872PH(I)Y

-265_

1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. Pin 99 is a No Connect (NC) for 128MB; A12 for 256MB, 512MB, and 1GB.

2. Pin 123 is a No Connect (NC) for 128MB, 256MB, and 512MB; A13 for 1GB

Figure 2: Module Layout

Table 3: Pin Assignment

(200-Pin SODIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VREF 51 VSS 101 A9 151 DQ42

SS 53 DQ19 103 VSS 153 DQ43

5 DQ0 55 DQ24 105 A7 155 VDD

7DQ157 VDD 107 A5 157 VDD

9Vdd59 DQ25 109 A3 159 VSS

11 DQS0 61 DQS3 111 A1 161 VSS

13 DQ2 63 VSS 113 VDD 163 DQ48

15 VSS 65 DQ26 115 A10/AP 165 DQ49

17 DQ3 67 DQ27 117 BA0 167 VDD

19 DQ8 69 VDD 119 WE# 169 DQS6

21 VDD 71 CB0 121 S0# 171 DQ50

23 DQ9 73 CB1 123 NC/A13 173 VSS

25 DQS1 75 VSS 125 VSS 175 DQ51

27 VSS 77 DQS8 127 DQ32 177 DQ56

29 DQ10 79 CB2 129 DQ33 179 VDD

31 DQ11 81 VDD 131 VDD 181 DQ57

33 VDD 83 CB3 133 DQS4 183 DQS7

35 CK0 85 NC 135 DQ34 185 VSS

37 CK0# 87 VSS 137 VSS 187 DQ58

39 VSS 89 NC 139 DQ35 189 DQ59

41 DQ16 91 NC 141 DQ40 191 VDD

43 DQ17 93 VDD 143 VDD 193 SDA

45 VDD 95 NC 145 DQ41 195 SCL

47 DQS2 97 NC 147 DQS5 197 VDDSPD

49 DQ18 99 NC/A12 149 VSS 199 NC

Table 4: Pin Assignment

(200-Pin SODIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

2VREF 52 VSS 102 A8 152 DQ46

SS 54 DQ23 104 VSS 154 DQ47

6DQ456DQ28 106 A6 156 VDD

8DQ558 VDD 108 A4 158 NC

10 VDD 60 DQ29 110 A2 160 NC

12 DM0 62 DM3 112 A0 162 VSS

14 DQ6 64 VSS 114 VDD 164 DQ52

16 VSS 66 DQ30 116 BA1 166 DQ53

18 DQ7 68 DQ31 118RAS#168 V

20 DQ12 70 VDD 120 CAS# 170 DM6

22 VDD 72 CB4 122 NC 172 DQ54

24 DQ13 74 CB5 124 NC 174 VSS

26 DM1 76 VSS 126 VSS 176 DQ55

28 VSS 78 DM8 128 DQ36 178 DQ60

30 DQ14 80 CB6 130 DQ37 180 VDD

32 DQ15 82 VDD 132 VDD 182 DQ61

34 VDD 84 CB7 134 DM4 184 DM7

36 VDD 86 NC 136 DQ38 186 VSS

38 VSS 88 VSS 138 VSS 188 DQ62

40 VSS 90 VSS 140 DQ39 190 DQ63

42 DQ20 92 VDD 142 DQ44 192 VDD

44 DQ21 94 VDD 144 VDD 194 SA0

46 VDD 96 CKE0 146 DQ45 196 SA1

48 DM2 98 NC 148 DM5 198 SA2

50 DQ22 100 A11 150 VSS 200 NC

Indicates a VDD or VDDQ pin Indicates a VSS pin

U1 U2 U3 U4 U5

PIN 1 PIN 199

(all odd pins) PIN 2

PIN 200 (all even pins)

Front View Back View

U11U10

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 5: Pin Descriptions

Refer to Pin Assignment Tables on page 3 for pin number and symbol correlation.

PIN NUMBERS SYMBOL TYPE DESCRIPTION

118, 119, 120 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define

the command being entered.

35, 37 CK0, CK0# Input Clock: CK and CK# are differential clock inputs distributed

through an on-board PLL to all devices. All address and control

input signals are sampled on the crossing of the positive edge of

CK and negative edge of CK#. Output data (DQ and DQS) is

referenced to the crossings of CK and CK#.

96 CKE0, Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the

internal clock, input buffers.and output drivers. Taking CKE LOW

provides PRECHARGE POWER- DOWN and SELF REFRESH

operations (all device banks idle), or ACTIVE POWER-DOWN (row

ACTIVE in any device bank). CKE is synchronous for POWER-

DOWN entry and exit, and for SELF REFRESH entry. CKE is

asynchronous for SELF REFRESH exit and for disabling the

outputs. CKE must be maintained HIGH throughout read and

write accesses. Input buffers (excluding CK, CK# and CKE) are

disabled during POWER-DOWN. Input buffers (excluding CKE)

are disabled during SELF REFRESH. CKE is an SSTL_2 input but

will detect an LVCMOS LOW level after VDD is applied.

121 S0# Input Chip Select: S# enables (registered LOW) and disables (registered

HIGH) the command decoder. All com- mands are masked when

S# is registered HIGH. S# is considered part of the command

code.

117, 116 BA0, BA1 Input Bank Address: BA0, BA1 define to which device bank an ACTIVE,

READ, WRITE, or PRECHARGE command is being applied.

99 (A12), 100, 101,102,

105, 106, 107, 108, 109,

110, 111, 112, 115,

123 (A13)

A0–A11

(128MB)

A0–A12

(256MB, 512MB)

A0–A13

(1GB)

Input Address Inputs: A0-A11/A12 provide the row address for ACTIVE

commands, and the column address, and auto precharge bit

(A10) for READ/WRITE commands, to select one location out of

the memory array in the respective device bank. A10 sampled

during a PRECHARGE command determines whether the

PRECHARGE applies to one device bank (A10 LOW, device bank

selected by BA0, BA1) or all device banks (A10 HIGH). The

address inputs also provide the op-code during a MODE

during the LOAD MODE REGISTER command.

11, 25, 47, 61, 77, 133,

147,169, 183

DQS0–DQS8 Input/

Output

Data Strobe: Output with READ data, input with WRITE data.

DQS is edge-aligned with READ data, centered in WRITE data.

Used to capture data.

12, 26, 48, 62, 78, 134,

148, 170, 184

DM0–DM8 Input Data Mask: DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH along with that input data

during a WRITE access. DM is sampled on both edges of DQS.

Although DM pins are input-only, the DM loading is designed to

match that of DQ and DQS pins.

71, 72, 73, 74, 79, 80, 83,

CB0–CB7 Input/

Output

Check Bits.

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

5, 6, 7, 8, 13, 14, 17, 18,

19, 20, 23, 24, 29, 30, 31,

32, 41, 42, 43, 44, 49, 50,

53, 54, 55, 56, 59, 60, 61,

65, 66, 67, 68, 127, 128,

129, 130, 135, 136, 139,

140, 141, 142, 145, 146,

151, 152, 153, 154, 163,

164, 165, 166, 171, 172,

175, 176, 177, 181, 182,

187, 188, 189, 190

DQ0–DQ63 Input/

Output

Data I/Os: Data bus.

195 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the

presence-detect data transfer to and from the module.

194, 196, 198 SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to configure

the presence-detect device.

193 SDA Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-detect

portion of the module.

1, 2 VREF Supply SSTL_2 reference voltage.

9, 10, 21, 22, 33, 34, 36,

45, 46, 57, 58, 69, 70, 81,

82, 92, 93, 94, 113, 114,

131, 132, 143, 144, 155,

156, 157, 167, 168, 179,

180, 191, 192

VDD Supply DQ Power Supply: +2.5V ±0.2V.

3, 4, 15, 16, 27, 28, 38,

39, 40, 51, 52, 63, 64, 75,

76, 87, 88, 90, 103, 104,

125, 126, 137, 138, 149,

150, 159, 161, 162, 173,

174, 185, 186

VSS Supply Ground.

197 VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V.

85, 86, 89, 91, 95, 97, 98,

99 (128MB), 122, 123

(128MB, 256MB,

512MB), 124, 158, 160,

200

NC – No Connect: These pins should be left unconnected.

Table 5: Pin Descriptions

Refer to Pin Assignment Tables on page 3 for pin number and symbol correlation.

PIN NUMBERS SYMBOL TYPE DESCRIPTION

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 3: Functional Block Diagram

SA0

SERIAL PD

SDA

SA1

SA2

BA0, BA1

A0-A11 (128MB)

A0-A12 (256MB, 512MB)

A0-A13 (1GB)

RAS#

CAS#

CKE0

WE#

BA0, BA1: DDR SDRAMS

A0-A11: DDR SDRAMS

A0-A12: DDR SDRAMS

RAS#: DDR SDRAMS

CAS#: DDR SDRAMS

CKE0: DDR SDRAMS

WE#: DDR SDRAMS

REF

DDR SDRAMS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U10

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U11

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

S0#

SCL

DM CS# DQS

DQS0

DM4

DQS4

DM1

DQS1

DM5

DQS5

DM2

DQS2

DM6

DQS6

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DM3

DQS3

DM7

DQS7

DM8

DQS8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DDSPD

DDR SDRAMS

SPD/EEPROM

PLL

DDR SDRAM X 2

DDR SDRAM X 1

CK0

CK0#

120 U9

4.7pF

NOTE:

1. All resistor values are 22Ω unless otherwise specified.

2. Per industry standard, Micron modules utilize various component speed

grades, as referenced in the module part numbering guide at

www.micron.com/numberguide.

Standard modules use the following DDR SDRAM devices:

MT46V16M8TG (128MB); MT46V32M8TG (256MB); MT46V64M8TG

(512MB); MT46V128M8TG (1GB)

Lead-free modules use the following DDR SDRAM devices:

MT46V16M8P (128MB); MT46V32M8P (256MB); MT46V64M8P (512MB);

MT46V128M8P (1GB)

Contact Micron for information on IT modules.

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

General Description

The Micron MT9VDDT1672PH, MT9VDDT3272PH,

MT9VDDT6472PH, and MT9VDDT12872PH, are high-

speed CMOS, dynamic random-access, 128MB,

256MB, 512MB, and 1GB memory modules organized

in x72 (ECC) configuration. DDR SDRAM modules use

internally configured quad-bank DDR SDRAM devices.

DDR SDRAM modules use a double data rate archi-

tecture to achieve high-speed operation. The double

data rate architecture is essentially a 2n-prefetch

architecture with an interface designed to transfer two

data words per clock cycle at the I/O pins. A single

read or write access for the DDR SDRAM module effec-

tively consists of a single 2n-bit wide, one-clock-cycle

data transfer at the internal DRAM core and two corre-

sponding n-bit wide, one-half-clock-cycle data trans-

fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at

the receiver. DQS is an intermittent strobe transmitted

by the DDR SDRAM device during READs and by the

memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with

data for WRITEs.

DDR SDRAM modules operate from differential

clock inputs (CK and CK#); the crossing of CK going

HIGH and CK# going LOW will be referred to as the

positive edge of CK. Commands (address and control

signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and out-

put data is referenced to both edges of DQS, as well as

to both edges of CK. A phase-lock loop (PLL) device on

the module is used to redrive the differential clock sig-

nals to the DDR SDRAM devices to minimize system

clock loading.

Read and write accesses to DDR SDRAM modules

are burst oriented; accesses start at a selected location

and continue for a programmed number of locations in

a programmed sequence. Accesses begin with the reg-

istration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address bits

registered coincident with the ACTIVE command are

used to select the device bank and row to be accessed

(BA0, BA1 select device bank; A0–A11 select device row

for 128MB; A0–A12 select device row for 256MB and

512MB; and A0–A13 select device row for 1GB). The

address bits registered coincident with the READ or

WRITE command are used to select the device bank

and the starting device column location for the burst

access.

DDR SDRAM modules provide for programmable

read or write burst lengths of 2, 4, or 8 locations. An

auto precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end of

the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,

thereby providing high effective bandwidth by hiding

row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-

patible with the JEDEC Standard for SSTL_2. All out-

puts are SSTL_2, Class II compatible. For more

information regarding DDR SDRAM operation, refer to

the 128Mb, 256Mb, 512Mb, or 1Gb DDR SDRAM data

sheets.

PLL Operation

A phase-lock loop (PLL) on the module is used to

redrive the differential clock signals CK and CK# to the

DDR SDRAM devices to minimize system clock load-

ing.

Serial Presence-Detect Operation

DDR SDRAM modules incorporate serial presence-

detect (SPD). The SPD function is implemented using

a 2,048-bit EEPROM. This nonvolatile storage device

contains 256 bytes. The first 128 bytes can be pro-

grammed by Micron to identify the module type and

various SDRAM organizations and timing parameters.

The remaining 128 bytes of storage are available for

use by the customer. System READ/WRITE operations

between the master (system logic) and the slave

EEPROM device (DIMM) occur via a standard I2C bus

using the DIMM’s SCL (clock) and SDA (data) signals,

together with SA(2:0), which provide eight unique

DIMM/EEPROM addresses. Write protect (WP) is tied

to ground on the module, permanently disabling hard-

ware write protect.

Mode Register Definition

The mode register is used to define the specific

mode of operation of DDR SDRAM device. This defini-

tion includes the selection of a burst length, a burst

type, a CAS latency and an operating mode, as shown

in the Mode Register Diagram. The mode register is

programmed via the MODE REGISTER SET command

(with BA0 = 0 and BA1 = 0) and will retain the stored

information until it is programmed again or the device

loses power (except for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-

rectly. The mode register must be loaded (reloaded)

when all device banks are idle and no bursts are in

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

progress, and the controller must wait the specified

time before initiating the subsequent operation. Vio-

lating either of these requirements will result in

unspecified operation.

Mode register bits A0–A2 specify the burst length, A3

specifies the type of burst (sequential or interleaved),

A4–A6 specify the CAS latency, and A7–A11 (128MB),

A7–A12 (256MB, 512MB), or A7–A13 (1GB) specify the

operating mode.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-

mable, as shown in Mode Register Diagram. The burst

length determines the maximum number of column

locations that can be accessed for a given READ or

WRITE command. Burst lengths of 2, 4, or 8 locations

are available for both the sequential and the inter-

leaved burst types.

eserved states should not be used, as unknown oper-

ation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1–Ai when the burst length is set to two,

by A2–Ai when the burst length is set to four and by

A3–Ai when the burst length is set to eight (where Ai is

the most significant column address bit for a given

configuration; see note 5 of Table 6, Burst Definition

Table, on page 9). The remaining (least significant)

address bit(s) is (are) used to select the starting loca-

tion within the block. The programmed burst length

applies to both read and write bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Table 6, Burst

Definition Table, on page 9.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the

availability of the first bit of output data. The latency

can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS

Latency Diagram, on page 9.

Figure 4: Mode Register Definition

Diagram

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

Operating Mode

A10

A12 A11

BA0

BA1

Burst LengthCAS Latency BT0*0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA0 and BA1) must be “0, 0” to select the

base mode register (vs. the extended mode register).

256MB and 512MB Modules

128MB Module

M3 = 0

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9765438210

M6-M0

M8 M7

Operating Mode

A10A12 A11BA0BA1

10111214

* M15 and M14 (BA1 and BA0)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9M10M12 M11

A13

M13

* M14 and M13 (BA0 and BA1) must be “0, 0” to select the

base mode register (vs. the extended mode register).

1GB Module

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

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NOTE:

1. For a burst length of two, A1-Ai select the two- data-

element block; A0 selects the first access within the

block.

2. For a burst length of four, A2-Ai select the four- data-

element block; A0-A1 select the first access within the

block.

3. For a burst length of eight, A3-Ai select the eight-

data-element block; A0-A2 select the first access within

the block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps

within the block.

5. i = 9 for 128MB, 256MB

i = 9, 11 for 512MB, 1GB

Figure 5: CAS Latency Diagram

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nominally coincident with clock edge n + m. Table 7,

CAS Latency (CL) Table, on page 9, indicates the oper-

ating frequencies at which each CAS latency setting

can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7–A11

(128MB), A7–A12 (256MB, 512MB

)

, or A7–A13 (1GB)

each set to zero, and bits A0–A6 set to the desired val-

ues.

A DLL reset is initiated by issuing a MODE REGIS-

TER SET command with bits A7 and A9–A11 (128MB);

A7 and A9–A12 (256MB, 512MB); or A7 and A9–A13

(1GB) each set to zero, bit A8 set to one, and bits A0–A6

set to the desired values. Although not required by the

Micron device, JEDEC specifications recommend

when a LOAD MODE REGISTER command is issued to

reset the DLL, it should always be followed by a LOAD

MODE REGISTER command to select normal operat-

ing mode.

Table 6: Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

00-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 7: CAS Latency (CL) Table

SPEED

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

CL = 2 CL = 2.5

-335 N/A 75 ≤ f ≤ 167

-262 75 ≤ f ≤ 133 75 ≤ f ≤ 133

-26A 75 ≤ f ≤ 133 75 ≤ f ≤ 133

-265 75 ≤ f ≤ 100 75 ≤ f ≤ 133

CK#

COMMAND

DQS

CL = 2

READ NOP NOP NOP

Burst Length = 4 in the cases shown

Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T0 T1 T2 T2n T3 T3n

DON’T CARETRANSITIONING DATA

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

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All other combinations of values for A7–A11

(128MB.), A7–A12 (256MB, 512MB), or A7–A13 (1GB)

are reserved for future use and/or test modes. Test

modes and reserved states should not be used because

unknown operation or incompatibility with future ver-

sions may result.

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these

additional functions are DLL enable/disable and out-

put drive strength. These functions are controlled via

the bits shown in the Extended Mode Register Defini-

tion Diagram. The extended mode register is pro-

grammed via the LOAD MODE REGISTER command

to the mode register (with BA0 = 1 and BA1 = 0) and

will retain the stored information until it is pro-

grammed again or the device loses power. The

enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0, /BA1 both low) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,

and the controller must wait the specified time before

initiating any subsequent operation. Violating either

of these requirements could result in unspecified oper-

ation.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is enabled,

200 clock cycles with CKE HIGH must occur before a

READ command can be issued.

Figure 6: Extended Mode Register

Definition Diagram

NOTE:

1. BA1 and BA0 (E13 and E12 for 128MB; E14 and E13 for

256MB, 512MB; or E15 and E14 for 1GB) must be “0, 1”

to select the Extended Mode Register (vs. the base

Mode Register).

2. QFC# is not supported.

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Operating Mode

A10

A11A2

BA1 BA0

1314

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Operating Mode

A10

A11

BA1 BA0

128MB Module

256MB and 512MB Modules

Operating Mode

Reserved

–

Valid

–

DLL

Enable

Disable

DLL

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

Drive Strength

Normal

E2 E0

E1,

Operating Mode

A10A11A12BA1 BA0

1011121415

E3E4

–

E6 E5

E7E8E9

–

E10E11

–

E12

–

E13

A13

1GB Module

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

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Commands

Table 8, Commands Truth Table, and Table 9, DM

Operation Truth Table, provide a general reference of

available commands. For a more detailed description

of commands and operations, refer to the Micron

128Mb, 256Mb, 512Mb, or 1Gb DDR SDRAM compo-

nent data sheets.

NOTE:

1. DESELECT and NOP are functionally interchangeable.

2. BA0–BA1 provide device bank address and A0–A11(128MB), A0–A12 (256MB, 512MB), or A0–A13 (1GB) provide row

address.

3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB, 1GB) provide column address;

A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–

BA1 are "Don’t Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don’t Care" except for CKE.

8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;

BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11(128MB), A0–A12

(256MB, 512MB), or A0–A13 (1GB) provide the op-code to be written to the selected mode register.

Table 8: Commands Truth Table

CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) HXXX X 1

NO OPERATION (NOP) LHHH X 1

ACTIVE (Select device bank and activate row) L L H H Bank/Row 2

READ (Select device bank and column, and start READ burst) L H L H Bank/Col 3

WRITE (Select device bank and column, and start WRITE burst) L H L L Bank/Col 3

BURST TERMINATE LHHL X 4

PRECHARGE (Deactivate row in device bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH

(Enter self refresh mode)

LLLH X 6, 7

LOAD MODE REGISTER L L L L Op-Code 8

Table 9: DM Operation Truth Table

Used to mask write data; provided coincident with the corresponding data

NAME (FUNCTION) DM DQS

Write Enable L Valid

Write Inhibit HX

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

VDD Supply Voltage Relative to VSS . . . . -1V to +3.6V

VDDQ Supply Voltage Relative to VSS . . . -1V to +3.6V

VREF and Inputs Voltage

Relative to Vss . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

I/O Pins Voltage

Relative to VSS. . . . . . . . . . . . . -0.5V to VddQ +0.5V

Operating Temperature,

TA (ambient - commercial) . . . . . . . . .0°C to +70°C

TA (ambient - industrial) . . . . . . . . . -40°C to +85°C

Storage Temperature (plastic) . . . . . .-55°C to +150°C

Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1–5, 14; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 2.3 2.7 V 32, 36

I/O Supply Voltage VDDQ 2.3 2.7 V 32, 36, 39

I/O Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V6, 39

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 39

Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 25

Input Low (Logic 0) Voltage VIL(DC)-0.3VREF - 0.15 V 25

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤

1.35V

(All other pins not under test = 0V)

Command/Address,

RAS#, CAS#, WE#,

CKE, S#

II-18 18 µA

CK, CK# II-5 5 µA

DM II-2 2 µA

OUTPUT LEAKAGE CURRENT

(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)

DQ, DQS IOZ -5 5 µA 46

OUTPUT LEVELS:

High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT)

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)

IOH -16.8 – mA

33, 34

IOL 16.8 – mA

Table 11: AC Input Operating Conditions

Notes: 1–5, 12, 48; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(AC)VREF + 0.310 – V 25, 35

Input Low (Logic 0) Voltage VIL(AC)–VREF - 0.310 V 25, 35

I/O Reference Voltage VREF(AC) 0.49 x VDDQ 0.51 x VDDQ V6

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

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Table 12: IDD Specifications and Conditions – 128MB

DDR SDRAM components only;

Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYMBOL -335 -262

-26A/

-265 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs

changing once every two clock cycles

IDD01,125 990 945 mA 20, 41

OPERATING CURRENT: One device bank; Active-Read-

Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT =

0mA; Address and control inputs changing once per clock

cycle

IDD11,215 1,080 1,080 mA 20, 41

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle; Power-down mode; tCK = tCK (MIN); CKE =

(LOW)

IDD2P27 27 27 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control

inputs changing once per clock cycle. VIN = VREF for DQ, DQS,

and DM

IDD2F405 405 360 mA 44

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW

IDD3P225 225 180 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One

device bank; Active-Precharge; tRC = RAS (MAX); tCK = tCK

(MIN); DQ, DM and DQS inputs changing twice per clock

cycle; Address and other control inputs changing once per

clock cycle

IDD3N450 450 405 mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;

One device bank active; Address and control inputs

changing once per clock cycle; CK = tCK (MIN); IOUT = 0mA

IDD4R1,260 1,170 1,125 mA 20, 41

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;

One device bank active; Address and control inputs

changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and

DQS inputs changing twice per clock cycle

IDD4W1,260 1,125 1,080 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD52,385 1,980 1,980 mA 20, 43

tREFC = 15.625µs IDD5A45 45 45 mA 24, 43

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD627 27 18 mA 9

OPERATING CURRENT: Four bank interleaving READs (BL=4)

with auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN);

Address and control inputs change only during Active READ,

or WRITE commands

IDD73,195 2,970 2,925 mA 20, 42

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

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Table 13: IDD Specifications and Conditions – 256MB

DDR SDRAM components only;

Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYMBOL -335 -262

-26A/

-265 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs

changing once every two clock cycles

IDD01,125 1,125 960 mA 20, 41

OPERATING CURRENT: One device bank; Active-Read-

Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN);

IOUT = 0mA; Address and control inputs changing once per

clock cycle

IDD11,530 1,440 1,305 mA 20, 41

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle; Power-down mode; tCK = tCK (MIN);

CKE = (LOW)

IDD2P35 36 36 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and

IDD2F450 405 405 mA 44

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank active; Power-down mode; tCK = tCK (MIN);

CKE = LOW

IDD3P270 225 225 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One

device bank; Active-Precharge; tRC = RAS (MAX); tCK = tCK

(MIN); DQ, DM and DQS inputs changing twice per clock

cycle; Address and other control inputs changing once per

clock cycle

IDD3N540 450 450 mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;

One device bank active; Address and control inputs

changing once per clock cycle; CK = tCK (MIN); IOUT = 0mA

IDD4R1,575 1,350 1,350 mA 20, 41

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;

One device bank active; Address and control inputs

changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and

DQS inputs changing twice per clock cycle

IDD4W1,400 1,200 1,200 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD52,295 2,115 2,115 mA 20, 43

tREFC = 7.8125µs IDD5A54 54 54 mA 24, 43

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD636 36 36 mA 9

OPERATING CURRENT: Four bank interleaving READs (BL=4)

with auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN);

Address and control inputs change only during Active READ,

or WRITE commands

IDD73,645 3,150 3,150 mA 20, 42

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

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Table 14: IDD Specifications and Conditions – 512MB

DDR SDRAM components only;

Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYMBOL -335 -262

-26A/

-265 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge; tRC =

tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing

once per clock cyle; Address and control inputs changing once

every two clock cycles

IDD01,040 1,040 920 mA 20, 41

OPERATING CURRENT: One device bank; Active-Read-Precharge;

Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address

and control inputs changing once per clock cycle

IDD11,280 1,280 1,160 mA 20, 41

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)

IDD2P40 40 40 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK

= tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2F360 360 320 mA 44

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank

active; Power-down mode; tCK = tCK (MIN); CKE = LOW

IDD3P280 280 240 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One

device bank; Active-Precharge; tRC = RAS (MAX); tCK = tCK

(MIN); DQ, DM and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once per clock cycle

IDD3N400 400 360 mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

device bank active; Address and control inputs changing once

per clock cycle; CK = tCK (MIN); IOUT = 0mA

IDD4R1,320 1,320 1,160 mA 20, 41

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

IDD4W1,400 1,240 1,080 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD52,320 2,320 2,240 mA 20, 43

tREFC = 7.8125µs IDD5A80 80 80 mA 24, 43

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD640 40 40 mA 9

OPERATING CURRENT: Four bank interleaving READs (BL=4) with

auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN); Address

and control inputs change only during Active READ, or WRITE

commands

IDD73,240 3,200 2,800 mA 20, 42

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

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Table 15: IDD Specifications and Conditions – 1GB

DDR SDRAM components only;

Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYMBOL -335 -262

-26A/

-265 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge; tRC =

tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing

once per clock cyle; Address and control inputs changing once

every two clock cycles

IDD01,040 1,040 1,160 mA 20, 41

OPERATING CURRENT: One device bank; Active-Read-Precharge;

Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address

and control inputs changing once per clock cycle

IDD11,280 1,280 1,440 mA 20, 41

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)

IDD2P40 40 80 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK

= tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2F360 360 480 mA 44

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank

active; Power-down mode; tCK = tCK (MIN); CKE = LOW

IDD3P280 280 240 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One

device bank; Active-Precharge; tRC = RAS (MAX); tCK = tCK

(MIN); DQ, DM and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once per clock cycle

IDD3N360 360 360 mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

device bank active; Address and control inputs changing once

per clock cycle; CK = tCK (MIN); IOUT = 0mA

IDD4R1,320 1,320 1,600 mA 20, 41

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

IDD4W1,240 1,240 1,680 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD52,320 2,320 2,640 mA 20, 43

tREFC = 7.8125µs IDD5A80 80 80 mA 24, 43

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD640 40 72 mA 9

OPERATING CURRENT: Four bank interleaving READs (BL=4) with

auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN); Address

and control inputs change only during Active READ, or WRITE

commands

IDD73,240 3,200 3,880 mA 20, 42

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Table 16: Capacitance)

Note: 11; notes appear on pages 19–22

PARAMETER SYMBOL MIN TYP MAX UNITS

Input/Output Capacitance: DQ, DQS, DM CIO 4.0 - 5.0 pF

Input Capacitance: Command and Address, S#, CKE CI118.0 - 27.0 pF

Input Capacitance: CK, CK# CI2-7.7- pF

Table 17: Electrical Characteristics and Recommended AC Operating Conditions

DDR SDRAM components only; notes appear on pages 19–22

Notes: 1–5, 12–15, 29, 47; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -335 -262 -26A/-265

UNITS NOTESPARAMETER SYMBOL MIN MAX MIN MAX MIN MAX

Access window of DQs from CK/CK# tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26

Clock cycle time CL = 2.5 tCK (2.5) 6 13 7.5 13 7.5 13 ns 40, 45

CL = 2 tCK (2) 7.5 13 7.5 13 10 13 ns 40, 45

DQ and DM input hold time relative to

DQS

tDH 0.45 0.5 0.5 ns 23, 27

DQ and DM input setup time relative to

DQS

tDS 0.45 0.5 0.5 ns 23, 27

DQ and DM input pulse width (for each

input)

tDIPW 1.75 1.75 1.75 ns 27

Access window of DQS from CK/CK# tDQSCK

-0.60

+0.60 -0.75 +0.75 -0.75 +0.75 ns

DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per

group, per access

tDQSQ 0.45 0.5 0.6 ns 22, 23

Write command to first DQS latching

transition

tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CK rising - hold

time

tDSH 0.2 0.2 0.2 tCK

Half clock period tHP tCH, tCL tCH, tCL tCH, tCL ns 30

Data-out high-impedance window from

CK/CK#

tHZ +0.70 +0.75 +0.75 ns 16, 37

Data-out low-impedance window from

CK/CK#

tLZ

-0.70

-0.75 -0.75 ns 16, 37

Address and control input hold time

(slow slew rate)

tIHS0.75 0.90 1.1 ns 12

Address and control input setup time

(slow slew rate)

tISS0.75 0.90 1.1 ns 12

Address and Control input pulse width

(for each input)

tIPW 2.2 2.2 2.2 ns

LOAD MODE REGISTER command cycle

time

tMRD 0.80 15 15 ns

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DQ-DQS hold, DQS to first DQ to go non-

valid, per access

tQH tHP -

tQHS

tHP -

tQHS

tHP-

tQHS

ns 22, 23

Data Hold Skew Factor tQHS 0.50 0.75 0.75 ns

ACTIVE to PRECHARGE command tRAS 42 70,000 40 120,000 40 120,000 ns 31, 48

ACTIVE to READ with Auto precharge

command tRAP 15 15 20 ns

ACTIVE to ACTIVE/AUTO REFRESH

command period

tRC 60 60 65 ns

AUTO REFRESH command

period

128MB,

256MB,

512MB tRFC

72 75 75 ns 43

1GB 120 120 120 ns 43

ACTIVE to READ or WRITE delay tRCD 15 15 20 ns

PRECHARGE command period tRP 15 15 20 ns

DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 38

DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 38

ACTIVE bank a to ACTIVE bank b

command

tRRD 12 15 15 ns

DQS write preamble tWPRE 0.25 0.25 0.25 tCK

DQS write preamble setup time tWPRES 000ns18, 19

DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 17

Write recovery time tWR 15 15 15 ns

Internal WRITE to READ command delay tWTR 111

tCK

Data valid output window (DVW) na tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns 22

REFRESH to REFRESH

command interval

128MB

tREFC

140.6 140.6 140.6 µs 21

256MB,

512MB, 1GB

70.3 70.3 70.3 µs 21

Average periodic refresh

interval

128MB

tREFI

15.6 15.6 15.6 µs 21

256MB,

512MB, 1GB

7.8 7.807.8µs

Terminating voltage delay to VDD tVTD 000ns

Exit SELF REFRESH to non-READ

command

tXSNR 75 75 75 ns

Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK

Table 17: Electrical Characteristics and Recommended AC Operating Conditions

(Continued)

DDR SDRAM components only; notes appear on pages 19–22

AC CHARACTERISTICS -335 -262 -26A/-265

UNITS NOTESPARAMETER SYMBOL MIN MAX MIN MAX MIN MAX

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Notes

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC

characteristics may be conducted at nominal ref-

erence/supply voltage levels, but the related spec-

ifications and device operation are guaranteed for

the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and IDD tests may use a VIL-to-VIH

swing of up to 1.5V in the test environment, but

input timing is still referenced to VREF (or to the

crossing point for CK/CK#), and parameter speci-

fications are guaranteed for the specified AC input

levels under normal use conditions. The mini-

mum slew rate for the input signals used to test

the device is 1V/ns in the range between VIL(AC)

and VIH(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver

will effectively switch as a result of the signal

crossing the AC input level, and will remain in that

state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmit-

ting device and to track variations in the DC level

of the same. Peak-to-peak noise (non-common

mode) on Vref may not exceed ±2 percent of the

DC value. Thus, from VDDQ/2, Vref is allowed

±25mV for DC error and an additional ±25mV for

AC noise. This measurement is to be taken at the

nearest VREF bypass capacitor.

7. VTT is not applied directly to the device. VTT is a

system supply for signal termination resistors, is

expected to be set equal to VREF and must track

variations in the DC level of VREF.

8. IDD is dependent on output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time at CL = 2 for -26A and -202, CL =

2.5 for -335 and -265 with the outputs open.

9. Enables on-chip refresh and address counters.

10. IDD specifications are tested after the device is

properly initialized, and is averaged at the defined

cycle rate.

11. This parameter is sampled. VDD = +2.5V ±0.2V,

VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA =

25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) =

0.2V. DM input is grouped with I/O pins, reflecting

the fact that they are matched in loading.

12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew

rate is < 0.5V/ns, timing must be derated: tIS has

an additional 50ps per each 100 mV/ns reduction

in slew rate from 500 mV/ns, while tIH is unaf-

fected. If the slew rate exceeds 4.5 V/ns, function-

ality is uncertain. For -335, slew rates must be ≥

0.5 V/ns.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and

CK# cross; the input reference level for signals

other than CK/CK# is VREF.

14. Inputs are not recognized as valid until VREF stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.

15. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is

VTT.

16. tHZ and tLZ transitions occur in the same access

time windows as data valid transitions. These

parameters are not referenced to a specific voltage

level, but specify when the device output is no

longer driving (HZ) or begins driving (LZ).

17. The intent of the Don’t Care state after completion

of the postamble is the DQS-driven signal should

either be high, low, or high-Z and that any signal

transition within the input switching region must

follow valid input requirements. That is, if DQS

transitions high [above VIHDC (MIN)] then it must

not transition low (below VIHDC) prior to tDQSH

(MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic

LOW) applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time,

depending on tDQSS.

20. MIN (tRC or tRFC) for IDD measurements is the

smallest multiple of tCK that meets the minimum

absolute value for the respective parameter. tRAS

(MAX) for IDD measurements is the largest multi-

ple of tCK that meets the maximum absolute

value for tRAS.

21. The refresh period 64ms. This equates to an aver-

age refresh rate of 15.625µs (128MB),

or 7.8251µs

Output

(VOUT)

Reference

Point

50Ω

VTT

30pF

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(

256MB

512MB

1GB). However, an AUTO

REFRESH command must be asserted at least

once every 140.6µs

(128MB) or 70.3µs (

256MB

512MB

1GB); burst refreshing or posting by the

DRAM controller greater than eight refresh cycles

is not allowed.

22. The valid data window is derived by achieving

other specifications: tHP (tCK/2), tDQSQ, and tQH

(tQH = tHP - tQHS). The data valid window derates

in direct porportion with the clock duty cycle and

a practical data valid window can be derived, as

shown in Figure 7, Derating Data Valid Window.

The clock is allowed a maximum duty cycle varia-

tion of 45/55, beyond which functionality is

uncertain. The data valid window derating curves

are provided below for duty cycles ranging

between 50/50 and 45/55.

23. Each byte lane has a corresponding DQS.

24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during

REFRESH command period (tRFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current

AC level through to the target AC level, VIL(AC)

or VIH(AC).

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to

maintain at least the target DC level, VIL(DC) or

VIH(DC).

26. JEDEC specifies CK and CK# input slew rate must

be ≤ 1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/

DM/DQS slew rate is less than 0.5 V/ns, timing

must be derated: 50ps must be added to tDS and

tDH for each 100 mv/ns reduction in slew rate. If

slew rate exceeds 4 V/ns, functionality is uncer-

tain. For -335, slew rates must be ≥ 0.5 V/ns.

28. VDD must not vary more than 4 percent if CKE is

not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same

amount.

Figure 7: Derating Data Valid Window

(tQH - tDQSQ)

3.750 3.700 3.650 3.600 3.550

3.500 3.450

3.400 3.350 3.300 3.250

2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55

Clock Duty Cycle

-335 @

CK = 6ns

-262/-26A/-265 @

CK = 10ns

-262/-26A/-265 @

CK = 7.5ns

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30. tHP min is the lesser of tCL minimum and ttCH

minimum actually applied to the device CK and

CK# inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not

allowed to be issued until tRAS(min) can be satis-

fied prior to the internal precharge command

being issued.

32. Any positive glitch must be less than 1/3 of the

clock and not more than +400mV or 2.9V, which-

ever is less. Any negative glitch must be less than

1/3 of the clock cycle and not exceed either -

300mV or 2.2V, whichever is more positive.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-

ature and voltage will lie within the outer

bounding lines of the V-I curve of Figure 8,

Pull-Down Characteristics.

b. The variation in driver pull-down current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve of Figure 8,

Pull-Down Characteristics.

c. The full variation in driver pull-up current from

minimum to maximum process, temperature

and voltage will lie within the outer bounding

lines of the V-I curve of Figure 9, Pull-Up Char-

acteristics

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve of Figure 9,

Pull-Up Characteristics.

e. The full variation in the ratio of the maximum to

minimum pull-up and pull-down current

should be between 0.71 and 1.4, for device

drain-to-source voltages from 0.1V to 1.0V, and

at the same voltage and temperature.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity

±10 percent, for device drain-to-source voltages

from 0.1V to 1.0V.

34. The voltage levels used are derived from a mini-

mum VDD level and the referenced test load. In

practice, the voltage levels obtained from a prop-

erly terminated bus will provide significantly dif-

ferent voltage values.

35. VIH overshoot: VIH(MAX) = VDDQ + 1.5V for a

pulse width ≤ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. VIL undershoot:

VIL(MIN) = -1.5V for a pulse width ≤ 3ns and the

pulse width can not be greater than 1/3 of the

cycle rate.

36. VDD and VDDQ must track each other.

37. tHZ (MAX) will prevail over tDQSCK (MAX) +

tRPST (MAX) condition. tLZ (MIN) will prevail

over tDQSCK (MIN) + tRPRE (MAX) condition.

38. tRPST end point and tRPRE begin point are not

referenced to a specific voltage level but specify

when the device output is no longer driving

(tRPST), or begins driving (tRPRE).

39. During initialization, VDDQ, VTT, and VREF must

be equal to or less than VDD + 0.3V. Alternatively,

VTT may be 1.35V maximum during power up,

even if VDD/VDDQ are 0Vs, provided a minimum

of 42Ω of series resistance is used between the VTT

supply and the input pin.

40. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As

such, future die may not reflect this option.

Figure 8: Pull-Down Characteristics Figure 9: Pull-Up Characteristics

160

140

OUT

(mA)

OUT

(V)

Nominal low

Minimum

Nominal high

Maximum

120

100

0.0 0.5 1.0 1.5 2.0 2.5

OUT

(V)

-20

OUT

(mA)

Nominal low

Minimum

Nominal high

Maximum

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0 0.5 1.0 1.5 2.0 2.5

Q - V

OUT

(V)

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41. Random addressing changing and 50 percent of

data changing at every transfer.

42. Random addressing changing and 100 percent of

data changing at every transfer.

43. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the

time the AUTO REFRESH command is registered,

CKE must be active at each rising clock edge, until

tREF later.

44. IDD2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. IDD2Q is

similar to IDD2F except IDD2Q specifies the

address and control inputs to remain stable.

Although IDD2F, IDD2N, and IDD2Q are similar,

IDD2F is “worst case.”

45. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.

This is followed by 200 clock cycles.

46. Leakage number reflects the worst case leakage

possible through the module pin, not what each

memory device contributes.

47. When an input signal is HIGH or LOW, it is

defined as a steady state logic HIGH or LOW.

48. The -335 speed grade will operate with tRAS (MIN)

= 40ns and tRAS (MAX) = 120,000ns at any slower

frequency.

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Initialization

To ensure device operation the DRAM must be ini-

tialized as described below:

1. Simultaneously apply power to VDD and VDDQ.

2. Apply VREF and then VTT power.

3. Assert and hold CKE at a LVCMOS logic low.

4. Provide stable CLOCK signals.

5. Wait at least 200µs.

6. Bring CKE high and provide at least one NOP or

DESELECT command. At this point the CKE input

changes from a LVCMOS input to a SSTL2 input

only and will remain a SSTL_2 input unless a

power cycle occurs.

7. Perform a PRECHARGE ALL command.

8. Wait at least tRP time, during this time NOPs or

DESELECT commands must be given.

9. Using the LMR command program the Extended

Mode Register (E0 = 0 to enable the DLL and E1 =

0 for normal drive or E1 = 1 for reduced drive, E2

through En must be set to 0; where n = most sig-

nificant bit).

10. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

11. Using the LMR command program the Mode Reg-

ister to set operating parameters and to reset the

DLL. Note at least 200 clock cycles are required

between a DLL reset and any READ command.

12. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

13. Issue a PRECHARGE ALL command.

14. Wait at least tRP time, only NOPs or DESELECT

commands are allowed.

15. Issue an AUTO REFRESH command (Note this

may be moved prior to step 13).

16. Wait at least tRFC time, only NOPs or DESELECT

commands are allowed.

17. Issue an AUTO REFRESH command (Note this

may be moved prior to step 13).

18. Wait at least tRFC time, only NOPs or DESELECT

commands are allowed.

19. Although not required by the Micron device,

JEDEC requires a LMR command to clear the DLL

bit (set M8 = 0). If a LMR command is issued the

same operating parameters should be utilized as

in step 11.

20. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

21. At this point the DRAM is ready for any valid com-

mand. Note 200 clock cycles are required between

step 11 (DLL Reset) and any READ command.

Figure 10: Initialization Flow Diagram

and V

Q Ramp

Apply V

REF

and V

CKE must be LVCMOS Low

Apply stable CLOCKs

Bring CKE High with a NOP command

Wait at least 200us

PRECHARGE ALL

Assert NOP or DESELECT for tRP time

Configure Extended Mode Register

Configure Load Mode Register and reset DLL

Assert NOP or DESELECT for tMRD time

PRECHARGE ALL

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRFC time

Optional LMR command to clear DLL bit

Assert NOP or DESELECT for tMRD time

DRAM is ready for any valid command

Step

Assert NOP or DESELECT commands for tRFC

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRP time

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NOTE:

1. The timing and switching specifications for the PLL listed above are critical for proper operation of DDR SDRAM

modules. These are meant to be a subset of the parameters for the specific device used on the module. Detailed

information for this PLL is available in JEDEC Standard JESD82.

2. The PLL must be able to handle spread spectrum induced skew.

3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required

to meet the other timing parameters. (Used for low-speed system debug.)

4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its

reference signal after power up.

5. Static Phase Offset does not include Jitter.

6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each

other.

7. The Output Slew Rate is determined from the IBIS model:

Table 18: PLL Clock Driver Timing Requirements and Switching Characteristics

Note: 1

PARAMETER SYMBOL

0°C ≤ TA ≤ +70°C

VDD = +2.5V ±0.2V

UNITS NOTESMIN NOMINAL MAX

Operating Clock Frequency fCK 60 - 170 MHz 2, 3

Input Duty Cycle tDC 40 - 60 %

Stabilization Time tSTAB -- 100ms4

Cycle to Cycle Jitter tJITCC -75 - 75 ps

Static Phase Offset t∅-50 0 50 ps 5

Output Clock Skew tSKO-- 100ps

Period Jitter tJITPER -75 - 75 ps 6

Half-Period Jitter tJITHPER -100 - 100 ps 6

Input Clock Slew Rate tLSI1.0 - 4 V/ns

Output Clock Slew Rate tLSO1.0 - 2 V/ns 7

GND

CDCV857

R=60

Ω

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Figure 11: Component Case Temperature vs. Air Flow

NOTE:

1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules.

2. The component case temperature measurements shown above were obtained experimentally. The typical system to be

used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered

memory modules. Case temperatures charted represent worst-case component locations on modules installed in the

internal slots of the system.

3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from

its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard

for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test

chamber.

4. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic soft-

ware application developed for internal use by Micron Technology, Inc.

100

0.0

0.5

1.0

2.0

Air Flow (meters/sec)

Degrees Celsius

Ambient Temperature = 25º C

Tmax

- memory stress software

Tave

- 3D gaming software

Tave

- memory stress software

Minimum Air Flow

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SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (as

shown in Figure 12, Data Validity, and Figure 13, Defi-

nition of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has been

met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (as shown in Fig-

ure 14, Acknowledge Response from Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and

its slave address. If both the device and a WRITE oper-

ation have been selected, the SPD device will respond

with an acknowledge after the receipt of each subse-

quent eight-bit word. In the read mode the SPD device

will transmit eight bits of data, release the SDA line and

monitor the line for an acknowledge. If an acknowl-

edge is detected and no stop condition is generated by

the master, the slave will continue to transmit data. If

an acknowledge is not detected, the slave will termi-

nate further data transmissions and await the stop

condition to return to standby power mode.

Figure 12: Data Validity Figure 13: Definition of Start and Stop

Figure 14: Acknowledge Response from Receiver

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

SCL

SDA

START

BIT

STOP

BIT

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 15: SPD EEPROM Timing Diagram

Table 19: EEPROM Device Select Code

Most significant bit (b7) is sent first

SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select Code (two arrays) 1010SA2SA1SA0RW

Protection Register Select Code 0110SA2SA1SA0RW

Table 20: EEPROM Operating Modes

MODE RW BIT WC BYTES INITIAL SEQUENCE

Current Address Read 1V

IH or VIL 1START, Device Select, RW = ‘1’

Random Address Read 0V

IH or VIL 1START, Device Select, RW = ‘0’, Address

1VIH or VIL 1reSTART, Device Select, RW = ‘1’

Sequential Read 1VIH or VIL ≥ 1Similar to Current or Random Address Read

Byte Write 0V

IL 1START, Device Select, RW = ‘0’

Page Write 0VIL ≤ 16 START, Device Select, RW = ‘0’

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising

edge of SDA.

2. This parameter is sampled.

3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA

remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 21: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

SUPPLY VOLTAGE VDD 2.3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD X 0.7 VDD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10µA

STANDBY CURRENT:

SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD

ISB –30µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz IDD –2mA

Table 22: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 µs

Data-out hold time tDH 200 ns

SDA and SCL fall time tF 300 ns 2

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 0.6 µs

Clock HIGH period tHIGH 0.6 µs

Noise suppression time constant at SCL, SDA inputs tI50ns

Clock LOW period tLOW 1.3 µs

SDA and SCL rise time tR0.3µs2

SCL clock frequency fSCL 400 KHz

Data-in setup time tSU:DAT 100 ns

Start condition setup time tSU:STA 0.6 µs 3

Stop condition setup time tSU:STO 0.6 µs

WRITE cycle time tWRC 10 ms 4

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 23: Serial Presence-Detect Matrix – 128MB, 256MB, 512MB

“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”

BYTE DESCRIPTION ENTRY(VERSION)

MT9VDDT1672PH MT9VDDT3272PH

MT9VDDT6472PH

0Number of SPD Bytes Used by Micron 128 80 80 80

1Total Number of Bytes in SPD Device 256 08 08 08

2Fundamental Memory Type DDR SDRAM070707

3Number of Row Addresses on Ass’y 12 or13 0C 0D 0D

4Number of Column Addresses on Ass’y 10 or 11 0A 0A 0B

5Number of Physical Ranks on DIMM 1 010101

6Module Data Width 72 48 48 48

7Module Data Width (Continued) 0 000000

8Module Voltage Interface Levels SSTL 2.5V 04 04 04

9SDRAM Cycle Time, tCK (CAS Latency =

2.5) (see note 2)

6ns (-335)

7ns (-262/-26A)

7.5ns (-265)

10 SDRAM Access from Clock, tAC (CAS

Latency = 2.5) (see note 1)

0.7ns (-335)

0.75ns (-262/-26A/-265)

11 Module Configuration Type ECC 020202

12 Refresh Rate/ Type 15.6µs or 7.8µs/SELF 80 82 82

13 SDRAM Device Width (Primary DDR

SDRAM)

8 080808

14 Error-checking DDR SDRAM Data

Width

8 080808

15 Minimum Clock Delay, Back-to-Back

Random Column Access

1 clock010101

16 Burst Lengths Supported 2, 4, 8 0E0E0E

Number of Banks on DDR SDRAM Device

4 040404

18 CAS Latencies Supported 2, 2.5 0C 0C 0C

19 CS Latency 0 010101

20 WE Latency 1 020202

21 SDRAM Module Attributes Unbuff, Diff CLK, PLL 24 24 24

22 SDRAM Device Attributes: General Fast/concurrent AP 00 C0 C0

23 SDRAM Cycle Time, tCK (CL = 2) (See

note

)

7.5ns (-335/-262/-26A)

10ns (-265)

24 SDRAM Access from CK, tAC (CL = 2)

(See note

)

0.7ns (-335)

0.75ns (-265/-26A)

25 SDRAM Cycle Time, tCK (CL = 1.5) N/A 000000

26 SDRAM Access from CK, tAC (CL = 1.5) N/A 000000

27 Minimum Row Precharge Time, tRP

(see note 5)

18ns (-335)

15ns (-262)

20ns (-26A/-265)

28 Minimum Row Active to Row Active,

tRRD

12ns (-335)

15ns (-262/-26A/-265)

29 Minimum RAS# to CAS# Delay, tRCD

(see note 5)

18ns (-335)

15ns (-262)

20ns (-26A/-265)

30 Minimum RAS# Pulse Width, tRAS (see

note 3)

42ns (-335)

45ns (-262/-26A/-265)

31 Module Rank Density

128MB, 256MB, 512MB

20 40 80

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. Device latencies used for SPD values.

2. Value for -262/-26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

3. The value of tRAS used for -265 modules is calculated from tRC - tRP. Actual device spec value is 40ns.

4. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-

mum slew rate is met.

5. The value of tRP, tRCD, and tRAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR

SDRAM device specification is 15ns.

32 Address and Command Setup Time, tIS

(see note 4)

0.8ns (-335)

1.0ns (-262/-26A/-265)

33 Address and Command Hold Time, tIH

(see note 4)

0.8ns (-335)

1.0ns (-262/-26A/-265)

34 Data/Data Mask Input Setup Time, tDS 0.45ns (-335

0.5ns (-262/-26A/-265)

35 Data/ Data Mask Input Hold Time, tDH 0.45ns (-335

0.5ns (-262/-26A/-265)

36-40 Reserved 00 00 00

41 Min Active Refresh Time tRC 60ns (-335/-262)

65ns (-26A/-265)

42 Minimum Auto Refresh to Active/Auto

Refresh Command Period, tRFC

72ns (-335)

75ns (-262/-26A/-265)

43 SDRAM Device Max Cycle Time, tCKMAX 12ns (-335)

13ns (-262/-26A/-265)

44 SDRAM Device Max DQS–DQ Skew

Time, tDQSQ

0.45ns (-335)

0.5ns (-262/-26A/-265)

45 SDRAM Device Max Read Data Hold

Skew Factor

0.55ns (-335)

0.75ns (-262/-26A/-265)

46 Reserved 00 00 00

47 DIMM Height 01 01 01

48–61 Reserved 00 00 00

62 SPD Revision Revision 1.0101010

63 Checksum For Bytes 0–62 -335

-262

-26A

-265

64 Manufacturer’s JEDEC ID Code MICRON 2C 2C 2C

65-71 Manufacturer’s JEDEC ID Code

(continued)

00 00 00

72 Manufacturing Location 01–12 01–0C 01–0C 01–0C

73-90 Module Part Number (ASCII) Variable Data Variable Data Variable Data

91 PCB Identification Code 1–9 01–09 01–09 01–09

92 Identification Code (Continued) 0 000000

93 Year Of Manufacture in BCD Variable Data Variable Data Variable Data

94 Week Of Manufacture in BCD Variable Data Variable Data Variable Data

95-98 Module Serial Number Variable Data Variable Data Variable Data

99-127 Manufacturer-Specific Data ( RSVD) –––

Table 23: Serial Presence-Detect Matrix – 128MB, 256MB, 512MB (Continued)

“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”

BYTE DESCRIPTION ENTRY(VERSION)

MT9VDDT1672PH MT9VDDT3272PH

MT9VDDT6472PH

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 24: Serial Presence- Detect Matrix – 1GB

“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”

BYTE DESCRIPTION ENTRY(VERSION)

MT9VDDT12872PH

0Number of SPD Bytes Used by Micron 128 80

1Total Number of Bytes in SPD Device 256 08

2Fundamental Memory Type SDRAM DDR 07

3Number of Row Addresses on Assembly 14 0E

4Number of Column Addresses on Assembly 11 0B

5Number of Physical Ranks on DIMM 201

6Module Data Width 72 48

7Module Data Width (Continued) 000

8Module Voltage Interface Levels SSTL 2.5V 04

9SDRAM Cycle Time, tCK (CAS Latency = 2.5)

(see note 2)

6ns (-335)

7ns (-262/-26A)

7.5ns (-265)

10 SDRAM Access from Clock, tAC (CAS Latency = 2.5)

(see note 1)

0.7ns (-335)

0.75ns (-262/-26A/-265)

11 Module Configuration Type ECC 02

12 Refresh Rate/ Type 7.8µs/SELF 82

13 SDRAM Device Width (Primary DDR SDRAM) x8 08

14 Error-checking DDR SDRAM Data Width x8 08

15 Minimum Clock Delay, Back-to-Back Random Column

Access

1 clock 01

16 Burst Lengths Supported 2, 4, 8 0E

17 Number of Banks on DDR SDRAM Device 404

18 CAS Latencies Supported 2.5 0C

19 CS Latency 001

20 WE Latency 102

21 SDRAM Module Attributes Unbuffered, Diff CLK, PLL 24

22 SDRAM Device Attributes: General Fast/concurrent AP C0

23 SDRAM Cycle Time, tCK (CAS Latency = 2)

(see note

)

7.5ns (-335/-26A/-262)

10ns (-265)

24 SDRAM Access from CK, tAC (CAS Latency = 2)

(see note

0.7ns (-335)

0.75ns (-262/-26A/-265)

25 SDRAM Cycle Time, tCK (CAS Latency = 1.5) N/A 00

SDRAM Access from CK,

AC (CAS Latency = 1.5)

N/A 00

27 Minimum Row Precharge Time, tRP (see note 5) 18ns (-335)

15ns (-262)

20ns (-265/-26A)

28 Minimum Row Active to Row Active, tRRD 12ns (-335)

5ns (-262/-26A/-265)

29 Minimum RAS# to CAS# Delay, tRCD (see note 5) 18ns (-335)

15ns (-262)

20ns (-26A/-265)

30 Minimum RAS# Pulse Width, tRAS (see note 3) 42ns (-335)

45ns (-262/-26A/-265)

31 Module Rank Density 1GB 01

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. Device latencies used for SPD values.

2. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

3. The value of tRAS used for -265 modules is calculated from tRC - tRP. Actual device spec value is 40ns.

4. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-

mum slew rate is met.

5. The value of tRP, tRCD, and tRAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR

SDRAM device specification is 15ns.

32 Address and Command Setup Time, tIS

(see note 4)

0.8ns (-335)

1.0ns (-262/-26A/-265)

33 Address and Command Hold Time, tIH

(see note 4)

0.8ns (-335)

1.0ns (-262/-26A/-265)

34 Data/Data Mask Input Setup Time, tDS 0.45ns (-335

0.5ns (-262/-26A/-265)

35 Data/ Data Mask Input Hold Time, tDH 0.45ns (-335

0.5ns (-262/-26A/-265)

36-40 Reserved 00

41 Min Active Refresh Time tRC 60ns (-335/-262)

65ns (-265/-26A)

42 Minimum Auto Refresh to Active/Auto Refresh

Command Period, tRFC

120ns 78

43 SDRAM Device Max Cycle Time, tCKMAX 12ns (-335)

13ns (-262/-26A/-265)

44 SDRAM Device Max DQS-DQ Skew Time, tDQSQ 0.45ns (-335)

0.5ns (-262/-26A/-265)

45 SDRAM Device Max Read Data Hold Skew Factor 0.55ns (-335)

0.75ns (-262/-26A/-265)

46 Reserved 00

47 DIMM Height 01

48–61 Reserved 00

62 SPD Revision Revision 1.0 10

63 Checksum For Bytes 0-62 -335

-262

-26A

-265

64 Manufacturer’s JEDEC ID Code MICRON 2C

65-71 Manufacturer’s JEDEC ID Code (continued) 00

72 Manufacturing Location 01–12 01–0C

73-90 Module Part Number (ASCII) Variable Data

91 PCB Identification Code 1–9 01–09

92 Identification Code (Continued) 000

93 Year of Manufacture in BCD Variable Data

94 Week of Manufacture in BCD Variable Data

95-98 Module Serial Number Variable Data

99-127 Manufacturer-Specific Data ( RSVD) –

Table 24: Serial Presence- Detect Matrix – 1GB (Continued)

“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”

BYTE DESCRIPTION ENTRY(VERSION)

MT9VDDT12872PH

128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)

200-PIN DDR SDRAM SODIMM

ADVANCE

pdf: 09005aef808ffe58, source: 09005aef808ffdc7 Micron Technology, Inc., reserves the right to change products or specifications without notice.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 16: 200-Pin SODIMM Dimensions

NOTE:

All dimensions are in inches (millimeters); or typical where noted.

Data Sheet Designation

Advance: This datasheet contains initial descrip-

tions of products still under development. Advance

applies to MT9VDDT12872PH only.

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete

power supply and temperature range for production

devices. Although considered final, these specifications

are subject to change, as further product development

and data characterization sometimes occur. Released

(No Mark) applies to MT9VDDT1672PH

MT9VDDT3272PH

and MT9VDDT6472PH only.

U1 U2 U3 U4 U5

0.150 (3.80)

MAX

PIN 1

2.667 (67.75)

2.656 (67.45)

0.787 (20.00)

TYP

0.071 (1.80)

(2X)

0.024 (0.61)

TYP

0.018 (0.46)

TYP

0.079 (2.00) R

(2X)

PIN 199

PIN 200 PIN 2

FRONT VIEW

0.079 (2.00)

0.236 (6.00)

2.504 (63.60)

0.096 (2.44)

0.039 (0.99)

TYP

1.256 (31.90)

1.244 (31.60)

BACK VIEW

0.043 (1.10)

0.035 (0.90)

U11U10

MAX

MIN